CS 350 Operating Systems

Fall 2019

Memory Management:

Segmentation

1

• Separate I and D spaces

Separate Instruction and Data Spaces

• One address space

• A program can have multiple virtual address space.

• One-dimensional address space with growing tables

Example: Compiler program without segmentation

• One process has multiple address spaces.

• Each address space grows or shrink, independently

Example: Compiler program with segmentation

Comparison of paging and segmentation

(a)-(d) Development of checkerboarding (external fragmentation)

(e) Removal of the checkerboarding by compaction

Implementation of Pure Segmentation

• Multics -- IBM mainframe systems. A pioneer of introducing

segment to modern architecture.

• Every process can have multiple virtual address spaces (or

segments)

• Each Segment has its own page table

• Advantage

• Each segment can have the full virtual address space allowed by

number of address bits

• Disadvantage

• Switching from one segment to another has a high context

switch penalty, even within the same process.

MULTICS — Paged Segmentation

Translation of a Multics Virtual Address▪ The segment number identify the specific address space of a segment –

using a table, the segment descriptor table

▪ Each entry contains the information of a segment, known as segment

descriptor, which specifies which

• Segment descriptor table has

one descriptor for each

segment

Segmentation with Paging: MULTICS

• Each segment descriptor points to a page table

• Each process can have multiple segments

• Multiple segments map to one linear address space

• Linear address space has one page table

Pentium — Paged Segmentation

Segment 3

Segment 2

Segment 1

Linear

Address Space

Physical

Memory

Page Table

Base 1

Limit 1

Base 2

Limit 2

Base 3

Limit 3

Step 1: Convert (selector, offset) pair to a linear address using segment descriptor

Translation of a Pentium Virtual Address

(or Virtual Address)

Step 2: Convert linear address

onto a physical address

using page table entry

Segment

Base address of the

segment

A Pentium selector(equivalent to Segment Number in Multics)

GDT = Global Descriptor Table

LDT = Local Descriptor Table

Segmentation with Paging: Pentium

Similar to MULTICS, but addresses a number of different design goals

• Code segment descriptor

• Data segment descriptors are slightly different

Four privilege levels in x86

• Chapter 16 in OSTEP

• Chapter 3: Modern Operating Systems, Andrew S. Tanenbaum

• Segmentation• http://en.wikipedia.org/wiki/Memory_segment

• x86• http://en.wikipedia.org/wiki/X86

• Intel Memory model• http://en.wikipedia.org/wiki/Intel_Memory_Model

References

Review: Memory Management

• Virtual Memory: Each process gets an illusion that it has more

memory than the physical RAM in the system. How?

• Address space:

• The abstraction that the OS is providing to the program/process:

• The program/process has an illusion that it is can use the memory

space starting at a particular address and going up to a very large

address space (address bits)

• Paging:

• Split up the address space into equal-sized units, which are called

pages. Correspondingly, split up the physical memory into equal-

sized units, called frames.

• OS decides which pages map to which frames (mapping)

Review: Memory Management

• Page Table:

• An array that stores the mapping from virtual page numbers (VPN)

to physical frame number (PFN)

• Per process data structure

• Linear page table

• Multi-level page table

• Comparations between them

• Know how to construct these page tables

• Key components:

• Virtual pages, physical frames, virtual page number (VPN),

physical frame number (PFN), page table entries (PTN)

• size of address space, number of virtual pages, number of page

table entries

Review: Memory Management

• Address Translation:

• By hardware --- MMU

• Input of MMU is VA; With the VA, MMU walks through page

table (could be multiple levels) to translate the VA to PA.

• 2-level page table!

• Page directory, (the second level) page tables

• Again, know how to construct them (by calculating the number

of entries, size, etc.). Refer to your quiz.

Review: Memory Management

• TLB:

• Paging is slow. Why?

• TLB is a small cache that speeds up the translation of virtual

addresses to the physical addresses

• via caching virtual-to-physical address translation

• Give a simple code, you should be able to figure out the TLB

activities -- TLB misses, TLB hits.

• Refer to your quiz questions and the example in the slides (need

to understand not to memorize.

• Cold start penalty and the solution

• TLB coverage

• Supepage

Review: Memory Management

• Page Fault:

• Page Replacement Algorithms:

• What is the main metric?

• Why OPR? Why LRU? And why NRU

• FIFO, second chance, and clock

• What is working set?

• Design discussions

• Segmentation:

• What is segmentation? Why is it needed?

• Comparisons between segmentation and paging.

• Paged segmentation. How does the address translation look like

with both paging and segmentation enabled?