Memory Interfacing & decoding in Intel CPU’s · BP XXXX XXXX SP 00000 23 WR 00001 95 When the P outputs CS an address between SI XXXX 8000000000toFFFFF7FFFF no IP XXXX DI XXXX 80000

Memory Interfacing & decoding inin

Intel CPU’s

Outline

• Address decoding

• Chip select

• Memory configurations

Minimum Mode

D7 - D0D7 - D0

A19 - A0A19 - A0

MEMORY

SimplifiedDrawing of

8088 MinimumMode

RDMEMR

WRMEMW

When Memory is selected?

Minimum Mode

220 bytes or 1MBD7 - D0D7 - D0

A19 - A0A19 - A0

MEMORY

SimplifiedDrawing of

8088 MinimumModeMode

RD

WR

MEMR

MEMW WRMEMWCS

What are the memory locations of a 1MB (220 bytes) Memory?1MB (2 bytes) Memory?

A19 to A0

(HEX)

AAAA11119876

AAAA11115432

AAAA11981000

AAAA7654

AAAA3210

(HEX) 9876 5432 100000000 0000 0000 0000 0000 0000FFFFF 1111 1111 1111 1111 1111FFFFF 1111 1111 1111 1111 1111

Example: 34FD0

0011 0100 11111 1101 00000011 0100 11111 1101 0000

Interfacing a 1MB Memory to the 8088 Microprocessor

FFFFDFFFFEFFFFF

192536

::A19A19CXBXAX

000000233F1C

FCA1DX

20020200212002220023

29127D13::

A0:

A0:

ESDSSS

XXXX2000XXXX

CS XXXX

1000710008

F48A

::

::D7

D0:

D7

D0:BP

XXXXXXXX

SP

1000210003100041000510006

2739428807

RDMEMR

XXXXSI

XXXXIP

XXXXDI

00001

1000010001

95

::

4598

::WRMEMW

230000000001 95

CS

Instead of Interfacing 1MB, what will happen if you interface a 512KB Memory?

What are the memory locations of a 512KB (219 bytes) Memory?512KB (2 bytes) Memory?

A18 to A0

(HEX)

AAAA11119876

AAAA11115432

AAAA11981000

AAAA7654

AAAA3210

(HEX) 9876 5432 100000000 0000 0000 0000 0000 00007FFFF 0111 1111 1111 1111 11117FFFF 0111 1111 1111 1111 1111

Interfacing a 512KB Memory to the 8088 Microprocessor

A18CXBXAX

000000233F1C

FCA1DX 7FFFF 36A18A19 What do we do with A19?

A0:

D7ESDSSS

XXXX2000XXXX

CS XXXX 7FFFD7FFFE

1925

::

::

A0:

D7

D0:

MEMRBP

XXXXXXXX

SP:

20020200212002220023

29127D13

:

D0:

RDMEMWXXXXSI

XXXXIP

XXXXDI2300000

00001 95

::

::WR

CS

What if you want to read physical address A0023?

A18CXBXAX

000000233F1C

FCA1DX 7FFFF 36A18A19

A0:

D7ESDSSS

XXXXA000XXXX

CS XXXX 7FFFD7FFFE

1925

::

::

A0:

D7

D0:

MEMRBP

XXXXXXXX

SP:

20020200212002220023

29127D13

:

D0:

RDMEMWXXXXSI

XXXXIP

XXXXDI2300000

00001 95

::

::WR

CS

What if you want to read physical address A0023?address A0023?

A19 to A0

(HEX)

AAAA11119876

AAAA11115432

AAAA11981000

AAAA7654

AAAA3210

(HEX) 9876 5432 1000A0023 1010 0000 0000 0010 0011

A19 is not connected to the memory soA19 is not connected to the memory so even if the 8088 microprocessor outputs a logic “1”, the memory

t “ ” thicannot “see” this.

What if you want to read physical address 20023?address 20023?

A18 to A0

(HEX)

AAAA11119876

AAAA11115432

AAAA11981000

AAAA7654

AAAA3210

(HEX) 9876 5432 100020023 0010 0000 0000 0010 0011

For memory it is the same as previousFor memory it is the same as previous one.

Interfacing two 512KB Memory to the 8088 Microprocessor

A18

A0:CX

BXAX

000000233F1C

FCA1DX

A19

7FFFD7FFFE7FFFF

192536

::

A18

A0:

D7

D0:

MEMRESDSSS

XXXX2000XXXX

CS XXXX

:20020200212002220023

29127D13

:

D7

D0:

RDMEMW

BPXXXXXXXX

SP2300000

00001 95WRCS

XXXXSI

XXXXIP

XXXXDI

20023

7FFFD7FFFE7FFFF

33

2C9812

::

A18

A0:

00001:

200202002120022

A39245

:

D7

D0:

RD

970000000001 D4WR

CS


• Problem: Bus Conflict. The two memory chips will provide data at the same time when microprocessor performs a memory read.microprocessor performs a memory read.

• Solution: Use address line A19 as an “arbiter”. If A19 outputs a logic “1” the upper memory is enabled (and the lower memory ismemory is enabled (and the lower memory is disabled) and vice-versa.


A18

A0:CX

BXAX

000000233F1C

FCA1DX

A19

7FFFD7FFFE7FFFF

192536

::

A18

A0:

D7

D0:

MEMRESDSSS

XXXX2000XXXX

CS XXXX

:20020200212002220023

29127D13

:

D7

D0:

RDMEMW

BPXXXXXXXX

SP2300000

00001 95WRCS

XXXXSI

XXXXIP

XXXXDI

20023

7FFFD7FFFE7FFFF

33

2C9812

::

A18

A0:

:200202002120022

A39245

:

D7

D0:

RD

970000000001 D4WR

CS

What are the memory locations of two consecutive 512KB (219 bytes) Memory?

A19 to A0

(HEX)

AAAA11119876

AAAA11115432

AAAA11981000

AAAA7654

AAAA3210

(HEX) 9876 5432 100000000 0000 0000 0000 0000 00007FFFF 0111 1111 1111 1111 11117FFFF 0111 1111 1111 1111 111180000 1000 0000 0000 0000 0000FFFFF 1111 1111 1111 1111 1111


A18

A0:CX

BXAX

000000233F1C

FCA1DX

A19

7FFFD7FFFE7FFFF

192536

::

A18

A0:

D7

D0:

MEMRESDSSS

XXXX2000XXXX

CS XXXX

:20020200212002220023

29127D13

:

D7

D0:

RDMEMW

BPXXXXXXXX

SP2300000

00001 95WRCSWhen the P outputs

an address between 80000 to FFFFF

When the P outputs an address between 00000 to 7FFFFXXXXSI

XXXXIP

XXXXDI

20023

7FFFD7FFFE7FFFF

33

2C9812

::

A18

A0:

80000 to FFFFF, this memory is selected

00000 to 7FFFF, this memory is selected

:200202002120022

A39245

:

D7

D0:

RD

970000000001 D4WR

CS


A18

A0:CX

BXAX

000000233F1C

FCA1DX

A19

7FFFD7FFFE7FFFF

192536

::

A18

A0:

D7

D0:

MEMRESDSSS

XXXX2000XXXX

CS XXXX

:20020200212002220023

29127D13

:

D7

D0:

RDMEMRMEMW

BP

ES

XXXXXXXX

XXXX

SP2300000

00001 95::RD

WRCS

XXXXSI

XXXXIP

XXXXDI

20023

7FFFD7FFFE7FFFF

33

2C9812

::

A18

A0:

:20020200212002220023

A3924533

:

D7

D0:

RD

970000000001 D4WR

CS


A18

A0:CX

BXAX

000000233F1C

FCA1DX

A19

7FFFD7FFFE7FFFF

192536

::

A18

A0:

A18

A0:

A19

D7

D0:

MEMRESDSSS

XXXX2000XXXX

CS XXXX

:20020200212002220023

29127D13

:

D7

D0:

RD

D7

D0:

RDMEMRMEMW

BP

ES

XXXXXXXX

XXXX

SP2300000

00001 95::RD

WRCS

RDWR

XXXXSI

XXXXIP

XXXXDI

20023

7FFFD7FFFE7FFFF

33

2C9812

::

A18

A0:

:20020200212002220023

A3924533

:

D7

D0:

RD

970000000001 D4WR

CS

What if we remove the lower memory?

A18

A0:CX

BXAX

000000233F1C

FCA1DX

A19

7FFFD7FFFE7FFFF

192536

::

A18

A0:

D7

D0:

MEMRESDSSS

XXXX2000XXXX

CS XXXX

:20020200212002220023

29127D13

:

D7

D0:

RDMEMW

BPXXXXXXXX

SP2300000

00001 95WRCS

XXXXSI

XXXXIP

XXXXDI

20023

7FFFD7FFFE7FFFF

33

2C9812

::

A18

A0:

:200202002120022

A39245

:

D7

D0:

RD

970000000001 D4WR

CS

What if we remove the lower memory?

A18

A0:CX

BXAX

000000233F1C

FCA1DX

A19

7FFFD7FFFE7FFFF

192536

::

A18

A0:

D7

D0:

MEMRESDSSS

XXXX2000XXXX

CS XXXX

:20020200212002220023

29127D13

:

D7

D0:

RDMEMW

BPXXXXXXXX

SP2300000

00001 95WRCSWhen the P outputs

an address between 80000 to FFFFF

When the P outputs an address between 00000 to 7FFFF noXXXXSI

XXXXIP

XXXXDI80000 to FFFFF, this memory is selected

00000 to 7FFFF, no memory chip is selected !!

Full and Partial Decoding

• Full Decoding– When all of the “useful” address lines are connected the

memory/device to perform selection

• Partial Decoding– When some of the “useful” address lines are connected

the memory/device to perform selectiony p– Using this type of decoding results into roll-over

addresses

Full Decoding

A18

A0:CX

BXAX

000000233F1C

FCA1DX

A19

7FFFD7FFFE7FFFF

192536

::

A18

A0:

D7

D0:

MEMRESDSSS

XXXX2000XXXX

CS XXXX

:20020200212002220023

29127D13

:

D7

D0:

RDMEMW

BPXXXXXXXX

SP2300000

00001 95WRCS

XXXXSI

XXXXIP

XXXXDI

Full Decoding

A19 to A0

(HEX)

AAAA11119876

AAAA11115432

AAAA11981000

AAAA7654

AAAA3210

(HEX) 9876 5432 100080000 1000 0000 0000 0000 0000FFFFF 1111 1111 1111 1111 1111FFFFF 1111 1111 1111 1111 1111

A19 should be a logic “1” for theA19 should be a logic 1 for the memory chip to be enabled

Full Decoding

A19 to A0

(HEX)

AAAA11119876

AAAA11115432

AAAA11981000

AAAA7654

AAAA3210

(HEX) 9876 5432 100000000 0000 0000 0000 0000 00007FFFF 0111 1111 1111 1111 11117FFFF 0111 1111 1111 1111 1111

Therefore if the microprocessorTherefore if the microprocessor outputs an address between 00000 to 7FFFF, whose A19 is a logic “0”, the

hi ill t b l t dmemory chip will not be selected

Partial Decoding

A18CXBXAX

000000233F1C

FCA1DX 7FFFF 36A18A19

A0:

D7ESDSSS

XXXX2000XXXX

CS XXXX 7FFFD7FFFE

1925

::

::

A0:

D7

D0:

MEMRBP

XXXXXXXX

SP:

20020200212002220023

29127D13

:

D0:

RDMEMWXXXXSI

XXXXIP

XXXXDI2300000

00001 95

::

::WR

CS

Partial Decoding

A19 to A0

(HEX)

AAAA11119876

AAAA11115432

AAAA11981000

AAAA7654

AAAA3210


The value of A19 is INSIGNIFICANT to theThe value of A19 is INSIGNIFICANT to the memory chip, therefore A19 has no bearing whether the memory chip will be enabled or not

Partial Decoding

A19 to A0

(HEX)

AAAA11119876

AAAA11115432

AAAA11981000

AAAA7654

AAAA3210


ACTUAL ADDRESSACTUAL ADDRESS

Partial Decoding

A19 to A0

(HEX)

AAAA11119876

AAAA11115432

AAAA11981000

AAAA7654

AAAA3210


ACTUAL ADDRESSACTUAL ADDRESS

Interfacing two 512K Memory Chips to the 8088 Microprocessor

A18

A0:

A19A18

A0:

D7

D0:

MEMR

512KB#2

D7

D0:

RD

8088Minimum

Mode

MEMW WRCS

512KB

A18

A0:

D7#1

D0:

RDWRCS

Interfacing one 512K Memory Chips to the 8088 Microprocessor

A18

A0:

A19A18

A0:

D7

D0:

MEMR

512KBD7

D0:

RD

8088Minimum

Mode

MEMW WRCS

Interfacing one 512K Memory Chips to the 8088 Microprocessor (version 2)

A18

A0:

A19A18

A0:

D7

D0:

MEMR

512KBD7

D0:

RD

8088Minimum

Mode

MEMW WRCS

Interfacing one 512K Memory Chips to the 8088 Microprocessor (version 3)

A18

A0:

A19A18

A0:

D7

D0:

MEMR

512KBD7

D0:

RD

8088Minimum

Mode

MEMW WRCS

Interfacing four 256K Memory Chips to the 8088 Microprocessor

256KB

A17

A0:

D7

A18A19

256KB#4D0

:

RDWRCS

A17

A0:

D7

D0:

MEMR

256KB#3

A17

A0:

D7

D0:

RD

8088Minimum

Mode

MEMRMEMW

RDWRCS

A17

A0:

256KB#2

A0D7

D0:

RDWRCSCS

256KB#1

A17

A0:

D7:

#1D0RDWRCS


256KB

A17

A0:

D7

A18A19

256KB#4D0

:

RDWRCS

A17

A0:

D7

D0:

MEMR

256KB#3

A17

A0:

D7

D0:

RD

8088Minimum

Mode

MEMRMEMW

RDWRCS

A17

A0:

256KB#2

A0D7

D0:

RDWRCSCS

256KB#1

A17

A0:

D7:

#1D0RDWRCS

Memory chip#__ is mapped to:

A19 t AAAA AAAA AAAA AAAA AAAAA19 to A0

(HEX)

AAAA11119876

AAAA11115432

AAAA11981000

AAAA7654

AAAA3210

----- ---- ---- ---- ---- ----

----- ---- ---- ---- ---- ----


256KB

A17

A0:

D7

A18A19

256KB#4D0

:

RDWRCS

A17

A0:

D7

D0:

MEMR

256KB#3

A17

A0:

D7

D0:

RD

8088Minimum

Mode

MEMRMEMW

RDWRCS

A17

A0:

256KB#2

A0D7

D0:

RDWRCSCS

256KB#1

A17

A0:

D7:

#1D0RDWRCS


256KB

A17

A0:

D7

A18A19

256KB#4D0

:

RDWRCS

A17

A0:

D7

D0:

MEMR

256KB#3

A17

A0:

D7

D0:

RD

8088Minimum

Mode

MEMRMEMW

RDWRCS

A17

A0:

256KB#2

D7

D0:

RDWRCS

256KB#1

A17

A0:

D7

D0:D0RDWRCS


256KB

A17

A0:

D7

A18A19

256KB#4D0

:

RDWRCSI1

I0 O3

A17

A0:

D7

D0:

MEMR

256KB#3

A17

A0:

D7

D0:

RD

8088Minimum

Mode

MEMRMEMW

RDWRCS

A17

A0:

O2

256KB#2

D7

D0:

RDWRCSO1

256KB#1

A17

A0:

D7

D0:D0RDWRCSO0

Interfacing several 8K Memory Chips to the 8088 P

8KB#?

A12

A0:

D7

D0:

A17A18A19

A12:

A13A14

RDWRCS

A15A16

:8088

Mi i

A0D7

D0:

MEMRMEMW

::

MinimumMode

8KB#2

A12

A0:

D7: #2D0RDWRCS

A12

8KB#1

A0:

D7

D0:

RDWRWRCS

8KB#128

A12

A0:

D7

D0:

A17A18A19

Interfacing 1288K Memory Chips to the 8088 P

A12:

A13A14

RDWRCS

A15A16

:8088

Mi i

A0D7

D0:

MEMRMEMW

::

MinimumMode

8KB#2

A12

A0:

D7: #2D0RDWRCS

A12

8KB#1

A0:

D7

D0:

RDWRWRCS

8KB#128

A12

A0:

D7

D0:

A17A18A19


A12:

A13A14

RDWRCS

A15A16

:8088

A0D7

D0:

MEMRMEMW

::

MinimumMode

8KB

A12

A0:

D7:

#2D0:

RDWRCS

A12

8KB#1

A12

A0:

D7

D0:

RDWRCS

Memory chip#__ is mapped to:

A19 t AAAA AAAA AAAA AAAA AAAAA19 to A0

(HEX)

AAAA11119876

AAAA11115432

AAAA11981000

AAAA7654

AAAA3210

----- ---- ---- ---- ---- ----

----- ---- ---- ---- ---- ----

Memory Terms

• CapacityCapacity – Kbit, Mbit, Gbit

• Organizationg– Address lines– Data lines

• Speed / Timing– Access time

W it bilit• Write ability– ROM– RAMRAM

ROM Variations

• Mask Rom

PROM OTP• PROM – OTP

• EPROM – UV_EPROM

• EEPROM

Fl h• Flash memory

RAM Variations

• SRAM

DRAM• DRAM

• NV-RAM– SRAM – CMOS

– Internal lithium battery

– Control circuitry to monitor Vcc

Memory Chip

A0 I/O0• 8K SRAM• to be specific:

8K 8 bit SRAM

A0A1A2A3A4

I/O0I/O1I/O2I/O3I/O4– 8Kx8 bits SRAM

6264

A4A5A6A7A8

I/O4I/O5I/O6I/O7

6264A9A10A11A12

CS2CS1

OEWE

CS2

6264 Block Diagram

6264 Function Table

Memory Chip

A0 Q0• 8K EPROM• to be specific:

8K 8 bit EPROM

A0A1A2A3A4

Q0Q1Q2Q3Q4– 8Kx8 bits EPROM

2764

A4A5A6A7A8

Q4Q5Q6Q7

2764A9A10A11A12

VPPC

GP

VPP

2764 Block Diagram

Chip enablep

Output enable

Operating Modes

Programming 2764

• after each erasure for UV-EPROM):– all bits of the M2764A are in the “1" state.

• The only way to change a “0" to a ”1" is by• The only way to change a 0 to a 1 is by ultraviolet light erasure.

• Programming mode when:– VPP input is at 12.5V– E and P are at TTL low.

• The data to the data output pins.The data to the data output pins. • The levels required for the address and data

inputs are TTL.

8KB#128

A12

A0:

D7

D0:

A17A18A19


A12:

A13A14

RDWRCS

A15A16

:8088

A0D7

D0:

MEMRMEMW

::

MinimumMode

8KB

A12

A0:

D7:

#2D0:

RDWRCS

A12

8KB#1

A12

A0:

D7

D0:

RDWRCS

Documents

Memory Interfacing & decoding in Intel CPU’s · BP XXXX XXXX SP 00000 23 WR 00001 95 When the P outputs CS an address between SI XXXX 8000000000toFFFFF7FFFF no IP XXXX DI XXXX 80000