Memory Devices, Circuits,and Subsystem Design

A INTRODUCTION

In the previous chapter, we began our study of the hardware architecture of the 8088-

and 8086-based microcomputer systems. This included a study of the MPU's memory

interface and the circuits needed to connect to a m€mory subsystem. We examined the

memory interface signals, read and write bus cycles, hardware organization of the mem-

ory address space, and memory interface circuits. In this chapter, we continue our study

of microcomputer hardware by examining the devices, circuits, and techniques used in

the design of memory subsystems. For this purpose, this chapter explores the following

toPics:

9.1 Program and Data Storage Memory

9.2 Read-Only Memory

9.3 Random Access Read/Write Memories

9.4 Panty, the Parity Bit, and Parity-Checker/Generator Circuit

9.5 FLASH Memory

9.6 Wait-State Circuitry

9.7 8038/8086 Microcomputer System Memory Circuitry

404

A 9.I PROGRAM AND DATA STORAGE MEMORY

Memory provides the ability to store and retrieve digital information and is one of the keyelements of a microcomputer system. By digital information, we mean that instructionsand data are encoded with 0s and 1s and then saved in memory. The ability to store infor-mation is made possible by the part of the microcomputer system known as the memoryunit. ln Chapter 1, we indicated that the memory unit of the microcomputer is partitioned

rnto apimary slorage seclion and secondary storage sect;on. Figure 9-1 illustrates thissubdivision of the memory unit.

Secondary storage memory is used for storage of data, information, and programs thatare not in use. Tlus part of th" -"*ory unit can be slow speed, but lt ,"qolr", u"ry l-g"storage capacity. For this reason, it is normally implemented with magnetic storage devices,such as the floppy disk and hard disk drive. Hmd disk drives used in today's personal com-puters have the ability to.store 10 gigabytes (Gbyte) to 8OGbytes of information.

The other part, primary storage memory is used for working information, such asthe instructions of the program currently being run and data that it is processing. Thissection normally requires high-speed operation but daes not normally require very largestorage capacity. Therefore, it is implemented with semiconductor memory devices.Most modern personal computers have 128 megabytes (128Mbytes) of primary storagememory.

Figure 9-1 shows that the primary storage memory is further partitioned intoprogram storage memory and data storage memory. The program storage part of thememory subsystem is used to hold information such as the instructions of the program.That is, when a program is executed by the microcomputer, it is read one byte or word ata time from the program storage part of the memory subsystem. These programs can beeither permanently stored in memory which makes them always available for execution,or temporarily loaded into memory before execution. The program storage m€mory sec-tion does not normally contain only instructions, it can also store other fixed informationsuch as constant data and lookup tables.

The program storage memory in a personal computer is implemented exactly thisway. It has a fixed part of program memory that contains the basic input/output system

Figure 9-1 Partitioning of themicrocomputer's memory unit.

Primary storage memory

Sec. 9. I Program and Data Storage Memory 405,

(BIOS). These programs are pelmanently held in a read-only memory device mounted onthe main processor board. Programs held this way in ROM are ca7led firmware because oftheir permanent nature. The typically size of a BIOS ROM used in a PC today is 2 megabits(MB), which equal 256Kbytes.

The much larger part of the program storage memory in a PC is built with dynamicrandom access read/write memory devices (DRAMS). They may be either mounted onthe main processor board or on an add-in memory module or board. use of DRAMsallows this part of the program storage memory to be either read from or written into. Itspurpose is again to store programs that are to be executed, but in this case they are loadedinto memory only when needed. Programs are normally read in from the secondary stor-age device, stored in the program storage part of memory, and then run. when the pro-gram is terminated, the part of the program memory where it resides is given back to theoperating system for reuse. Moreover, if power is turned off, the contents of the RAM-based part of the program storage memory are lost. Due to the temporary nature of theseprograms, they are referred to as software.

Earlier we indicated that the primary storage memory of a microcomputer is typi-cally l28Mbytes. This number represented the total of the DRAM part of the memorysubsystem and is given as the size of memory because the RoM BIoS is almost negligi-ble when compared to the amount of DRAM. In the PC, a major part of primary storageis available for use as program storage memory.

In other microcomputer applications, such as an electronic game or telephone, thecomplete program storage memory is implemented with ROM devices.

Information that frequently changes is stored in the data storage part of themicrocomputer's memory subsystem. For instance, the data to be processed by the micro-computer is held in the data storage part of the primary storage memory. when a pro-gram is run by the microcomputer, the values of the data can change repeatedly. Forthis reason, data storage memory must be implemented with RAM. In a pc, the datadoes not automatically reside in the data storage part of memory. Just like software, itis read into memory from a secondary storage device, such as the hard disk. Any partof the PCs DRAM can be assigned for data storage. The operating system softwaredoes this.

when a program is run, data are modified while in DRAM and writing them to thedisk saves the new values. Data does not have to be numeric in form; they can also bealphanumeric characters, codes, and graphical patterns. For instance, when running aword processor application, the data are alphanumeric and graphical information.

A 9.2 READ-ONLY MEMORY

we begin our study of semiconductor memory devices with the read-only memory(RoM). RoM is one type of semiconductor memory device. It is most widely used inmicrocomputer systems for storage of the program that determines overall system opera-tion. The information stored within a RoM integrated circuit is permanent-ornonvolatile. This means that when the power supply of the device is turned off, the storedinformation is not lost.

4|,6 Memory Devices, Circuits, and Subsystem Design Chap. 9

ROM, PROM, and EPROM

For some ROM devices, information (the microcomputer program) must be builtin during manufacturing, and for others the data must be electrically entered. Theprocess of entering the data into a ROM is called programming. As the name ROMimplies, once entered into the device this information can be read only. For this reason,these devices are used primarily in applications where the stored information would notchange frequently.

Three types of ROM devices are in wide use today: the mask-programmable read-only memory GOM), the one-time-programmable read-only memory (PROM), and theerasable programmable read-only memory (EPROM). Let us continue by looking moreclosely into the first type of device, the mask-programmable read-only memory. Thisdevice has its data pattern programmed as part of the manufacturing process and is knownas mask programming. Once the device is programmed, its contents can never bechanged. Because of this fact and the cost for making the programming masks, ROMs areused mainly in high-volume applications where the data will not change.

The other two types of read-only memories, the PROM and EPROM, differ fromthe ROM in that the user electrically enters the bit pattern for the data. Programming isusually done with an instrument known as an EPROM programmer. Both the PROM andEPROM are programmed in the same way. Once a PROM is programmed, its contentscannot be changed. This is the reason they are sometimes called one-time programmablePROMs. On the other hand, exposing an EPROM to ultraviolet light erases the informa-tion it holds. That is, the programmed bit pattern is cleared out to restore the device to itsunprograrnmed state. In this way, the device can be used over and over again simply byerasing and reprogramming. PROMs and EPROMs are most often used during the designof a product, for early production, when the code of the microcomputer may need fre-quent changes, and for production in low-volume applications that do not warant makinga mask programmed device.

Figure 9-2(a) shows a typical EPROM programmer unit. Programming units likethis usually have the ability to verify that an EPROM is erased, program it with new data,verify correct programming, and read the information out of a programmed EPROM. Anerasing unit such as that shown in Fig. 9-2(b) can be used to erase a number of EPROMICs at one time.

Bfock Diagram of a Read-Only Memory

Figure 9-3 shows a block diagram of a typical read-only memory. Here we see thatthe device has three sets of signal lines: the address inputs, data outputs, and controlinputs. This block diagram is valid for a ROM, PROM, or EPROM. Let us now look atthe function of each of these sets of signal lines.

The address bus is used to input the signals that select between the storage locationswithin the ROM device. In Fig. 9-3 we find that this bus consists of 11 address lines, Aethrough A1e. The bits in the address are arranged so that .4.16 is the MSB and As is theLSB. With an 11-bit address, the memory device has 211 :2048 unique byte-storagelocations. The individual storage locations correspond to conseculive addresses over therange 000000000002 : 00016 through 11111111111 2: 7FF6.

Sec. 9.2 Read-Only Memory 407

(a)

(b)

Figure 9-2 (a) EPROM programming unit. (Data I/O, Inc.) (b) EPROM eras-ing unit. (Ultra-Violet Products, Inc.)

Earlier we pointed out that information is stored inside a ROM, PROM, orEPROM as either a binary 0 or binary 1. Actually, 8 bits of data are stored at everyaddress. Therefore, the organization of the ROM is described as 2048 X 8. The totalstorage capacity of the ROM is identified as the number of bits of information it canhold. We know 2048 bytes corresponds to 16,384 bits; therefore, the device we aredescribing is actually a 16K bit or 16KB ROM.

404 Memory Devices, Circuits, and Subsystem Design Chap. 9

Control busControl bus Figure 9-3 Block diagram of a ROM.

By applying the address of a storage location to the address inputs of the ROM, thebyte of data held at the addressed location is read out onto the data lines. The block dia-gram in Fig. 9-3 shows that the data bus consists of eight lines labeled as Os through 07.Here 07 represents the MSB and Os the LSB. For instance, applying the addressAro . . Arfu : 100000000002 : 40016 will cause the byte of data held in this storagelocation to be output as O7O6O5OaO3O2OrO6.

EXAMPLE 9.I

Suppose the block diagram in Fig. 9-3many bytes of informaiion can be stored

Solution

had 15 address lines and eight data lines. Howin the ROM? What is its total storage capacity?

With 8 data lines, the number of bytes is equal to the number of locations, which is

2rs :32,768bytes

This gives a total storage of

32,768 x 8:262,l44bits

The control bus represents the control signals required to enable or disable the

ROM, PROM, or the EPROM device. The block diagram in Fig. 9-3 identifies two con-trol inputs: output enable (Og) ana chip enable (CE). For example, logic 0 at OE enablesthe three state ouq)uts, Os through 07, of the device. ff OE is switched to the 1 logiclevef , these outputs are disabled (put inthe htgh-Z state). Moreouet, CE must be at logic0 for fhe device to be active. Logic 1 at CE puts the device in a low-power standby mode.When in this state, the data outputs are in the high-Z state independent of the logic level

of OE. [n this way we see that both OE and CE must be at their active 0 logic levels for

the device to be ready for operation.

Sec. 9.2 Read-Only Memory 409

Read Operation

It is the role of the MPU and its memory interface circuitry to provide the addressand control input signals and to read the output dataat the appropriate times.during thememory-read bus cycle. The block diagram in Fig. 9-4 shows a typical read-only mem-ory interface. For a microprocessor to read a byte of data from the device, it must applya binary address to inputs Ae through A1e of the EPROM. This address gets decodedinside the device to select the storage location of the byte of data that is to be read.Remember that the microprocessor must switch CE and OE to logic 0 to enable thedevice and its outputs. Once done, the byte of data is made available at 06 through 07 andthe microprocessor can read the data over its data bus.

Standard EPROM lCs

A large number of standard EPROM ICs are available today. Figure 9-5 lists thepart numbers, bit densities, and byte capacities of nine popular devices. They range in sizefrom the l6KB density (2K X 8) 2716 device, to the 4MB (512K X 8) 27C040 device.Higherdensity devices, such as the 27C256 through 27C020, are now popular for systemdesigns. In fact, many manufacturers have already discontinued some of the olderdevices. such as the 2'716 ar'd 2732. Let us now look at some of these EPROMs in moredetail.

The 27C256 is an EPROM IC manufactured with the CMOS technology. Lookingat Fig. 9-5, we find that it is a 256I<8 device, and its storage array is organized as32K x 8 bits. Figure 9-6 shows the pin layout of the 27C256. Here we see that it has

Figure 9-4 Read-only memory interface.

Memory Devices, Circuits. and Subsystem Design Chap. 9

CS

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27162732

27C6427Cl2827C25627C51227C01027CO2027C040

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1 6 K x 83 2 K x e

1 2 8 K x 8256K x I512K x I figur€ 9-5 Stmddd EPROM

15 ad&ess inputs, labeled Ao through Ara, eight data outputs, identified as Oo through 07.and lwo control signals CE and OE.

From our earlier descriprion of the read operaiion, it appears that after the inputs ofthe EPROM arc set up, the output is available innedialely; however. in pracrice this isnot tuue. A short delay exists between ad&ess inputs and data ouQuts This leads us totlree imponant timing propefies delined for the read cycle of an EPROM: dccess rir?€(r(:d, chip enable tlne, (1.). and chip-deselect t ?e (tDF). The values of these timingproperties are provided in the read cycle switching characteristics shown in Fig. 9 7(a)and identified in the switching waveforms shown in Fig. 9-7(b).

Access timefells us llow long it takes to access dala stored in an EPROM HeI€ weassume that boih CE and OE are already at rheir active 0 levels, and then the address isapplied to the inputs of the EPROM. In this case. the deiay tAcc occurs before the datasored al rhe lddre'.ed locdlion a'e.rable dr rhe ouPu!s The microproce.sor mu{ uail alleast this long before rcading the data; otherwise, invalid results may be obtained. Figue9 7(a) shows that ihe standard EPROMS are available with a vanety of access time rat-ings. The ma{imun values of access time are given as 170 ns. 200 ns, and 250 ns Thespeed of the device is selected lo match that of the MPU. If the access iime of the fasteststan&rd device is too iong for rhe MPU, wait state circuitry needs to be added to theinterface. In this way, wait states can be inserted to slow down the memory read bus

Chip-enable time is similar to access time. In fact, for most EPROMS they are equalin value. They differ in how lhe device is set up initially. This tine the ad&ess is appliedand OE is switched to 0, ften the read operatron is initiated by ma.king CE active There-fore, tcE represents the chip-enable-to-output delay instead of the address-io-output delayLooking at Fig. 9 7(a), we see that the maxinum values of tcE are llso 170 ns, 200 ns,and 250 ns.

Chip'deselect time is the opposite of access or chip-enable time. It represents theamount of time the device takes for the data outpuls to retun to the high-Z state afier OEbecomes inactive-thal is. the recovery time of the outputs. Figure 9-7(a) shows thal lhema\imJm \alues for .hi. rining propery aJe 55 n'. 55 n'. and 60 n..

In an erased EPROM. all storage cetis hold logic 1. The device is put into the plo-grannning mode by switching on the VFp power supply. Once in this mode. the address ofthe storage location lo be Fogrammed is applied to the address inputs, and dte byte of

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data to be loaded into this location is supplied as inputs to the data leads. Nole lhat thedara oulputs acl as inputs when the EPROM is set up for Fogramming mode of opera-tion. Next the CE input is pulsed to load the dara. Actually, a complex series of prognm

and verify operations are performed to program each storage locarion in an EPROM Thetwo widely used progamming sequences arc he Quick-Pulse Prot|ranming Algorithmand the Intenigent Prcgramming Algorithn. Flowcharts for these programming algorithms are given in Figs. 9 8(a) and (b), rcspeciively.

Figure 9-9 presents another goup of import:nl electricai characteristics for the27C256 EPROM. They arc the device's dc electrical operaring characteristics CMOSEPROMS are designed to provide TTl-compatible input and output logic levels. Here wefind the output iogic level ratings are VoH.j" = 3.5 V and VoL-* = 0 45 V Also plo-

vided is the operating cunent rating of ihe device, identified as I1]c : 30 mA This showsthat if the device is operating at 5 Y it will consume 150 mW of power

Figure 9 5 also shows the pjn layouts for the 2716 through 27C512 EPROMdevices. In this diagram, we find that both the 27C256 and 27C512 are available in a28 pin package. A comparison of the pin configurarion of rhe 21C512 with that ofihe 27C256 shows that the only differences between tbe two pinouts are that pin I onthe 27C512 becomes the new address input Ars, and Vm, which was at pin 1 on the27C256, becomes a second function perforned by pin 22 on t]:.e 2'1C512.

Expanding EPROM Word Lenqth and Word Capacity

In many applications, the microcomputer system requiremenis for EPROM aregreater than what is available in a single device. Therc are two basic rcasons for expand-

414 Memory Devices, Circuits. and Subsystem Design Chap. 9

Fieure 9-E (a) Quick-PnlsPrcgEtuning Algorilhm fl owchdrEeprinted by pernission ofl elCorpontion: Cotyright Intel CorP.1989) O) Ifte igent ProsrartuninsAleoritbm flo{cbrn (Reprinted bYlemission of Intel Corpomtion;copyrigh Intel Cor?. 1989)

ing EPROM capacity: firs! the byte-wide length is not large enough; and second, the totalstorage capacty is not enough b''tes. Both of tlese expansiotr needs can be salisfied byinterconnecting a number of ICs.

For instance, the 8086 microprocessor has a l6-bit data bus. Thercforc, its progam

memory subsystem n€eds to be implemented with two 27C256 EPROMS connect€d' as

shown in Fig. 9-10(a). Nolice ihat the individual address inputs, chip enable lines, and

output enable lines on lhe two devices are comected in para]lel. On the other hand, theeigh dara outputs of each device aJe used to supply eight lines of the MPU'S 16-bit databus. This circuit configuation has a total stomge caPacity equal to 32K words or 5 12KB

Figue 9-t0O) shows how F o 27C25G can be interconnecied to exprnd ihe number ofb$es of stolage. Here the individual addrcss ilputs, data oulputs, ad output enableLines of the two devices are comected in parallel. Howev€r, the CE inpu.s of the individ-ual devices rcmain independent and can be suPPlied by diffe.ed chip enable outputs,

Sec.9.2 Readonly Memory 415

tbl

Figure 9-8 (continued)

identifiert as CS6 and CS,, of an address decoder circuir. In this way, only one of rhe twodevices is enabled at one time. This con€guration results in a totat storage capaciry of64Kbytes or 512KB. When several EPROMS arc used in an 8088-based microcomputerthey are connected in this way- To double the word capacity of fte circuir in Fig. 9 I 0(a),this same connection must be made for each of the EpROMs.

416 Memory Devices. Circuits, and Subsystem Design Chap. 9

*-d Parameter llin Typ(3) Unil Tesl Condliionr_ nplt oad cutrert 0.01 1 . 0,: Oulpulleakagscurrenl- Vpp read cutr€nt 5 200=_ vcccLirent standby TTL I 1 . 0

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' ' , f n imum O.C. inpLl vohage s 0.5V. Dur i rgra.stions, rhe inpuis may urdershool to -2,0v'.r periods ess thar 20 ns. l\,laximlm D.C. vo lage:: outpul p ns is Vcc + 0.5V wh ch may ove6h@l:c Vcc + 2V fo. per iods less lhan 20 ns.

: !oerati.g temperalure is ior conmerc al prodLcl€f.ed by lhis sp€cilicalion. Enended lemperaiLrc.ptions are avaiiable i. EXPRESS and Mililary

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5. Mal mum Aclive power usage s lhe sum lpp + lcc.The maximum curr€nlvalue is wilh oulpr'ls Oolo

6. Oulpul shortedlor no more ihan ore second. Nomore lhan ore oLtput shoded ar a rlm€. los issampled bLi nor lqpo/oiested.

7. Vpp may be one dode vohagedrcp bslowVcc,l!may be connecred directlyto vcc. Also, vcc mustbe appled s nutaneously or belore VpF andr€moved slmLllaneously or afierVpp.

8. VtL, V H levels ai -rTL inpLrs.

Figue 9-9 DC electrical chdacierisLics of ttre 27C256. (Reprinred by permi$lon of Intel Coporatioq Copyright Inrel Corp. 1989)

9.3 RANDOM ACCESS READ/XVRITE MEMORIES

The memory section of a microcomputer system is normatty formed ftom borh read-onlyi\emaies and tundon access rca.y||ntu menones GAM). Eariier we pointed out thatthe ROM is used &r store permanent informaiion such as rhe microcompurer,s hardwarecontrol prograrn. RAM is similar to ROM in thar its srorage locarion can be accessed ina random order, but it is different from ROM in rwo imDorianr ways. First. data stored in

5e.. 9.3 Random Access Read/Write Menories 417

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RAM is not permanent in nature- that is, it can be altered. RAM can be used to save daraby writing to it, and later the data can be read back for additional Focessing. Because ofits read and write features, RAM finds wide use where dara and Drosrams need ro beplaced in memoD onl, rempo|aril). I or rhi5 rea"on. r is normalll u,eJro.rore Aara anoapplication Fograms for execurion. The second difference is thar RAM is yotade tharis, if power i9 removed from RAM, rhe stored data are lost.

Static and Dynamic |?AMs

Two types of RAMS are in wide use today: the sr.rtic MM (SW\M) and bnamic8,411 (DRAM). For a static RAM, dara, once enrered. remain valid as lons as the Dower.upply i . nor rumed off On rhe oder hano. to rerajn dara in a DRAV. i r i i nor .urnc,enrjust to maintain the po\rer supply. For this type of device, we must borh keep the powersupply tumed on and periodically restore the data in each storage locarion. This addedrequircment is necessary because the storage elements in a DRAM are capacitive nodes.If the storage nodes are not recharged within a specific interval of rime, data fie lost. Thisrccharging Focess is known as r?tdrr;n8 the DRAM.

Block Diagram of a Static RAM

Figue 9 I I shows a block diagram of a ry?ical static RAM tC. By comparing thisdiagram with the one shown for a ROM in Fig. 9 3, we see rhat they are similar in manyways. For example. ihey both have address Lines, data lines, and control lines. These sig-nal buses pedorm similar fu.ctions when ihe RAM is operated. Because of rhe RAMSread/r:dte capabiliiy. dala lines, however, act as both inputs and outputs. For rhis reason,they are identified as a bidtuectional bus.

A varieiy of static RAM ICs a.re currently available. They ditrer borh in densiry andorganization. The most commonly use.d densities in sysiem designs are rhe 64KB and256KB devices. The stucture of the dara bus determines the organization of the SRAMSstonge array. Pigure 9-11 sbows an 8-bir data bus. This type of oryanization is krown asa ,]te-wd, SRAM. Deyices are also manufadured with by 1 and by 4 data I/O organi-zanons. The 64KB density resuits in three standard device organizarions: 64KX 1,16K x zl. and 8K x 8.

The address bus on the SRAM ir Fig. 9 1 1 consists of the lines tabeled Ao rhroushAr?. This 13 bit address is what is needed to select between rhe 8K individuat storagelocations in an 8K x 8 bit SRAM lC. The l6K x 4 and 64K x I devices require a 14-bit and 16 bit address, respectively.

SBAItv1

Conlrolbus

CE, OE, WE

' r/o-t/o. '

Fture9-11 Block dias@ of astatic R-AM.

S e c . 9 . 3 Random Access Read/Write Memories 419

To eirher rcad ilom or wdte to SRAM, the device must fust b€ chip enabled. Jusr likef o r a R O N ' I . L l . . . o o n e b y , $ i l c h i n g h e e F i 4 o u l o l r h e 5 R A M r o l o F i i O . f a r r i e r w e i n d r -cated that data lnes I/O0 through I/O7 in Fig. 9-11 are bidirecrionali This means thar rheyact as rnputs when writing data into the SRAM or as ou@uts wher reading data ftom rheSRAM. Tle.ening of, ne$ conuol ,igndl. rhe i dr? ?ndbl" dE, inpu.. derermines hos rhedata lines operate. During all write op€mtions to a storage localion wirhin the SRAM, rheappropdate WE inputs mus! be switched tu rhe 0 logic level. This configures the data linesar Inpur.. On $e orher hand. r'daLr dre !o be rad liom a .torage localion. \VE is lefl dl rheI logic revel. when readirg ddr? {rom lhe SRAM. ourpur endble ,OE) mu,l be ac!i\e Appl}-ing the active mernory signal. logic 0, at ihis input. enables the device's tlrc€-siare ourputs.

A Static RAL4 System

Tfuee-slate data bus lines of SRAM devices allow for rhe parallel connectionneeded to expand data memory using muitiple devices. For example, Fig. 9-12 showshow four 8K x 8-bit SRAMS are interconnected to form a 16K x 16-bir memory system.ln this cifcuit. the separate Cl ioput" of tir" SneV fcs in bant 0 are wired together andconnected to a common chip'setect input CSo. The same type of connecrion is used forthe SRAMS in bank I using chip,€elecr input CSr. These iryurs are acrivated by rhe chip,select output of the address decodef circuit and must be logic 0 to setect a bank ofSRAMS for operation. The OE inputs of rhe individual SRAMS are connecred in parallel.The conbined ourpur-endble i rpur rhaL re'ulr . i . dr i 'en bl rhe MIf f i ourpur or rne mem-ory intedace circuit and enables the oueurs of ail SRAMS during all memory-fead buscycle.. Srtru dJly. ,he \^ rire enable. ot all SRAMS are ,upptjed from \{t!T\\ ro wrire rothe selecGd bank. Note that the memory sysrem allows only word writes and reads.

Standard Static RAM ICs

Figure 9-13 lists a number of standard static RAM lcs. Here we find their parnumbers, densities, and organizations. For example, the 4361,4363, and 4364 are al64KB density devices; howevet they are each organized ditrerently. The 4361 is a 64K xI-bit device, the 4363 is a l6K x 4-bit device, and rhe 4364 is an 8K x 8-bit devic€.

The pin layouts of the 4364 and 43256A ICs ar€ given in Figs. 9-14(a) and (b), respec-tively. Looking at the 4364 we see ihar ir is almost ideniical ro the block diagam shown inFig. 9-1L The one differcnce is that it has two chip-enable lines instead of one. They arelabeled CEr and CE . Noie that logic 0 activates one, and logic 1 acrivaies the other. Both ofthese chip enable inputs must be ar their acrive logic levels ro enable rhe device for operation.

EXAMPLE 9.2

How does the 43256A SRAM ditrer from the block diagran in Fig. 9 il?

Solutionlr ha. rqo addir ional addrers inpL,c. A. l rnd Cr, . and .he chip-enable inpur is Izbeled . iinstead of CE.

420 Memory Devices, Circujts, and Subsystem Design Chap. 9

BAN( O

SRAM O8 K X 8

frE (Lov Byte)

dE

BANK OSRAM 18 K X 8

FE(nigh Btt )

dE

BANK I

WE

SRAM 28 K X 8

aE (t,w Byte)

dE

BANK I

SRAM 3_ 8 K X 8

(Eigh B)1e)rliElm

d5, 6,IGI,M

Flgur€ 9-12 16K x 16-bit SRAM circuit.

421

As Fig.9-15 shows, the 4364 is available in four speeds. For example, theminimum rcad cycle and write cycle iime for the 4364-10 is 100 ns. Figure 9-16 isa list of the 4364's dc electrical charactedstics. Note fl) shows that the 100 ns devicedraws a maximum of 45 mA when operating at maxnnurn ftequency (mininumcycle time).

SFAMDsnslty(btts) Organization

43614363436443254

43256443r000A

64K64K64K

256K256K

I l'/l

l 6 K x 4S K X S

32K x I128K x I

UO,

Iigur€ 9-13 Siandard SR4M

!o.

NC

Vo'

G N D

WE

Figure 9-r4 (a) 4364 pi! layout. (b) 432564 pin hyolt.

Memory Devices. Circuits, and Subsystem Design Chap.

5

3

1 2

2A

27

26

23

22

2 1

20

r 3

r 5

2

3

5

6

3

r 0

1 3

2A

21

25

23

22

2 1

20

1 6

1 5

422

4364.104364.124364.154344.20 Fi8ure 9-15 Speed sele.tions lbr lhe

4364 SRAM.

SRAM Read and Write Cycle Operation

Figure 9-17 ilusrrabs the waveforms for a typical wdte cycle. Let us trace theevents that taLe place dlrring the wriie cycle. Here we see lhat all critical timing is refer-enced to the point at which the ad&ess becomes valid. Note that the minimum durationof the write cycle is idertified as twc. This is the 100-ns w te cycle time of he 4364-10.The address musl remain slable for ihis complete inteflal of rime

Next, CEL and CE, become active and must rcmain active until the end of the writeclcle The durar ion or r \e\e pu\e\ are roenrihed ai Cl. , to end ol | |ntp ' in? \ \ \ t \ a1dCE2to end ofwrite tine (kwt. As the waveforrns show. we are assuming here that theybegin at any time after the occunence of the ad&ess but before the leading edge of WE.The minimum value for both of ihese times is 80 ns. On the other hand, WE is shown notto occur until the inreflal rAs elapses. This is the dd&err'r€rry tim? and rcpresents theminimum amount of time the address inputs must be stable before WE can be switchedto logic 0. For the 4364. however, this pzfarneter is equal to 0 ns. The s.idth ofthe writeenable pulse is ideniilied as twp, and its minimum value equals 60 ns.

Data appiied !o the qr{ data inputs are written into the device s)mckonous with thetrailing edge of WE. Nole that the dat2 must be valid for an inte al equal to tDw beforeftis edge. This intenal, called data valid to end of l',',r.r, has a minimum value of 40 nsfor ihe 4364-10. Moreover it is shown to renain valid for an intewal of lime equal to tDHafter ihis edge. This dara- hou nne, howercl irst llke address-senrp time, equals 0 ns forthe 4364. Finally, a short recovery period takes place after WE retums to logic 1 beforethe write cycle is complete. This intervrl is identified as twR in the waveforms, and itsminimurn value equals 5 ns.

The read cycle of a static RAM, such as the 43@1, is similar to that of a ROM.Figue 9-18 gives wavefoms of a read operation.

Standard Dynamic |?AM lcs

Dynamic RAMS are available in higher densities than staiic RAMS. Corently, themost widely used DRAMS are dre 64K-bit, 256K bit, 1M bit, and 4M-bit devices. FiSure9 19 lists a rumber of popular DRAM ICs. Herc we fitrd the 21648, organized as 64K xI bit; the 21256, oryanized as 256K X i bit;the 2146,1, organized as 64K x 4 bits;the421000. organized as lM x 1 bit; and the 424256, oqanized as 256K x 4 bits. Pin layoutsfor the 21648,27256, ar'd 421000 arc shown in Figs. 9-20(a), (b). and (c), respectively

Some other benelits of using DRAMS over SRAMS are that they cost less, consumeless power, and their 16- and 18-pin packages take up less space. For these reasons. DRAMSare nonnaly used in apptications that require a large amount of memory. For example. mostsystems that support al least lMbyte of data memory are designed using DRAMS.

sec. 9.3 Random Access Read/Write Memories 423

Llmits

Mln ryp Max t nit Test condltions

tLr

ourput lsakag6 FA Y4)=ov!o vo.

cE=VrLo roE =vHor

Opelaling suPPlY rccAlCE2=vrH

{1)

1 0cE, = vrH'lvo = o'DCcunent

mA CEl <0.2 V'cE >vcc- 0.2 v

vH>vcc-0,2v'l= 1 MHz,l /o =0

CE2 = vr(2)

(3) mA dE1 > vcc-{.2 vcE,>vcc-o2V

mA cEr< 0.2 v(3)

Ouiput vollage, Vor 0.4

high2.4

(1) fD€64no/10L:45 mA max

!P04364'1212U12LL: 40 mA max

u PD4364_ 15/151,/1sLL: 40 mAriaxpPD4364_20/2OU20LL: 35 nA max

l2r uPD4364-u:5 mAmar l3l /PD4364-u:2 mArai' ;pDa36n-ul: 3 mA hax FPO4364_xxL: 100 LA rat

; PD436+rxLL: 3 rA mar JPD4364-XXLL:50 llAmd

424

Figun 9-16 DC elatricalcbarscteri'uc' ofthe 13#

1. A wiis occu6 du ng the ov€rlap ot a bw cEr and a high CE, and a low frE2. CEaor WE lor CErl must b€ high [low] duiig any addrsss transaclion3. ll oE is high ihe l/O pins remain jn a high-impedanc€ slale.

FiguE 9-u write-cycle tining diagrm.

The 21648 is one ofthe older NMOS DRAM devices. Figure 9 21Fesents a blockdiagram of the device. Looking at the block diagram, we find that it has eight addressinputs, Ao through A?, a data input and a daia output narked D and Q, respectivety, andthree control inputs, rowaddress stmbe (RAS), column addrcss stnbe (CAS), and

The storage alray within the 21648 is capable of storing 65,536 (64K) individualbits of data. To address this many storage locations, we need a 16-bit address; however.

sec. 9.3 Random Access Read/Write Memodes 425

this device's package has just 16 pins. For this reason. the 16-bit addrcss is divided intotwo separate parts: an 8-bit r.on dddr"ss and an 8-bit col nn addrcss. T\ese two patrrs ofthe ad(lless are time-mulliplexed intp the device over a single set of address lines, Anlhrough A7. First the row address iq applied to A0 through A7. Then RAS is pulsed to logic0 to latch it into the device. Next, the column address is applied and stsobes cAS to logicO. This 16-bit address selects which one of the 64K siorage locations is to be accessed

Data are either written into or read Iiom the addressed storage location in DRAMS.W.ite data are applied io the D input and read data are output at Q. The logic levels ofcontlol signals W. RAS, and CAS tell the DRAM whether a rcad or write data transfer istaking place and control the thte-state outputs. For example, during a write operation,the logic level at D is latched into the addressed storage location at the frlling edge ofeither CAS or W. If W is switched to logic 0 by an active MWTC signal before CAS, an

.r' !s rtu ei nxdb bt

DRAI1/I (blts)

216482125621464

42100042425644100

44160416800416400416160

64K256K256K

1 M1 M4M4M4M

16M161\416M

256K x 1

256K x4

1Mx4256Kx 16

8 l M x 2

l M x l 6

Figure 9-18 Read-cycle ftning

Figur€ 9-19 Standdd DRAM

426 Memory Devices, Circuits, and subsystem Design Chap. 9

cas

o

D

w

FAS

cas-

o

N.C.

D

5

o

cas-

0

w

N.C.

FiguE 9-20 (a) 21648 ?in layout. (b) 21256 lin layout. (c) 421000 pin

427

cas

early write cycle is performed. Dunng this rype of write cycle, the outpuis are maintained

ln fte hign-Z smte it oughout the complele bus cycle The fact that the output is putir

the high-Z state dudng the wdte operation allows the D input and Q outpui of the DITAM

rc be ;ed together. The Q outpui is also in the high'Z state whenever CAS is logic 1 This

is the connection and rnode of operation nomaliy used when altaching DRAMS to the

bidirectional data bus of a microprocessor Figure 9-22 shows how 16 21648 devices are

connected to make up a 64K x 16-bii DRAM arravThe 21649 aft; has the ability to perfoin what are called page'modz accesses lf

MS is bft at logic 0 after the row address is latched inside l]le device, the address is

naintained withi; dre device. Then, by simply supPlving successive column addresses'

data cells along the selecled row a.re accessed This permits faster access of memory by

eliminating the time needed to set up and strobe additional row adikesses'

Earlier we poinled out lhat the key difference between the DRAM and SRAM is

that the storage cells in lhe DRAM need to be periodicalv refreshedi otherwise, thev lose

their data. TJmaintain the integrity of the data in a DRAM, each of the rows of the stor'

age array nust typica y be refreshed periodically, such as every 2 ms All the stomge

cells in an array are refieshed by simpiy cycling through the row addresses As long as

CAS is held at loglc 1 during the refresh cycle' no data a.re output.

Extemal cir;uitry is required to perfom the addless muhiplexing, RAS/CAS gen-

emtion, and refresh operations for a DRAM subsvstem. DuM'refresh cantnner ICs arc

available to permit easy implementation of these functions.

Battery BackuP for the |?AM Subsystem

Even though RAM ICs are volatile, in some equipment it is necessary to mal(e all

or part of the RAM memory subsystem nonvolatile (e.g , 3n electronic cash register) ln

thi; application, a power failure could rcsult in the loss of ireplaceable information about

the operation of ihe business.To satisfy the nonvolatile requirement, addltional circuitry can be included in the

RAM subsystern. These circuits must sense the occurrence of a power failure and auto-

matically switch the memory subsystem over to a backup baltery An orderly transrtion

must take place from system power to battery power' Therefore, when a loss of power is

detect€d, the power-fail circuil must pemit the completion of any read or write cycle that

Figure 9-21 Block diagrm of the21648 DRAM.

424 Ivlemory Devices. Circuits, and Subsystem Design Chap 9

429

DRAM O6.,{K X I

cAs

DRAM 1564KX I

wRl

RAS

Figur€ 9-22 gK x l6-bit DRAM circuit.

is in progress and then lock the memory against the occurrence of additional readfwrite

operaiio;. The rnenory subsystem remains in this state until power is restored- Itr thG

way, the RAM subsystem can be made ai least temporarily nonvolatile

A 9.4 PARIry THE PARITY BIT, AND PARITY-CHECKER/GENERAIOR CIRCUIT

In microcomputer systems, the data exchanges that lake place between the MPU and the

memory musi be done without error' However, problems such as noise, transient signals'

or eve; bad menory bits can produce erors in the iransfer of data and instructions For

instance, the stonge location for I bit in a large DRAM afiay mdy be bad and stlrck al

the 0 logic level. This will not present a problem if the logic level of the data wnttenlo

the storage locahon is O, but if it is 1, rhe value will always be read as 0 To improve the

rcliability of information transfer between lhe MPU and memory, a p1ri,J bit c^1&

added to each byle of dala. To implemen! alata translers'rti\h pati\y, a patity'checkerl

Sareldlor circuit is requiredFigure 9-23 shows a parity-checker/generator circuii added to the memory interface

of a microcomputer syslem. Note lhat tbe data passed between the MPU and memory

subsystem is applied in parallel to the parity-checker/generator circLlit Assuming thal the

microprocessor has an 8-bit data bus, data words read from or written to memory by the

Figure 9-23 Data-storage m€mory interface with paritv-cheker generatof,

DBAMO

OBAM!

DBAM,

DRAMs

DFAI',44

DRAt',ts

DF4I\46

DRAI\,I7

t\4PU

8.BIT 9-B]T

430 Memory Devices. Circuits, and Subsynem Design chap 9

MPU over the data bus arc sti1l byte-wide, but the data stored in memory is 9 bits long.The data in memory consists of 8 bits of data and I parity bir. Assuming rhat the memory aray is constructed with 256K x 1-bii DRAMS, then ihe memory anay for a mem-ory subsystem with parity would have nine DRAM ICs instead of eighr. The extra DRAMis needed for siomge of the parity bit for each byte of data stored in the other eightDRAM devices.

The parity-checker/generator circuit can be set up ro t)rodtce elthet even parid orodd patitJ. The 9-bir \tord of data stored in memory has even parity if it contains an evennumber of bits that are at the 1 logic level and odd pariry if the number of birs ar logic Iis odd.

Let us assume that the circuit in Fig. 9 23 is used to generate and check for evenpariqj. If the byt€ ol dara wrinen to memory over rhe MPU'S dara bus is FFH, the bimrydata is illllillr. This blre has 8 birs at logic l-that is. it atready has even parity.Thereforc, the parify checker/generaror circuit, which operates in the parity generaiemode, outputs logic 0 on the parity bit line (PB), and rhe 9 bits of dara siored in memoryis 0111111i 1r. On the other hand, if the b)1e wriften to nemory is 7FH. the binary wordare 011111112. Since only 7 bits are at logic I, parity is odd_ In this case. dre pariry-checker/generator circuit makes the parity bit logic 1, and the 9 bits of dara saved in mern-ory is 10111111ir. Notice that the data held itr memory has even pariq,. In this way, wesee that duing all data menory write cycles, the parify-checker/generator circuit simplychecks tbe data that are to be stored in memory and genenres a parity bit. The parig, biris attached to the originat 8 bils of data to make ir 9 birs. The 9 birs of dara stored in mem-ory have even parity.

The psrity checker/generator works differently when data are read from memory.Now the circuit must perform its parity check tuncrion. Note drat the 8 birs of dala fromthe addressed storage location in memory are sent directly ro the MPU. However. ar thesame time, this byte and the parity bit are applied to the inputs of the pariiy-checker/gen-erator circuit. This circuit checks to determine wherher ihere ls an even or odd number oflogic ls in the word with parity. Again we will assune that the circuit is set up to checkfor even parity. ff the 9 bits of data read from memory arc found to have an even numberof bits at the i togic level, parity is correcdhe parity-checker/genentor signals this factto the MPU by maldng the parity eror (PE) output inactive logic 1. This signal is normally sent to the MPU to identify whether or not a memory paliry e,",rr has occun€d Ifan odd number of bits are found to be logic 1. a parig' eror has been detected and PE isset to 0 to tell ihe MPU of the error condition. Once alerted to the enor. the MPU can doany one of a number of things under software control to recover. For inslance, it couldsimply repeat the memory-read cycle to see if it takes place colrectly the next time.

The ?4AS280 device implenents a parity-checker/genentor function similar to thatjusl described. Figure 9-24(a) shows a block diagam of the device. Note that it has ninedata-input lines, which are labeled A thrcugh L In the menory interface, lircs A tlrough Hare attached to data bus lines D0 through D7, respectiveu and during a read operation theparily bit outpul of the rnemory aray, DpB, is applied to the I input.

The function table in Fig. 9-24(b) describes rhe operation of the 74AS280. It showshow ihe tEvEN and toDD outputs respond to an even or odd number of data inputs at logic1 Note lhat if there are 0, 2. 4. or 8 inputs at logic I, rlre :E\rEr{ outpui switches to logicI and loDD to logic 0. This output response signals the even parity condition.

Sec. 9.4 Pariq/, The Parity BjL and Parity'Checker/Generator Circuit 431

74AS280

NUI\4BEF OF INPUTS ATHRU ITHAT AAE HIGH

OUTPUTS' EVEN ! ODD

0,2,4,6,81,3,5,7,9 L

L

(b)

Di

x1

FisuE 9-24 (a) Btock diagram of th€ 74AS280. (Texas Irstrum€ntt Incorpo-nted) (b) Fundion table. (Texas Instrum€nts IncorpoEt€d) (c) Even-larirycheckq/generator connection.

ooDrD2D3D4D5D6

BcDE 74As2go

GH

I

4t2

In practical applicaiions, the tBvEN and DD outputs are used to produce the parity bit and parity elTor signal lines. Figure 9 24(c) is an even parity-checker/generatorconnguntion. Note $at loDD is used as the parity bit (Dp, output that gets applied to thedata inpur of the parity bit DRAM in the memory array. During a write operation MEMRis 0, which mates the I input 0, and fterefore dle parity of the b),te dep€nds only on databits D0 through D?, which arc applied to the A through H inputs of the 74AS280. As longas the input at A through H has an even number of bits at logic 1 during a memory writecycle, toDD. whicb is DpB, is at logic 0 and the 9 bits of data written to memory retain aneven number of bits that arc 1, or even pariry. On rlle orhel hand. if the incoming byt€ atA through H has an odd number of bits that are logic I, IoDD switches to logic l. Thelogic 1 at DpB along with the odd number of ls in the original byte again give the 9 bitsof data stored in memory an even parity.

Let us next look at what happens in the parily-checker/generator circuit during amemory-rcad clcle for the data stomge memory subsysten. When $e MPU is rcading abyte of data ilom memory, the 74AS280 performs the parity-check operation. In responseto the MPU'S rcad request. the memory array ouFuts 9 biis of data. They are applied toinputs A though I of dre parity-checker/generator cncuir. The 74AS280 checks the par-ity and adjusts the logic levels of:EvEN and:oDD to reFesent this p3rity. ff parity is evenas expected, IEVIN, which represents the pariry enor (PE) signal, is at Iogic 1. Tbis tellsthe MPU that a valid data Eansfer is tahing place. However if the data at A tlrcugh I hasan odd number of bits at loeic 1, t€wN switches to logic 0 and inforns the MPU that aparity error has occurred.

In a 16-bit microcomputer system, such as that built with the 8086 MPU, them arenormally two 8-bit banks of DRAM lcs in the daia-storage memory array. In this case, oparity bit DRAM is added to each bank. Therefore, padty is implemented separately foreach of rhe two bytes of a data word stored in memory. This is important because the8086 can read either blaes or words of data from memory For this rason, two parit-checker/generator circuits are also requned, one lor the upper eight lines of the dala busand one for the lower eight lines. Gatiry them together combines the parity er/or outputsof ihe two circuits and lhe resulting pariry elror signal is supplied to the MPU. ln thisway, the MPU is notified of a parity enor if it occurs in an even-addressed byte data trans-fe! odd-addrcssed byte data tansfer, or in either or both bytes of a 16-bit data transfer

9.5 FLAsH MEMORY

Another memory teclnology imporiant to the study of microcomputer systems is what iskno\tn as FL4SH menory. FLASH menory devices are similar to EPROMS in maryways, but ,re differcnt in several very important ways. In fact, FLASH memories act justlite EPROMS: they are nonvolatile, are read jusr like an EPROM, and Fogram with anEPROM-like algoriftn.

The key difference between a FLASH nemory and an EPROM is that its memorycells aft erased electricaly, instead of by exposure to ultmviolet light. That is, the stomgealTay of a FLASH memory can be both electically erased and rcprogrammed with newdata. Unlike RAMS, ihey are not byte ensable and writeable. when an erase operation isperformed on a FLASH memory, either the complete memory anay or a large block ofstorage locations, notjust one byte, is erased. Moreover, the ense process is complex and

sec.9.5 FLASH Memory 433

c4n take as long as severzl seconds. This erase opetalion can be followed by a write

oieration-a progranming cycle-that ioads new data inro the storage location This

write operation alio takes a long time when compared to the write cycle times of a RAW'

iven through FLASH memories are writeable, like EPROMS thev find their widest

use in microcomputer systems for stoFge of firmware. However their limited erase/

rewdte capability enables their use in applications where data must be rewritten' lhough

not frequently. Some examples: implementation of a nonvolatile writeable iookup table'

in-systern programning for coale updates, and solid state drives An exanple of the use

of fl-e.Sff -".ory ut i tookup table is the storage of a directory of phone numbels in a

cellular phone.

Block Diagram of a FLASH Memory

Earlier we pointed out that FLASH memodes operate in a way very similar to an

EPROM. Figure t 25 shows a biock diagram of a typicat FLASH memory derice Let us

compare ttriit'toct aiagram ro that of dle RoM in Fig. 9-3 Ad&ess lines Aqr through Ar7'

clip enalte 1CE), ard output enable (CE) serve the exacl same tunction for both devices'

Th;t is, the addrcss picks the storage localion that is to be accessed. CE enables the

alevice for operation. and OE enables lhe data to ihe outputs during lead cycles . -.We a[o see thar drey differ in two wavs First, the data bus is ideniified as bidirec-

tional. because the FLASH memory can be used in an application where it is wnlten into

as well as read from. Second, another contol input, write enable (WE), is Provided This

signal must be at its aciive 0logic level during all write opemtions to the device ln fl t'

this block diagram is exactly tbe same as that given for SRAM iD Fig 9-1 I '

Bulk-Erase. Boot Block, and FlashFile FLASH Memories

Fl ASH memor) device' are availaore $i'h 'e\eral drfferenr memol anay d-rchj_

lecturec. The'e drchirecture\ relate ro ho$ the oe\ice i' organiTeo lor lhe purpo'e olera*

ing. Eadier we poinled out that when an erase operation is perfonrcd to a FLASH m€m-

of device, either all or a large block of memory storage locations are emsed The three

standard FLASH memory aray architectures. ,tll-€ ruse' boot block' a'\d FlashFile arc

,ho\rn rD Fig. a-2o. lr d bull' era'e de\ke. Ihe compere norage arra) i'arranged-" a

sinele block. Whenever an erase operation is perfomed' the conlents of all storage loca-

OE

WE

434

Figure 9-25 Block diagram of aFLA.sH nemory

and Subsynem Design ChaP. 9Memory D€vi.es, Circuits,

Figue 9_26 FLASH neElory amy dchitectures.

ttons are cleared. This is the architedure used in the desigtr of the earliest FLASH mem_ory oevrces.

, . More mod€m FLASH memory devices emptoy either tte boot block or FlashFilearcbirecmre for their memory army Tbey add granui*f,y a *. p-gr"_*rg pr*.._. N."Ioe comptete memory array does oot bave !o be eras. . mr*i, .".f,

"f ,1,. i"A.p."A.",blocks of srorac€ locarions eras€s s€paratety. Nore thal ,f," Uo"t" o,

" boo. flo"-t'a"i1""are asymmetsical is size. There is one smalt btock hown * ,n" f-, flr"t fni. U""ll,intended for stomge of the boot code for the sysrem. lwo smarl brocks ihat are ca'edparamerer blocks folow it. Their inrdded r'Ise irlor ..-e" .f **j, ;;;;;:;;;for instance, a system corfgumtion table or looKup rme. l..inally, ther€ are a number ofmuch larger blocls of memory ideutifren as tain blo&s, wh"* mJ n"".r*

""a" " "i"rJBoot btock devices are idended for us in a r"riety of "p;[";*^";;;;;smaller memory cE acity and benefit fiom the I0.'' ^ *.*" ;",-"t,-".-,-,"_-#i,fr #".TSI1"TP..:.h1T"}*'"',T;to srart up the microcomputer is held in lh€ boot bl;k p*

"i ,r," fr,CSH _";"; Wh""

E.^.I:::i "^p::.* oo. a memory_toadins prosrao rs copred from tbe boor area ol

li1 i.j ?: ffi:; ;i:HHffi"#',fi';ff5#J#'J5#"*:,1H1tror_e\LemaJ.\tomge device \uch as a drive: the firmw*. i" *tn n ioro t. rnuio fto.fiii

il:'#'.:.Tf:i [X'S; il.'.ffi;i;"'"'- '" execukd ou' or FLASH b nj'program rn advance; inste"a, ,fr"y

"." p-g--fj

sec. 9.5 F|A5H Memory 435

FlashFile architecture FLASH memory devices differ from boo! block devices in

that ihe memory aray is organized into equal-sized biocks. For this reason, it is said to

be symmetncally blocked. This type of organization is primailv used in the design of

high-dersity devices. High-density flash devices are used in applications tbat require a

large amount of code or data ro be stored (e.9 , a FLASH memory drive).

Standard Bulk-Erase FLASH Memories

Bulk-erase FLASH memories are the oldest type of FLASH devices and aft avail-

able in densities sirnllar to those of EPROMS Figure 9-27 lists the part number' bit den-

sity, and storage capacity of some of the popular devices Note that the part numbers of

FLASH devices are similar to those used for th€ EPROMS described earlier The differ-

ences are that the 7 in the EPROM part number is replaced by an 8, represeniing FLASH,

and instead of a C, which is used to identify that ihe circuilry of6e EPROM is made with

a CMOS process, an F identifies FLASH t€chnology. Remernber the 2MB EPROM was

labeled 27C020i therefore, the 2MB FLASH memory is labeled as 28F020 This device

is organized as 256K byte-wide stonge locations,Since FLASH memories are electrically erased, they do not need to be manufac-

tured in a windowed package. For this reason, and the trend toward the use of surface-

mount packaging, the most popular package fbr housing FLASH memory ICs is the plas-

tic leaded chip canier, or PLCC as it is commonly known. Figure 9-28(a) shows the

PLCC pin layout of the 28F020. All of the devices listed in Fig 9-27 are manufaclwed

in this same-size package and with compatible pin layoutsLooking at the signals identified in the pin layout, we 6nd ftat the device is exacdy

the same as the block diagram in Fig, 9-25 To select belween its 256K byte-wide stor_

age locations, it has 18 address inputs, Ao *uough Ar?, and to support byte-wide data-read

and -write transfers, it has an 8-bit dala bus, DQo through DQ?. Finally, to enable *le chip

and ils ouLputs and dininguish belween read- and write-dah Eansfer\. it has conFol lines

eE, o-E, and wE-, respeclivel). As Fig.9-281b) shows. lhe de\ice is lrvailable with rcad

access iimes ranging from 70 ns for the 28F020"?0 to I50 ns for the 28F020-150The power supply voltage and cuffent requirements depend on whether the FLASH

memory is perforining a read. erase, or write operation. During read mode of operation'

the 28FO2O is powered by 5V 1107o between the V.c 6nd V$ pins, and it draws a maxi_

mum cunent of 30 mA. On the other hand, when ei$er an €rase or .irite cycle is takingplace. l2V a5% musl also be appl ied lo rhe \ee po$er sLrpply inpul

The 28F256, 28F512, 28F010, and 28F020 employ a bulk-erase storage arrav For

$is red'on. when an era\e operalion i' peformed lo lhe derice. all byte' rn the 'torage

FLASHoenslty(bli6) (bytes)

28F25624F51228F0102AFO20

256K5l2K

1tM2M

3 2 K x 86 4 K x 8

128K ! 8256K x I Figure 9-27 Standard bulk emse

FLASH memory devices.

436 Memory Devices, circuits. and Subsystem Design chap 9

5 O 2 96 2 A7 Nzerozo 278 32-LEAD PLCC 26I 0.450 xo.sso 251O TOP VIEW 24

4 3 2 1 3 2 3 1 3 A

12 22't3 21

1 4 1 5 1 6 1 7 1 a 1 9 2 0

f f f,,e,39 t

oE'

DO?

cgjggdf

2AFA2Q 7024F020 902Am2Q 12028F020150

90 ns120 ns150 ns

ligure 9-28 (a) Pin layout of ihe28F020. (Reprinted by lermision ofInlei Coporation, Copyrighr InteiCorp. 1995) (b) Srmdtrd speedselections for the 28F020.

aray are restored to FFr6, which represents the erased siare. The merhod emDloyed toelr 'ethe28F020n ASH memor) l ( is known a. I he , , t . , (- . rau r t |o, ihn. A no;chrr lthat outlines the sequence of events that must iaLe piace ro erase a 28F020 is given jn Fig.9-29. This progranming sequence can be pedormed ejther with a FLASH memory-programning instrument or by rhe soflware of rhe rnicrcprocessor ro which the FLASHdevice js attached. Let us next look more closeiy ar holv a 28F020 is erased.

To change the contenrs of a memory array rhai is, either erase the storage alTayor write bytes ofdata into ihe array commands mnsi be wrinen ro rhe FLASH mem-ory device. Untike ar EPROM, a FLASH memory has an intemal command resister.f rpu-e c.10 l isr5 rhe c, ,mmand. rhJ can be i" \Jed ro rhe .8F020. . tore r trai Ltrerinclude a / .dd {redd memor} i . \p/ uf and t tu\c r .er rp era.e./era,er. rrd rra,e va,r , f -carton (erase verify) colnjnands. These three are used as pafi of rhe quick-erase algorithm plocess. The command regisrer can be accessed oniy $,hen +i2V is apptied ro theV," pin of the 28F020.

Figure 9 29 also inciudes a table of the bus operation and commdnd acrivitv tharLale, pld(e dunng an e a.( uperar ion ot rhe 78F02,r Fror rhe bu, oprral ion dnd com-mand columns, we see rhat as pan of the erase process. the nicroFocessor (or progran_ming insiument) must issue a ser up ems€y'erase cornmand, fo owed bv an erase ;erifvcomiran! JDJ 'hen J,eal con,Trna .o rhe FLASH de\ ice tr anc, rh, ov ctecunnsi

Sec.9.5 FLASH Memory 437

E ire memory must = 00H

Dudlon ot €rEe oped|on

R.ad byle lo v€dly eEsuF

r€gisr€r tor Ead oF€dons

Fisun 9-29 Quick-erase alsonthn ofthe 28F020. (Reprinted by permissionof Intel Cd?oration, CopFight Itrt€l CoA. 1995)

438

Bus Fhsl Bus Cycle S€cond Bus Cycle

Data

00H

Read inl€ ligeii de.iirier codes 3 90H

20H x 20H

Erase v€diy EA AOH EVD

Sllup program/prc9am X 40H PD

c0H

Figure 9-30 28F020 coMd denritions. (Reprinled by permission of IntelCorporation. Colyright Intel Corp. 1995)

FLASH memory programming control program that causes the write of rhe command tothe FLASH memory device at the appropdate rime. Adually, atl storage locations in thememory array must always be prograrnmed with 0016 before initiating the erase process.

Figure 9-29 shows that two consecurive set up erase/erase conmands are used inthe quick erase sequeDce. The fiIsr one prepares the 28F020 ro be erased, and the secondinitiates the erase plocess. Figure 9 30 shows that this sequence is identified as two writecycles. During both of these bus cycles. a value of data equal to 2016 is wriften io anyaddress in the ad&ess range of dre FLASH device being erased. Once these commandshave been issued, a siate-machine within the device auiomatically initiates and directs rheerase Focess dmugh completion.

The next step in lhe quick erase process is to determine whether or nor rhe devicehas erased completely. This is done with the erase verify command. Figure 9 30 showsthat this operation requires a write cycle followed by a read cycle. During the write cycle.the data bus canies the emse veriry cornlnand, A.016, and rhe ad&ess bus ca.ries theaddress of the storage location that is to be tested, EA. The read cycle that follows is usedto transfbr the data from the storage location conesponding to EA to the MPU. This darais identified as EVD in Fig. 9-30. The flowchan sbows thar ihe MPU musr verify thafthevalue of data read out of FLASH is FFr6. This erase veriry sep is repeated for every stor-age localion in the 28F020. If any storage location does not verify ensure by rcadingback FFr6, the complete erase process is immediately repeated.

After complete erasure has been verified, the softwa.e must issue a read conmandto the device. Fiom Fig. 9 30, we find that it requires a single write bus cycle and isaccompanied by any address that coresponds to the FLASH device being erased and acommand data value of 0016. lssuing this command puts the device into ihe read modeand readies it for read operation. Figure 9 31 outlines the quick-puke prcBnmming algo-r'ttt,, of the 28F020. This Focess is similar to that jusr described for erasing devices!however it uses rhe rer Lp and pragrum (set lp pro9tedtlpro$am\. program wrilication(program verili), and read (read nemory) commands.

sec.9.5 F|/SH Memory 431'

Dala = coH; slops progGm

egisler lor Gad op€Btons

FiguE 9-31 Quick puls progl:]lming aleo.i$m of the 28F020 (Reprintedby pemission of lrtel Cortomdon, Copyrigbt ldrel Cor?. I 995)

Standard Boot Block FLASH Memories

Ea ier we pointed out that boot block FLASH memories are designed for use in

embedded microprocessor apptication. These newer devices are arailable in higher densi

ties than bulk erase devices. Fie. 9-32 shows the pir lalouts for three compatible stan

dad densities: the 2MB, 4MB, dd 8MB devices. Notice that ihe conesponding devices

are jdentifi€d with lne part nunbe.s 28F002. 28F004, and 28F008. respectivelv These

devices have different densities but have a colnmon set of operating features and capabil-

ities. The pinout information given is for a 40-pin rrin sMll outline packaqe (:TSOP)

440 Memory Devices, circujts. and subsystem Design chap. 9

4039JO

37363534

32o l

302S2827zoz52423

21

2 \ J

45o

789

1 01 11 21 31 4t (

t o1 71 81 920

A t oArsAr+ArsAtzArrAsAs

|/vE#RP#

28F008

TA;;ll A r s l

tftll A r z ll A r r ll A s ll A e llwE# |I R P # |l v p p llwP# |

Irltftlt & ll A " ll n l llA ; l

28F008

tr;-lI G N D Itla. I| (119 |

I A:ro Il D o z ll D o o ll D Q s ll D o o ll v c c Il v c c Il N c Il D a s ll D a z ll D a r Il D o o ll o E # lI G N D Il c E # ll A o I290530-3

28FOO2

tr;lI G N D It N c Il N c Il A r o Il D a z ll D a o ll D a s ll D o o ll v c c Il v c c Il N c Il D a s ll D a z ll D o r Il D o o ll o E # lI G N D Il c E # llA ' I

AttGNDNCNCAroDQzDQoDQsDQ+VccVccNCDQsDQzDQrPaooE#GND

Ao

Figure 9-32 Pin-layout comparison ofthe TSOP 28F002, ZdFOO+, a"O28F008 ICs.

These devices offer a number of new architectural features when compared to the

bulk-erase devices just described. One of the most important of these new features is what

is known as Smartvoltage. This capability enables the device to be programmed with

either a 5-V or 12-V value ofvpp. In fact, the device can be installed into a circuit using

either value of Vpp. This is because the device has the ability to automatically detect and

adjust its programming operation to the value of the programming supply voltage in use.

These devices afe available with either of two read voltage, V"" supply ratings: Smart 5,

which opetates off a 5Y Y"", and Smart 3, which operates off a 3V Vc..A second important difference is that devices are available at each of these three

densities that can be organized with either an S-bit or 16-bit bus. A block diagram of sucha device is shown in Fig. 9-33(a). This device is identified as a 28F004/28F400. The28F004 device is available in the 40-pin TSOP package and only operates in the S-bit databus mode. The 28F400 device has 16 data lines, Ds through D15, and can be configuredto operate with either an S-bit or 16-bit data bus. This is done with the BYTE input. Logic0 at BYTE selects byte-wide mode of operation and logic 1 chooses word-wide operation.To permit the extra data lines, the 28F400 is housed in a 56-lead TSOP.

Remember that the storage array of a boot block device is arranged as multipleasymmetrically sized, independently erasable blocks. In fact, the 28F004 has onel6Kbyte boot block, two 8Kbyte parameter blocks, three 128Kbyte main blocks, and afourth main block that is only 96Kbytes. Two different organizations of these blocks areavailable, as shown in Fig. 9-33(b). The configuration on the left is known as the top boot(T), and that on the right is known as the bottom boot {B). Note that they differ in howthe blocks are assigned to the address space. That is, the T version has the 16l(byte bootblock at the top of the address space (highest address), followed by the parameter blocks,and then the main blocks. The address space of the B version is a mirror image; therefore,the l6Kbyte boot block starts at the bottom of the address space (lowest address).

Another new feature introduced with the boot block architecture is that of a hard-ware-lockable block. In the 28F004/28F400. the l6Kbvte boot block section can be

Sec. 9.5 FLASH Memorv 441

c-oEweWP

ne 1r+OO ontyl

(F400 only)

20000H1 FFFFH

BYTE

(a)

TFFFFH

7C000HTBFFFH74000H79FFFH78000H77FFFH

60000Hcr TFrn

40000H3FFFFH

TFFFFH

60000H5FFFFH

40000H3FFFFH

08000HOTFFFH06000H05FFFH04000HOSFFFH

00000H

20000H1 FFFFH

00000H

Note:Address = A[18:0]

Figure 9-33 (a) Block diagram of the 28F004128F400. (Reprinted by permis-sion of Intel Corporation, Copyright Intel Corp. 1995) (b) Top and Bottom bootblock organization of the 28F004. (Reprinted by permission of Intel Corpora-tion, Copyright Intel Corp. 1995)

locked. If external hardware applies logic 0 to the write protect 1Wt) input, the boot

block is locked. Any attempt to erase or program this block when it is locked results in

an error condition. Therefore, we say that the boot block is write protected. It an in-systemprogramming application, the boot block part of the storiile anay typically would con-tain the part of the microcomputer program (boot program) that is used to load the sys-tem software into FLASH memory. For this reason, it would be locked and shouldremain that way.

Looking at Fig. 9-\(a), die find one more new input on the 28F004128F400, thereset/deep power-down (RP) input. This input must be at logic 1 to enable normal read,

(b)

28FOO4/400

16K-byte Boot block

8K-byte Parameter block

8K-byte Parameter block

96K-bvte Main block

128K-byte Main block

128K-byte Main block

128K-byte Main block

28F004-T

128K-byte Main block

128K-byte Main block

128K-byte Main block

96K-byte Main block

8K-byte Parameter block

8K-bvte Parameter block

16K-byte Boot block

28F004-B

442 Memory Devices, Circuits, and Subsystem Design Chap. 9

erase, and program operations. During read operations, the device can draw as much as

60 mA of current. If the device is not in use, it can be put into the deep power-down mode

to conserve power. Tp do this, external circuitry must switch RP to logic 0. In this mode,

it draws just 0.2 pA.The last difference we will describe is that Ihe 28F004128F400 is equipped with

what is known as aatomatic erase and write. No longer do we need to implement the

complex quick-erase and quick-pulse programming algorithms in software as done for the

28F02O.Instead, the 28F004/28F400 uses a command user interface (CUD, status regis-

ter and write-state machine to initiate an internally implemented and highly automated

method of erasing and programming the blocks of the storage €uray.Let us now look briefly at how an erase operation is performed. The command bus

definitions of the 28F004128F400 are shown in Fig. 9-34(a), the bit definitions of its sta-

tus register are given in Fig. 9-34(b), and its erase cycle flowchart in Fig. 9-34(c). Here

we see that all that needs to be done to initiate an erase operation is to write to the device

a command bus definition that includes an erase setup command and an erase confirm

command. These commands contain an address that identifies the block to be erased. In

response to these commands, the write state machine drives a sequence that automaticallyprograms all of the bits in this block to logic 0, verifies that they have been programmed,

erases all of the bits in the block, and then verifies that each bit in the block has been

erased. While it is performing this process, the write state machine status bit (WSMS) of

the status register is reset to 0 to say that the device is busy. The microcomputer's soft-

ware can simply poll this bit to see if it is still busy. When WSMS is read as logic 1(ready), the erase operation is complete and all the bits in the erased block are at the 1

logic level. In this way, we see that the new programming software only has to initiate the

automatic erase process and then poll the status register to determine when the erase oper-

ation is finished.

Standard FlASHFile FLASH Memories

The highest-density FLASH memories available today are those designed with the

FLASHFiIe architecture. As pointed out earlier, they use a symmetrically sized, indepen-

dently erasable organization for blocking of their storage array. Two popular devices, the

8MB 28F008S5 and the 16MB 28F016SA/SY are intended for use in large-code storage

applications and to implement solid-state mass-storage devices such as the FLASH card

and FLASH drive.A block diagram of the 28F016SA/SV FLASHFiIe memory device is shown in

Fig. 9-35(a) and its pin layout for a shrink small outline package (SSOP) is given in

Fig. 9-35(b). Comparing this device to the 28F004/28F400 in Fig. 9-33(a), we find

many similarities. For instance, both devices have an address bus, data bus, and control

signals OE, WE, WP, RP, and BYTE, and they serve similar functions relative to device

operation. One difference is that there are now two chip-enable inputs, labeled CEs and

CE1, instead of just one. Both of these inputs must be at logic 0 to enable the device for

operation.Another chaage found on the 28F016SA/SV is the addition of the ready/busy

(RY/BY) output. This output has been provided to further reduce the software overhead

Sec. 9.5 FIASH Memory 443

Command NotesFirst Bus Cycle Second Bus Cycle

Oper Addr Data Oper Addr Data

Read array 8 Write X FFH

Intelligent identif ier 1 Write X 90H Read IA ilD

Read status register 2,4 Write X 70H Read X SRD

Clear status register Write X 50H

Word/byte write Write WA 40H Write WA WD

Alternate word/byte write 6 ,7 Write WA 1 0 H Write WA WD

Block erase/confirm o , I Write BA 20H Write BA DOH

Erase suspend/resume Write X BOH Write X DOH

AddressBA = Block AddresslA = ldentifier AddressWA = Write AddressX = Don't Care

Notes.'1. Bus operations are defined in Tables 4 and 5.2. lA = ldentifier Address: A0 = 0 for manufacturer code, A0 = 1 for device code.3. SRD-Data read from Status Register.4. llD = Intelligent ldentifier Data. Following the Intelligent ldentifier command, two Read

operations access manufacturer and device codes.5. BA = Address within the block being erased.6. WA = Address to be written. WD = Data to be written at location WD.7. Either 40H or 10H commands is valid.8. When writing commands to the device, the upper data bus [DQ6-DQ1s] = X (28F400 only)

which is either Vls or V1s, to minimize current draw.(a)

Figure 9-34 (a) 28F004 command bus definitions. (Reprinted by permissionof Intel corporation, copyright Intel corp. 1995) (b) Status register bit defini-tions. (Reprinted by permission of Intel Corporation, Copyright Intel Corp'1995) (c) Erase operation flowchart and bus activity. (Reprinted by permissionof Intel Corporation, Copyright Intel Corp. 1995)

on the MPU during the erase and programming processes. When this output is 0, it sig-

nals that the on-chip write-state machine of the FLASH memory is busy performing an

operation. Logic 1 means that it is ready to start a new operation. For the boot block

devices we introduced earlier, the busy condition had to be determined through software

by polling the WSMS bit of the status register. One approach for the 28F016SA/SV is that

software could poll RY/BYas an input waiting for the FLASH device to be ready. On the

other hand, this signal could be used as an intemrpt input to the MPU. In this way' no

software and MPU overhead is needed to recognize when the FLASH memory is ready

to perform another operation. This is the default mode ofoperation and is known as level

mode.

DataSRD = Status Register DatallD = ldentifier DataWD = Write Data

444 Memory Devices. Circuits, and Subsystem Design Chap. 9

WSMS ESS ES DWS VPPS R R R

Notes:

SR.7 = WRITE STATE MACHINE STATUS Write State Machine bit must first be checked to

(WSMS) determine ByteMord program or Block Erase

1 = Ready completion before the Program or Erase Status bits are

0 = Busy checked for success.

SR.6 = ERASE-SUSPEND STATUS (ESS) When Erase Suspend is issued, WSM halts execution

1 = Erase Suspended and sets both WSMS and ESS bits to "1 ." ESS bit

0 = Erase in Progressioompleted remains set to "1" until an Erase Resume command isissued.

SR.s = ERASE STATUS When this bit is set to "1 ," WSM has applied the

1 = Error in Block Erasure maximum number of erase pulses to the blgck and is still

0 = Successful Block Erase unable to successfully verify block erasure.

SR.4 = pROGRAM STATUS When this bit is set to "1 ," WSM has attempted but failed

1 = Error in ByteMord Program to program a byte or word.0 = Successful ByteMord Program

SR.3 = Vpp STATUS The Vpp Status bit, unlike an A'/D converter, does not

1 = Vpp Low Detect, Operation Abort provide continuous indication of Vpp level. The WSM

0 = Vpp OK interrogates Vpp level only after the Byte Write or Erasecommand seouences have been entered, and informs

ffi'it",f, Ji:rui:':lt,ff '"J#$'"""tl.li:"'.'J"*bewteen Vpp;6 and Vpp6.

SR.2-SR.O = RESERVED FOR FUTURE These bits are reserved for future use and should beENHANCEMENTS masked out when polling the Status Register.

(b)

Figure9-34 (continued)

The function of the RY/BY output can be configured for a number of different

modes of operation under software control. Writing a device configuration code to the

28F016SA/SV does this. For instance, it can be set to produce a pulse on write or a pulse

on erase or even be disabled.The last signal line in the block diagram that is new is the 3/5 input. Note that this

input is implemented only on the 28F016SA IC. Logic 1 at this input selects 3.3V oper-

ation for V"", and logic 0 indicates that a 5V supply is in use. Since the 28F016SV is a

SmartVoltage device, this input is not needed.Figure 9-35(c) illustrates the blocking of the 28F016SA/SV configured for byte-

wide mode of operation. Here we find that the 16MB address space is partitioned into 32

independent 64K byte blocks. Note that block 0 is in the address range from 00000016

through 00FFFF16 and block 31 corresponds to the range 1F000016 through 1FFFFF16. If

Sec. 9.5 FLASH Memory 445

Start

Write 20Hblock address

Write DOH andblock address

Readregr

stalusster l-

\-,k Yes

1

Full statuscheck if desired

Block erasecomplete

BusOperation

Command Comments

Write Erase setup Data = 20HAddr = Within block to be erased

Write Eraseconfirm

Data = DoHAddr = Within block to be erased

Read Status register datatoggle CE# or OE#to update status register

Standby Check SR.71 = WSM ready0 = WSM busy

Repeat for subsequent block erasures.Full Status Check can be done a{ter each block erase,

or after a sequence of block erasures.Write FFH after the last ooeration to reset device to read

arrav mooe.

Suspend EraseLOOp

(c)

Figure9-34 (continued)

the device is strapped for word-mode operation with logic I at the BYTE input, there arestill 32 blocks, but they are now 32K words in size.

Just as for the 28F004128F400, the 28F016SA/SV supporrs block locking. How-ever, in these devices, the 32 blocks are independently programmable as locked orunlocked. In fact, there is a separate block status register for each of the 32 blocks. Thisblock status register contains both control and status bits related to a corresponding block.The block-lock status (BLS) bit, bit 6 in this register, is an example of a control bit. Whenit is set to logic 1 under software control, the corresponding block is configured asunlocked and write and erase operations is permitted. Changing it to logic 0 locks theblock so that it cannot be written into or erased. BitT,block status (BS), is an exampleof a status bit that can be read by the MPU. Logic 1 in this bit means that the block isready, and logic 0 signals that it is busy. When the write-protect (WP) input is active(logic 0), write and erase operations are not permitted to those blocks marked as lockedwith an 0 in the BLS bit in their corresponding block status register.

Finally, the internal algorithms and hardware of the 28F016SA/SV have beenexpanded to improve programming performance. For instance, two 256-byte (128-word)write buffers have been added into the architecture to enable paged data writes. Moreover,the programming algorithm has been enhalced to support queuing of commands andoverlapping of erase and write operations. Therefore, additional commands can be sent toa device while it is still executing a prior command. They are held in the queue untilprocessed. The overlapping write/erase capability enables the devices to erase one blockwhile writing data to another. All these features result in easier and faster programmingfor the 28F016SA/SV.

446 Memory Devices, Circuits, and Subsystem Design Chap. 9

. iFFFFF

1 F0000lEFFFF1 E0000lDFFFF1 D0000lCFFFF'tco000

180000lAFFFF1400001gFFFF't90000l8FFFF18000017FFFFr7000016FFFF1 6000015FFFF15000014FFFF14000013FFFF'13000012FFFF12000011FFFF110000lOFFFF100000

OFFFFF0F0000

0E0000ODFFFF0D0000

0c0000OBFFFF080000OAFFFF0A0000OgFFFF090000OSFFFF080000

07000006FFFF060000

050000O4FFFF040000O3FFFF03000002FFFF020000OlFFFF010000OOFFFF

RIP*A 1 lA t 0A9A1MA3

A5A6A7GNDA8

DQ9DOIDQ8DO0AOBYTE*NCNCDQ2DQ.1ODQ3DQ11GND

(a)

cE0#412A 1 34 1 4A 1 5

3y5*c E l #

NC4204.19A 1 8A174 1 6

GNDDQ6

DOl4DO7

DOl5RY/BY#

oE#WE*

DQ13DO5

DQ12DQ4

RP 3/5 (SA only)

Figure 9-35 (a) Block diagram of the 28F016SA/SV FlashFile memory. @) Pin layout.(Reprinted by permission of Intel Corporation, Copyright Intel Corp. 1995) (c) Byte-widemode memory map. (Reprinted by permission of Intel Corporation, Copyright Intel Corp.199s)

(c)(b)

28FO16SA/SV

BYTE

64K-byte block 31

64K-byte block 3p64K-byte block 29

64K-byte block 28

64K-byte block 27

64K-byte block 26

64K-byte block 25

64K-byte block 24

64K-byte block 23

64K-byte block 2264K-byte block 21

64K-byte block 2064K-byte block 19

64K-byte block 18

64K-byte block 17

64K-byte block 16

64K-byte block 15

64K-byte block 14

64K-byte block 13

64K-byte block 12

64K-byte block 11

64K-byte block 10

64K-byte block 9

64K-byte block 8

64K-byte block 7

64K-byte block 6

64K.byte block 5

64K-byte block 4

64K-byte block 3

64K-byte block 2

64K-byte block 1

64K-byte block 0

&1SV

cE0*4124 1 34 1 44 1 5&

cE i"#NC

4204 1 9A 1 8A1?4 1 6

SltD:06

lQr 4DO7

to155T BYJ

oE*d€s

fo13rc5

:o12I,l

54

5 1

494847464544434241403938

34

313029

2 t I3 v4

7891 0t l

1 41 51 61 71 81 9202 1

24

26

2A

DT28FO16SA56-Lead SSOPStandard pinout

1 .8mm x 16mm x 23.7mmTop view

{,47

A 9.6 WAIT-STATE CIRCUITRY

Depending on the access time of the memory devices used and the clock rate of the MPU,a number of wait states may need to be inserted into external memory read and writeoperations. In our study of 8088/8086 bus cycles in Chapter 8, we found that the memorysubsystem signals the MPU whether or not wait states are needed in a bus cycle with thelogic level applied to its READY input.

The circuit that implements this function for a microcomputer system is known asa wait-state generator Figure 9-36(a) shows a block diagram of this type of circuit. Notethat the circuit has six inputs and just one output. The two inputs located at the top of thecircuit, CSs and CS1, are outputs of the memory chip-select logic. They could represent

-qc-St

MRDCMWTE

RESET

CLK

csocsr

MRDCnawr,e

Data input

(b)

Figure 9-36 (a) Wait-state generator circuit block diagram. (b) Typical wait-state generator circuit.

(a)

Wait-stategenerator

D P RrrY

CLKDFF

D+ypeflip-flop

448 Memory Devices, Circuits, and Subsystem Design Chap. 9

the chip selects for the program storage and data-storage memory subsystems, respec-

tively, and tell the circuit whether or not these parts of the memory subsystem are being

accessed. The two middlg inputs are the memory read command (MRDC) and memory

write command (MWTC) outputs of the bus controller. They indicate that a read or write

operation is taking place to the memory subsystem. The last two inputs are the system

reset (RESET) signal and system clock (cLK) signals. The output is \pADY.The circuit in Fig. 9-36(b) can be used to implement a wait-state generator for an

8088/8086-based ryicrocomputer system. To design this cireuit, we must select the appro-

priate D-type flip-flop, shift register, and gates.

Let us look briefly at how this wait-state generator circuit works. The READY out-

put is returned directly to the READY input of the MPU. Logic 1 at this output tells the

MPU that the current read/write operation is to be completed. Logic 0 means that the

memory bus cycle mlst be extended by inserting wait states.

Whenever an external memory bus cycle is initiatedJhe D-type flip-flop is used to

start the wait-state generation circuit. Before either CSo, CS1, or RESET becomes active,

the Q output of the flip-nop is held at logic 1 and signals that wait states are not neeqed.

The Q output, logic 0, is applied to the CLR input of the shift register. Logic 0 at CLR

holds it in the reset state and holds outputs 0 through 7 9ll at logic 0'

Whenever a read or write operation takes place to a storage location in the exter-

nal memory's address range, a logic 0 is produced at either CSe or CS1 and a logic 0 is

produced at either MRDC or MWTC. The active chip-select input makes the D input of

in" nip-nop logic 1 and the ffansition to logic 0 by the read/write command signal

causes the flip-flop to set. This makes the Q output switch to logic 1 and Q to logic 0.

Now READY tells the MPU to start inserting wait states into the current memory bus

cycle. The Q output makes both'ihe CI-n and data input of the shift register logic 1.

Therefore, it is released and the logic 1 at the data input shifts up through the register

synchronous with clock pulses from the MPU's system clock. When the select wait-state

output becomes logic 1, it makes the RS input of the ffip-flop active, thereby resetting the

Q output to logic 0 and Q to logic 1. Thus, the READY output returns to logic 1 and ter-

minates the insertion of wait states, and the MPU completes the bus cycle.'The number

of wait states inserted depends on how many clock periods READY remains at logic 0.

Simply attaching the select #ait-state line to a different output of the shift register can

change this. For instance, the connection shown in Fig. 9-36(b) represents operatron

with two wait states.

A 9.7 8088/8086 MICROCOMPUTER SYSTEMMEMORY CIRCUITRY

In Chapter 8 we introduced the bus cycles, hardware organization of the memory address

space, and memory interface circuits of the 8088/8086-based microcomputer system' The

earlier sections of this chapter covered the types of memory devices used in the memory

subsystem. Here we will show how the memory interface circuits and memory subsystem

are interconnected in a simple microcomputer system, shown in Fig. 9-37(a). We will use

the informatiqn we have acquired to analyze the memory circuits of this microcomputer

system.

Sec. 9.7 8088/8086 Microcomputer System Memory Circuitry 449

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Program Storage Memory

Earlier we found that program storage memory is used to store fixed information

such as instructions of the program or tables of data. This part of the microcomputer's

memory subsystem is typically implemented with nonvolatile memory devices, such as

the ROM, PROM, EPROM, or FLASH memory. EPROM devices, such as the 2716,

2764, and 27C256, are organized with a byte-wide output; therefore, a single device is

required to supply the 8-bit data bus of the 8088. They need to be arranged to provide a

word-wide output when used in an 8086 system.Figure 9-37(a) shows how a2716 is connected to the demultiplexed system bus of

a minimum-mode 8088-based microcomputer. This device supplies 2Kbytes of program

storage memory. To select one of the2K storage locations within the 2'716, ll bits of

address are applied to address inputs As through 416 of the EPROM. If 46 through 416 of

the 8088's address bus supply these inputs, the address range colresponding to program

memory is from

AroAs. .Ao : 000000000002 : 0000016

to

A toAq ' 'Ao : 111111111112 : 007FF16

assuming that A,e. . Atr : 0. .0 generates the chip select signal CS*. Data outputs

De through D7 of the EPROM are applied to data bus lines D6 through D7, respectively,

of the 8088's system data bus. Data held at the addressed storage location are enabled

onto the data bus by the control signal MEMR (memory read), which is applied to the OE

(output enable) input of the EPROM.In most applications, attaching several EPROM devices to the system bus expands

the capacity of program storage memory. In this case, high-order bits of the 8088's

address are decoded to produce chip-select signals. For instance, two address bits, A11 and

A12, cor be decoded to provide four chip-select signals. Each of these 'chip-selects

is

applied to the CE (chip-enable) input of one EPROM. When an address is on the bus, just

one of the outputs of the decoder becomes active and enables the corresponding EPROM

for operation. By using fow 27I6s, the program storage memory is increased to 8Kbytes.

Now that we have explained how EPROMs are attached to the 8088's system bus, let

us trace through the operation of the circuit for a bus cycle in which a byte of code is

fetched from program storage memory. During an instruction acquisition bus cycle, the

instruction fetch sequence of the 8088 causes the instruction to be read from memory byte

by byte. The values in CS and IP are combined within the 8088 to give the address of a

storage location in the address range of the program storage memory. This address is out-

put on 46 through A1e and latched into the address latches synehronously with the signal

ALE. Bits A6 through 416 of the system address bus are applied to the address inputs of

the 2716. This part of the address selects the byte of code to be output. When the 8088

r.ryrrch"r RD to logic 0 and IO/M to logic 0, the control signal generation circuit switches

MEMR to logic 0. Logic 0 at MEMR enables the outputs of the 2716 and the byte of data

at the addressed storage location is output onto system data bus lines Ds tbrough D7. Early

Sec. 9.7 8088/8086 Microcomputer System Memory Circuitry 45i'

in the read bus cycle, the 8088 switches DTIR to logic 0 to signal the bus transceiver thatdata are to be input to the microprocessor, and later in the bus cycle DEN is switched tologic 0 to enable the transceiver for operation. Now the byte of data is passed from the sys-tem data bus onto the multiplexed address/data bus from which it is read by the MPU.

The circuit in Fig. 9-37(b) shows a similar circuit for a minimum-mode 8086microcomputer system. Note that because of the 16-bit data bus, two octal transceiversand two EPROMs are required.

Figure 9-3'1(c) shows the program storage memory implementation for a maximum-mode 8088 microcomputer system. Let us look at how this circuit differs from theminimum-mode circuit of Fig. 9-3'7(a). The key difference in this circuit is that the 8288bus controller is used to produce the control signals folthe memory interface. Rememberthat in maximum mode the code output on status lines 56 through 52 identifies the type ofbus cycle that is in progress. During all read operations_of program memory the 8088outputs the instruction fetch memory bus status code, S2S1Sg : 101, to the 8288. Inresponse to this input, the bus controller produces the memory read command (MRDC)output, which is used as the OE input of the 2716 EPROM and enables it for data output.

In the maximum-mode circuit, the 8288, rather than the 8088, produces the controlsignals for the address latches and data bus transceiver. Notice that three address latchesare again used, but this time the ALE output of the 8288 is used to strobe the memoryaddress into these latches. ALE is applied to the STB inputs of all three latch devices inparallel. The direction of data transfer through the data bus transceiver is set by the DT/Routput of the bus controller and the DEN output is used to generate the OE input of thetransceiver. Since DEN, not DEN, is produced by the 8288, an inverter is constructedfrom the NAND gate that drives OE of the transceiver.

Data Storage Memory

Information that frequently changes is stored in the data storage part of the micro-computer's memory subsystem (e.g., application programs and data). This part of thememory subsystem is normally implemented with random access read/write memory(RAM). If the amount of memory required in the microcomputer is small, for instance,less than 32Kbytes, the memory subsystem will usually be designed with static RAMs.On the other hand, systems that require alarger amount of data storage memory normallyuse dynamic RAMs (DRAMs), which provide larger storage capacity in the same sizepackage. DRAMs require refresh support circuits. This additional circuitry is not war-ranted if storage requirements are small.

A lKbyte random access read/write memory is also supplied in the minimum-mode8088-based microcomputer circuit in Fig. 9-37(a). This part of the memory subsystem isimplemented with two 2742 static RAM ICs. Each2142 contains 1K,4-bit storage loca-tions; therefore, they both supply storage forjust 4 bits of the byte. The storage locationto be accessed is selected by a 10-bit address, which is applied to both RAMs in parallelover address lines ̂ 46 through Ae. Data are read from or written into the selected storagelocation over data bus lines D6 through D7. Of course, through software, the 8088 canread data from memory either as bytes, words, or double words. The logic level ofMEMV/ (memory write), which is applied to the write enable 1Wn; input of both RAMs

454 Memory Devices, Circuits, and Subsystem Design Chap. 9

in parallel, signals whether a read or write bus cycle is in progress. MEMR is appliedto the OD (output disable) input of both RAMs in parallel. When a write cycle is inprogress, RD is at logic 1, which disables the outputs of the RAMs. Now the data linesact as inputs.

Just as for program storage memory, simply attaching additional banks of staticRAMs to the system bus can expand data storage memory. Once again, high-orderaddress bits can be decoded to produce chip-select signals. Each chip-select output isapplied to the chip-enable input of both RAMs in a bank and, when active, enables thatbank of RAMs for operation.

Let us assume that the value of a byte-wide data operand is to be updated in mem-ory. In this case, the 8088 must perform a write bus cycle to the address of the operand'sstorage location. First, the address of the operand is formed and output on the multiplexedaddress/data bus. When the address is stable, a pulse at ALE is used to latch it into theaddress latches. Bits As through Ae of the system address bus are applied to the addressinputs of the 2742s. This part of the address selects the storage location into which thebyte of data is to be written. Next the 8088 switches DT/R to logic I to signal the octaltransceivers that data are to be output to memory. Later in the bus cycle, DEN is switched

Figure 9-38 (a) Devices to be usedin the system design of Example 9.3(p. 458). (b) Memory map of thesystem to be designed. (c) Memoryorganization for the system design.(d) Address range analysis folhe .design of chip select signals CSo, CS1,

CS2, and CS:. (e) Chip-select logic.

SRAM

Ao-Ars

OE

WE

u E 1

wc2

EPROM

Sec .9 .7 8088/8086 Microcomputer System Memory Circuitry 455

oooool6

99lllr-u-0400016

07FFF16

F800016

i9|ffr'-Fooool6

FFFFFl6

32K ByteSRAM

32K ByteEPROM

(b)

SRAM1, SRAM2

SRAM3, SRAM4

EPROMl

EPROM2

(b) Figure 9-38 (continued)

to logic 0 to enable the data bus transceiver for operation. Now the byte of data is outputon the multiplexed address/data bus and passed through the tran'sceiver to the system databus and data inputs of the RAMs. Finally, the byte of data is written into the addressedstorage location synchronously with the occurrence of the MEMW control signal.

The data storage memory circuitry of a minimum-mode 8086 system is also shownin Fig. 9-3'7(b). Here we see that two banks of RAM ICs are required.

Figure 9-37(c) shows the data storage memory circuit of a maximum-mode 8088microcomputer. Similar to our description of the program storage memory part of this cir-cuit, the difference between the maximum-mode and minimum-mode data storage mem-ory circuits lies in the fact that the 8288 bus controller produces the control signals for thememory and bus interface logic devices. When the 8088 is accessing data storage mem-ory it outputs either the read memory (101) or write memory (110) bus status code. Thesecodes are decoded by the 8288 to produce appropriate memory control signals. Forinstance, the status code 110 (write memory) causes the memory write command(MWTC) and advanced memory write command (ry) outputs to become active dur-ing all write bus cycles. Figure 9-37(c) sholr/qlhat MWTC or MEMW is used to drive theWE input of the 2142 SRAMs. When MWTC is at its active 0 logic level, the input

456 Memory Devices, Circuits, and Subsystem Design Chap. 9

Ao-Ars

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Figure9-38 (continued)457

A t s . " " " " " " " " ' A o

0000016 = 0000 0000 0000 0000 0000

0 3 F F F , 6 = 0 0 0 0 0 q 1 1 l l l l l l l l l l l l'" ._eso

0400016 = 0000 0100 0000 0000 0000

0 7 F F F , ^ = O 0 0 Q 0 l , l l l l l l l l l l l l l l' - -cSr

F8000r6 = 1111 1000 0000 0000 0000

F B F F F T 6 = , 1 l l l l P l l l l l l l l l l l l l l

Cs2

FC000r6 = 1111 1100 0000 0000 0000

F F F F F T T , = . l l l l l l , l I l l l l l ! l l l l l l

es3

Figureg-38 (continued)

buffers of the SRAMS are enabled for operation. On the other hand, during read bus

cvcles. MRDC or MEMR is used to enable the outputs of the SRAMs'

EXAMPLE 9.3

(d)

DesignamemorySystemconsistingof32KpytesofR/wmemoryand32KbytesofRoMmem"ory. Use SfinM devices to imllement R/W memory and EPROM devices to imple-

ment ROM memory. The memory devices to be used are shown in Fig. 9-38(a) (p' 455)'

R/W memory is to reside over the address range 0000016 ttfough 07FFFI6 and the

addressrangeofRoMmemoryistobeF8000l6throughFFFFF16'Assumethatthe8088microprocessor system bus signals that follolv are available for use: As through Ars, Do

through D7, MEMR, and MEMW'

Sqlution

First let us determine the number of SRAM devices needed to implement the R/W mem-

ory. Since each device provides 2r+ , 4 or 16K X 4 of storage' the number of SRAM

devices needed to implement 32Kbytes of storage is

No. of SRAM devicas : 32Kbytel(16K x 4) : 4

To provide an 8-bit data bus, tw9 sR.AMs must be connected in parallel' Two pairs con-

nected in this way are then piaced in series to implement the R/W address range, and each

458 Memory Devices, Circuits, and Subsystem Design Chap' 9

o V o

B V r

c

Arz

Are

Ale

At

Ara

Arg

(e) Figure L38 (continued)

par implements l6Kbytes. The first pair, SRAM' and SRAM2, implements the addressrange 0000016 through 03FFF16, and the second pair, SRAM3 and SRAMa, implementsaddresses 0400016 through 07FFF16. The memory map in Fig. 9*38(b) shows the deviceallocation for this implementation.

Next let us determine the number of EPROM devices that arc needed to implementthe ROM memory. In this case, each device provides 214 x 8 or l6Kbytes of storage. Toimplement 32Kbytes of storage, the number of EPROM devices needed is

. No. of EPROM devices - 32Kbyte/l6Kbyte : 2

These two devices must bp connected in series to implement the ROM address rangeand each device implements l6Kbytes of storage. As shown in the memory map inFig. 9-38(b), the first device, EPROMI, implements the address range F800016 t}roughFBFFF16, The second device, EPROM2, implements the adhress range FC00016 throughFFFFF16. t

Sec. 9.7 8088/8086 Microcomputer System Memory Circuitry 459

The memory organization based on the preceding allocation of devices.is shownin Fig. 9-38(c). Notice that we have used the various 8088 system bus signals(l\q_ .|rq, Do - Dz, MEMR, and MEMW) to draw the circuit diagram. For example, theMEMW signal is applied to the WE input of all four SRAMs in parallel, but it is not con-nected to the EPROMs.

The four chip select signals. CSo. CS,, CS2. and CSr, that are used in the circuit needto be produced for the appropriate address ranges. To design the circuit for generating thechip-select signals, we first analyze the address ranges as showrl in Fig. 9-38(d) to deter-mine the address bits that should be used. For instance, to generate the range representedby SRAMI and SRAM2, CS6 should be active for A1eA1sA17A16A15A1a : 0000002. Sim-ilarly the other address ranges tell us which address bits are needed to produce the otherchip-select signals. This informatidn is used in Fig. 9-38(e) to design the chip-select logiccircuit with

'74F138 three-line to eisht-line decoders.

REVIEW PROBLEMS

Sect ion 9.11. Which part of the primary storage memory is used to store instructions of the pro-

gram and fixed information such as constant data and lookup tables? Data thatchanges frequently?

2. What does BIOS stand for?3. What term is used to refer to programs stored in ROM?4. Can DRAMs be used to construct a program storage memory?

Section 9.25. What is meant by the term nonvolatile memory?

6. What does PROM stand for? EPROM?

7. What must an EPROM be exposed to in order to erase its stored data?

8. If the block diagram in Fig. 9-3 has address lines Ae through 4,16 and data lines Dsthrough D7, what are its bit density and byte capacity?

9. Summarize the read cycle of an EPROM. Assume that both CE and OE are activebefore the address is applied.

1.0. Which standard EPROM stores 64K 8-bit words?

11. What is the difference between a 2'7C64A and a 27C64A-l?

12. What are the values of Vss and Voo for the intelligent programming algorithm?

13. What is the duration of the programming pulses used for the intelligent programmingalgorithm?

Section 9.314. What do SRAM and DRAM stand for?

L5. Are RAM ICs examples of nonvolatile or volatile memory devices?

460 Memory Devices, Circuits, and Subsystem Design Chap. 9

16. What must be done to maintain valid data in a DRAM17. Find the total storage capacity of the circuif similar

devices are 43256As.

18' List the minimum values of each of the write cycle parameters that follow for the4364-10 SRAM: twc, tcwr, tcwz, twp, tpy7, and tq,j.

19. Give two benefirs of DRAMs over SRAMs.20. Name the two parts of a DRAM address.21. Show how the circuit in Fig.922 can be expanded to 12gK x 16 bits.22' Give a disadvantage of the use of DRAMs in an application that does not require a

large amount of memory.

Section 9.423' What type of circuit can be added to the data storage memory interface to improve

the reliability of data transfers over the data bus?24. rf inFig. 923 the data read from memory is 100100100 2 , whatis its parity? Repeat

the same if the data is 0111100002?25. If the input to a74A5280 parity-checker/generator circuit that is set up for odd par-'

ity checking and generation is IH. . . A : 111111111 2,whatare its outputs?26. what changes must be made to the circuit in Fig. 9-24(c)to convert it to an odd par-

ity configuration?

27. Make a drawing similar to that shown inFigg24(c) that can be used as the parity_checker/generator in the data storage memory subsystem of an g0g6 microcomputersystem. Assume that parity checking is performed independently for the uppei analower banks of the memory array and that the parity enor ootpoi, for the two banksare combined to form a single parity error signal.

Section 9.528. what is the key difference between a FLASH memory and an EpRoM?29. What is the key difference between the bulk-erase architecture and the boot block or

FlashFile architectures?

30. What is the key difference between the boot block architecture and the FlashFilearchitecture?

31. What architedure is used in rhe 2gF010 FLASH memory IC?32. what power supply voltage musr be applied to a 2gF0r0 device when it

erased or written into?33. Give the names of two boot block FLASH devices.

is being

34. what value v"" power supply voltages can be applied to a smart 5 boot brockFLASH IC? What value Vno power supply voltages?

35. Name the three types of blocks used in the storage array of the 2gF004. How manyof each is provided? What are their sizes?

36. Name two FlashFile FLASH memory devices.37. what is rhe function of the Ry/By- ourpur of the 2gF016sA/sv?

device?

to Fig, 9-I2 if the memory

Review Problems 461

Section 9.638. What function does a wait-state generator circuit perform?

39. What output signal does the wait-state generator produce?

40. Does the circuit in Fig. 9-36(b) produce the same number of wait states for the mem-

ory subsystems corresponding to both chip selects?

41. What is the maximum number of wait states that can be produced with the circuit in

Fig. 9-36(b)?

Section 9.742. Make a diagram showing how 2'764 EPROMs can be connected to form a l6Kbyte

program storage memory subsystem. Also show a l6Kword program memory sub-

system.

43. If we assume that the high-order address bits in the circuits formed in problem 42 are

all logic 0, what is the address range of the program memory subsystems?

44. How marry 2142 static RAMs would be needed in the memory array of the circuit in

Fig. 9-37(a) if the capacity of data storage memory were to be expanded to

64Kbytes?

45. How many 2716 EPROMs would be needed in the program memory array in the cir-

cuit of Fig.9-37(a) to expand its capacity to 96K bits? If 2732s wete used instead of

2716s,how many devices are needed to implement the 96K-bit program memory?

46. Repeat the design in Example 9.3 for t!9!986 microprocessor system bus signals As

through A1e, D',throu*h Drs, MEMR, MEMW' and BHE' Use the same memory and

device specifications.

462 Memory Devices, Circuits, and Subsystem Design Chap' 9