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Memory Consistency Models 1

Memory Consistency Models 1. Uniform Consistency Models Only have read and write operations Sequential Consistency Pipelined-RAM Causal Consistency Coherence

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Page 1: Memory Consistency Models 1. Uniform Consistency Models Only have read and write operations Sequential Consistency Pipelined-RAM Causal Consistency Coherence

Memory Consistency Models

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Page 2: Memory Consistency Models 1. Uniform Consistency Models Only have read and write operations Sequential Consistency Pipelined-RAM Causal Consistency Coherence

Uniform Consistency Models

• Only have read and write operations• Sequential Consistency• Pipelined-RAM• Causal Consistency• Coherence• Processor Consistency

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Page 3: Memory Consistency Models 1. Uniform Consistency Models Only have read and write operations Sequential Consistency Pipelined-RAM Causal Consistency Coherence

Sequential Consistency• All processes order all writes in the same order• Operations in the system can be ordered such that it appears

they were executed by a single process.• Formal definition:

An execution E with operations O is Sequentially Consistent if there exists a total order (O, >) such that

1. and

2. (O,>) is valid

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),(),( OO prog

Page 4: Memory Consistency Models 1. Uniform Consistency Models Only have read and write operations Sequential Consistency Pipelined-RAM Causal Consistency Coherence

Pipelined Ram• All processes order all writes in program order

• Formal Definition:

An execution E with operations O is Pipelined RAM if for all processes p there exists a total order (Op ⋃ Ow , >p) such that

1. and

2. (Op ⋃ Ow , >p) is valid

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),(),( pwpprog

wp OOOO

Page 5: Memory Consistency Models 1. Uniform Consistency Models Only have read and write operations Sequential Consistency Pipelined-RAM Causal Consistency Coherence

Coherence• All processes view all writes to the same location in the same

order.

• Formal Definition:

An execution E with operations O is Coherent if for all locations x there exists a total order (Ox , >x) such that

1. and

2. (Ox , >x) is valid

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),(),( xxprog

x OO

Page 6: Memory Consistency Models 1. Uniform Consistency Models Only have read and write operations Sequential Consistency Pipelined-RAM Causal Consistency Coherence

Causal Consistency• All processes order writes such that it satisfies Lamport’s

happens-before relation

• Formal Definition:

An execution E with operations O is Causally Consistent if for all processes p there exists a total order (Op ⋃ Ow , >p) such that

1. and

2. (Op ⋃ Ow , >p) is valid

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),(),( pwphb

wp OOOO

Page 7: Memory Consistency Models 1. Uniform Consistency Models Only have read and write operations Sequential Consistency Pipelined-RAM Causal Consistency Coherence

Hybrid Models• Distinguish between different types of memory accesses• Release Consistency

– Provides acquire and release operations• Entry Consistency

– Each shared variable has a lock• Scope Consistency

– Variables are associated with locks automatically• Weak Consistency

– Orders synchronization operations

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Page 8: Memory Consistency Models 1. Uniform Consistency Models Only have read and write operations Sequential Consistency Pipelined-RAM Causal Consistency Coherence

Release Consistency

• Hybrid Model• Operations available:– Read – read local copy– Write – write to local copy– Acquire – update local copy– Release – send updates of local copy

• Acquire and Release ops are sequentially consistent

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Page 9: Memory Consistency Models 1. Uniform Consistency Models Only have read and write operations Sequential Consistency Pipelined-RAM Causal Consistency Coherence

Acquire-release Order

• (O, ) – acquire-release order• O1 o2 if o1 o2 and– o1 and o2 are on the same data item, or

– o1 is an acquire, or

– o2 is a release, or

– There exists o st o1 o and o o2

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aro

aro

prog

aro

aro

Page 10: Memory Consistency Models 1. Uniform Consistency Models Only have read and write operations Sequential Consistency Pipelined-RAM Causal Consistency Coherence

Definition of RC• A computation is Release Consistent if• Each process orders its own ops, all writes, release and

acquire operations• Such that the order satisfies the acquire-release order• The acquire and release ops are ordered such that

– All processes agree on the ordering (SC)– Each acquire is immediately followed by its matching release.

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