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Memory
Stephen A. Edwards
Columbia University
Spring 2012
Early Memories
Williams Tube CRT-based random access memory,1946. Used on the Manchester Mark I. 2048 bits.
Early Memories
Mercury acousticdelay line.
Used in the EDASC,1947.
32 × 17 bits
Early Memories
Magnetic core memory, 1952. IBM.
Early Memories
Magnetic drum memory. 1950s & 60s. Secondarystorage.
Modern Memory ChoicesFamily Programmed Persistence
Mask ROM at fabrication ∞
PROM once ∞
EPROM 1000s, UV 10 years
FLASH 1000s, block 10 years
EEPROM 1000s, byte 10 years
NVRAM ∞ 5 years
SRAM ∞ while powered
DRAM ∞ 64 ms
Implementing ROMs
0/1
0
Z: “notconnected”
0
1
0
1
1
1
Add. Data
00 01101 11010 10011 010
2-to-4Decoder
A1A0
0 1 1
1 1 0
1 0 0
0 1 0
Wordline 00
Wordline 11
Wordline 22
Wordline 33
Bitline 0
D0
Bitline 1
D1
Bitline 2
D2
Implementing ROMs
0/1
0
Z: “notconnected”
0
1
0
1
1
1
Add. Data
00 01101 11010 10011 010
2-to-4Decoder
1A10A0
0 1 1
1 1 0
1 0 0
0 1 0
Wordline 00
Wordline 11
Wordline 22
Wordline 33
Bitline 0
D0
Bitline 1
D1
Bitline 2
D2
1 0 0
0
0
1
0
Implementing ROMs
0/1
0
Z: “notconnected”
0
1
0
1
1
1
Add. Data
00 01101 11010 10011 010
2-to-4Decoder
A1A0
0
1
2
3
D0D1D2
Implementing ROMs
0/1
0
Z: “notconnected”
0
1
0
1
1
1
Add. Data
00 01101 11010 10011 010
2-to-4Decoder
A1A0
0
1
2
3
D0D1D2
0 01
1
1
0
1
Mask ROM Die Photo
A Floating Gate MOSFET
Cross section of a NOR FLASH transistor. Kawai et al., ISSCC 2008 (Renesas)
Floating Gate n-channel MOSFET
Channel
Drain Source
Floating Gate
Control GateSiO2
Floating gate uncharged; Control gate at 0V: Off
Floating Gate n-channel MOSFET
Channel
Drain Source
Floating Gate
Control GateSiO2+++++++++
−−−−−−−−+++++++++
−−−−−−−−
Floating gate uncharged; Control gate positive: On
Floating Gate n-channel MOSFET
Channel
Drain Source
Floating Gate
Control GateSiO2
−−−−
−−−−++++
++++
Floating gate negative; Control gate at 0V: Off
Floating Gate n-channel MOSFET
Channel
Drain Source
Floating Gate
Control GateSiO2++++++++
−−−−−−−
−−++
Floating gate negative; Control gate positive: Off
EPROMs and FLASH use Floating-Gate MOSFETs
Static Random-Access Memory Cell
Word line
Bit line Bit line
Layout of a 6T SRAM Cell
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Weste and Harris. Introduction to CMOS VLSI Design.Addison-Wesley, 2010.
Intel’s 2102 SRAM, 1024 × 1 bit, 1972
2102 Block Diagram
SRAM Timing
A12A11
A2A1A0
CS2
D7D6
D1D0
......
CS1
WEOE
62648K × 8SRAM
CS1
CS2
WE
OE
Addr 1 2
Data write 1 read 2
6264 SRAM Block Diagram
CY6264-1
A1A2A3A4A5A6A7A8
I/O0
256 x 32 x 8ARRAY
INPUT BUFFER
COLUMN DECODERPOWERDOWN
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7CE1CE2WE
OE
Toshiba TC55V16256J 256K × 16
A17A16
A2A1A0
D15D14
D1D0
......
UBLBWEOECE
256K × 16SRAM
Dynamic RAM Cell
Row
Column
Ancient (c. 1982) DRAM: 4164 64K × 1
A7A6
A2A1A0
Din Dout
...
WECASRAS
416464K × 1DRAM
Basic DRAM read and write cycles
RAS
CAS
Addr Row Col Row Col
WE
Din to write
Dout read
Page Mode DRAM read cycle
RAS
CAS
Addr Row Col Col Col
WE
Din
Dout read read read
Samsung 8M × 16 SDRAM
BA1BA0A11A10
A2A1A0
UDQMLDQM
CKECLK
DQ15DQ14
DQ1DQ0
...
...
WECASRASCS
8M × 16SDRAM
Bank Select
Data Input Register
8M x 4 / 4M x 8 / 2M x 16
8M x 4 / 4M x 8 / 2M x 16
Sense A
MP
Outp
ut B
uffe
rI/O
Contro
l
Column Decoder
Latency & Burst Length
Programming Register
Addre
ss R
egis
ter
Row
Buffe
r
Re
fresh
Cou
nte
r
Row
Decoder
Col. B
uffe
r
LR
AS
LC
BR
LCKE
LRAS LCBR LWE LDQM
CLK CKE CS RAS CAS WE L(U)DQM
LWE
LDQM
DQi
CLK
ADD
LCAS LWCBR
8M x 4 / 4M x 8 / 2M x 16
8M x 4 / 4M x 8 / 2M x 16
Timing Register
SDRAM: Control Signals
RAS CAS WE Action
1 1 1 NOP0 0 0 Load mode register0 1 1 Active (select row)1 0 1 Read (select column, start burst)1 0 0 Write (select column, start burst)1 1 0 Terminate Burst0 1 0 Precharge (deselect row)0 0 1 Auto Refresh
Mode register: selects 1/2/4/8-word bursts, CASlatency, burst on write
SDRAM: Timing with 2-word bursts
Clk
RAS
CAS
WE
Addr Op R C C
BA B B B
DQ W W R R
Load Active Write Read Refresh
