MB86R11 Evaluation Board - Fujitsu€¦ · In MB86R11EVB, to realize the switching of each resource according to the setting mode by an enable control, the buffer is inserted between

MB86R11 Evaluation Board

MB86R11EVB

Hardware Manual

January, 2011 The 1.1 edition

FUJITSU SEMICONDUCTOR LIMITED

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MB86R11 Evaluation Board MB86R11EVB Hardware Manual

Preface

Objectives and Intended Reader MB86R11EVB is an evaluation board of LSI MB86R11 for graphics applications. This manual describes hardware specifications of MB86R11EVB for engineers who evaluate MB86R11 basic function.

Trademarks ARM is a registered trademark of ARM Limited in the EU and other countries. Cortex is a trademark of ARM Limited in the EU and other countries. The company names and brand names herein are the trademarks or registered trademarks of their respective owners.

Notation Term Description

MB86R11EVB Generic term of MB86R11 evaluation board which is a set of MB86R11EVB-CPU01 (CPU board), MB86R11EVB-BASE01 (Base board), and MB86R11EVB-OPT01 (Option board).

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• The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering.

• The information, such as descriptions of function and application circuit examples, in this document are

presented solely for the purpose of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information.

• Any information in this document, including descriptions of function and schematic diagrams, shall not be

construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU SEMICONDUCTOR or any third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of any third-party's intellectual property right or other right by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein.

• The products described in this document are designed, developed and manufactured as contemplated for

general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products.

• Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or

loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions.

• Exportation/release of any products described in this document may require necessary procedures in

accordance with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.

• The company names and brand names herein are the trademarks or registered trademarks of their respective

owners.

All rights reserved, Copyright FUJITSU SEMICONDUCTOR LIMITED 2011

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Revision History Date Ver. Contents

2011/1/13 1.0 Newly issued

2011/1/25 1.1 Table 9-1 Revised description

Added FPGA specifications

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Contents

1. Outline of MB86R11EVB..................................................................................... 1

1.1. Composition ............................................................................................................................................ 1 1.2. General specifications ............................................................................................................................. 2 1.3. External view .......................................................................................................................................... 3 1.4. Connection configuration........................................................................................................................ 5

2. Outline of Hardware............................................................................................ 6

2.1. Hardware specifications of CPU board ................................................................................................... 6 2.2. Hardware specifications of Base board ................................................................................................... 7 2.3. Hardware specifications of Option board................................................................................................ 9 2.4. Block diagram....................................................................................................................................... 10

3. Details of hardware............................................................................................11

3.1. CPU board..............................................................................................................................................11 3.1.1. External Bus...................................................................................................................................11 3.1.2. DDR2 .............................................................................................................................................11 3.1.3. USB-Host .......................................................................................................................................11 3.1.4. USB-Function ............................................................................................................................... 12 3.1.5. ARM JTAG/ETM.......................................................................................................................... 12 3.1.6. Selection of boot flash memory..................................................................................................... 13 3.1.7. Pin Multiplex Switch..................................................................................................................... 14 3.1.8. Jumper setting ............................................................................................................................... 16

3.2. Base board............................................................................................................................................. 17 3.2.1. FPGA ............................................................................................................................................ 17 3.2.2. External Bus.................................................................................................................................. 17 3.2.3. Display .......................................................................................................................................... 18 3.2.4. Capture .......................................................................................................................................... 24 3.2.5. Ethernet ......................................................................................................................................... 26 3.2.6. EEPROM ...................................................................................................................................... 26 3.2.7. I2S (AUDIO)................................................................................................................................. 26 3.2.8. CAN .............................................................................................................................................. 27 3.2.9. USART (UART)............................................................................................................................ 28 3.2.10. GPIO ............................................................................................................................................. 29 3.2.11. SDIO ............................................................................................................................................. 30 3.2.12. TS.................................................................................................................................................. 31 3.2.13. MediaLB ....................................................................................................................................... 32 3.2.14. Pin Multiplex Switch..................................................................................................................... 33

3.3. Option board ......................................................................................................................................... 37 3.3.1. Display .......................................................................................................................................... 37 3.3.2. I2S (AUDIO)................................................................................................................................. 43 3.3.3. CAN .............................................................................................................................................. 44 3.3.4. USART (UART)............................................................................................................................ 44 3.3.5. LIN................................................................................................................................................ 45

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3.3.6. SDIO ............................................................................................................................................. 46 3.3.7. PWM ............................................................................................................................................. 47 3.3.8. IrDA .............................................................................................................................................. 48 3.3.9. IDE................................................................................................................................................ 49 3.3.10. SPI-FLASH (Quad)....................................................................................................................... 50 3.3.11. SPI-FLASH (Single) ..................................................................................................................... 50 3.3.12. I2C................................................................................................................................................. 50 3.3.13. General-purpose ADC................................................................................................................... 51 3.3.14. TCON............................................................................................................................................ 52 3.3.15. External INT.................................................................................................................................. 52

4. Board interface ................................................................................................. 53

4.1. CPU – Base board I/F ........................................................................................................................... 53 4.2. Base – Option board I/F ........................................................................................................................ 58 4.3. Customer I/F ......................................................................................................................................... 63

5. Memory map ..................................................................................................... 66

5.1. MB86R11EVB memory map................................................................................................................ 66 5.2. FPGA register........................................................................................................................................ 66

5.2.1. VERSION register ........................................................................................................................ 67 5.2.2. PINMUX register .......................................................................................................................... 68 5.2.3. DEVICE_SEL register .................................................................................................................. 70 5.2.4. ACC_TEST register ...................................................................................................................... 71 5.2.5. FPGA signal timing....................................................................................................................... 72

6. Allocation of peripheral resource and I2C port.............................................. 73

7. Power system diagram..................................................................................... 74

8. Clock system diagram...................................................................................... 77

1 1. Outline of MB86R11EVB


1. Outline of MB86R11EVB This chapter describes the outline of MB86R11EVB.

1.1. Composition MB86R11EVB consists of following 3 evaluation boards:

MB86R11EVB-CPU01 (CPU board) This board mounts MB86R11.

MB86R11EVB-BASE01 (Base board) This board has external I/F and the power supply input part.

MB86R11EVB-OPT01 (Option board) This board mounts only the external peripheral functions.

The pin of MB86R11 is multifunctional, and is switched by the external pin setting or the register setting. In MB86R11EVB, to realize the switching of each resource according to the setting mode by an enable control, the buffer is inserted between MB86R11 and each resource. This board executes an enable control with FPGA, and has the selector function of Display and Capture.



1.2. General specifications The table below shows the general specifications.

Table 1-1 General specifications No. Item Contents Remarks

1 Board name CPU board Base board Option board

2 Function

DDR2 Flash ROM Display I/F Capture I/F Ethernet I/F I2S I/F MLB I/F CAN I/F LIN (USART) / UART I/F SD I/F USB I/F PWM I/F GPIO I/F IrDA I/F IDE I/F TS I/F JTAG I/F TRACE I/F I2C I/F A/D I/F TCON Quad-SPI SFI External Bus DMA REQ External INT SW LED

3 Operating ambient temperature

Normal temperature

4 Storage temperature 0 to 70°C

5 Humidity Normal humidity No condensation

6 Environment friendly Conforming product

7 Power supply AC adaptor input +12V 5A or less

8 Board dimensions

CPU board W H = 127mm 117.5mm

Base board W H = 330mm 222.5mm

Option board W H = 222.5mm 105mm



1.3. External view The external view of MB86R11EVB is shown as follows.

Figure 1-1 External view of MB86R11EVB

External view of CPU board

Figure 1-2 External view of CPU board



External view of Base board

Figure 1-3 External view of Base board

External view of Option board

Figure 1-4 External view of Option board



1.4. Connection configuration The connection configuration is shown as follows.

Base Board

CPU Board Option Board

Base Board

CPU Board

Option BoardMB86R1

1

A B

A B

CPUboard side connector CN8Base board side connector

CN31

CPU board side connector CN9Base board side connector

CN32

Option board side connectorCN7

Base board side connectorCN33

Option board side connectorCN8

Base board side connectorCN34

Figure 1-5 Connection configuration of MB86R11EVB

6 2. Outline of Hardware


2. Outline of Hardware This chapter describes the outline of hardware of MB86R11EVB.

2.1. Hardware specifications of CPU board Table 2-1 shows the hardware specifications of CPU board.

Table 2-1 Hardware specifications of CPU board Used CPU

1 MB86R11 PBGA-544pin

Installed function

No. Item Contents Remarks

1 DDR2 MT47H64M16HR-25E_IT (Micron) 2 1Gbit (64M×16bit) 2

2 NOR-FLASH JS28F512M29EWL (Numonyx) 2 512Mbit (32Mword 16bit) 2

This is a composition when 32bit bus is connected. When boot from NOR-FLASH is used, it becomes a composition of 512Mbit 1 because the bus is fixed to 16bit.

3 USB-Host 292303-1 (Tyco) USB-A connector

USB-Host 292303-1 (Tyco) USB-A connector (Exclusive use with USB-Function)

4

USB-Function UX60SC-MB-5ST (HRS) Mini-B connector (Exclusive use with USB-Host)

5 ICE PS-20PE-D4T1-B1 (JAE) JTAG connector

6 TRACE 2-5767004-2 (Tyco) ETM connector

7 Base board connection 53647-1674 (Molex) 2 160pin stack



2.2. Hardware specifications of Base board Table 2-2 shows the hardware specifications of Base board.

Table 2-2 Hardware specifications of Base board (1/2) Used FPGA

1 Spartan6 XC6SLX100-2FGG676C (Xilinx) FBGA-676pin

No. Item Contents Remarks

DVI-D The connector is DVI-I. SiI164BCT64 (Silicon Image)

CVBS ADV7343BSTZ (Analog devices)

Analog RGB ADV7343BSTZ (Analog devices)

RSDS (Header pin) OQW-11-4.2-20PW (Mac8)

1.27mm pitch

Diplay0

External output (Header pin) OQW-11-4.2-20PW (Mac8)

1.27mm pitch

DVI-D The connector is DVI-I. SiI164BCT64 (Silicon Image)

1 Display (2ch)

Display1 External output (Header pin) OQW-11-4.2-20PW (Mac8)

1.27mm pitch

DVI-D SiI1161CT (Silicon Image) The connector is DVI-I.

CVBS (YUV) ADV7403KSTZ (Analog devices) Capture0

External input (Header pin) OQW-11-4.2-20PW (Mac8)

1.27mm pitch

CVBS (YUV) ADV7403KSTZ (Analog devices)

Video Component (720P) ADV7403KSTZ (Analog devices)


1.27mm pitch



1.27mm pitch


2 Capture (4ch)

Capture1


1.27mm pitch

3 Ethernet RJ45 connector TM21R-5C-88 (HRS)

GbE-PHY 88E1111-B2-BAB-C000 (Marvell)

Stereo mini Jack 1 STX-3500-4N (Kycon)

OUTPUT 4 I2S (CH0: AUDIO)

Stereo mini Jack 1 STX-3500-4N (Kycon)

INPUT

5 MediaLB Connector for evaluation (Header pin)A3A-10PA-2SV (71) (Hirose)

2.0mm pitch

6 CAN (CH0) D-sub9 RDED-9P-LNA (4-40) (55) (HONDA TSUSHIN)

D-sub9 RDED-9P-LNA (4-40) (55) (HONDA TSUSHIN)

7 USART/UART (CH0, CH1)

External input/output (Header pin) OQW-11-4.2-03PW (Mac8)

1.27mm pitch

8 SD (CH0) SD card slot DM1AA-SF-PEJ(HRS)



Table 2-2 Hardware specifications of Base board (2/2) No. Item Contents Remarks

LED for power supply (Green) LED 1 SML-310MT (ROHM)

It lights when SW17 is turned on when the power is supplied to the Base board.

LED for FPGA reset (Green) LED 1 SML-310MT (ROHM)

It lights when FPGA is reset. 9 LED

LED for configuration (Green) LED 1 SML-310MT (ROHM)

It lights when the FPGA configuration is completed.

LED 4 SML-310MT (ROHM)

Green LED CH11-14

External input/output (Header pin) OQW-11-4.2-03PW (Mac8)

10 GPIO 10

CH5-10 SW 6 SKRPABE010 (ALPS ELECTRIC)

Tact switch

11 TS External pin (Header pin) OQW-11-4.2-07PW (Mac8)

1.27mm pitch

12 I2C (CH0, CH1) For setting of IC

13 EEPROM BR25S256F (ROHM) 256Kbit

SW 1 SKRPABE010 (ALPS ELECTRI)

Tact switch INT_A0

External input (Header pin) FFC-03ASM1 (HONDA TSUSHI)

2.54mm pitch 14 External INT

INT_A1 External input (Header pin) FFC-03ASM1 (HONDA TSUSHI)

2.54mm pitch

15 NAND FLASH MT29F2G08ABAEAWP (Micron) 2Gbit (8bit Bus)

JTAG 98424-G52-14ALF (FCI) For FPGA writing 16

FPGA configuration Config-ROM S25FL032P0XMFI011 (SPANSION) Quad SPI

17 CPU board connection 52837-1679 (Molex) 2 160pin stack

18 Option board connection 52837-1679 (Molex) 2 160pin stack

19 Customer board connection connector

87BFN100R-3F (KEL) 100pin right angle

20 MB86R11 mode selection switch 8bit slide switch 4 CHS-08B (NIDEC COPAL ELECTRONICS)

21 Capture input selection switch 8bit slide switch CHS-08B (NIDEC COPAL ELECTRONICS)



2.3. Hardware specifications of Option board Table 2-3 shows the hardware specifications of Option board.

Table 2-3 Hardware specifications of Option board No. Item Contents Remarks

Diplay0 DVI-D The connector is DVI-I. SiI164BCT64(Silicon Image)

Diplay1 DVI-D The connector is DVI-I. SiI164BCT64(Silicon Image)

DVI-D The connector is DVI-I. SiI164BCT64(Silicon Image)

1 Display (3ch)

Diplay2 External output (Header pin) OQW-11-4.2-20PW (Mac8)

1.27mm pitch

OUT: Stereo mini Jack 1 STX-3500-4N (Kycon)

2 I2S (CH1)

IN: Stereo mini Jack 1 STX-3500-4N (Kycon)

3 I2S (CH2, CH3) External input/output (Header pin) OQW-11-4.2-04PW (Mac8)

1.27mm pitch

4 CAN (CH1) D-sub9 RDED-9P-LNA (4-40) (55) (HONDA TSUSHIN)

5 LIN (USART)/UART (CH5) B2B-PH-SM4-TB (JST)

6 SD 2 (CH1, CH2) SD card slot DM1AA-SF-PEJ (HRS)

7 PWM 12 External output (Header pin) OQW-11-4.2-07PW (Mac8)

1.27mm pitch

8 IrDA External input/output (Header pin) OQW-11-4.2-06PW (Mac8)

1.27mm pitch

9 I2C (CH2～4) External input/output (Header pin) FFC-03ASM1 (HONDA TSUSHIN)

2.54mm pitch

10 General-purpose ADC External input/output (Header pin) OQW-11-4.2-05PW (Mac8)

1.27mm pitch

11 TCON External output (Header pin) OQW-11-4.2-07PW (Mac8)

1.27mm pitch

12 SPI-FLASH (Quad) S25FL064P0XMFI001 (Spansion) 64Mbit

13 SPI-FLASH (Single) W25Q32BVSSIG (Winbond) 32Mbit

14 External INT (CH2) External input (Header pin) OQW-11-4.2-04PW (Mac8)

1.27mm pitch

15 DMA REQ External input/output (Header pin) FFC-03ASM1 (HONDA TSUSHIN)

2.54mm pitch

16 IDE External input/output (Header pin) WCAW-20-2-22PW (Mac8)



2.4. Block diagram Figure 2-1 shows the block diagram of MB86R11EVB.

MB86R11 FPGA DISP0

DISP1

DISP2

DDR2

Nor Flash

ICE

TRACE

USB-Host

USB-Host

USB-Function

CAP0

PIN

PIN

PIN

DISP0

DISP1

PIN

CAP1

PIN

CAP2

PIN

CAP3

PIN

Ethernet

CAN

USART

SD Card

TS

NANDFlash

AUDIO

GPIO

AUDIO

USART

SD Card

PWM

IrDA

DMA REQ

Quad SPI

SPI Flash

I2C

A/D

TCON

INT

Enable signal of each buffer

MLB

PIN

PIN

I2C

EEPROM

INT

CAN

PIN

PIN

(RS

DS

)

IDE

LIN

Figure 2-1 Block diagram of MB86R11EVB

11 3. Details of hardware


3. Details of hardware This chapter describes details of the hardware of MB86R11EVB.

3.1. CPU board Single-chip system LSI MB86R11 with built-in CoreTex-A9 is used for CPU.

Table 3-1 CPU No. Item Model number Manufacturer Quantity Remarks

1 CPU MB86R11 Fujitsu Semiconductor 1 PBGA544pin

3.1.1. External Bus

NOR-FLASH of 1Gbit (512Mbit) is connected to External Bus of CPU board.

Table 3-2 NOR-FLASH No. Item Model number Manufacturer Quantity Remarks

1 NOR-FLASH JS28F512M29EWL Numonyx 2 128MB (32Mword×16bit×2)

3.1.2. DDR2

The CPU board has 2Gbit (1Gbit 2) as DDR2 interface. It is a composition in which 4Gbit (2Gbit 2) can be connected.

Table 3-3 DDR2 No. Item Model number Manufacturer Quantity Remarks

1 DDR2 MT47H64M16HR-25E_IT MICRON 2 256MB (64Mb 16bit 2)

3.1.3. USB-Host

The CPU board has the USB2.0-Host by 2 ports (CN3 and CN5). The CN3 is exclusively used with Function (CN4).

Table 3-4 USB-Host No. Item Model number Manufacturer Quantity Remarks

1 USB connector 292303-1 Tyco 2 TypeA

2 High side switch TPS2061D TI 1 Power supply control

3 Crystal oscillator MXO3-7050 48MHz MITADENPA 1 48MHz/50ppm All USB ports



3.1.4. USB-Function

The CPU board has the USB2.0-Function by 1 port (CN4). VBUS is connected to INT_A[1].

Table 3-5 USB-Function No. Item Model number Manufacturer Quantity Remarks

1 USB connector UX60SC-MB-5ST HRS 1 miniB

2 Schmitt buffer SN74LVC1G17DCK TI 1 VBUS detection

3 Crystal oscillator MXO3-7050 48MHz MITADENPA 1 48MHz/50ppm All USB ports

3.1.5. ARM JTAG/ETM

The CPU board has JTAG (CN1) and the ETM connector (CN2) for the ARM debugging. Enable ETM probe (HLX600TP) and JTAG cable (HLX600JP) of YDC AdviceLUNA to be connected.

Table 3-6 ARM JTAG/ETM No. Item Model number Manufacturer Quantity Remarks

1 JTAG PS-20PE-D4T-B1 JAE 1 2列20極

2 ETM 2-5767004-2 Tyco 1 2列38極



3.1.6. Selection of boot flash memory

The CPU board has the switch that selects the boot memory. It can select either of NOR-FLASH or NAND-FLASH of the external memory.

Table 3-7 Slide switch No. Item Model number Manufacturer Quantity Remarks

1 Slide switch MAS-D20A1 Fujisoku 1

SW1 (Selection of boot memory type)

Table 3-8 SW1 setting SW1 Boot memory type Remarks

MB86R11 side NAND-FLASH Cannot used The other side NOR-FLASH (Default) Default

NOR-FLASH

NAND-FLASH

MB86R11



3.1.7. Pin Multiplex Switch

The setting of each switch on CPU board is as follows.

Table 3-9 DIP SW No. Item Model number Manufacturer Quantity Remarks

1 DIP SW CHS-08B NIDEC COPAL ELECTRONICS

2

SW2 (PLLMODE)

Table 3-10 SW2 setting SW2 Signal Description Default

4:1 CRIPM[3:0] ON=0, OFF=1 SW[4, 3, 2, 1]=[ON, ON, ON, ON]=0000 SW[4, 3, 2, 1]=[OFF, OFF, OFF, OFF]=1111

SW[4, 3, 2, 1]= [OFF, ON, ON, ON]

5 PLLBYPASS OFF=PLL clock is not bypassed. ON=PLL clock is bypassed.

OFF

6 PSMODE ON=PSMODE are reflected to the PLL clock frequency. OFF=PSMODE are not reflected to the PLL clock frequency

ON

7 VINTHI ON=The exception vectors are located at 0xFFFF_0000. OFF=The exception vectors are located at 0x0000_0000.

OFF

8 USB_S Use USB-Host (CN3) / USB-Function ON=USB-Host (CN3) OFF=USB-Function (CN4)

OFF

8 1

ON Default



SW3 (MPXMODE)

Table 3-11 SW3 setting SW3 Signal Description Default

2:1 MPXMODE[1:0] SW[2:1]=[OFF, OFF]=Mode0 SW[2:1]=[OFF, ON]=Mode1 SW[2:1]=[ON, ON]=Mode1 SW[2:1]=[ON, OFF]=Mode2

SW[2, 1]= [OFF, OFF]

3 MPXMODE[2] OFF=Mode0 ON=Mode2

ON

4 NOR_EAEN NOR-FLASH bus select ON=32bit OFF=16bit

OFF

5 JTAGSEL JTAG select OFF= Normal ON=DFT

OFF

6 TEST MODE TEST mode OFF= Normal ON= TEST mode

OFF

7 TRACEEN0 Pin Group B ETM ON=Used OFF=Unused

OFF

8 TRACEEN1 Pin Group H ETM ON= Used OFF= Unused

OFF

ON

8 1

Default



3.1.8. Jumper setting

The CPU board has the header pin that has the following functions.

Table 3-12 General-purpose pin header No. Item Model number Manufacturer Quantity Remarks

1 General-purpose pin header

FFC-2ASM1 HONDA TSUSHIN 7 1 row, 2 poles

Table 3-13 Jumper setting CN Function Description Default

10 OSC Open (Fixed) Open

11 VRH0 Short= ADC is not used. Open= ADC is used.

Short

12 VRH1 Short= ADC is not used. Open= ADC is used.

Short

13 VRL0 Short= ADC is not used. Open= ADC is used.

Short

14 VRL1 Short= ADC is not used. Open= ADC is used.

Short

15 VIN0 Short= ADC is not used. Open= ADC is used.

Short

16 VIN1 Short= ADC is not used. Open= ADC is used.

Short

Note:

CN11-16 must "OPEN" when the ADC connector of the Option board is used.



3.2. Base board The AC adaptor is connected to this board, and it supplies power to each board. The signal of the Display, Capture, and External Bus are connected to FPGA, and an enable control is performed for the buffer of each resource according to the mode that the user set.

3.2.1. FPGA

The FPGA of the Base board provides a selector function of Display and Capture and a buffer enable control functions of each resource. External Bus connects the following signals with FPGA: lower 10 bits of address (A[11:1]) 32 bits control signal (excluding the signal for NAND) of data

Table 3-14 FPGA No. Item Model number Manufacturer Quantity Remarks

1 FPGA XC6SLX100-2FGG676C Xilinx 1 Spartan6 2 Writing connector 98424-G52-14ALF FCI 1 2 rows, 14 poles 3 Configuration ROM S25FL032P0XMFI011 SPANSION 1 32Mbit

3.2.2. External Bus

The 256MB NAND-FLASH is connected to External Bus of the Base board. To connect External Bus signals with customer's board, they are connected to the connector. Refer to "4.3 Customer I/F" for detail.

Table 3-15 External Bus No. Item Model number Manufacturer Quantity Remarks

1 NAND-FLASH MT29F2G08ABAEAWP MICRON 1 256MB (8bit×256Mbit)



3.2.3. Display

The Base board has 2 ports (Display0 and Display1) as an image output interface, and is output with the DVI connector. In addition, only the Diplay0 port has CVBS and the analog RGB connector for the analog output. The pin header of Display is described below.

Table 3-16 Display No. Item Model number Manufacturer Quantity Remarks

1 DVI transmitter SiI164BCT64 SiliconImage 2

2 DVI-I connector 1734148-1 Tyco 2

3 Video DAC ADV7343 AnalogDevices 1

4 AnalogRGB connector 1-1734570-1 Tyco 1 Dsub15

5 NTSC connector LPR6520-0804F SMK 1

6 Display Header pins I/F OQW-11-4.2-20PW Mac8 2 2 rows, 40 poles 1.27mm pitch

(Remark) DISP0 connector DVI-I=CN1, CVBS=CN4, RGB=CN3,Header pin=CN20 DISP1 connector DVI-I=CN2,Header pin=CN27

Figure 3-1 Display circuit



Table 3-17 Capture (CH0) pin assignment No. Signal name I/O Description No. Signal name I/O Description

1 GND - Ground 21 GND - Ground


3 B0 I 23 HD I

4 B1 I 24 VD I

5 B2 I 25 DE I

6 B3 I 26 - -

7 B4 I 27 GND - Ground


9 B6 I 29 R0 I

10 B7 I 30 R1 I

11 GND - Ground 31 R2 I


13 G0 I 33 R4 I

14 G1 I 34 R5 I

15 G2 I 35 R6 I

16 G3 I 36 R7 I

17 G4 I 37 GND - Ground


19 G6 I 39 CLK I


(Remark) The physical pin assignment is the same as the audio general-purpose pin header.

Table 3-18 Capture YUV (CH0, CH1, CH2, CH3) pin assignment No. Signal name I/O Description No. Signal name I/O Description

1 V0 I 2 GND - Ground








17 CLK I 18 GND - Ground

19 - - 20 GND - Ground




SW1 (DISP0_DAC_CTRL)

Set SW1[2:1]=[OFF, OFF] when I2C0 is used.

SW1 Signal Description Default

(I2C mode)

1 DSEL /

SDA

Dual edge clock select / I2C Data This pin is an open collector input/output. If I2C bus is enabled (ISEL=OFF), then this pin is the I2C data line. If the I2C bus is disabled (ISEL=ON), then this pin selects whether single clock dual edge is used.

Dual Edge clock select: DSEL=OFF:

IDCK+ latches input data on both falling and rising clock edges. DSEL=ON:

IDCK+/IDCK- latches input data on only falling or rising clock edges. In 24-/12-bit mode:

DSEL=OFF (dual edge): IDCK+ is used to latch data on both falling and rising edges.

DSEL=ON (single edge): IDCK+ latches 1st half data and IDCK- latches 2nd half data.

OFF

2 BSEL /

SCL

Input bus select / I2C clock. This pin is an open collector input. If I2C bus is enabled (ISEL=OFF), then this pin is the I2C clock input. If the I2C is disabled (ISEL=ON), then this pin selects the input bus width.

Input Bus Select: BSEL=OFF:

selects 24-bit input mode BSEL=ON:

selects 12-bit input mode

OFF

3 EDGE /

HTPLG

Edge select / Hot Plug input. If the I2C bus is enabled (ISEL=OFF), then this pin is used to monitor the "Hot Plug" detect signal (Please refer to the DVI or VESA P&D and DFP standards). This Input is ONLY 3.3V tolerant and has no internal de-bouncer circuit. If I2C bus is disabled (ISEL=ON), then this pin selects the clock edge that will latch the data. How the EDGE setting works depends on whether dual or single edge latching is selected.

Dual Edge Mode (DSEL = OFF) EDGE=ON:

the primary edge (first latch edge after DE is asserted) is the falling edge. EDGE=OFF:

the primary edge (first latch edge after DE is asserted) is the rising edge. (Note) In 24-bit Single Clock Dual Edge mode, EDGE is ignored.

Single Edge Mode (DSEL=ON) EDGE=ON:

the falling edge of the clock is used to latch data. EDGE=OFF:

the rising edge of the clock is used to latch data.

OFF

ON

8 1

Default




(I2C mode)

4 DKEN De-skewing enable. I2C mode (ISEL=OFF)

DKEN pin must be set to OFF. DK[3:1] pins are ignored and the De-skewing increments are selected through the I2C interface.

Non I2C mode (ISEL=ON) DKEN=ON:

then default De-skewing setting is used. DKEN=OFF:

then DK[3:1] is used as the De-skewing setting.

OFF

7:5 CTL[1:3] /

A[1:3] /

DK[1:3]

The use of these multi-function inputs depends on the settings of ISEL and DKEN. ISEL=ON, DKEN=ON:

General-Purpose Input CTL[1:3] pins are active, for backward compatibility. These pins must be used to send DC signals only during the blanking time.

ISEL=ON, DKEN=OFF DK[1:3] are active, these inputs are used to select the De-skewing setting for the input bus.

ISEL=OFF, DKEN=OFF A[1:3] are active, these bits are used to set the lower 3 bits of the I2C device

address.

SW[7, 6, 5] =A[1, 2, 3] =[OFF, OFF, OFF] I2C device address: 0111, A3, A2, A1 =0111000 (*1) *1) ON="1", OFF="0"

8 ISEL /

RST#

I2C Interface Select. ISEL=OFF:

I2C interface is active. ISEL=ON:

I2C is inactive and the chip configuration is read from the configuration strapping pins. This pin also acts as an asynchronous reset to the I2C interface controller.

(Note) When the I2C interface is active, DKEN must be set OFF.

OFF

Refer to the data sheet of SiI164BCT64 for detail.



SW2 (DISP_DAC_CTRL1)



(I2C mode)

1 DSEL /

SDA







OFF

2 BSEL /

SCL





OFF

3 EDGE /

HTPLG








OFF

ON

8 1

Default




(I2C mode)






OFF

7:5 CTL[1:3] /

A[1:3] /

DK[1:3]





address.

SW[7,6,5] =A[1, 2, 3] =[ON, OFF, OFF] I2C device address: 0111, A3, A2, A1 =0111001 (*1) *1) ON="1", OFF="0"

8 ISEL /

RST#





OFF




3.2.4. Capture

The Base board has 4 ports as an image output interface. Capture0 can be input from DVI, NTSC, and the pin header, and Capture1 can be input from HD, NTSC, and the pin header. Capture2/3 can be input from NTSC and the pin header.The pin header of Capture is described below.

Table 3-19 Capture No. Item Model number Manufacturer Quantity Remarks

1 Video decoder ADV7403 AnalogDevices 4

2 Crystal oscillator MXO3-5032 28.63636MHz MITADENPA 1 28.63636MHz/50ppm

3 NTSC connector LPR6520-0804F SMK 4

4 HD connector LPR6520-0804F SMK 3

5 DVI receiver SiI1161 SiliconImage 1


7 EEPROM 24LC21A/P Microchip Technology

1 Socket mounting

8

9

(Remark) Capture0 connector DVI-I=CN5, NTSC=CN6,Header pin=CN35 Capture1 connector HD=CN39~CN41, NTSC=CN8,Header pin=CN28 Capture2 connector NTSC=CN9,Header pin=CN29 Capture3 connector NTSC=CN10,Header pin=CN30

Sil1161

PD#

ADV7403

R

3.3V

R

3.3V

OE#

OE#

OE#

OE#

ADV7403

OE#

OE#

ADV7403

CAP0

CAP1

CAP2/3

R

3.3V

R

3.3V

R

3.3V

R

3.3V

R

3.3V

R

3.3V

SW1

SW2

SW3

SW4/5

SW1=L & SW2=L : H

SW1=L & SW2=H : H

I2C0

I2C0

I2C1

Circuit x 2

Figure 3-2 Capture input path select circuit



Table 3-20 Capture (CH0) pin assignment No. Signal name I/O Description No. Signal name I/O Description



3 B0 I 23 HD I

4 B1 I 24 VD I

5 B2 I 25 DE I

6 B3 I 26 - -



9 B6 I 29 R0 I

10 B7 I 30 R1 I



13 G0 I 33 R4 I

14 G1 I 34 R5 I

15 G2 I 35 R6 I

16 G3 I 36 R7 I



19 G6 I 39 CLK I



Table 3-21 Capture YUV (CH0, CH1, CH2, CH3) pin assignment No. Signal name I/O Description No. Signal name I/O Description









17 CLK I 18 GND - Ground

19 - - 20 GND - Ground




3.2.5. Ethernet

The Base board has 1 port (CN11) as the Ethernet interface for GbE.

Table 3-22 GbE No. Item Model number Manufacturer Quantity Remarks

1 GbE-PHY 88E1111-B2-BAB-C000 Marvell 1

2 LAN connector TM21R-5C88(50) HRS 1

3 Transformer H5007NL Pulse 1

4 Xtal CX-8045G 25MHz KYOCERA 1 25MHz

3.2.6. EEPROM

The EEPROM is connected to SPI0 of the Base board.

Table 3-23 EEPROM No. Item Model number Manufacturer Quantity Remarks

1 EEPROM BR25S256F ROHM 1 256Kbit

3.2.7. I2S (AUDIO)

As for the Base board, I2C0 1ch is connected to the audio device as the audio interface. The audio device is connected to interface (CN12, 13) for the connection of the microphone and the speaker. I2C0 is connected to the audio device.

Table 3-24 I2S (AUDIO) No. Item Model number Manufacturer Quantity Remarks

1 Audio CODEC WM8976 Wolfson 1

2 Audio mini-jack STX-2500-3N KYCON 2 φ3.5



3.2.8. CAN

As for the Base board, CAN0 1ch is connected to the Dsub9 connector (CN14) as the CAN interface.

Table 3-25 CAN No. Item Model number Manufacturer Quantity Remarks

1 Transceiver SN65HVD234 TI 1

2 Dsub9 connector RDED-9P-LNA(4-40)(55) HRS 1

3 Switch G-12AP Nihon Kaiheiki 1

SW3 (CAN CH0)

SW3 Description

CAN CH0 Bus termination is inactive.

CONNECT Bus termination is active. (default)

Figure 3-3 SW3 (CAN CH0) circuit

CA

N C

H0

CONNECT



3.2.9. USART (UART)

As for the Base board, 2ch of USART0/1 is connected to the Dsub9 connector (CN15, CN17) and the general-purpose pin header as the UART interface.

Table 3-26 UART No. Item Model number Manufacturer Quantity Remarks

1 Transceiver MAX3232CUE MAXIM 1 2port type



OQW-11-4.2-03PW Mac8 2 2 rows, 6 poles

Table 3-27 Details of serial port No. Item Contents Remarks

1 Baud rate Software control

2 Data length Software control

3 Parity Software control

4 Stop bit Software control

5 Flow control N/A

6 Signal definition DTE Interlink cable



3.2.10. GPIO

MB86R11 has 126 channels as the GPIO interface. The GPIO interface of 10 channels is used in the Base board. They are connected to a tact switch, LED, and a general-purpose connector. The 6 channels are used for the tact switch, and the 4 channels are used for LED and the pin header. In addition, GPIO19-21 is used for the power supply control of the SD card.

Table 3-28 GPIO No. Item Model number Manufacturer Quantity Remarks

1 LED SML-310MT ROHM 4 Green

2 Tact switch SKRPABE010 ALPS ELECTRIC 6

3 General-purpose connector

OQW-11-4.2-03PW Mac8 1 2 row, 6 poles

Figure 3-4 GPIO circuit

Table 3-29 GPIO pin assignment No Signal name I/O Description

1 GND - Ground

2 GPIO[11] IO LED0

3 GPIO[12] IO LED1

4 GPIO[13] IO LED2

5 GPIO[14] IO LED3

6 GND - Ground



3.2.11. SDIO

The Base board mounts SD0 1ch as the SDIO interface, and is connected to the SD card slot (CN21). The power supply to the SD card is controlled with the pin of MB86R11 (see Figure 3-).

Table 3-30 SDIO No. Item Model number Manufacturer Quantity Remarks

1 SD card slot DM1AA-SF-PEJ HRS 1

No. SD power supply control pin SD card Remarks

1 INT_A5 (GPIO19) SD CH0 0: PWR ON

2 INT_A6 (GPIO20) SD CH1 0: PWR ON (It is mounted on the Option board.)

3 INT_A7 (GPIO21) SD CH2 0: PWR ON (It is mounted on the Option board.)

Figure 3-5 SDIO circuit



3.2.12. TS

The Base board has the TS interface. This interface is connected to pin header (CN23).

Table 3-31 TS No. Item Model number Manufacturer Quantity Remarks



Table 3-32 TS connector No Signal name I/O Description

1 D0 O

2 D1 O

3 D2 O

4 D3 O

5 D4 O

6 D5 O

7 D6 O

8 D7 O

9 TSCTL1 O

10 TSCTL2 O

11 GND - Ground

12 GND - Ground

13 CLK O

14 GND - Ground

(Remark) The physical pin assignment is the same as the general-purpose pin header.



3.2.13. MediaLB

This Base board has one connector (CN24) as the MediaLB interface.

Table 3-33 MediaLB No. Item Model number Manufacturer Quantity Remarks

1 Connector for MOST controller connection

A3A-10PA-2SV(71) HRS 1 2 rows, 10 poles

Table 3-34 MOST debug connector pin assignment No Signal name I/O Description

1 GND - Ground

2 MLBCLK IO

3 GND - Ground

4 MLBSIG IO

5 GND - Ground

6 MLBDAT IO

7 GND - Ground

8 N.C. -

9 GND - Ground

10 N.C. -




3.2.14. Pin Multiplex Switch

The pin of MB86R11 can be switched by MPXMODE[2:0] or the register setting. In the Base board, the same setting as the register setting is set with an external switch.

Table 3-35 DIP SW No. Item Model number Manufacturer Quantity Remarks

1 DIP SW CHS-08B NIDEC COPAL ELECTRONICS

7

SW10 (SW_CB) SW10 switches the PIN mode of "PIN Group B and C" of MB86R11.

Table 3-36 SW10 setting SW10 Group Description Default

3:1 B SW[3, 2, 1]=[ON, ON, OFF]: Mode1 SW[3, 2, 1]=[ON, OFF, OFF]: Mode3 SW[3, 2, 1]=[OFF, ON, OFF]: Mode5 Others: depended on setting of MPXMODE[2] MPXMODE[2] =OFF: Mode0 MPXMODE[2] =ON: Mode2

SW[3, 2, 1]=[OFF, ON, OFF]

6:4 C SW[6, 5, 4]=[ON, ON, ON]: Mode0 SW[6, 5, 4]=[ON, ON, OFF]: Mode1 SW[6, 5, 4]=[ON, OFF, ON]: Mode2 SW[6, 5, 4]=[ON, OFF, OFF]: Mode3 Others: Mode0

SW[6, 5, 4]=[ON, ON, ON]

8:7 - - SW[8, 7]=[OFF, OFF]

8 1

ON Default



SW11 (SW_ED) SW11 switches the PIN mode of "PIN Group E and D" of MB86R11.


1 D SW[1]=[OFF]: Mode5 SW[1]=[ON]: Mode0

ON

3:2 - - SW[3, 2]=[ON, ON]

6:4 E SW[6, 5, 4]=[ON, ON, ON]: Mode0 SW[6, 5, 4]=[ON, ON, OFF]: Mode1 SW[6, 5, 4]=[ON, OFF, ON]: Mode2 SW[6, 5, 4]=[ON, OFF, OFF]: Mode3 SW[6, 5, 4]=[OFF, ON, OFF]: Mode5 Others: Mode0

SW[6, 5, 4]=[ON, ON, ON]

8:7 - - SW[8, 7]=[OFF, OFF]

SW12 (SW_GF) SW12 switches the PIN mode of "PIN Group F and G" of MB86R11.


3:1 F SW[3, 2, 1]=[ON, ON, ON]: Mode0 SW[3, 2, 1]=[ON, ON, OFF]: Mode1 SW[3, 2, 1]=[ON, OFF, OFF]: Mode3 SW[3, 2, 1]=[OFF, ON, ON]: Mode4 Others: Mode0

SW[3, 2, 1]=[ON, ON, ON]

6:4 G SW[6, 5, 4]=[ON, ON, ON]: Mode0 SW[6, 5, 4]=[ON, ON, OFF]: Mode1 SW[6, 5, 4]=[ON, OFF, ON]: Mode2 SW[6, 5, 4]=[ON, OFF, OFF]: Mode3 Others: Mode0

SW[6, 5, 4]=[ON, ON, ON]

8:7 - - SW[8, 7]=[OFF, OFF]

8 1

ON Default

8 1

ON Default



SW14 (SW_IH) SW14 switches the PIN mode of "PIN Group I and H" of MB86R11.


3:1 H SW[3, 2, 1]=[ON, ON, ON]: Mode0 SW[3, 2, 1]=[ON, ON, OFF]: Mode1 SW[3, 2, 1]=[ON, OFF, ON]: Mode2 SW[3, 2, 1]=[ON, OFF, OFF]: Mode3 SW[3, 2, 1]=[OFF, ON, ON]: Mode4 SW[3, 2, 1]=[OFF, ON, OFF]: Mode5 Others: Mode0

SW[3, 2, 1]=[ON, ON, ON]

6:4 I SW[6, 5, 4]=[ON, ON, ON]: Mode0 SW[6, 5, 4]=[ON, ON, OFF]: Mode1 SW[6, 5, 4]=[ON, OFF, ON]: Mode2 SW[6, 5, 4]=[ON, OFF, OFF]: Mode3 SW[6, 5, 4]=[OFF, ON, OFF]: Mode5 Others: Mode0

SW[6, 5, 4]=[ON, ON, ON]

8:7 - - SW[8, 7]=[OFF, OFF]

8 1

ON Default



SW19 (DEVICE_SEL) The Caputure0-3 and the color space can be selected by the SW19[5:1] bits. In addition, FPGA internal memory can be checked by the SW19[8:6].

Table 3-40 SW19 setting SW19 Function Color Space Input Description Default

RGB 24bit CN5(DVI) SW[2, 1]=[ON, OFF] or SW[2, 1]=[OFF, OFF]

NTSC 8bit YCbCr CN6 (CVBS) SW[2, 1]=[ON, ON]

RGB 24bit CN22 (PIN_HEADER)

2:1 Capture 0

NTSC 8bit YCbCr CN35 (PIN_HEADER)

SW[2, 1]= [OFF, ON]

SW[2, 1] =[ON, ON]

NTSC/HD 8bit YCbCr

CN8 (CVBS) CN39 (HD_Y) CN40 (HD_Pb) CN41 (HD_Pr)

SW[3]=ON 3 Capture 1

NTSC/HD 8bit YCbCr

CN28 (PIN_HEADER) SW[3]=OFF

ON

NTSC 8bit YCbCr CN9 (CVBS) SW[3]=ON 4 Capture 2

NTSC 8bit YCbCr CN29 (PIN_HEADER) SW[3]=OFF

ON

NTSC 8bit YCbCr CN10 (CVBS) SW[3]=ON 5 Capture 3

NTSC 8bit YCbCr CN30 (PIN_HEADER) SW[3]=OFF

ON

8:6 Memory check

- - FPGA internal memory check SW[8, 7, 6]=[ON, ON, OFF] (*1) Group B=Mode0: 32bit access Others:16bit access

SW[8, 7, 6] =[OFF, OFF, OFF]

*1) Memory access: MEM_XCS[1] is used. MEM_EA[26:12] are not used.

8 1

ON Default



3.3. Option board All functions of MB86R11 can be used by using the CPU board, the Base board, and the Option board. The Option board has the Dual monitor function and the HDMI connector.

3.3.1. Display

The Option board mounts three DVI connectors as an image output interface. The pin header of Display is described below.

Table 3-41 Display No. Item Model number Manufacturer Quantity Remarks

1 DVI transmitter SiI164BCT64 SiliconImage 3


(Remark) DISP0 connector DVI-I=CN9 DISP1 connector DVI-I=CN10 DISP2 connector DVI-I=CN11




(I2C mode)

1 DSEL /

SDA







OFF

2 BSEL /

SCL





OFF

ON

8 1

Default




(I2C mode)

3 EDGE /

HTPLG








OFF






OFF

7:5 CTL[1:3] /

A[1:3] /

DK[1:3]





address.

SW[7, 6, 5] =A[1, 2, 3] =[OFF, OFF, OFF] I2C device address: 0111, A3, A2, A1 =0111000 (*1) *1) ON="1", OFF="0"

8 ISEL /

RST#





OFF







(I2C mode)

1 DSEL /

SDA







OFF

2 BSEL /

SCL





OFF

3 EDGE /

HTPLG








OFF

ON

8 1

Default




(I2C mode)






OFF

7:5 CTL[1:3] /

A[1:3] /

DK[1:3]





address.

SW[7, 6, 5] =A[1, 2, 3] =[ON, OFF, OFF] I2C device address: 0111, A3, A2, A1 =0111001 (*1) *1) ON="1", OFF="0"

8 ISEL /

RST#





OFF







(I2C mode)

1 DSEL /

SDA







OFF

2 BSEL /

SCL





OFF

3 EDGE /

HTPLG








OFF

ON

8 1

Default




(I2C mode)






OFF

7:5 CTL[1:3] /

A[1:3] /

DK[1:3]





address.

SW[7, 6, 5] =A[1, 2, 3] =[OFF, ON, OFF] I2C device address: 0111, A3, A2, A1 =0111010 (*1) *1) ON="1", OFF="0"

8 ISEL /

RST#





OFF




3.3.2. I2S (AUDIO)

The Option board has 3 channels as an audio interface. This interface is connected to audio mini-jack and the general-purpose pin header for the connection of the microphone and the speaker.

Table 3-42 I2S (AUDIO) No. Item Model number Manufacturer Quantity Remarks

1 Audio CODEC WM8976 Wolfson 1

2 Audio mini-jack STX-2500-3N KYCON 2 φ3.5

3 Audio speaker FFC-2ASM1 HONDA TSUSHIN 1 1 row, 2 poles



Table 3-43 I2S2 / 3 connector No Signal name I/O Description

1 GND - Ground

2 GND - Ground

3 ECLK I

4 SCK B

5 WS B

6 SDI I

7 SDO O

8 GND - Ground


Table 3-44 I2S1/ I2S2/ I2S3 connector list No Function CH Description

1 Microphone 1 CN4 pin jack

2 1 CN5 pin jack

3

Speaker

1 CN39 pin header 1Pin: Rch 2Pin: Lch

4 Pin header 2 CN19

5 Pin header 3 CN21



3.3.3. CAN

The Option board has 1 channel as the CAN interface. This interface is connected to Dsub9 connector (CN6).

Table 3-45 CAN No. Item Model number Manufacturer Quantity Remarks

1 Transceiver SN65HVD234 TI 1


3 Switch G-12AP Nihon Kaiheiki 1

3.3.4. USART (UART)

The Option board has 3 channels (ch2-ch4) as the UART interface. This interface is connected to the general-purpose pin header. The correspondence of the UART channel and the connector is as follows. Ch2=CN18 Ch3=CN20 Ch4=CN22

Table 3-46 UART No. Item Model number Manufacturer Quantity Remarks



Table 3-47 USART2-4 pin header No Signal name I/O Description

1 TX O Transmission data

2 RX I Reception data



3.3.5. LIN

The Option board has 1 channel (USART ch5) as the LIN interface. This interface is connected to 2pin connector (CN28). The interface of LIN Host and Function can be switched by setting CN27. The power supply to the BAT power pin of the LIN transceiver can select either of the following 2 methods by jumper pin (CN25): Supply the power by the Option board. Input the power from header pin (CN26).

The USART5_SCK signal is connected to sleep pin (Low active) of the device.

Table 3-48 LIN No. Item Model number Manufacturer Quantity Remarks

1 Transceiver TJA1020T NXP 1

2 Connector B2B-PH-SM4-TB JST 1 2 poles

Table 3-49 LIN connector pin assignment No Signal name I/O Description

1 GND - Ground

2 LIN_BUS0 IO LIN signal

Table 3-50 Jumper setting CN Function Description Default

25 LIN PWR 1-2: It is connected to EML (+5V). 2-3: It is connected to USR (external VCC).

1-2

27 LIN Host/Function select Short=Host Open=Function

Open

Figure 3-6 LIN circuit of Option board (Selection of LIN PWR and Host/Function)



3.3.6. SDIO

The Option board has 2 channels of Ch1 (CN31) and Ch2 (CN32) as the SDIO interface. This interface is connected to the SD card slot. The power supply to the SD card is controlled with the pin of MB86R11 (see Figure 3-).

Table 3-51 SDIO No. Item Model number Manufacturer Quantity Remarks

1 SD card slot DM1AA-SF-PEJ HRS 2

No. SD power supply control pin SD card Remarks

1 INT_A5 (GPIO19) SD CH0 0: PWR ON (It is mounted on the Base board.)



Figure 3-7 SDIO circuit of Option board



3.3.7. PWM

The Option board has 12 channels as the PWM interface. This interface is connected to the pin header (CN29 and CN30). CN29 is connected with CR integrating circuit, and CN30 is not connected with it.

Table 3-52 PWM No. Item Model number Manufacturer Quantity Remarks

1 Register 1.1kΩ ROHM 12

1 Capacitor 0.01µF Murata Manufacturing

12



Table 3-53 PWM connector pin assignment No Signal name I/O Description

1 PWM0 O PWM CH0

2 PWM 1 O PWM CH1

3 PWM 2 O PWM CH2

4 PWM 3 O PWM CH3

5 PWM 4 O PWM CH4

6 PWM 5 O PWM CH5

7 PWM 6 O PWM CH6

8 PWM 7 O PWM CH7

9 PWM 8 O PWM CH8

10 PWM 9 O PWM CH9

11 PWM 10 O PWM CH10

12 PWM 11 O PWM CH11

13 GND - Ground

14 GND - Ground




3.3.8. IrDA

The Option board has general-purpose connector (CN24) as the IrDA.

Table 3-54 IrDA No. Item Model number Manufacturer Quantity Remarks

1 General-purpose connector


Table 3-55 IrDA connector pin assignment No Signal name I/O Description

1 XIN I

2 IRTX O

3 IRRX1 I

4 ID0 I

5 ID1 I

6 ID2 I

7 ID3 I

8 IRSL0 O

9 IRSL1 O

10 IRSL2 O

11 GND - Ground

12 GND - Ground




3.3.9. IDE

The Option board has ATA2.5inch connector (CN33) as the IDE interface. The connection specification is Host.

Table 3-56 IDE No. Item Model number Manufacturer Quantity Remarks

1 ATA connector WCAW-20-2-22PW MAC8 1

Table 3-57 IDE connector pin assignment No Signal name I/O Description No Signal name I/O Description

1 XDRESET O 23 XDIOW O


3 DD7 B 25 XDIOR O

4 DD8 B 26 GND - Ground

5 DD6 B 27 DIORDY I

6 DD9 B 28 CSEL I

7 DD5 B 29 XDDMACK O


9 DD4 B 31 DINTRQ I

10 DD11 B 32 XIOCS16 O

11 DD3 B 33 DA1 O

12 DD12 B 34 XCBLID O

13 DD2 B 35 DA0 O

14 DD13 B 36 DA2 O

15 DD1 B 37 XDCS0 O

16 DD14 B 38 XDCS1 O

17 DD0 B 39 XDASP I


19 GND - Ground 41 +5V -

20 N.C. - 42 +5V -

21 DDMARQ I 43 GND - Ground

22 GND - Ground 44 N.C. -




3.3.10. SPI-FLASH (Quad)

The Option board has the SPI-FLASH (Quad) interface. This interface is connected to the SPI-FLASH of 32Mbit and the general-purpose pin header.

Table 3-58 SPI-FLASH (Quad) No. Item Model number Manufacturer Quantity Remarks

1 SPI-FLASH (Quad) S25FL064P Spansion 1 64Mbit

3.3.11. SPI-FLASH (Single)

The Option board has 32Mbit as SPI-FLASH (Single).

Table 3-59 SPI-FLASH (Single) No. Item Model number Manufacturer Quantity Remarks

1 SPI-FLASH (Single) W25Q32BVSSIG Winbond 1 32Mbit

3.3.12. I2C

The Option board has 3 channels (Ch2-Ch4) as the I2C interface. This interface is connected to the general-purpose pin header. I2C2-I2C3 and I2C3-I2C4 can be looped by the jumper pin. The correspondence of the I2C channel and the connector is as follows.

Ch2=CN14 Ch3=CN15 Ch4=CN16

Table 3-60 I2C No. Item Model number Manufacturer Quantity Remarks


FFC-3ASM1 HONDA TSUSHIN 3 1 row, 3 poles

Table 3-61 I2C pin assignment No Signal name I/O Description

1 SCL IO SCL

2 SDA IO SDA

3 GND - Ground

Table 3-62 I2C setting CN Function Description

37 I2C2-I2C3 SCL

38 I2C2-I2C3 SDA

Short=Loop-back Open=Normal

40 I2C3-I2C4 SCL

41 I2C3-I2C4 SDA

Short= Loop-back Open= Normal



3.3.13. General-purpose ADC

The Option board has general-purpose connector (CN1) as the general-purpose ADC interface. This interface is connected to the operational amplifier. The operational amplifier power supply connects +3.3V with the plus side, and connects GND with the minus side.

Table 3-63 General-purpose ADC connector pin assignment No. Item Model number Manufacturer Quantity Remarks

1 ADC connector FFC-2ASM1 HONDA TSUSHIN 1 2 rows, 10 poles

Table 3-64 General-purpose ADC connector pin assignment No Signal name I/O Description

1 VIN0 I Analog input CH0

2 VR0 O Reference voltage output CH0

3 VRH0 I High side voltage input CH0

4 VRL0 I Low side voltage input CH0

5 VIN1 I Analog input CH1

6 VR1 O Reference voltage output CH1

7 VRH1 I High side voltage input CH1

8 VRL1 I Low side voltage input CH1

9 +3.3V - Power supply

10 GND - Ground

Note:

The CN11-16 of the CPU board must "OPEN" when this connector is used.



3.3.14. TCON

The Option board has general-purpose pin header (CN34) as the TCON interface.

Table 3-65 TCON No. Item Model number Manufacturer Quantity Remarks

1 TCON OQW-11-4.2-07PW Mac8 1 2 rows, 14 poles

Table 3-66 TCON connector pin assignment No Signal name I/O Description

1 TS0 I/O

2 TS1 I/O

3 TS2 I/O

4 TS3 I/O

5 TS4 I/O

6 TS5 I/O

7 TS6 I/O

8 TS7 I/O

9 TS8 I/O

10 TS9 I/O

11 TS10 I/O

12 TS11 I/O

13 GND - Ground

14 GND - Ground


3.3.15. External INT

The Option board has 7 channels as the External INT interface. The 5 ports are connected to a general-purpose connector (CN36).

Table 3-67 EIRQ No. Item Model number Manufacturer Quantity Remarks



Table 3-68 External INT connector pin assignment No Signal name I/O Description

1 INT_A[2] I External INT2

2 GND - Ground

3 Reserved - -

4 Reserved - -

5 Reserved - -

6 Reserved - -

7 GND - Ground

8 GND - Ground


53 4. CPU – Base board I/F


4. Board interface

4.1. CPU – Base board I/F The CPU board and the Base board are connected by two 160pin stack connectors.

Table 4-1 CPU – Base board I/F No. Item Model number Manufacturer Quantity Remarks

1 Connector receptacle 52837-1679 Molex 2 Base Board

2 Connector header 53647-1674 Molex 2 CPU Board



The connector pin assignment is shown as follows.

Table 4-2 Stack connector pin assignment [CPU (CN8), Base (CN31)] (1/2) No. Name No. Name

A1 +5V B1 +5V

A2 +5V B2 +5V

A3 +3.3V B3 +3.3V

A4 +3.3V B4 +3.3V

A5 DISP0G0 B5 DISP0G4




A8 DISP0R0 B8 DISP0R4



A12 DISP0R3 B12 DISP0R7 A13 GND B13 GND

A14 DISP0CLKO B14 DISP0CLKI

A15 DISP0CLKOX B15 GND

A16 GND B16 DISP0DE

A17 N.C B17 DISP0GV

A18 MEM_MNREX B18 MEM_XWR3

A19 MEM_MNWEX B19 MEM_XWR2

A20 MEM_ALE B20 MEM_XWR1

A21 MEM_CLE B21 MEM_XWR0

A22 MEM_RDY B22 GND

A23 MEM_XRD B23 MEM_CLK A24 GND B24 GND

A25 MEM_ED31 B25 MEM_ED23







A32 MEM_ED24 B32 MEM_ED16 A33 GND B33 GND

A34 MEM_EA26 B34 MEM_EA13















A46 MEM_EA14 B46 MEM_EA1 A47 GND B47 GND









A56 MEM_XCS0 B56 MLB_SIG

A57 MEM_XCS1 B57 MLB_DATA

A58 MEM_XCS2 B58 MLB_CLK A59 GND B59 GND

A60 CAN0_TX B60 CAN0_RX

A61 CAN1_TX B61 CAN1_RX

A62 GND B62 SPI0_SS

A63 SPI0_SCK B63 SPI0_DO

A64 GND B64 SPI0_DI

A65 I2C0_SCL B65 I2C0_SDA

A66 I2C1_SCL B66 I2C1_SDA

A67 INT_A0 B67 INT_A4



A70 N.C B70 INT_A7

A71 N.C B71 N.C

A72 N.C B72 N.C A73 GND B73 GND

A74 N.C B74 N.C

A75 MPXMODE0 B75 N.C

A76 MPXMODE1 B76 N.C

A77 MPXMODE2 B77 XRST

A78 N.C B78 N.C A79 GND B79 GND

A80 GND B80 GND




A1 +3.3V B1 +3.3V

A2 +3.3V B2 +3.3V

A3 DISP0B0 B3 DISP0B4




A7 DISP0HSYNC B7 DISP0VSYNC

A7 GND B7 DISP0CSYNC A8 GND B8 GND

A10 USART0_SCK B10 USART1_SCK

A11 USART0_SOUT B11 USART1_SOUT

A12 USART0_SIN B12 USART1_SIN







A19 PWM_O6 B19 PWM_O8

A20 PWM_O7 B20 GND

A21 GND B21 GND

A22 SD0DAT0 B22 SD0DAT2


A24 ISD0CD B24 ISD0WP

A25 SD0CMD B25 OSDCLK0

A26 I2S0_SDO B26 I2S1_SDO

A27 I2S0_SDI B27 I2S1_SDI

A28 I2S0_WS B28 I2S1_WS

A29 I2S0_SCK B29 I2S1_SCK

A30 I2S0_ECLK B30 I2S1_ECLK A31 GND B31 GND

A32 DISP1VI_0 B32 DISP1VI_4



A35 DISP1VI_3 B35 DISP1VI_7 A36 GND B36 GND

A37 GND B37 DISP1CLK A38 GND B38 GND

A39 AD_VIN0 B39 AD_VIN1

A40 AD_VRH0 B40 AD_VRH1




A41 AD_VRL0 B41 AD_VRL1

A42 SELFL B42 N.C

A43 AD_VR0 B43 AD_VR1

A44 CAP3VI_0 B44 CAP3VI_4



A47 CAP3VI_3 B47 CAP3VI_7 A48 GND B48 GND

A49 CAP3CLK B49 CAP2CLK A50 GND B50 GND








A58 CAP1VI_3 B58 CAP1VI_7 A59 GND B59 GND

A60 CAP0CLK B60 CAP1CLK A61 GND B61 GND

A62 CAP0R0 B62 CAP0R4



A65 CAP0R3 B65 CAP0R7 A66 GND B66 GND

A67 CAP0G0 B67 CAP0G4




A71 CAP0B0 B71 CAP0B4




A75 CAP0VS B75 CAP0FID

A76 CAP0HS B76 CAP0VAL A77 TRACEEN0 B77 GND

A78 TRACEEN1 B78 XSRST A79 GND B79 GND

A80 GND B80 GND

58 5. Base – Option board I/F


4.2. Base – Option board I/F The Base board and the Option board are connected by 160pin stack connector.

Table 4-4 Base – Option board I/F No. Item Model number Manufacturer Quantity Remarks

1 Connector receptacle 52837-1679 Molex 2 Base board

2 Connector header 53647-1674 Molex 2 Option board



The connector pin assignment is shown as follows.

Table 4-5 Stack connector pin assignment [Base (CN7), Option (CN33)] (1/2) No. Name No. Name

A1 3V B1 3V

A2 3V B2 3V

A3 QD0SCK B3 QD0SDI0

A4 GND B4 QD0SDI1

A5 QD0SEL0 B5 QD0SDI2

A6 QD0SEL1 B6 QD0SDI3

A7 QD0SEL2 B7 QD0SEL3

A7 GND B7 GND

A8 GND B8 GND

A10 OSDCLK1 B10 SD1DATA0

A11 SD1CMD B11 SD1DATA1

A12 ISD1WP B12 SD1DATA2

A13 ISD1CD B13 SD1DATA3

A14 GND B14 GND

A15 GND B15 GND

A16 GND B16 GND

A17 AD_VIN0 B17 AD_VRH0

A18 AD_VR0 B18 AD_VRL0

A19 AD_VIN1 B19 AD_VRH1

A20 AD_VR1 B20 AD_VRL1

A21 GND B21 GND

A22 GND B22 GND

A23 GND B23 GND

A24 DISP2B7 B24 DISP0R7








A32 GND B32 GND












A41 GND B41 GND

A42 DISP0CKP B42 DISP0CKN

A43 GND B43 GND

A44 DISP2R7 B44 DISP0B7








A52 GND B52 GND

A53 GND B53 DISP0DE

A54 I2S1_SCL B54 DISP0HD

A55 I2S1_SDA B55 DISP0VD

A56 GND B56 GND

A57 DISP2GV B57 DISP1R7

A58 DISP2DE B58 DISP1R6

A59 DISP2CSYNC B59 DISP1R5

A60 DISP2VD B60 DISP1R4

A61 DISP2HD B61 DISP1R3

A62 GND B62 GND

A63 DISP2CKO B63 -

A64 GND B64 GND

A65 DISP1VD B65 DISP1R2

A66 DISP1HD B66 DISP1R1

A67 DISP1DE B67 DISP1R0

A68 GND B68 GND

A69 DISP1B0 B69 DISP1G7








A77 GND B77 GND

A78 DSIP1CKO B78 -

A79 GND B79 GND

A80 GND B80 GND




A1 3V B1 3V

A2 3V B2 3V

A3 PWM_O0 B3 PWM_O2

A4 PWM_O1 B4 PWM_O3

A5 I2S2_ECLK B5 I2S2_SDI

A6 I2S2_SCK B6 I2S2_SDO

A7 I2S2_WS B7 GPIO86

A7 GND B7 GND

A8 BUF_EN_RSV B8 SDIO_MMC2

A10 SD_PWR1 B10 SDIO_MMC1

A11 SD_PWR2 B11 GND






A17 USART2_SIN B17 USART3_SIN A18 GND B18 GND

A19 SPI1HOLD B19 SPI1SCK

A20 SPI1DO B20 SPI1SS

A21 SPI1DI B21 GND

A22 GND B22 GND


A24 - B24 INT_A6

A25 INT_A4 B25 INT_A7 A26 GND B26 GND

A27 GND B27 I2S3SCK

A28 I2S3WS B28 I2S3SDI

A29 I2S3ECLK B29 I2S3SDO

A30 GND B30 GND



A33 USART4_SIN B33 USART5_SIN A34 UART2_XCTS B34 UART3_XCTS

A35 PWM_O6 B35 PWM_O8

A36 PWM_O7 B36 GND

A37 GND B37 GND



A40 ISD0CD B40 ISD0WP




A41 SD0CMD B41 OSDCLK0 A42 GND B42 GND

A43 I2S0_SDO B43 I2S1_SDO

A44 I2S0_SDI B44 I2S1_SDI

A45 I2S0_WS B45 I2S1_WS A46 GND B46 GND

A47 I2S0_SCK B47 I2S1_SCK A48 GND B48 GND

A49 I2S0_ECLK B49 I2S1_ECLK A50 GND B50 GND




A54 DISP1VI_3 B54 DISP1VI_7 A55 GND B55 GND

A56 GND B56 DISP1CLK A57 GND B57 GND

A58 CAN1_TX B58 CAN1_RX A59 GND B59 GND

A60 I2S2 B60 I2S3

A61 GND B61 GND

A62 CAP1CLK B62 CAP1VI_0

A63 GND B63 CAP1VI_1


A65 CAP1VI_5 B65 CAP1VI_3 A66 QUADSPI0_A B66 GND

A67 QUADSPI0_B B67 PWM4_5

A68 PWM6_8 B68 PWM0_3

A69 INT4_7 B69 I2C2

A70 INT_0_3 B70 SPI1_C

A71 USART0_2 B71 USART3

A72 USART4_5 B72 IRDA

A73 TCON B73 QUADSPI1_E

A74 IDE66 B74 I2S1

A75 QUADSPI1_F B75 -

A76 PWM9_11 B76 I2C3_4

A77 XSRST1 B77 CAN1

A78 GND B78 GND

A79 GND B79 GND

A80 5V B80 5V

63 6. Customer I/F


4.3. Customer I/F The Base board and the Customer's board are connected by 100pin connector.

Table 4-7 Connector for Customer's board connection (CN38) No. Item Model number Manufacturer Quantity Remarks

1 Right angle connector 87BFN100R-3F KEL 1 Receptacle

64 6. Customer I/F


Table 4-8 Customer's board connector (1/2) No. Name I/O No. Name I/O

99 3V - 100 3V -

97 3V - 98 3V -

95 GND - 96 GND -

93 GND - 94 GND -

91 MEM_MNREX O 92 MEM_XWR3 O

89 MEM_MNWEX O 90 MEM_XWR2 O

87 MEM_ALE O 88 MEM_XWR1 O

85 MEM_CLE O 86 MEM_XWR0 O

83 MEM_RDY I 84 MEM_XRD O

81 GND - 82 GND -

79 GND - 80 MEM_CLK O

77 GND - 78 GND -

75 MEM_ED31 B 76 MEM_ED23 B








59 GND - 60 GND -

57 MEM_EA26 O 58 MEM_EA13 O






45 GND - 46 GND -








29 GND - 30 GND -





65 6. Customer I/F


Table 4-8 Customer's board connector (2/2) No. Name I/O No. Name I/O

19 GND - 20 GND -





9 GND - 10 INT_A7 -

7 MEM_XCS0 O 8 XSRST1 -

5 MEM_XCS1 O 6 MEM_XCS2 O

3 GND - 4 GND -

1 GND - 2 GND -

66 9. Allocation of peripheral resource and I2C port


5. Memory map

5.1. MB86R11EVB memory map MB86R11EVB memory map is shown as follows.

Table 5-1 Memory map

Class Attributes Device Physical Address Remarks

SFI0 EEPROM (32KB) 0x06000000-0x06007FFF

SFI1 SPI-FLASH (4MB) 0x16000000-0x163FFFFF

SDRAM bus Bus width=32bit DDR2 (256MB) 0x40000000-0x47FFFFFF

External bus CS0#

Bus width=16bit Nor Flash (64MB) 0xE0000000-0xE3FFFFFF

NAND Flash (256MB) 0xE0000000-0xEFFFFFFF Cannot used

CS#1

Bus width=16bit/32bit FPGA (4KB) 0xEC000000-0xEC000FFF

CS#2

Bus width=16bit Customer External board 0xE8000000-0xEBFFFFFF

5.2. FPGA register

5.2.1. FPGA register list

Table 5-2 register list

Address[h] Name Function

00 VERSION Version register

04 PINMUX PINMUX register

08 DEVICE_SEL DEVICE_SEL register

0C～FF ACC_TEST Test register (*)

* Setting of the SW19(DEVICE_SEL) bit[8:6]=[ON,ON,OFF]. Address is 1 word. It is overwrited when writing at a different address.

Table 5-3 Access type

meaning Sign

Read Write

R/W possible possible

R possible Invalid

Read/Write value of the reserved bit is 0.



5.2.2. VERSION register

VERSION(00h)

bit 31 30 29 28 27 26 25 24

R/W R

Initial 0000_0000

Name Reserved

bit 23 22 21 20 19 18 17 16

R/W R

Initial 0000_0000

Name Reserved

bit 15 14 13 12 11 10 9 8

R/W R

Initial xxxx_xxxx

Name Version

bit 7 6 5 4 3 2 1 0

R/W R

Initial xxxx_xxxx

Name Revision

Revison(bit7-0) FPGA Revision Version(bit15-8) FPGA Version



5.2.3. PINMUX register

PINMUX(04h)

bit 31 30 29 28 27 26 25 24

R/W R R R

Initial 0000 xxx x

Name Reserved G_I G_H

bit 23 22 21 20 19 18 17 16

R/W R R R

Initial xx xxx xxx

Name G_H G_G G_F

bit 15 14 13 12 11 10 9 8

R/W R R R R

Initial 0 xxx xxx x

Name Reserved

G_E G_D G_C

bit 7 6 5 4 3 2 1 0

R/W R R R

Initial xx xxx 000

Name G_C G_B Reserved

The read value of PINMUX is changed by the DIPSW setting. 000 : mode0 001 : mode1 010 : mode2 011 : mode3 100 : mode4 101 : mode5



G_B(bit5-3) Set value of SW_CB[3:1](Base Board SW10) Read attribute : ON=”L” G_C(bit8-6) SW_CB[6:4](Base BoardのSW10) set value Read attribute : ON=”L” G_D(bit11-9) SW_ED[1](Base Board SW11) set value SW_ED[1]=ON(mode0) : ”000”, OFF(mode5) : ”101” G_E(bit14-12) SW_ED[6:4](Base Board SW11) set value Read attribute : ON=”L” G_F(bit18-16) SW_GF[3:1](Base Board SW12) set value Read attribute : ON=”L” G_G(bit21-19) SW_GF[6:4](Base Board SW12) set value Read attribute : ON=”L” G_H(bit24-22) SW_IH[3:1](Base Board SW14) set value Read attribute : “ON”=”L” G_I(bit27-25) SW_IH[6:4](Base Board SW14) set value Read attribute : ON=”L”



5.2.4. DEVICE_SEL register

DEVICE_SEL(08h)

Bit 31 30 29 28 27 26 25 24

R/W R

Initial 0000_0000

Name Reserved

Bit 23 22 21 20 19 18 17 16

R/W R R

Initial 000_0000 x

Name Reserved MPXMODE[2]

bit 15 14 13 12 11 10 9 8

R/W R

Initial xxxx_xxxx

Name DEVICE_SEL

bit 7 6 5 4 3 2 1 0

R/W R R R R

Initial 0000 x 0 xx

Name Reserved SELFL Reserved MPXMODE[1:0]

MPXMODE[1:0](bit1-0) MPXMODE[1:0](CPU Board SW3) set value Read attribute : ON=”H” SELFL(bit2) SELFL(CPU Board SW1) set value Read attribute : NOR=”L” DEVICE_SEL(bit15-8) DEVICE_SEL(Base Board SW19) set value Read attribute : ON=”L” MPXMODE[2](bit16) MPXMODE[2](CPU Board SW3) set value Read attribute : ON=”H”



5.2.5. ACC_TEST register

ACC_TEST(0C～FF)

bit 31 30 29 28 27 26 25 24

R/W R/W

Initial 0000_0000

Name ACC_TEST

bit 23 22 21 20 19 18 17 16

R/W R/W

Initial 0000_0000

Name ACC_TEST

Bit 15 14 13 12 11 10 9 8

R/W R/W

Initial 0000_0000

Name ACC_TEST

Bit 7 6 5 4 3 2 1 0

R/W R/W

Initial 0000_0000

Name ACC_TEST

ACC_TEST(bit31-0) Access Test register.

Setting of the SW19(DEVICE_SEL) bit[8:6]=[ON,ON,OFF]. The access except the above setting is “Hi-Z”. Address is 1 word. It is overwrited when writing at a different address.



5.2.6. FPGA signal timing

FPGA signal timing is shown as follows.

MEM_CLK

MEM_XCS[1]

MEM_XRD

Read Write

MEMCS register min setting

RACC : 1 (2cycle)RADC : 0 (0cycle)

RIDLC : 0(1cycle)WACC : 2(3cycle)

WADC : 0(1cycle)WWEC : 0(1cycle)WIDLC : 0(1cycle)

MEM_EA[11:0]

MEM_ED[31:0]

0XX 0XX

Read Data Write Data

MEM_XWRx

RIDLC WIDLC

Figure 5-1 Access timing Remarks

The frequency of MEM_CLK is 100MHz less. The half word and word can be access. FPGA is the connection of MEM_EA[11:1]. MEM_EA[26:12] is not decode. The register of 00-08h address can be read any time. The judgment of the 16bit/32bit connection of the Ex-bus width uses MPXMODE[2].



6. Allocation of peripheral resource and I2C port MB86R11EVB has the I2C port of 5 channels. Ch0 and Ch1 of I2C are allocated in the control of the peripheral resource. The slave address must not overlap if you use the port allocated in the peripheral resource for the interface with the outside.

Table 6-1 Allocation of peripheral resource and I2C port

Peripheral resource I2C port

Group Slave address Remarks

Control 0100000 CAP0_VDEC

VBI 0010000 ALSB=0


VBI 0010010 ALSB=1

DISP0_VDAC － 0101010 ALSB=0

DISP0_DVI - 0111000 Low order 3 bits are variable.


CH0

AMP(AUDIO) － 0011010


VBI 0010000 ALSB=0


VBI 0010010 ALSB=1

AMP(AUDIO) － 0011010



CH1


CH2

CH3

CH4

74 10. Power system diagram


7. Power system diagram The power system diagram is shown as follows.

Figure 7-1 Power system diagram of Base board



The power supply of +5V and +3.3V is supplied from the Base board to CPU board through the stack connector.

Figure 7-2 Power system diagram of CPU board



The power supply of +5V and +3.3V is supplied from the Base board to Option board through the stack connector.

Figure 7-3 Power system diagram of Option board

77 11. Clock system diagram


8. Clock system diagram The clock system diagram of MB86R11EVB is shown as follows.

Figure 8-1 Clock system diagram of MB86R11EVB

Documents

MB86R11 Evaluation Board - Fujitsu€¦ · In MB86R11EVB, to realize the switching of each resource according to the setting mode by an enable control, the buffer is inserted between