MAX5078.PDF

General DescriptionThe MAX5078A/MAX5078B high-speed MOSFET driverssource and sink up to 4A peak current. These devicesfeature a fast 20ns propagation delay and 20ns rise andfall times while driving a 5000pF capacitive load.Propagation delay time is minimized and matchedbetween the inverting and noninverting inputs. Highsourcing/sinking peak currents, low propagation delay,and thermally enhanced packages make the MAX5078A/MAX5078B ideal for high-frequency and high-power circuits.

The MAX5078A/MAX5078B operate from a 4V to 15Vsingle power supply and consume 40A (typ) of supplycurrent when not switching. These devices have aninternal logic circuitry that prevents shoot-through duringoutput state changes to minimize the operating currentat a high switching frequency. The logic inputs are pro-tected against voltage spikes up to +18V, regardless ofthe VDD voltage. The MAX5078A has CMOS input logiclevels while the MAX5078B has TTL-compatible inputlogic levels.

The MAX5078A/MAX5078B feature both inverting andnoninverting inputs for greater flexibility in controlling theMOSFET. They are available in a 6-pin TDFN (3mm x3mm) package and operate over the automotive temper-ature range of -40C to +125C.

ApplicationsPower MOSFET Switching Motor Control

Switch-Mode Power Supplies Power-Supply Modules

DC-DC Converters

Features 4V to 15V Single Power Supply 4A Peak Source/Sink Drive Current 20ns (typ) Propagation Delay Matching Delay Between Inverting and

Noninverting Inputs VDD / 2 CMOS (MAX5078A)/TTL (MAX5078B) Logic

Inputs 0.1 x VDD (CMOS) and 0.3V (TTL) Logic-Input

Hysteresis Up to +18V Logic Inputs (Regardless of VDD

Voltage) Low Input Capacitance: 2.5pF (typ) 40A (typ) Quiescent Current -40C to +125C Operating Temperature Range 6-Pin TDFN Package

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4A, 20ns, MOSFET Driver

________________________________________________________________ Maxim Integrated Products 1

Ordering Information

MAX5078AMAX5078B

VDD

IN+

IN-

OUT

GND

4V TO 15V

N

PWM IN

Typical Operating Circuit

19-3346; Rev 1; 9/05

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxims website at www.maxim-ic.com.

*EP = Exposed pad.

PART TEMPRANGEPIN-PACKAGE

TOPMARK

PKGCODE

MAX5078AATT-40C to+125C

6 TDFN-EP* AHL T633-1

MAX5078BATT-40C to+125C

6 TDFN-EP* AHM T633-1

Selector Guide

PART PIN-PACKAGE LOGIC INPUTMAX5078AATT 6 TDFN-EP VDD / 2 CMOS

MAX5078BATT 6 TDFN-EP TTL

6 IN+1IN-

TDFN-EP

TOP VIEW

GND 2

GND 3

OUT5

VDD4

MAX5078

Pin Configuration


2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS(VDD = 4V to 15V, TA = -40C to +125C, unless otherwise noted. Typical values are at VDD = 15V and TA = +25C.) (Note 1)

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functionaloperation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure toabsolute maximum rating conditions for extended periods may affect device reliability.

(Voltages referenced to GND.)VDD ..............................................................................-0.3V to +18VIN+, IN- ........................................................................-0.3V to +18VOUT .................................................................-0.3V to (VDD + 0.3V)OUT Short-Circuit Duration.......................................................10msContinuous Source/Sink Current at OUT_ (PD < PDMAX).....200mA

Continuous Power Dissipation (TA = +70C)6-Pin TDFN-EP (derate 18.2mW/C above +70C) .......1454mW

Junction-to-Case Thermal Resistance (JC) .......................8.5C/WOperating Temperature Range..............................-40C to +125CStorage Temperature Range .................................-65C to +150CJunction Temperature...........................................................+150CLead Temperature (soldering, 10s)......................................+300C

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PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITSPOWER SUPPLYVDD Operating Range VDD 4 15 V

VDD Undervoltage Lockout UVLO VDD rising 3.00 3.5 3.85 V

VDD Undervoltage LockoutHysteresis

200 mV

VDD Undervoltage Lockout toOutput Delay

VDD rising 12 s

VDD = 4V 28 55IDD

IN+ = 0V, IN- = VDD(not switching) VDD = 15V 40 75

AVDD Supply Current

IDD-SW Switching at 250kHz, CL = 0 0.5 1.2 2.2 mA

DRIVER OUTPUT (SINK)TA = +25C 1.1 1.8VDD = 15V,

IOUT = -100mA TA = +125C 1.5 2.4

TA = +25C 2.2 3.3Driver Output Resistance PullingDown

RON-NVDD = 4.5V,IOUT = -100mA TA = +125C 3.0 4.5

Peak Output Current (Sinking) IPK-N VDD = 15V, CL = 10,000pF 4 A

VDD = 4.5V 0.45Output-Voltage Low IOUT = -100mA

VDD = 15V 0.24V

Latchup Protection ILUP Reverse current IOUT (Note 2) 400 mA

DRIVER OUTPUT (SOURCE)TA = +25C 1.5 2.1VDD = 15V,

IOUT = 100mA TA = +125C 1.9 2.75

TA = +25C 2.75 4Driver Output Resistance PullingUp

RON-PVDD = 4.5V,IOUT = 100mA TA = +125C 3.75 5.5

Peak Output Current (Sourcing) IPK-P VDD = 15V, CL = 10,000pF 4 A

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_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)(VDD = 4V to 15V, TA = -40C to +125C, unless otherwise noted. Typical values are at VDD = 15V and TA = +25C.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

VDD = 4.5VVDD -0.55

Output-Voltage High IOUT = 100mA

VDD = 15VVDD -0.275

V

LOGIC INPUT (Note 3)

MAX5078A0.7 xVDDLogic 1 Input Voltage VIH

MAX5078B (Note 4) 2.1

V

MAX5078A0.3 xVDDLogic 0 Input Voltage VIL

MAX5078B 0.8

V

MAX5078A0.1 xVDDLogic-Input Hysteresis VHYS

MAX5078B 0.3

V

Logic-Input-Current Leakage IN+ = IN- = 0V or VDD -1 +0.1 +1 A

Input Capacitance CIN 2.5 pF

SWITCHING CHARACTERISTICS FOR VDD = 15V (Figure 1)CL = 1000pF 4

CL = 5000pF 18OUT Rise Time tRCL = 10,000pF 32

ns

CL = 1000pF 4

CL = 5000pF 15OUT Fall Time tFCL = 10,000pF 26

ns

Turn-On Delay Time tD-ON CL = 10,000pF (Note 2) 10 20 34 ns

Turn-Off Delay Time tD-OFF CL = 10,000pF (Note 2) 10 20 34 ns

SWITCHING CHARACTERISTICS FOR VDD = 4.5V (Figure 1)CL = 1000pF 7

CL = 5000pF 37OUT Rise Time tRCL = 10,000pF 85

ns

CL = 1000pF 7

CL = 5000pF 30OUT Fall Time tFCL = 10,000pF 75

ns

Turn-On Delay Time tD-ON CL = 10,000pF (Note 2) 18 35 70 ns

Turn-Off Delay Time tD-OFF CL = 10,000pF (Note 2) 18 35 70 ns

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4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)(VDD = 4V to 15V, TA = -40C to +125C, unless otherwise noted. Typical values are at VDD = 15V and TA = +25C.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITSMATCHING CHARACTERISTICS

VDD = 15V, CL = 10,000pF 2Mismatch Propagation Delays fromInverting and Noninverting Inputs toOutput

tON-OFFVDD = 4.5V, CL = 10,000pF 4

ns

Note 1: All devices are 100% tested at TA = +25C. Specifications over -40C to +125C are guaranteed by design.Note 2: Limits are guaranteed by design, not production tested.Note 3: The logic-input thresholds are tested at VDD = 4V and VDD = 15V.Note 4: TTL compatible with reduced noise immunity.

RISE TIME vs. SUPPLY VOLTAGE(CL = 5000pF)

MAX

5078

toc0

1

SUPPLY VOLTAGE (V)

RISE

TIM

E (n

s)

14121086

10

20

30

40

50

60

04 16

TA = +125C

TA = +25C

TA = -40C

FALL TIME vs. SUPPLY VOLTAGE(CL = 5000pF)

MAX

5078

toc0

2

TA = +125C

TA = +25C

TA = -40C

FALL

TIM

E (n

s)

10

20

30

40

50

60

0

SUPPLY VOLTAGE (V)141210864 16

PROPAGATION DELAY TIME,LOW-TO-HIGH vs. SUPPLY VOLTAGE

(CL = 5000pF)

MAX

5078

toc0

3

TA = +125C

TA = +25C

TA = -40C

PROP

AGAT

ION

DELA

Y (n

s)

10

20

30

40

50

60

0


MAX

5078

toc0

4

PROPAGATION DELAY TIME,HIGH-TO-LOW vs. SUPPLY VOLTAGE

(CL = 5000pF)

TA = +125C

TA = +25C

TA = -40C

PROP

AGAT

ION

DELA

Y (n

s)

10

20

30

40

50

60

0


IDD-SW SUPPLY CURRENTvs. SUPPLY VOLTAGE

MAX

5078

toc0

5

SUPPLY VOLTAGE (V)

I DD-

SW S

UPPL

Y CU

RREN

T (m

A)

14121086

1

2

3

4

5

6

04 16

DUTY CYCLE = 50%VDD = 15V, CL = 0

1MHz

50kHz100kHz

500kHz

SUPPLY CURRENT vs. SUPPLY VOLTAGEM

AX50

78 to

c06

SUPPLY VOLTAGE (V)

SUPP

LY C

URRE

NT (m

A)

14121086

10

20

30

40

50

60

70

80

90

100

04 16

DUTY CYCLE = 50%VDD = 15V, CL = 4700pF

1MHz

50kHz100kHz

500kHz

Typical Operating Characteristics(TA = +25C, unless otherwise noted.)

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_______________________________________________________________________________________ 5

INPUT THRESHOLD VOLTAGEvs. SUPPLY VOLTAGE

MAX

5078

toc0

7

SUPPLY VOLTAGE (V)

INPU

T TH

RESH

OLD

VOLT

AGE

(V)

14121086

1

2

3

4

5

6

7

8

9

10

04 16

MAX5078A(CMOS INPUT)

VIN RISING

VIN FALLING

MAX

5078

toc0

8

SUPPLY VOLTAGE (V)

INPU

T TH

RESH

OLD

VOLT

AGE

(V)

14121086

0.5

1.0

1.5

2.0

2.5

3.0

04 16

INPUT THRESHOLD VOLTAGEvs. SUPPLY VOLTAGE

VIN RISING

VIN FALLING

MAX5078B(TTL INPUT)

SUPPLY CURRENT vs. LOGIC-INPUTVOLTAGE (INPUT LOW-TO-HIGH)

MAX

5078

toc0

9

LOGIC-INPUT VOLTAGE (V)

SUPP

LY C

URRE

NT (

A)

1412108642

100

200

300

400

500

00 16

MAX5078B (TTL INPUT)VDD = 15V

MAX

5078

toc1

0


SUPP

LY C

URRE

NT (

A)

1412108642

100

200

300

400

500

00 16

SUPPLY CURRENT vs. LOGIC-INPUTVOLTAGE (INPUT HIGH-TO-LOW)

MAX5078B (TTL INPUT)VDD = 15V

MAX

5078

toc1

1


SUPP

LY C

URRE

NT (m

A)

1412108642

1

2

3

4

5

00 16

SUPPLY CURRENT vs. LOGIC-INPUTVOLTAGE (INPUT LOW-TO-HIGH)

MAX5078A (CMOS INPUT)VDD = 15V

MAX

5078

toc1

2


SUPP

LY C

URRE

NT (m

A)

1412108642

1

2

3

4

5

00 16

SUPPLY CURRENT vs. LOGIC-INPUTVOLTAGE (INPUT HIGH-TO-LOW)

MAX5078A (CMOS INPUT)VDD = 15V

DELAY MISMATCH BETWEEN IN+AND IN- TO OUT vs. TEMPERATURE

MAX

5078

toc1

3

TEMPERATURE (C)

DELA

Y M

ISM

ATCH

(ns)

1007550250-25

-4

-2

0

2

4

6

-6-50 125

OUTPUT FALLING

OUTPUT RISING

MAX5078A (CMOS INPUT)VDD = 4.5V, CL = 10,000pF

MAX

5078

toc1

4

TEMPERATURE (C)

DELA

Y M

ISM

ATCH

(ns)

1007550250-25

-4

-2

0

2

4

6

-6-50 125

DELAY MISMATCH BETWEEN IN+AND IN- TO OUT vs. TEMPERATURE

OUTPUT FALLING

OUTPUT RISING

MAX5078A (CMOS INPUT)VDD = 15V, CL = 10,000pF

LOGIC-INPUT VOLTAGE vs. OUTPUT VOLTAGE(VDD = 4V, CL = 5000pF)

MAX5078 toc15

IN-2V/div

20ns/div

OUT2V/div

IN+ = VDD

Typical Operating Characteristics (continued)(TA = +25C, unless otherwise noted.)

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6 _______________________________________________________________________________________


MAX5078 toc16

40ns/div

LOGIC-INPUT VOLTAGE vs. OUTPUT VOLTAGE(VDD = 4V, CL = 10,000pF)

IN-2V/div

OUT2V/div

IN+ = VDD

MAX5078B (TTL INPUT)

MAX5078 toc17

20ns/div


IN-2V/div

OUT2V/div

IN+ = VDD


MAX5078 toc18

40ns/div


IN-2V/div

OUT2V/div

IN+ = VDD


MAX5078 toc19

20ns/div


IN-2V/div

OUT5V/div

IN+ = VDDMAX5078B (TTL INPUT)

MAX5078 toc20

40ns/div


IN-2V/div

OUT5V/div

IN+ = VDDMAX5078B (TTL INPUT)

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_______________________________________________________________________________________ 7

MAX5078 toc22

40ns/div


IN+ = VDD

IN-2V/div

OUT5V/div


VDD vs. OUTPUT VOLTAGEMAX5078 toc23

2ms/div

VDD5V/div

OUT5V/div

IN+ = 15VIN- = GNDCL = 10,000pF


MAX5078 toc24

2ms/div

VDD vs. OUTPUT VOLTAGE

IN+ = 15VIN- = GNDCL = 10,000pF

VDD5V/div

OUT5V/div



MAX5078 toc21

20ns/div


IN-2V/div

OUT5V/div

IN+ = VDD


Detailed DescriptionVDD Undervoltage Lockout (UVLO)

The MAX5078A/MAX5078B have internal undervoltagelockout (UVLO) for VDD. When VDD is below the UVLOthreshold, OUT is pulled low independent of the state ofthe inputs. The undervoltage lockout is typically 3.5V with200mV typical hysteresis to avoid chattering. When VDDrises above the UVLO threshold, the output goes high orlow depending upon the logic-input levels. Bypass VDDusing a low-ESR ceramic capacitor for proper operation(see the Applications Information section).

Logic InputsThe MAX5078A has CMOS logic inputs while theMAX5078B has TTL-compatible logic inputs. The logicinputs are protected against the voltage spikes up to18V, regardless of the VDD voltage. The TTL and CMOSlogic inputs have 300mV and 0.1 x VDD hysteresis,respectively, to avoid double pulsing during transition.The low 2.5pF input capacitance reduces loading andincreases switching speed.

The logic inputs are high impedance and must not be leftfloating. If the inputs are left open, OUT can go to anundefined state as soon as VDD rises above the UVLOthreshold. Therefore, the PWM output from the controllermust assume proper state when powering up the device.

The MAX5078A/MAX5078B have two logic inputs, provid-ing greater flexibility in controlling the MOSFET. Use IN+for noninverting logic and IN- for inverting logic operation.Connect IN+ to VDD and IN- to GND, if not used.Alternatively, the unused input can be used as anON/OFF function. Use IN+ for active-low shutdown logicand IN- for active-high shutdown logic (see Figure 3). SeeTable 1 for all possible input combinations.

Driver OutputThe MAX5078A/MAX5078B have low RDS(ON) p-channeland n-channel devices (totem pole) in the output stagefor the fast turn-on/turn-off, high-gate-charge switchingMOSFETs. The peak source or sink current is typically4A. The output voltage (VOUT) is approximately equal toVDD when in high state and is ground when in low state.The driver RDS(ON) is lower at higher VDD resulting inhigher source-/sink-current capability and faster switch-ing speeds. The propagation delays from the noninvert-ing and inverting logic inputs to OUT are matched to 2nstypically. The break-before-make logic avoids any cross-conduction between the internal p- and n-channeldevices, and eliminates shoot-through, thus reducing thequiescent supply current.

Applications InformationRLC Series Circuit

The drivers RDS(ON) (RON), internal bond/lead induc-tance (LP), trace inductance (LS), gate inductance (LG),and gate capacitance (CG) form a series RLC circuit with a second-order characteristic equation. Theseries RLC circuit has an undamped natural frequency(0) and a damping ratio () where:

The damping ratio needs to be greater than 0.5 (ideally1) to avoid ringing. Add a small resistor (RGATE) inseries with the gate when driving a very low gate-charge MOSFET, or when the driver is placed awayfrom the MOSFET.

01

2

=

+ +

=

+ +

( )

( )

L L L C

R

L L LC

P S G G

ON

P S G

G

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8 _______________________________________________________________________________________

Pin Description

PIN NAME FUNCTION1 IN- Inverting Logic-Input Terminal. Connect to GND when not used.

2, 3 GND Ground

4 VDD Power Supply. Bypass to GND with one or more 0.1F ceramic capacitors.

5 OUT Driver Output. Sources or sinks current to turn the external MOSFET on or off.

6 IN+ Noninverting Logic-Input Terminal. Connect to VDD when not used.

EPExposed Pad. Internally connected to GND. Do not use the exposed pad as the only electricalground connection.

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_______________________________________________________________________________________ 9

Use the following equation to calculate the series resistor:

LP can be approximated as 2nH for the TDFN package.LS is on the order of 20nH/in. Verify LG with the MOS-FET vendor.

Supply Bypassing and GroundingPay extra attention to bypassing and grounding theMAX5078A/MAX5078B. Peak supply and output currentsmay exceed 4A when driving large external capacitiveloads. Supply voltage drops and ground shifts createnegative feedback for inverters and may degrade thedelay and transition times. Ground shifts due to poordevice grounding may also disturb other circuits sharingthe same AC ground return path. Any series inductancein the VDD, OUT, and/or GND paths can cause oscilla-tions due to the very high di/dt when switching theMAX5078A/MAX5078B with any capacitive load. Placeone or more 0.1F ceramic capacitors in parallel as closeto the device as possible to bypass VDD to GND. Use aground plane to minimize ground return resistance andseries inductance. Place the external MOSFET as closeas possible to the MAX5078A/MAX5078B to further mini-mize board inductance and AC path impedance.

Power DissipationPower dissipation of the MAX5078A/MAX5078B consistsof three components: caused by the quiescent current,capacitive charge/discharge of internal nodes, and theoutput current (either capacitive or resistive load).Maintain the sum of these components below the maxi-mum power dissipation limit.

The current required to charge and discharge the inter-nal nodes is frequency dependent (see the IDD-SWSupply Current vs. Supply Voltage graph in the TypicalOperating Characteristics). The power dissipation (PQ)due to the quiescent switching supply current (IDD-SW)can be calculated as:

PQ = VDD x IDD-SWFor capacitive loads, use the following equation to esti-mate the power dissipation:

PCLOAD = CLOAD x (VDD)2 x fSWwhere CLOAD is the capacitive load, VDD is the supplyvoltage, and fSW is the switching frequency.

Calculate the total power dissipation (PT) as follows:

PT = PQ + PCLOADUse the following equations to estimate the MAX5078A/MA5078B total power dissipation when driving a ground-referenced resistive load:

PT = PQ + PRLOADPRLOAD = D x RON(MAX) x ILOAD2

where D is the fraction of the period the MAX5078A/MA5078Bs output pulls high, RON(MAX) is the maximumon-resistance of the device with the output high, andILOAD is the output load current of the MAX5078A/MAX5078B.

Layout InformationThe MAX5078A/MAX5078B MOSFET drivers source andsink large currents to create very fast rising and fallingedges at the gate of the switching MOSFET. The highdi/dt can cause unacceptable ringing if the tracelengths and impedances are not well controlled.

RL L L

CRGATE

P S G

GON

+ +

( )

VIHVIL

90%

10%

VIHVIL

tRtF

tD-OFF1 tD-ON1

tD-OFF2 tD-ON2

IN+

OUT

IN-

RISING MISMATCH = tD-ON2 - tD-ON1FALLING MISMATCH = tD-OFF2 - tD-OFF1

Figure 1. Timing Diagram

P

N

MAX5078AMAX5078B

BREAK-BEFORE-

MAKECONTROL

VDD

OUT

GND

IN-

IN+

Figure 2. MAX5054 Simplified Diagram (1 Driver)

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Use the following PC board layout guidelines whendesigning with the MAX5078A/MAX5078B:

Place one or more 0.1F decoupling ceramiccapacitors from VDD to GND as close to the deviceas possible. Connect VDD and GND to large copperareas. Place one bulk capacitor of 10F (min) onthe PC board with a low resistance path to the VDDinput and GND of the MAX5078A/MAX5078B.

Two AC current loops form between the device andthe gate of the driven MOSFET. The MOSFET lookslike a large capacitance from gate to source when thegate pulls low. The active current loop is from theMOSFET gate to OUT of the MAX5078A/MAX5078B,to GND of the MAX5078A/MAX5078B, and to thesource of the MOSFET. When the gate of the MOSFETpulls high, the active current is from the VDD terminalof the decoupling capacitor, to VDD of theMAX5078A/MAX5078B, to OUT of the MAX5078A/MAX5078B, to the MOSFET gate, to the MOSFETsource, and to the negative terminal of the decouplingcapacitor. Both charging current and dischargingcurrent loops are important. Minimize the physical dis-tance and the impedance in these AC current paths.

Keep the device as close to the MOSFET as possible.

In a multilayer PC board, the inner layers shouldconsist of a GND plane containing the dischargingand charging current loops.

Pay extra attention to the ground loop and use alow-impedance source when using a TTL logic-input device. Fast fall time at OUT may corrupt theinput during transition.

Exposed PadThe TDFN-EP package has an exposed pad on the bot-tom of its package. This pad is internally connected toGND. For the best thermal conductivity, solder theexposed pad to the ground plane in order to dissipate1.9W. Do not use the ground-connected pad as theonly electrical ground connection or ground return. UseGND (pins 2 and 3) as the primary electrical groundconnection.


10 ______________________________________________________________________________________

MAX5078

VDD

GNDIN-

IN+ OUTPWMINPUT

ONOFF

Figure 3. Unused Input as an ON/OFF Function

Table 1. MAX5078 Truth TableIN+ IN- OUTLow Low Low

Low High Low

High Low High

High High Low

Additional Application Circuits

MAX5078AMAX5078B

VDD

IN+

IN-

OUT

GND

VDD

N

VS

Figure 4. Noninverting Application

MAX5078AMAX5078B

VDD

IN+

IN-

OUT

GND

4V TO 15V

N

VS

VOUT

FROM PWMCONTROLLER

(BOOST)

Figure 5. Boost Converter

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______________________________________________________________________________________ 11

MAX5078AMAX5078B

IN+

IN-

OUT

GND

N

VOUT

FROM PWMCONTROLLER

(BOOST)

VDD

MAX5078AMAX5078B

IN+

IN-

OUT

GND

4V TO 15V

VDD

P

Figure 6. MAX5078A/MAX5078B In High-Power SynchronousBuck Converter

PWM IN

VOUTVIN

MAX5078

VDD

IN+

IN-

OUT

GND

4V TO 15V

MAX5078

VDD

IN+

IN-

OUT

GND

MAX5078

OUT

IN-

IN+

GND

VDD

SIGNAL FROM PRIMARY

4V TO 15V

Figure 7. Forward Converter with Secondary-Side Synchronous Rectification

Chip InformationTRANSISTOR COUNT: 258

PROCESS: CMOS

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Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses areimplied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.

Package Information(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline informationgo to www.maxim-ic.com/packages.)

6, 8

, &10

L, D

FN T

HIN

.EP

S

LC LC

PIN 1INDEX AREA

D

E

L

e

LA

e

E2

N

G1

221-0137

PACKAGE OUTLINE, 6,8,10 & 14L,TDFN, EXPOSED PAD, 3x3x0.80 mm

-DRAWING NOT TO SCALE-

k

e

[(N/2)-1] x eREF.

PIN 1 ID

0.35x0.35

DETAIL A

b

D2

A2

A1

COMMON DIMENSIONS

SYMBOL MIN. MAX.

A 0.70 0.80

D 2.90 3.10

E 2.90 3.10

A1 0.00 0.05

L 0.20 0.40

PKG. CODE N D2 E2 e JEDEC SPEC b [(N/2)-1] x e

PACKAGE VARIATIONS

0.25 MIN.k

A2 0.20 REF.

2.300.101.500.106T633-1 0.95 BSC MO229 / WEEA 1.90 REF0.400.05

1.95 REF0.300.050.65 BSC2.300.108T833-1

2.00 REF0.250.050.50 BSC2.300.1010T1033-1

2.40 REF0.200.05- - - - 0.40 BSC1.700.10 2.300.1014T1433-1

1.500.10

1.500.10

MO229 / WEEC

MO229 / WEED-3

0.40 BSC - - - - 0.200.05 2.40 REFT1433-2 14 2.300.101.700.10

T633-2 6 1.500.10 2.300.10 0.95 BSC MO229 / WEEA 0.400.05 1.90 REF

T833-2 8 1.500.10 2.300.10 0.65 BSC MO229 / WEEC 0.300.05 1.95 REF

T833-3 8 1.500.10 2.300.10 0.65 BSC MO229 / WEEC 0.300.05 1.95 REF

-DRAWING NOT TO SCALE- G2

221-0137

PACKAGE OUTLINE, 6,8,10 & 14L,TDFN, EXPOSED PAD, 3x3x0.80 mm

DOWNBONDSALLOWED

NO

NO

NO

NO

YES

NO

YES

NO

Documents

MAX5078.PDF