MATLAB and Simulink in the - enclustra.com · MATLAB® and Simulink® in the FPGA Design Process MathWorks® & Enclustra Seminar “Model based Design for FPGA and SoC Development”

MATLAB® and

Simulink® in the

FPGA Design

Process

MathWorks® & Enclustra Seminar

“Model based Design for FPGA

and SoC Development”

Zurich, December 1, 2015

Marc Oberholzer

Vice President, Engineering

Enclustra GmbH

Agenda

Enclustra company profile

FPGA basics

FPGA design flow

Bit-true VHDL implementation with MATLAB®

FPGA to host communication using FPGA Manager™

Prototyping with MATLAB® and FPGA Manager™

Example FPGA projects involving MATLAB®/Simulink®

Conclusions

- 2 -

Agenda


FPGA basics

FPGA design flow





Conclusions

- 3 -

Enclustra Company Profile

Quick Facts

- 4 -

Focused on FPGA Technology – Everything FPGA!

Headquarters in Technopark, Zurich, Switzerland

Founded in 2004 – successfully in business for 11 years!

20 employees (12 FPGA engineers)

Vendor-Independent


FPGA Design Center

- 5 -


FPGA Solution Center

- 6 -

FPGA and SoC Modules

IP Cores and Solutions

FPGA Manager

IP Solution

Agenda


FPGA basics

FPGA design flow





Conclusions

- 7 -

FPGA Basics

The big Picture

- 8 -

FPGA stands for

Field Programmable Gate Array,

describing an integrated circuit

designed to be configured to

a specific function after

manufacturing.

LogicBlock

LogicBlock

LogicBlock

LogicBlock

LogicBlock

LogicBlock

DSP B

lock

DSP B

lock

DSP B

lock

RAM

Blo

ckRAM

Blo

ckRAM

Blo

ck

S S S S

S S S S

S S S S

S S S S

I/O

I/O

I/O

I/O

I/O

I/O I/O I/O I/O I/O

I/O I/O I/O I/O I/O

I/O

I/O

I/O

I/O

I/O

FPGA Basics

Internals: Configurable Logic Blocks

- 9 -

Configurable logic blocks consisting of look-up tables (LUTs) and Flip-Flops

(FFs) are the basic building units of every FPGA design.

Look-Up Table(LUT) Flip-Flop

(FF)

Configurable Logic Block

A0

A1

A2

A3Q

Z

O

CLK

Multiplexer(MUX)

CFG

++ x

A

B

C

MULT

ACCU

ADD

OPMODE

DSP Block

Pre-Adder Multiplier Post Adder / Accumulator

FPGA Basics

Internals: Digital Signal Processing (DSP) Blocks

- 10 -

DSP blocks are used to efficiently implement fixed-point arithmetic operations

commonly used in DSP algorithms (up to 2’000 GMAC/s in today’s FPGAs).

FPGA Basics

Internals: Memory Blocks

- 11 -

Memory blocks are used for

storing and buffering larger

amounts of data very close to

the processing units.

DIA

ADDRA

WEA

CLKA

RSTA

ENA

DIB

ADDRB

WEB

CLKB

RSTB

ENB

DOA

DOB

MemoryArray

Port A Access Logic

Port B Access Logic

Memory Block

FPGA Basics

Internals: I/O Blocks

- 12 -

I/O blocks are used to

interface to the outside

world. Flip-Flop(FF)

Flip-Flop(FF)

Flip-Flop(FF)

Buffer

Buffer

Pad

I/O Block

OUT_ENA

DOUT

DIN

CFG

CFG

CFG

FPGA Basics

Internals: Hard Macro Blocks

- 13 -

Hard macro blocks can be

looked at as small embedded

ASICs implementing complex

standard functions like

communication interfaces and

even complete microcontroller

systems.

LogicBlock

RAM

Blo

ck

DSP B

lock

LogicBlock

LogicBlock

RAM

Blo

ck

DSP B

lock

LogicBlock

LogicBlock

RAM

Blo

ck

DSP B

lock

LogicBlock

S S S S

S S S S

S S S S

S S S S

I/O

I/O

I/O

I/O

I/O

I/O I/O I/O I/O I/O

I/O I/O I/O I/O I/O

I/O

I/O

I/O

I/O

I/O

Agenda


FPGA basics

FPGA design flow





Conclusions

- 14 -

FPGA Basics

FPGA Design Flow: Requirements

- 15 -

Requirements

Specification

System

Design

Functional

Blocks

Implemen-

tation

Top-Level

Integration

Physical

Implemen-

tation

Functional

Require-

ments

Perfor-

mance

Require-

ments

Etc.

Environ-

Mental

Require-

ments

FPGA Basics

FPGA Design Flow: System Design

- 16 -

Requirements

Specification

System

Design

Functional

Blocks

Implemen-

tation

Top-Level

Integration

Physical

Implemen-

tation

Overall

System

Design

Algorithm

Design

Detailed

Archi-

tecture

Design

Pin

Assign-

ments,

Clock and

Reset

Strategy

FPGA Basics

FPGA Design Flow: Functional Blocks

- 17 -

Requirements

Specification

System

Design

Functional

Blocks

Implemen-

tation

Top-Level

Integration

Physical

Implemen-

tation

Functional

Blocks

Detailed

Design

Functional

Blocks

Design

Entry

Block-Level

Functional

Verification

FPGA Basics

FPGA Design Flow: Top-Level Integration

- 18 -

Requirements

Specification

System

Design

Functional

Blocks

Implemen-

tation

Top-Level

Integration

Physical

Implemen-

tation

Top-Level

Integration

Top-Level

Functional

Verification

FPGA Basics

FPGA Design Flow: Physical Implementation

- 19 -

Requirements

Specification

System

Design

Functional

Blocks

Implemen-

tation

Top-Level

Integration

Physical

Implemen-

tation

Synthesis

Place

and

Route

Static

Timing

Analysis

Bitstream

Generation

and

FPGA

Configu-

ration

In-Circuit

Verification

Agenda


FPGA basics

FPGA design flow





Conclusions

- 20 -

Bit-True VHDL Implementation with MATLAB®

The typical Scenario

- 21 -

Automated HDL code generation, of course!

What if automated HDL code generation is not an option?

Enclustra‘s cl_fix library is one possible answer.

We often receive customer algorithms implemented in MATLAB, which should

be ported to an FPGA. How to make sure that the FPGA implementation

exactly matches the MATLAB implementation?

% MATLAB function result = cl_fix_add (a, a_fmt, b, b_fmt, result_fmt, round, saturate)

% VHDL function cl_fix_add ( a : std_logic_vector; a_fmt : FixFormat_t; b : std_logic_vector; b_fmt : FixFormat_t; result_fmt : FixFormat_t; round : FixRound_t := Trunc_s; saturate : FixSaturate_t := Warn_s) return std_logic_vector;

FPGA-Optimized Algorithm

MATLABFixed Point

Approved


Methodology and Design Flow

- 22 -

Enclustra’s cl_fix library enables the customer to easily compare the

performance of the FPGA-optimized MATLAB algorithm to the original

MATLAB algorithm.

Customer Algorithm

MATLABFloating Point

Algorithm

Optimi-

zation

for FPGA

FPGA-Optimized Algorithm

MATLABFixed Point

Algorithm

Verification

FPGAImplemen-

tation

VHDLFixed Point

Verified


Methodology and Design Flow

- 23 -

Enclustra’s cl_fix library enables automatic, bit-true verification of VHDL code

and physical FPGA implementations against golden models implemented in

MATLAB.

FPGA-

Optimized Algorithm

MATLABFixed Point

Approved

Algorithm

Implemen-

tation

FPGAImplemen-

tation

VHDLFixed Point

FPGA

Implemen-

tation

Verification

Agenda


FPGA basics

FPGA design flow





Conclusions

- 24 -

FPGA to host communication using FPGA Manager

What is FPGA Manager?

- 25 -

Ethernet, USB 2.0/3.0, PCI-Express link types

Available for Windows and Linux

Common host SW API for all link types

Common FPGA IP core user interface for all link types

Up to 16 bidirectional streams

Memory mapped access

Blocking and non-blocking send and receive operations

Optimized for throughput

Packet loss tolerance and detection

Flexible licensing model

FPGA Manager is a powerful and easy to use FPGA to host computer

communication solution based on the requirements we experienced during

our customer projects of the past years.

- 26 -


MATLAB Host API

% Create a device with one stream DeviceHandle = FpgaManager_Device_Create('udp://192.168.33.12', 1); StreamHandle = FpgaManager_Stream_Create();

% Create stream 0, frame based, upstream enabled, downstream enabled FpgaManager_Device_CreateStream(DeviceHandle, StreamHandle, 0, true, true, true);

% Load FPGA Manager DLL loadlibrary('FpgaManager.dll', @FpgaManagerMatlab);

% Open device and stream FpgaManager_Device_Open(DeviceHandle); FpgaManager_Stream_Open(StreamHandle);

% Create send and receive buffers SendArray = [1,2,3,4]; ReceiveArray = zeros(1,4);

% Send (4 bytes, blocking) FpgaManager_Stream_Send(StreamHandle, SendArray, 4, 0);

% Receive (4 bytes, blocking) ReceiveArray = FpgaManager_Stream_Receive(StreamHandle, 4, 0);

% Close device (non-forcing) FpgaManager_Stream_Close(StreamHandle, false); FpgaManager_Device_Close(DeviceHandle, false);

A lightweight and easy

to use host API is

provided for MATLAB

and other languages.

- 27 -


FPGA Tool Integration

FPGA Manager provides seamless integration into Xilinx Vivado IP Integrator

and Altera Quartus II Qsys.

Agenda


FPGA basics

FPGA design flow





Conclusions

- 28 -

Prototyping with MATLAB and FPGA Manager

Overview

- 29 -

Enclustra‘s FPGA Manager IP Solution enables direct communication with an

FPGA-based system from MATLAB – ideally suited for prototyping!


Host Programming Language Migration

- 30 -

Seamlessly migrate from MATLAB to your production programming

language without having to modify the host API or the FPGA design.

FPGA ManagerIP Core

Memory Mapped

FPGA

Streams

FPGA ManagerLibrary

Host Computer

UserDesign

FPGA ManagerIP Core

Memory Mapped

FPGA

Streams

FPGA ManagerLibrary

Host Computer

UserDesign

UserApplication


Link Type Migration

- 31 -

Seamlessly migrate from one link type to another without having to

significantly modify the host computer software.

Agenda

- 32 -


FPGA basics

FPGA design flow





Conclusions

Example FPGA projects involving MATLAB/Simulink

Drive Control Platform

- 33 -

Develop the FPGA firmware for the next-generation drive

control platform. It should look to the customer‘s

SW engineers like the perfectly suited microcontroller.

Up to four independently controllable axes

Support for DC, brushless DC and stepper motors

Proprietary control algorithms

Control algorithms modeled with Simulink by the customer

VHDL implementation and integration by Enclustra

Validation and verification by Simulink/VHDL co-simulation


Drive Control Platform

- 34 -

Using Simulink as an „executable specification language“

for the proprietary control algorithms significantly reduced

the risks of misunderstandings and misinterpretation.


Bluetooth Qualification Setup

Develop the FPGA Firmware and the host computer

interface for a Bluetooth qualification setup. Re-use code

developed in previous projects as much as possible.

Transmit and receive Bluetooth packets

Transmit packets with TX defects (e.g. frequency offset)

High tolerance for defects in the RX path

Modelling with MATLAB

Bit-true implementation and check in VHDL (HDL design entry)

Defect analysis in MATLAB

- 35 -


Bluetooth Qualification Setup

The bit-true VHDL implementation has only been started

after the customer reviewed and accepted the MATLAB

models Reduced risk for the customer and for the service

provider!

- 36 -

StimuliGenerator

Bit-TrueModel

Bit-TrueVHDL

Implementation

ResponseCheck

MATLAB VHDL Test Bench MATLAB

DefectAnalysis

Agenda

- 37 -


FPGA basics

FPGA design flow





Conclusions

Conclusions

MATLAB / Simulink in the FPGA Design Process

- 38 -

MATLAB and Simulink are industry standard

tools that are widely used in the FPGA

design process.

HDL code generation is only one aspect.

Other aspects like algorithm design, bit-true

modelling, data analysis, etc. still have the

biggest share today for us at Enclustra.

Conclusions

HDL Code Generation vs. HDL Design Entry

- 39 -

Choose the appropriate tool for every task

in your FPGA design project.

HDL code generation is generally a good

choice for processing blocks.

HDL design entry generally is (still) the way to

go for communication interfaces and logic-

heavy blocks.

Conclusions

Team Up! – FPGA Manager and MATLAB

- 40 -

FPGA Manager easily integrates FPGA

designs with MATLAB using Ethernet, USB

and PCI-Express.

Direct access to FPGA data from MATLAB.

Seamless migration between link types and

host computer programming languages.

No proprietary/specific hardware required,

almost every FPGA evaluation board will do.

Questions?

- 41 -

Marc Oberholzer

Vice President, Engineering

[email protected]

+41 43 343 39 47

Quarterly newsletter:

[email protected]

Upcoming Events:

Embedded World February 23-25, 2016 Messezentrum Nürnberg Germany

mailto:[email protected]

mailto:[email protected]

Image References

- 42 -

Slide 4 FPGA image and Xilinx Alliance Program logo courtesy of xilinx.com

Slide 4 Altera DSN logo courtesy of www.altera.com

Slide 4 Lattice LEADER logo courtesy of latticesemi.com

Slide 4 Microsemi logo courtesy of microsemi.com

Slide 4 map pin image courtesy of C at clker.com

Slide 5 left image courtesy of ddpavumba at FreeDigitalPhotos.net

Slide 6 left image courtesy of digitalart at FreeDigitalPhotos.net

Slides 33 and 34 left image courtesy of Master isolated images at FreeDigitalPhotos.net

Slides 35 and 36 left image courtesy of Stefan Holliland at all-free-download.com

Slide 38 left image courtesy of dan at FreeDigitalPhotos.net

Slide 39 left image courtesy of cjansuebsri at FreeDigitalPhotos.net

MATLAB logo courtesy of The MathWorks, Inc.

All other images courtesy of Enclustra GmbH

Documents

MATLAB and Simulink in the - enclustra.com · MATLAB® and Simulink® in the FPGA Design Process MathWorks® & Enclustra Seminar “Model based Design for FPGA and SoC Development”