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Unicamp - University of Campinas

Author: Tiago Davi Curi Busarello

Data: July 2013

Project: Controller Design for the project: "DC-Bus Voltage Control in Controlled

DC-Voltage Power Port".

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Parameters

Cdc 9625 106−

⋅:= DC-Bus Capacitor

fs 3240:= Switching Frequency [Hz]

VDC 1450:= DC-Bus voltage reference [V]

Voltage Sensor GainHv

1

1000:=

Vt_pk 1:= Carrier Peak Voltage

fc 6.2:= Cut-off Frequency in Hz

MFd 55:= Desired Phase Margin [degree]

DC-Bus Voltage Plant. According to Chapter 7 in

"Voltage-Sourced Converters in Power Systems:

Modeling, Control and Applications" by A. Yazdani and R.

Iravani. Here, it is included the Sensor Gain and the PWM

transfer Function

Tdc f( )2−

Cdc 2⋅ π⋅ f⋅ i⋅Hv⋅

1

Vt_pk⋅:=

ModTdc f( ) 20 log Tdc f( )( )⋅:=

FaseTdc f( ) arg Tdc f( )( )180

π⋅:=

PI Controller

kpidc 125:=

wzbdc 42:=

CPIdc f( ) kpidc2 π⋅ f⋅ i⋅ wzbdc+

2 π⋅ f⋅ i⋅⋅:=

ModCPIdc f( ) 20 log CPIdc f( )( )⋅:=

FaseCPIdc f( ) arg CPIdc f( )( )180

π⋅:=

Open-Loop Bode Diagrams (Voltage Plant, PI controller and Total open-loop)

MAdc f( ) Tdc f( ) CPIdc f( )⋅:=

ModMAdc f( ) ModTdc f( ) ModCPIdc f( )+:=

FaseMAdc f( ) FaseTdc f( ) FaseCPIdc f( )+:=

0.01 0.1 1 10 100 1 103

× 1 104

× 1 105

×

100−

50−

0

50

100

ModTdc f( )

ModCPIdc f( )

ModMAdc f( )

f

0.01 0.1 1 10 100 1 103

× 1 104

× 1 105

×

200−

100−

0

100

FaseTdc f( )

FaseCPIdc f( )

FaseMAdc f( )

f

Phase Margin

FaseMAdc fc( ) 42.846=

Closed-Loop Bode Diagrams

MFdc f( )CPIdc f( ) Tdc f( )⋅

1 CPIdc f( ) Tdc f( )⋅+:=

ModMFdc f( ) 20 log MFdc f( )( )⋅:=

FaseMFdc f( ) arg MFdc f( )( )180

π⋅:=

0.01 0.1 1 10 100 1 103

×

40−

20−

0

0

20

40

60

80

100

ModMFdc f( ) FaseMFdc f( )

f

PSIM Implementation

KPSIM kpidc 125=:=

TsPSIM1

wzbdc0.024=:=