Mark Bohr on Intel’s Technology Leadership nm enhancements improve performance and extend technology ... High Perf Transistors Yes Yes Low Leakage Transistors ... Mark Bohr on Intel’s

TECHNOLOGY AND MANUFACTURING DAY

technologyLeadershipMARK BOHRINTEL SENIOR FELLOW, TECHNOLOGY AND MANUFACTURING GROUPDIRECTOR, PROCESS ARCHITECTURE AND INTEGRATIONSEPTEMBER 19, 2017


Legal DisclaimerDISCLOSURES

China Tech and Manufacturing Day 2017 occurs during Intel’s “Quiet Period,” before Intel announces its 2017 third quarter financial and operating results. Therefore, presenters will not be addressing third quarter information during this year’s program.

Statements in this presentation that refer to forecasts, future plans and expectations are forward-looking statements that involve a number of risks and uncertainties. Words such as “anticipates,” “expects,” “intends,” “goals,” “plans,” “believes,” “seeks,” “estimates,” “continues,” “may,” “will,” “would,” “should,” “could,” and variations of such words and similar expressions are intended to identify such forward-looking statements. Statements that refer to or are based on projections, uncertain events or assumptions also identify forward-looking statements. Such statements are based on management’s expectations as of September 19-20, 2017, and involve many risks and uncertainties that could cause actual results to differ materially from those expressed or implied in these forward-looking statements. Important factors that could cause actual results to differ materially from the company’s expectations are set forth in Intel’s earnings release dated July 27, 2017, which is included as an exhibit to Intel’s Form 8-K furnished to the SEC on such date. Additional information regarding these and other factors that could affect Intel’s results is included in Intel’s SEC filings, including the company’s most recent reports on Forms 10-K, 10-Q and 8-K reports may be obtained by visiting our Investor Relations website at www.intc.com or the SEC’s website at www.sec.gov.


10 nm Hyper Scaling22FFL technology Future Research


14 nm hyper Scaling features

14 nm uses aggressive feature scaling to deliver unprecedented 0.37x logic cell area scaling

Fin Pitch Interconnect Pitch Cell Height Gate Pitch

60 nm 42 nm 80 nm 52 nm 840 nm 399 nm 90 nm 70 nm

.70x .65x .48x .78x



14 nm products

Wide range of 14 nm products in volume production on various derivative technologies


10 nm Hyper Scaling

10 nm features aggressive pitch scaling - world’s first self-aligned quad patterning

Fin Pitch Min Metal Pitch Cell Height Gate Pitch


.81x .69x .68x .78x


Double Quad

Pattern Pattern


10 nm Hyper Scaling

Aggressive scaling & new features deliver 2.7x transistor density improvement

Fin Pitch Min Metal Pitch Cell Height Gate Pitch Dummy Gate Gate Contact

42 nm 34 nm 52 nm 36 nm 399 nm 272 nm 70 nm 54 nm Double Single Std COAG

.81x .69x .68x .78x

14 nm 10 nm 14 nm 10 nm 14 nm 10 nm 14 nm 10 nm 14 nm 10 nm 14 nm 10 nm

Contact

Contact

Double Quad

Pattern Pattern


3rd generation finfets

10 nm fins are ~25% taller and ~25% more closely spaced than 14 nm

10 nm14 nm22 nm

53 nm

34 nm


Contact over active gate is a revolutionary feature for another ~10% area scaling

Transistor

Contact

Contact Over Active gate

Transistor

FinsContact

Ga

te

Ga

te


Single dummy Gate

14 nm 10 nmSingle

Dummy Gate

Active Gate

Active Gate

Dummy Gates

Process innovations enable denser single dummy gate at cell borders


Fin pitch and metal pitch scaling allow cell height to scale 0.68x from 14 nm

14 nm399nm Height

10 nm272nm Height

(0.68x)

Cell Height

Gate Pitch Gate Pitch

Cell Height

Cell Library Height Scaling


0.01

0.1

1

2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020

Logic

Area

(relative)

HVM Wafer Start Date

45nm

22nm

14nm

10nm

32nm

.37x

.37x

.45x

.49x

Logic Transistor density

Hyper scaling delivers better-than-normal logic area scaling

Logic Cell

Width

Logic

Cell

Height

Gate Pitch

Logic Area Metric


1

10

100

2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020

Transistor

Density

MTr / mm2


Intel

45nm

22nm

14nm

10nm

32nm

2.7x

2.5x

2.1x

2.3x


Hyper scaling delivers better-than-normal transistor density improvement

60/40 NAND+SFF

Density Metric


1

10

100

2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020

Transistor

Density

MTr / mm2


Intel

45nm

22nm

14nm

10nm

32nm

100.8

3.3

7.5

15.3

37.5

MTr / mm2


10 nm hyper scaling features result in transistor density above 100 MTr/mm2

60/40 NAND+SFF

Density Metric


10

100

20/22 nm 14/16 nm 10 nm

Transistor

Density

(MTr/mm2)

Inte

l 2

2F

FL

Sa

msung

20

nm

TS

MC

20

nm

Sa

msung

10

nm

Sa

msung

14

nm

TS

MC

10

nm

TS

MC

16

nm

Inte

l 1

4 n

m

Inte

l 1

0 n

m

100.8

48.1 51.6

Logic Transistor density comparison

Intel 10 nm is a full generation denser than other “10 nm”

60/40 NAND+SFF

Density Metric


10 nm technology density ComparisonIntel TSMC Samsung

10 nm 10 nm 10 nm

Fin Pitch 34 36 42 nm

Gate Pitch 54 66 68 nm

Minimum Metal Pitch 36 42 48 nm

Logic Cell Height 272 360 420 nm

Logic Trans. Density 100.8 48.1 51.6 MTr/mm2

Logic Trans. Density 1x 0.48x 0.51x Relative

Intel 10 nm is ahead of other “10 nm” technologies on every density metric


0.01

0.1

45nm 32nm 22nm 14nm 10nm 7nm

SRAM

Cell Area

(um2)HP .0441LV .0367HD .0312

um2

10 nm offers a range of SRAM cells for density and power/performanceSRAM cell area scaled ~0.6x from 14 nm

SRAM AREA SCALING


2009 2011 2013 2015 2017 2019 2021

Dynam

ic C

ap

acitance

(lo

g s

cale

)

Process Readiness Date

22nm

14nm

10nm

32nm

Lower

Power

2009 2011 2013 2015 2017 2019 2021

Tra

nsis

tor P

erf

orm

ance

(lo

g s

cale

)


22nm

14nm

10nm

32nm

Higher

Performance

2009 2011 2013 2015 2017 2019 2021

Pe

rfo

rmance

pe

r W

att (

log

scale

)


22nm

14nm

10nm

32nm

Better

Perf/Watt

Transistor performance and power

10 nm transistors provide improved performance per watt

Performance Power Performance per Watt


2009 2011 2013 2015 2017 2019 2021

Dynam

ic C

ap

acitance

(lo

g s

cale

)


22nm

14nm

10nm

32nm

10+ 10++

Lower

Power

14+ 14++

2009 2011 2013 2015 2017 2019 2021

Tra

nsis

tor P

erf

orm

ance

(lo

g s

cale

)


22nm

14nm

10nm

32nm

10++

10+14++

14+

Higher

Performance

2009 2011 2013 2015 2017 2019 2021

Pe

rfo

rmance

pe

r W

att (

log

scale

)


22nm

14nm

10nm

32nm

10++

10+

Better

Perf/Watt 14++

14+

Transistor performance and power

10 nm enhancements improve performance and extend technology life

Performance Power Performance per Watt


Active

Power

Performance

Intel

10 10++

Samsung

TSMC~30%

~20%Lower

Power

Higher

Performance

10nm performance and power Comparison

Intel 10 nm has a considerable performance lead over other “10 nm”


Derivative technologies

Multiple derivative options offered for each technology generation

CPU SoC

High Perf Transistors Yes Yes

Low Leakage Transistors - Yes

Analog/RF Transistors - Yes

HV I/O Transistors - Yes

High-Q Inductors - Yes

Precision Resistors Yes Yes

MIMCAP Yes Yes

Low Cost Dense High Perf

Interconnect Stack Options

Device Options


• Intel’s 10 nm process technology has the world’s tightest transistor & metal pitches along with hyper scaling features for leadership density

• Intel’s 10 nm technology is a full generation ahead of other “10 nm” technologies

• Intel’s 10 nm process technology is on track to commence manufacturing in 2H’17

• Hyper scaling extracts the full value of multi-patterning schemes and allows Intel to continue the economic benefits of Moore’s Law

10 nm Summary




22FFL is the world’s first FinFET technology for low power IOT and mobile products

Advanced FinFET transistors based on proven 22 nm and 14 nm features

>100x leakage power reduction with new ultra-low leakage transistor option

Simplified interconnects and design rules based on 22 nm technology

New levels of design automation

Fully RF design enabled

Cost competitive with other industry 28/22 nm planar technologies

Intel’s new 22FFL technology


22FFL dimensions22 nm 22FFL 14 nm

Transistor FinFET FinFET FinFET

Fin Pitch 60 45 42 nm

Gate Pitch 90 108 70 nm

Metal Pitch 80 90 52 nm

Logic Cell Ht 840 540 399 nm

Trans. Density 15.3 19.4 37.5 MTr / mm2

SRAM Cell .092 .088 .050 um2

22FFL is based on proven 22 nm and 14 nm features


22FFL devices

High performance transistors

Ultra low leakage transistors

Analog transistors

High voltage I/O transistors

High voltage power transistors

Good device matching

22FFL offers a wide range of devices for digital and analog/RF design

Low 1/F noise

Deep N-well isolation

Precision resistor

MIM capacitor

High resistance substrate

High-Q inductors


FinFET Performance and leakage Advantage

FinFETs provide a significant performance and leakage advantage over any planar transistor

Intel 22 nm Tri-Gate announcement, April 2011

2.0

0.6

0.8

1.0

1.2

1.4

1.6

1.8

0.5 0.6 0.7 0.8 0.9 1.0 1.1

Operating Voltage (V)

TransistorGate Delay(normalized)

22 nm Tri-Gate

32 nmPlanar

18% Faster

37% Faster

1E-05

0.0001

0.001

0.01

0.1

1

10

0.0 0.2 0.4 0.6 0.8 1.0

Planar

Tri-Gate

Reduced Leakage

Gate Voltage (V)

Channel Current

(normalized)


0.0001

0.001

0.01

0.1

1

10

100

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

Total Leakage(nA/um)

Drive Current (mA/um)

22FFL

22GP

0.85V

>18x

Lower Leakage

Lower

Leakage

Higher

Performance

22FFl high performance transistors

22FFL provides high performance transistors with drive currents similar to 14nm++

>40% Higher Drive

at Same Leakage


0.0001

0.001

0.01

0.1

1

10

100

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

Total Leakage(nA/um)

Drive Current (mA/um)

22FFL

22FFL

Low Leakage

22GP

>500x

Lower Leakage

0.85V

>18x

Lower Leakage

Lower

Leakage

Higher

Performance

22FFL Low leakage transistors

22FFL provides the lowest leakage transistors for any mainstream technology


Intel Custom Foundry’s robust Ecosystem

22FFL is fully supported by a robust design ecosystem

Other names and brands may be claimed as the property of others

Design Service

Soft IP

Advanced IPFoundation IP

Design Tools & Flows

Intel Custom

Foundry


22FFL is an exciting new technology that provides a compelling combination of

performance, power, density and ease-of-design for low power IOT and mobile products

22FFL technology High transistor drive currents similar to Intel 14 nm

Low leakage transistors with >500x lower total leakage than 22GP

Die area scaling better than industry 28/22 nm technologies

Wide range of advanced analog/RF devices

Extensive use of single patterning for affordable ease-of-design

Mature die yield with use of proven 22/14 nm features

Cost competitive with other 28/22 nm planar technologies

Industry standard PDK1.0 available now

Production readiness in Q4 2017




Innovation enabled technology pipeline

Intel has been the industry leader in bringing innovative technologies from research to high volume manufacturing


High-k Metal Gate FinFETs Contact over Gate

SA Double Patterning SA Quad Patterning

Manufacturing Development Research

Contact

Gat

e


Innovation enabled technology pipeline

We have a wide range of options in research to continue Moore’s Law

Future options subject to change


High-k Metal Gate FinFETs Contact over Gate

SA Double Patterning SA Quad Patterning

Manufacturing Development Research

III-V

10nm

III-V Transistors 3D Stacking Material Synthesis

2D Materials Nanowires EUV Patterning

Interconnects Beyond CMOS Dense Memory

Contact

Gat

e


Research projects

10nm

Nanowire Transistors III-V Transistors 3D Stacking Dense Memory

Dense Interconnects EUV Patterning Neuromorphic Computing Spintronics


Intel Oregon Campus

Intel’s main research & development site


Intel Oregon Campus

Research Development

Manufacturing

Sort/Test

Automation Reliability

Modeling

Advanced Design

Technology leadership is the result of close collaboration at one site


Summary• Hyper scaling on Intel 14 nm and 10 nm technologies provides

better than normal scaling and delivers improved cost per transistor and performance per watt

• Intel’s 10 nm technology is a full generation ahead of other “10 nm” technologies

• 22FFL provides a compelling combination of performance, power, density and ease-of-design for low power IOT and mobile products

• Multiple technology options now in research will enable the continuation of Moore’s Law for at least the next 10 years

Documents

Mark Bohr on Intel’s Technology Leadership nm enhancements improve performance and extend technology ... High Perf Transistors Yes Yes Low Leakage Transistors ... Mark Bohr on Intel’s