Marek Perkowski’sProductions present:Marek Perkowski’s

Productions present:

Lectures on Logic SynthesisLectures on Logic Synthesis

Some slides come from various sources, including Adam Postula, Mark Schulz and U.C. Berkeley

ECE 572Advanced Logic Synthesis

Dr Marek Perkowski

mperkows@ee.pdx.edu

http://www.ee.pdx.edu/~mperkows

•Introduction

•Grading

•What is this class about

Do not take notesDo not take notes

You will get all You will get all slidesslides

PSU sequence of classes This is a complete sequence related to digital logic design automation.

ECE 171 ECE 271

Logic Synthesis

Sequential Circuits

WinterWinter

Design with

VHDL/Verilog

SpringSpring Formal

Verification

and Design

SpringSpring

Testing and

Design for Test

FallFall

FallFall

Quantum Computing

Objective of Subject Students will have the understanding and experience

of CAD/EDA techniques in combinational circuit design.

Students will be aware of state-of-the-art techniques in the realization of digital designs - specifically the use of Rapid Prototyping Techniques.

Students will learn modern EDA (Electronic Design Automation) approaches and fundamentals of building tools

What in coming weeks? Look to my WWW Page. Review and Introduction. Properties of functions (symmetry, unateness, etc). Representations of Functions, Relations and State

Machines. Spectral approachesSpectral approaches based on transforms and

diagrams Applications outside circuit design.

Required Background You require, and are assumed to know, the material presented to you in

ECE 171ECE 171 and ECE 271ECE 271 or equivalent This material covered basic Boolean algebra, truth tables,

Karnaugh maps (K-maps), simple minimization techniques using Karnaugh maps, and some basic design skills in Boolean algebra.

Knowledge of programming in C, C++, Java, Basic, Lisp or similar language is useful but not a mustbut not a must.

Everybody will create animated PowerPointanimated PowerPoint presentations and his WWW Page with a new material and project descriptions.

Review.What this part of the course covers.

Combinational Circuit Design

–Review of Karnaugh Maps

–Minimization of combinational logic circuits using Karnaugh Maps

–CAD Techniques of combinational logic circuit minimization

–Binary Decision Diagrams

Review.What this part of the course covers(cont).

Combinational Circuit Design

– Functional Decomposition

– Graph Coloring and Set Covering Techniques

– MSI building blocks: multiplexers, decoders, ROM’s and PLA’s

– Arithmetic circuits

– Introduction to data structures and optimization

What is covered in the course? Advanced Logic and Tools design

–Advanced Decision Diagrams,

–Two level minimization theory, graph coloring, Boolean Equations, implicit methods

–Functional Decomposition

–Reed-Muller Logic and Linearly Independent Logic

Grading System Homeworks = 45 % Midterm 1 = 15 % Midterm 2 = 15 % Final Exam = 25 %

– Final examination (3 Hours or take home) - Questions from all the course, but with emphasis on the second half of the course.

– Midterm Examination (open book, in class)– Homeworks– Presentations of homeworks

Remember that all exams are:

Remember that I emphasize in this class not only hard work but also….

TEXTBOOKS Strongly Recommended

– Gary Hachtel and Fabio Somenzi, Logic Synthesis and Verification Algorithms, Kluwer Academic Publishers, 1996.

– Randy Katz, Contemporary Logic Design, Benjamin/Cummings, 1994

– Perkowski and Mishchenko, 1999-2000

Useful

– Capilano Computing, LogicWorks 3, 1995 (includes 3.5” diskette for Windows). This is a simulation program .

Other Information There is a WWW Home page for this subject. Most PowerPoint 4.0 slides you see here, plus a Postscript

printable version with 6 slides per page will be available. Lectures will be available within 24 hours after the lecture is

given (mainly because I will be completing the lectures on Sunday nights and Monday mornings prior to the lecture).

All sorts of other info will be there as well. Class announcements will appear in the “class schedule”

pages of this class at the WWW page of Marek Perkowski. Assignment:Assignment: Find this page using Google Engine. Type

+Perkowski +Marek and next go to “Classes that I teach”

Other Information Send emails with questions. I will post news for class students of this group. I

presume that it is read within 2 or 3 working days. YOU ARE RESPONSIBLE FOR READING THE NEWS IN CLASS SCHEDULE LINK!

Any Other Administrative Details?

! Now is the time to ask

Design Design Example:Example:Hall Light Hall Light

DesignDesign

Design Example:Hall Light Design

Problem Specification:– You are to design a device which will control the

hall lights. There are two switches, one at each end of the hallway, and a light in the middle of the hall. The light can be turned on or off from either switch.

– Give the truth table of the controller for this system.– Specify the truth table in its simplest form (ie, use a

simplification or minimization technique).

SolutionStep 1: Block Diagram

This is a BLOCK DIAGRAM of the system we are to design. The aim of this diagram is to identify the INPUTS and OUTPUTS of

the system - both for you the designer and for the customer as well. Discuss the design with the customer to ensure that this is what is desired (required).

Switch 1

Switch 2

Light

Logic Circuit

BLOCK DIAGRAMS:Some Homespun Philosophy

There needs to be some method of “sketching a solution on the back of an envelope”.

This is used to discuss the design with the customer and the other members of the design team.

Show ALL the INPUTS and OUTPUTS. When we come to sequential designs, this includes the clock signal.

BLOCK DIAGRAMS:Some Homespun Philosophy

In practice, have the customer agree to this specification. Everything which follows depends upon this specification - if it is wrong then all your design efforts are wasted.

These basic ideas apply to any work you do as an engineer - ensure that the customer of your services knows what you are doing and what you have assumed.

Step 2:Label the Inputs

We usually use acronyms for the names of the inputs and outputs. This saves typing, but may obscure the significance of a signal. Choose the acronyms carefully.

In this case, let us make the following assignments:

– S1 for hall switch 1.

– S2 for hall switch 2.

– Z for the output to the light fitting. Z is the conventional symbol used to signify an output.

Solution Step 3:Draw Up the Truth Table

TRUTH TABLES

– These are the single most important item you will learn about in digital design.

– Industrial designers VERY RARELY USE K-MAPS!!!!

– K-Maps are a useful tool with which to gain experience in logic design, and to solve VERY SIMPLE minimization problems.

– “Real Designers” use CAD packages on computers to perform logic minimization.

TRUTH TABLES For combinational circuits, we need to have a

standard manner in using truth tables:

INPUTS OUTPUTS We usually enter the input combinations in increasing numerical value, start at the value 000...00 and working up to 111...11

That is, we enter the values systematically.

Initial Table LayoutInputs Outputs

S1 S2 Z0 00 11 01 1

Note that the input entries are made first, and placed in increasing numerical order.

Complete the Truth Table

When both switches are off the light is off. When either switch is on, the light is on. When both switches are on, the light is off.

Inputs Outputs

S1 S2 Z0 0 00 1 11 0 11 1 0

Step 4:Simplify the Truth Table

In this example, we were asked to simplify the truth table, if possible.

From your last course, you learnt of two possible techniques to simplify the truth table:– express the truth table as a (set of) symbolic equations, and

use the laws of Boolean algebra to simplify the equation.– map the truth table onto a suitable (set of) K-map(s), and use

the relevant techniques to simplify the truth table. In practice, K-maps are always a simpler tool than

symbolic equations, so that is what we use here.

K-Map Realization

From previous courses, you will realize that there is nothing further that we can do to reduce the number of terms in the truth table, assuming the Sum of Sum of ProductsProducts (SOP) realization.

0 1

1 0

S1S2

0 1

00

2

1

3

1

Solution

We accept this as the requested solution to our original design request.

Inputs Outputs

S1 S2 Z0 0 00 1 11 0 11 1 0

Circuit Realization

This circuit is called a two-level AND-OR realizing thegiven function. It is also called SOP - Sum of Products

S1

S2’

S1’

S2 The same circuitThe same circuit can be realizedcan be realized with single EXOR gatewith single EXOR gate

Circuit Realization with EXOR

S1S1

S2S2

Karnaugh Karnaugh MapsMaps

Minterms and Minterms and MaxtermsMaxterms

YZ

WX 00 01

00

01

0 1

54

3 2

67

11 10

412

8 9 11 10

141513

11

10

Karnaugh Map

11 11

11 11 11

11

11

1111 11

0

0

0 0 0

0

True minterm False minterm

Gray Code

Gray code provides that the adjacent geometrically cells (minterms) are adjacent in sense of Hamming distance, they differ in one Boolean value only

Natural number of the cell

The Next Step Draw circuit. Produce a schematic. Test circuit. Fix bugs, and update documentation. Produce PCB. Test ... Package Check with customer again! Get Paid!!!!!!!!!

YZ

WX 00 01

00

01

0 1

54

3 2

67

11 10

412

8 9 11 10

141513

11

10

Karnaugh Map

Sum of Products Logic

Draw and analyze the schematics

The cover shown here is: X’Y’+X’Z’+

W’Y’Z+

W’XY+YZ’

This cover is not minimal

YZ

WX 00 01

00

01

0 1

54

3 2

67

11 10

412

8 9 11 10

141513

11

10

Karnaugh Map A better cover has the following primes:

+X’Y’ (essential) +

YZ’ (essential)

+W’XZ(non-essential)

Now you can prove that this cover is exact minimal solution

Observe that the grey prime is now redundant (X’Z’)

INTRO: Covering, set INTRO: Covering, set covering, unate coveringcovering, unate covering

EXOR and EXOR and ESOP ESOP

Minimization Minimization IntroIntro

YZ

WX 00 01

00

01

0 1

54

3 2

67

11 10

412

8 9 11 10

141513

11

10

Karnaugh Map

11 11

11 11 11

11

11

1111 11

Exclusive Exclusive Sum of Sum of Products Products LogicLogic

Draw and analyze the schematics

Even/Odd Covering

Exclusive Sum of Exclusive Sum of Products Logic ESOP Products Logic ESOP is the following:is the following:

W’Y’YZ’ W’Z W’X’Z

YZ

WX 00 01

00

01

0 1

54

3 2

67

11 10

412

8 9 11 10

141513

11

10

11 11

11 11 11

11

11

1111 11

Exclusive Sum of Exclusive Sum of Products LogicProducts Logic

This is the best ESOP

and in this case also the same groups are used in the best SOP. This is because the groups are disjoint.

Improvement:Improvement:

W’Y’YZ’ W’Z W’X’Z = W’Y’ YZ’ W’Z(1 X’)= W’Y’ YZ’ W’ZX

Short Review of Exor Logic A A = 0 A A’ = 1 A 1=A’ A’ 1=A A 0=A A B= B A A B = B A

A(B C) = AB AC A+B = A B AB A+B = A B when AB = 0 A (B C) = (A B) C (A B) C = A (B C) A+B = A B AB =

A B(1 A) = A BA’

These rules are sufficient to minimize Exclusive Sum of Product expression for small number of variables

We will use these rules in the class for all kinds of reversible, quantum, optical, etc. logic. Try to remember them or put them to your “creepsheet”.

YZ

WX 00 01

00

01

0 1

54

3 2

67

11 10

412

8 9 11 10

141513

11

10

11 11

00 11 00

11

00

0000 00

0

0

0 0 1

1

Natural number of the cell

This ESOP is : W’X’YZ

Learn how to design graphically such solutions

To To RememberRemember

What should you review for next time?

Please review the Kmap, implicants and covering from any undergraduate textbook such as Roth or Katz

Review basic Boolean algebra, De Morgan rules, factorization and flip-flops (D,T,JK).

You should be able to take arbitrary Kmap of 5 variables, truth table, netlist or expression and convert it to a truth table or Kmap.

Next you should be able to minimize it and draw a schematic with gates such as EXOR, NAND, NOR, etc.

You should be able to reformulate problem expressed in English as a Boolean minimization or decision problem.

SOP and ESOP logic and circuits. These are the minimum information to start practical design problems.

Homework Generate a random, but rather complex (not trivial)

function of four variables. Draw the Kmap for this function Find the minimal ESOP. The function should be

selected in such a way that the minimal ESOP will have four product terms, not trivial and the terms should be not disjoint. Minimize both graphically and algebraically.

Draw the circuit using standard logic gates such as AND, NOT and EXOR for this circuit.

For comparison, find the minimal SOP (using set covering) for this function. Draw the circuit.

What should have we just learnt? As a designer, we need a systematic approach to designing. We need ensure that the customer agrees to the product we

intend to design. This involves many interactions with the customer to ensure

that the final product will be accepted. We need sufficient documentation to ensure that, in the event of

a dispute and threat of non-payment, we have SIGNED documents which show the customer agreed to everything we did.

Do no more than you will get paid for! That is, no extras that YOU think the customer might like.

Please review Karnaugh Maps (Kmaps, for short) for 2,3,4 and 5 variables. The adjacent cells - geometrically and in the sense of Hamming

distance. Enumeration of cells (minterms) Don’t care minterms and how to use them How to find prime implicants How to find Sum-of-Products (SOP) Covers of sets of true

minterms with prime implicants. What are essential prime implicants and distinct vertices.

– Distinct vertices are minterms that are covered by only one prime

– Essential primes are primes that cover distinct vertices

What should you review? Review basic Boolean algebra, De Morgan rules, factorization and

flip-flops (D,T,JK). You should be able to take arbitrary Kmap of 5 variables, truth table,

netlist or expression and convert it to a truth table or Kmap. Next you should be able to minimize it and draw a schematic with

gates such as EXOR, NAND, NOR, etc. You should be able to reformulate problem expressed in English as a

Boolean minimization or decision problem. These are the minimum information to start practical design

problems.

For Advanced Students If it is too easy, do not worry. The class is for everybody. I will go fast through repetition material. Quite advanced material will soon appear.

Important for this year1. Memristors and IMPLY

2. TANT networks

3. Negative Gate networks

4. Bi-Decomposition

5. AC decomposition

6. Trees of NANDs

7. ESOP, RM, PPRM, AND-OR-EXOR circuits

8. Systolic Processors

9. Data Flow

10. Image Processing Processors

Sources

Some slides come from various sources, including Adam Postula, Mark Schulz and U.C. Berkeley