March 4 - 7, 2018 Hilton Phoenix / Mesa Hotel Mesa ......Session 3A Presentation 2 Burn-in & Test Strategies Workshop March 4-7, 2018 Key Drivers for SLT (System Level Test) Karthik

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March 4 - 7, 2018

Hilton Phoenix / Mesa Hotel

Mesa, Arizona

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Really? - System Level Test BiTS 2018 Session 3A Presentation 2

March 4-7, 2018 Burn-in & Test Strategies Workshop www.bitsworkshop.org

Key Drivers for SLT

(System Level Test) Karthik Ranganathan

Astronics Test Systems

BiTS Workshop

March 4 - 7, 2018

Conference Ready

mm/dd/2014



Agenda

• What is System-Level Test (SLT)?

• How is SLT done today?

• What are the trends driving need for more SLT?

• What are the key challenges and opportunities?

Key Drivers for SLT (System Level Test) 2



What is System-Level Test (SLT)?

• Application-specific functional tests that are performed

– on an IC Device Under Test (DUT)

– which is temporarily placed in a socket while SLT tests are applied

– to help “guarantee” that a device will meet its targeted specs and

performance goals when it is ultimately used in the final system.

• System includes both hardware and software

– Hardware – Device Under Test (DUT), sockets, application boards, power supplies, etc.

– Software – firmware, device drivers, operating systems, applications, etc.


System-Level Test ensures that the device is tested similar to the end user experience

http://images.cxotoday.com/2013/02/semiconductor_2ipaO.jpg



What is System-Level Test (SLT)?

• 2 perspectives … component vs system

– Component perspective - does the device meet its specs?

– System perspective – does the “system” work when all the DUTs are

combined with software at the board level?


System-Level Test ensures that the device is tested similar to the end user experience

http://images.cxotoday.com/2013/02/semiconductor_2ipaO.jpg



How is System-Level Test Done Today?

A Brief History of Time…

• Functional Test used to be the way to go

– then designs started to get more complex

• Structural Test emerged; improved fault coverage

– device complexity continued to increase, quality became

important as well (hardware & software working together)

• System-Level Test is emerging to insure optimal

performance of the integrated system

– but how do we afford it?


Mesh of SLT, structural and

functional test leads to

maximum test coverage

Functional

Test

Structural

Test

System Level

Test

100%

Test

Coverage




Key Considerations

“How much SLT” is determined by:

– “Component” or “System” perspective not

covered by ATE

– Importance of hardware and software interactions

– Volume, Market segment, Product Life Time

– Product Quality and Reliability Requirements

– Thermal Requirements

– Time-to-Market (TTM), Time-To-Volume (TTV), Time-To-Profit (TTP)

– Cost of test escapes

– End Market Requirements (i.e., safety)


SLT Testing

Quality

Requirements

Cost of Test

Escapes?

Component

or System

Perspective?




Other Considerations for SLT

– Test Time: seconds, minutes, hours

– Purpose: for TTM, qualification, production

– Tester:

• “SLT on ATE”

• “SLT specialized equipment”

• “SLT Massively Parallel”


SLT Testing

Quality

Requirements

Cost of Test

Escapes?

Component

or System

Perspective?




Examples of equipment used today


Low Parallel SLT

Increasing SLT Unit Volume

Massively Parallel SLT

SLT on ATE

SLT on custom

hardware

Co

st

pe

r D

UT

Volume



Agenda

• What is System-Level Test (SLT)?

• How is SLT done today?

• What are the trends driving need for more SLT?

• What are the key challenges and opportunities?




What drives increasing need for more SLT?


Technical Drivers

Concurrent Scenario Testing

Guardband Stack &

Yield Overkill

Node Shrink at

Speed Coverage

Voltage Frequency Scaling

Packaging / 2.5 & 3D

PVT Corner

Explosion

Business Drivers

Drive for higher yield

Risk of untested transistors

New Packaging

Risk

Faster TTM and

TTV ramps

People’s lives

depend on our

product

Escape costs



Lower technology nodes dramatically increase

number of untested transistors

Moore’s Law doubles transistor count every technology node

# of Untested Transistors increasing:


At 99.5% coverage (static ATPG)

Millions untested (10 nm)

At 85% coverage (at speed ATPG)

Billions untested (10 nm)



Concurrent Scenario Testing: real-world scenarios

Consumer DUT


How to generate test patterns for these scenarios without significant overkill?

Automotive Infotainment DUT Medical Pacemaker DUT

Production ATE: Replicating real world scenarios: MONTHS

System-Level Test: Replicating real world scenarios: MINUTES

https://www.bing.com/images/search?view=detailV2&ccid=AQj5TCs4&id=1A5AF6F490C9C30A459D4A51255DD2A8C1409AED&thid=OIP.AQj5TCs46rWob3VOWQCggQEsDq&q=picture+of+an+android+phone&simid=608002285040567373&selectedIndex=11&ajaxhist=0



Guard Band Stack and Yield Overkill

• Definitions

– Guard Band added margin for

worst case / ATE test

– Headroom = VDD (Supply Voltage)

/ CMOS threshold (turn on voltage


SLT can help reduce the “fear of throwing away good parts” that comes with lower nodes

Source: Samsung

VD

D

Process Node

http://images.dailytech.com/nimage/Samsung_Analyst_Day_9_Die_Shrinks_Roadmap.png



Technology Node (nm)

Vdd (V)

100 mV Guardband as a

% of Vdd

CMOS Threshold

(V)

Headroom Vdd- Threshold

(V)

100mV Guardband as % of headroom

90 1.4 7.1% 0.5 0.9 11.1%

65 1.2 8.3% 0.5 0.7 14.3%

45 1.1 9.1% 0.5 0.6 16.7%

28 1 10.0% 0.5 0.5 20.0%

20 0.9 11.1% 0.45 0.45 22.2%

14 0.8 12.5% 0.4 0.4 25.0%

10 0.7 14.3% 0.4 0.3 33.3%

Guard Band Stack and Yield Overkill

With lower nodes, Guard Band becomes a higher percentage of VDD, “eating into the headroom”


SLT can help reduce the “fear of throwing away good parts” that comes with lower nodes

Assume: 100mV Guard Band (could also be ~100MHz Guard Band)



DVFS Explosion + PVT Corners

• Dynamic Voltage Frequency

Scaling (DVFS)

– Ensures the DUT works at different

power conditions by simulation and

testing of each power situation

• Process Voltage Temperature

(PVT) Corners

– Addresses process and temperature

variations with simulation and testing


Without SLT, it is difficult if not impossible to test all scenarios! F

req

ue

nc

y

Voltage

Sleep

Mode

Hi-speed

Mode

Nominal

Mode



DVFS Explosion + PVT Corners

Designers lack time to compensate for

the DVFS and PVT Corner Explosion:

there isn’t enough test time to run all

the patterns!

SLT offers the advantages of

booting and running the DUT

natively in different voltage modes,

simulating end user experience


Without SLT, it is difficult if not impossible to test all scenarios!

Source: Mentor

0

100

200

Significant Increase in PVT Corners

Process Node

https://www.semiwiki.com/forum/content/5454-how-16nm-14nm-finfets-require-new-spice-simulators.html



Conventional Test Methods No Longer Catch Fails

3D process geometries are driving

new defect types that aren’t covered

by static ATPG*, at speed ATPG

(TDF**), and other test methods

IPs from different vendors: coverage

was easier with one IP.

High speed, bidirectional interfaces

have faster read/write turnaround times

than the latency of ATE

*ATPG – Automatic test pattern generation for structural test


System-Level Test screens for these fail mechanisms

Source: ASE Group

SiP Module Cross Section

FinFET Cross Section

Source: Cadence

http://www.aseglobal.com/en/Products/4-1-6-3.asp

https://community.cadence.com/CSSharedFiles/blogs/ii/2012/Richard_Goering/finfet1.jpg



Challenges and Opportunities

Challenges

• Lack of fault coverage metric to assess

SLT effectiveness

• Complex nature of System-Level Test

Failures makes it difficult to diagnose root

cause of failures

• SLT Equipment Challenges

– No “one size fits all”

– Correlation between SLT and ATE

– Cost to add SLT

– Limited throughput

– Large form factors

Opportunities

• More systematic approaches to create

“commonality”

• Ecosystem of standards, tools, and

equipment for efficient SLT flow

• Close the loop with Data Analytics


Being Addressed

with Massively

Parallel SLT



We need higher yield!

My customers demand quality!

My new 3D packaging prevents

using certain test modes

Our TTM and TTV ramps are fast

but our test pattern generation is slow

People’s lives depend on us!

Summary: Why is more SLT needed?


Less SLT

More SLT

• Cost of SLT

• Lower quality

targets

• Concurrent Scenarios

• Guard Band Overkill

• High Speed Buses

• Complexity

• Marginal defects

• PVT Corners

• Mission Test



Reference


For additional information about SLT,

please see our whitepaper at:

https://www.astronics.com/test-systems/whitepaper-system-level-

testing-for-semiconductors

https://www.astronics.com/test-systems/whitepaper-system-level-testing-for-semiconductors













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March 4 - 7, 2018 Hilton Phoenix / Mesa Hotel Mesa ......Session 3A Presentation 2 Burn-in & Test Strategies Workshop March 4-7, 2018 Key Drivers for SLT (System Level Test) Karthik