March 3 - 6, 2019 Mesa, Arizona Archive - TestConX...Session 1B Presentation 2 TestConX Workshop March 3-6, 2019 MIPI Tiny SneakPeek: An Optimized Debug Protocol for efficient Platform

March 3 - 6, 2019

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On the Bus - Advanced bus protocols for validationTestConX 2019Session 1B Presentation 2

March 3-6, 2019TestConX Workshop www.testconx.org

MIPI Tiny SneakPeek: An Optimized Debug Protocol for

efficient Platform DebugRolf Kühnis

Intel Corporation

Mesa, Arizona ● March 3 - 6, 2019



DisclaimerIntel technologies’ features and benefits depend on system configuration and may require

enabled hardware, software or service activation. Performance varies depending on system configuration. No computer system can be absolutely secure. Check with your system

manufacturer or retailer or learn more at www.intel.com.

Intel, the Intel logo are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries.

*Other names and brands may be claimed as the property of others

MIPI Tiny SneakPeek: An Optimized Debug Protocol for efficient Platform Debug 2



Agenda• What is MIPI® Sneak Peek Protocol (SPP™)• Usage model of MIPI ® SPP™ • Conclusions and call to action




SneakPeek Protocol: A “Container”


Source: Wikipedia.de Containertransport; CC BY-SA 3.0 Source: Wikipedia Containerization; CC BY 2.0

Source: Wikipedia Intermodal container; CC BY-SA 2.0Source: Wikimedia 40 foot container double semi truck; CC

BY 3.0



SneakPeek Protocol (SPP™) Overview• Packet based protocol

– Simple enough to be implemented in dedicated HW modules

• Command/ Response protocol driven by the debug tooling (DTS)• Focus on system and debug peripheral memory access• Network latency tolerant for higher throughput while maintaining

error feedback through command/ response


Network + Adaptor

DTS TS



MIPI®: SneakPeek• No dedicated port

needed• Stability depends on

network/ PHY• Debug solution might

be impacted by power states


Memory Agent #0

SneakPeek Command Engine

SneakPeekNetworkAdaptor

System interconnect to memory, peripherals etc.

DTS

Memory Agent #1

NetworkController

Memory Agent #2

Net

wor

k C

onne

ctio

n

SoC state machine

N

W

C

S

commonregisters

AS01

regi

ster

s

AS00

regi

ster

s

AS02

regi

ster

s

PHY

Debug IP

Core 1Core 0



SneakPeek Command Engine (SPE)



Memory Agent #0

SneakPeekCommand Engine



DTS

Memory Agent #1

NetworkController

Memory Agent #2

Address-mappedchip-to-chipinterconnect

MemoryAgent #3

Net

wor

k C

onne

ctio

n

Chip 1 Chip 2System interconnect to memory, peripherals etc.

state machine

N

W

C

S

commonregisters

AS01

regi

ster

s

AS00

regi

ster

s

AS02

regi

ster

s

AS03

regi

ster

s

*conceptual

Access Spaces



SPP Command/ Response OpcodesCommands (issued by the DTS):• Pad• Nop• InitializeSPEngine• UnblockSPEngine• ReadSPConfig• WriteSPConfig• ReadSystem• WriteSystem• WriteReadSystem• LoopTrigSystem

Responses (sent by the TS):• Pad• Nop• AckInitalizeSPEngine• AckUnblockSPEngine• ReadSPConfigData• WriteSPConfigResult• ReadSystemData• WriteSystemResult• WriteReadSystemData• LoopTrigSystemResult


Memory Agent #0

SneakPeek Command Engine

Memory Agent #1

Memory Agent #2

state machine

N

W

C

S

commonregisters

AS01

regi

ster

s

AS00

regi

ster

s

AS02

regi

ster

s



Performance Impact


C

R

late

ncy

C

R

late

ncy

C

R

late

ncy

C

R

late

ncy

C

R

late

ncy

C

R

C

R

C

R

C

R

late

ncy

• Data rate strongly dependent on latency

• “Short accesses” create significant overhead due to link latency– Pipelining reduces latency overhead

• Dedicated block access further optimizes performance– E.g. supported through action/ event

* Credit: “From Virtual Targets to USB: Upcoming SoC Debugging Approaches” Michael Eick (Lauterbach) and Rolf Kuehnis (Intel); MAD Workshop 2014



What is MIPI SneakPeek Protocol (SPP)?• Layered Solution• Key elements

– FSM SPE– Data Format + Error

Handling


PHY PHY

NetworkAdaptor

SneakPeekManager

NetworkStack


NetworkStack

SneakPeekCommand

Engine

System& Debug

Memory Maps

DTS TS

MemoryAgents

DebugApplicationTransaction

Mapping


Mapping


Mapping

DebugRequests

DebugRequests

SneakPeekCommandPacketsin SPTBs

SneakPeekResponsePacketsin SPTBs

SneakPeekCommandPacketsin SPTBs

SneakPeekResponsePacketsin SPTBs

Network Data Transport Units

Network Data Transport Units

Address-mappedreads & writes

Physical (Layer 1)

Network (Layer 3)

Session (Layer 5)Transport (Layer 4)

Application (Layer 7)Presentation (Layer 6)

Data Link (Layer 2)

Conceptual OSI layers

Stopped Starting

NormalStopping

Start_SPP_FailStart_SPP_OK

NormalProtocol Flow

Stop_SPP

Stop_SPP_Done

Start_SPP

Reset

* Finite State Machine (FSM)SneakPeek Engine (SPE)



SneakPeek Protocol (SPP)• Pairing Command/Response • FullSPP can bundle several

command/responses into a single SP Transfer Block (SPTB)– Optimized for high bandwidth

interfaces

• TS does not generate spontaneous traffic


DTS Network Adaptor +Network +

TS Network Adaptor

TSSneakPeek

Memory Agent

TSSneakPeekCommand

Engine

TSSystemMemory

DTS SneakPeek

Driver

DTSDebug

Application

Prog

ram

Dow

nloa

dVe

rify

Upl

oad

Incr

easi

ng ti

me



One Size fits all?• Depending on application, the SPP

overhead is significant– Minimal header size is 16 Bytes

• The TinySPP flavor was introduced to better cope with low bandwidth I/Fs– Minimal header size is 4 Bytes– Short addressing capabilities– Introduction of actions in commands and

events in responses


Source: Wikipedia.de Containertransport; Public Domain



SneakPeek Protocol FlavorsFeature TinySPP FullSPP

# of Access Spaces 8 (3-bit field) 32 (5-bit field)

Sequence NumberN/A. Additional requirements to network:• Messages stay in order• Guaranteed Delivery• DTS/TS has to do book-keeping

Present

Standard Size Field Chosen by TS Different optionSize of Transaction Byte Count (TBC) Field 7 bits 16 bits

Short Addressing 6-bit address replacement supported. Short addressing is required in TinySPP N/A

Packet Alignment Byte aligned 16-Byte aligned

Shortest Packet Length 4 Bytes 16 Bytes




TinySPP• Optimized for low bandwidth interfaces. Primary target is MIPI I3C


Event ActionNo Event to Report No Action to be Performed

Execution State Changed to Start Change Execution State to Start

Execution State Changed to Stop Change Execution State to Stop

Trace Activity Changed (Start/ Stop) Change Trace Activity (Start/ Stop)

Reset Occurred Reset

Trigger Trigger

Trace Attention Needed Reserved

Communication (RX) Data Ready Communication (TX) Data Ready

Vendor defined Event 1 Vendor defined Action 1

Vendor defined Event 2 Vendor defined Action 2

• Focus on 32-bit systems– Use SP register to go beyond

32-bit

• “Short addressing” to optimize local accesses

• Use: – Action and event to reduce

latency



JTAG Payload• Added new opcodes with focus

on JTAG:– Write TDI don’t read TDO– Write TDI and read TDO– Polling loops and triggering conditions


0x0

0x1 0x2

0x3

0x4

0x5

0x6

0x7

0x8

0x9

0xA

0xB

0xC

0xD

0xE

0xF

Current State Next State Data Usage TMS Sequence State Progression0x0 0x0 Not Used 1[, 1, 1, …, 1] Test-Logic-Reset0x0 0x1 Not Used 0[, 0, 0, …, 0] Run-Test/Idle0x0 0x2 Not Used 0, 1 Run-Test/Idle, Select-DR-Scan

0x0 0x3 Not Used 0, 1, 0 Run-Test/Idle, Select-DR-Scan, Capture-DR

0x0 0x4 Shift Data 0, 1, 0, 0[, 0, 0, …, 0] Run-Test/Idle, Select-DR-Scan, Capture-DR, Shift-DR

Etc………



Example: SPP Data Format


FullSPP

TinySPP

Opcode Version

Reserved

Command Sequence Number

Transaction Byte Count or Reserved

AddressLow or SignatureLow or Reserved

AddressHigh or SignatureHigh or Reserved

LCP SRI COF

AccessSpace or RsvdSize or Rsvd

Action

30 2931 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Address or SignatureLow or Not transmitted

LCP Last Command PacketSRI Send Response ImmediatelyCOF Continue on FaultS Use Short Address

Opcode VersionTransaction Byte Count or Reserved LCP SRI COF AccessSpace

or RsvdActionSAddr[7:2] or Res SPCONF_ADDR[1:0]



Usage Model of MIPI SPPDebug goes network: • GbD for IP Sockets• GbD for USB• Debug for I3C SM


NetworkController

NetworkController

NetworkController

SneakPeekCommand Engine #1

OtherNetworkClient(s)

GigabitTrace #1

SPPNetworkAdaptor

GbTNetworkAdaptor

SneakPeekCommand Engine #2

SPPNetworkAdaptor

GigabitTrace #2

GbTNetworkAdaptor

NetworkController

Trace Application(GbT #2)

Debug Application(s)

OtherNetworkClient(s)

Network

GbTNetworkAdaptor

SPPNetworkAdaptor

SPPNetworkAdaptor

NetworkDriver

NetworkDriver

NetworkDriver

NetworkController

Trace Application(GbT #1)

GbTNetworkAdaptor

NetworkDriver

DTS #1

DTS #2

TS #2

TS #1



Conclusions• MIPI Sneak Peek Protocol provides a scalable debug/

test solution– Meets the high and low bandwidth link requirements– Can be implemented in Software or Hardware– Reusable solution across different product segments




Call to Action• Adopt and implement the flexible MIPI Debug Solution• Join the MIPI Debug WG

– Currently participants are SoC, IP, Tools vendors– Requires MIPI Contributor membership– Telcos every other Tuesday at 9am pacific time

• 90-120 minutes depending on the agenda– Three F2F sessions with all MIPI WGs

• Generally meet for 4 days




Further Information• MIPI Debug WG Public Page• MIPI Architecture Overview for Debug• MIPI Debug on Wikipedia




Sources unless otherwise noted• MIPI ®

– MIPI SneakPeek Protocol Specification v1.0– MIPI Architecture Overview for Debug v1.2

• IEEE– IEEE 1149.1-2013 Standard for Test Access Port and Boundary-Scan Architecture

• Wikipedia– CC BY-SA 3.0– Public domain– Creative Commons– Wikimedia Commons

• Intel® Corporation


Documents

March 3 - 6, 2019 Mesa, Arizona Archive - TestConX...Session 1B Presentation 2 TestConX Workshop March 3-6, 2019 MIPI Tiny SneakPeek: An Optimized Debug Protocol for efficient Platform