Manufacturers - Applied Materials...to a recipe-controllable process parame - ter. For core APF CD control, this pro - cess parameter is the BARC trim time. The BARC trim is typically

Serving

Semiconductor

Manufacturers

Worldwide With

Enabling Process

Technology

Serving

Semiconductor

Manufacturers

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Enabling Process

Technology

In This Issue:• AerialImaging,theUltimateDefectClassifier

• NewCleaningTechnologyforAdvancedPhotomasks

• APCfor32nmDoublePatterning

• GriddedDesignRulesforContinuedCMOSScaling

V o l u m e 6 , I s s u e 2 , 2 0 0 8

Challenges and Solutions Through-SiliconVia Technology —

Publisher: Betty Newboe

Email: [email protected]

Chief Editor: Connie Duncan


Editor: Richard Lewington


Assistant Editor: Priya Gopalakrishnan

Advisory Board: Rudi Hendel, Ph.D.,

David Kyser, Ph.D., Omkaram Nalamasu, Ph.D.,

Reza Arghavani, Ph.D.

Nanochip Technology Journal is published by Applied Materials, Inc. in cooperation with United Business Media LLC © Copyright Applied Materials, Inc. 2008, for external use.

Cover Art: Elements Group

All trademarks so designated or otherwise indicated as product names or services are trademarks of Applied Materials, Inc. in the U.S. and other countries. All other product and service marks contained herein are trademarks of their respective owners.

Front Cover: The industry is moving to 3-D packaging using through-silicon vias. Deep Reactive Ion Etch (DRIE) is the preferred technology for this etch application.

www.appliedmaterials.com

One of the most exciting developments taking place in the IC industry is the work being done on through-silicon via (TSV) technology, an emerging solution for inter-connecting 3-D chip stacks. This new approach promises better device performance, lower power consumption, reduced costs and the integration of heterogeneous devices. In this issue, we highlight the challenges and progress being made in TSV formation with an exclusive article featuring the viewpoints of some of Applied’s leading tech-nologists in this area.

Applied is working on several different TSV approaches at its Maydan Technology Center (MTC), where we are focusing on unit process robustness, cost-effectiveness and integration. This effort leverages Applied’s broad range of process technologies and extends to several joint TSV projects with key industry partners and suppliers. Being able to use the MTC to leverage the broad range of Applied's process technologies, platforms and expertise gives us broader insight into overall manufacturability and the capability to deliver optimized and differentiated solutions.

Our research at the MTC on TSV etch processes is featured in an article that reviews both via-first and via-last applications. Since each of these have very different process requirements, the etch reactor must be flexible enough to handle both approaches. We introduce a new hardware and process scheme that provides excellent sidewall roughness without any trade-off in silicon etch rate.

Much of the other research discussed in this issue has also been conducted at the MTC, including the development of a new tantalum barrier process that addresses low k dielectric damage issues in advanced dual damascene interconnect structures and a demonstration of the use of integrated metrology to improve CD control in double patterning wafers.

Representing groundbreaking work in inspection technology, an article from our engineering team in Israel demonstrates that aerial imaging detection technology is the ultimate classifer between printing and non-printing defects, since it allows a very high detection rate without nuisance effects. This property can enable a simple migration from the 65nm node to beyond 32nm by tuning the detection limit.

In addition, we are pleased to present an article from Dr. Michael Smayling – an alum of Applied’s MTC and now of Tela Innovations – on one-dimensional gridded design rules (GDR). This approach has been shown to have a number of advantages over two dimensional cells, including smaller area, better gate CD control and the elimination of hotspots. The MTC scientists have also demonstrated 22nm logic cells with Tela by leveraging the emerging Self-Aligned Double Patterning process scheme at this year’s SPIE. Dr. Smayling predicts that 1-D GDR cells will enable continued simple scaling of CMOS logic to the 16nm node and beyond.

I hope that you enjoy this issue of the Nanochip Technology Journal and find the articles interesting and informative. Please feel free to contact me or the authors if you have any questions. We appreciate your comments and feedback.

A Message from Ken MacWilliamsVice President and General Manager of Applied Materials' Maydan Technology Center

To receive extra copies of the Nanochip Technology Journal or to add colleagues to the mailing list, please email the following information to:

[email protected]

• Name • Title • Company • Business address

Ken MacWilliams

2 Closed-LoopCDControlforSADPScheme

Integrated metrology improves wafer-to-wafer CD control and minimizes double patterning overlay errors.

8 PhotomaskCleaningfor45nmandBeyond

Photoresist stripping without using haze-promoting sulfuric acid-based chemistries extends mask lifetime.

23 VirtualMetrologyImprovesThermalUniformityforCriticalAnneals

Innovative approach can significantly reduce wafer processing errors, enhance yield and minimize production costs.

28 AerialImaging–theOptimalClassifierofPhotomaskDefectPrintabilityBreakthrough inspection technique filters out nuisance non-printing defects, allowing “true” defect detection.

33 GriddedDesignRules–1-DDesignEnablesScalingofCMOSLogic

Benefits of 1-D include smaller area requirement, better gate CD control, and elimination of hotspots.

38 InnovativeEndpointTechnologyOptimizesCMPProcessControl

In situ film thickness monitoring optimizes manufacturing yield and device performance.

42 NovelApproachExtendsPVDTa BarrierTechnologyto32nmandBelow New process preserves delicate low k trench

integrity, demonstrates excellent electrical and reliability performance.

46 ReducingLowkDamagewithCO2

PlasmaEtch CO

2 plasma has the potential to replace O

2 plasma

for the ashing process.

c o n t e n t s

Special Focus: TSV 14 Through-SiliconViaTechnologies—ChallengesandSolutions

19 DeepSiliconEtchforTSVIncreasesPerformanceandProductivity

Nanochip Technology Journal Issue Two 2008 1

Volume6,Issue2,2008

2 Issue Two 2008 Nanochip Technology Journal

Closed-Loop CD Control for SADP Scheme

I n teg ra ted Met ro l ogy

Wafer-to-wafer (WTW) critical dimension (CD) control through the implementation of integrated metrology (IM) has been applied to 32nm self-aligned double patterned (SADP) wafers. A standard deviation of 0.6nm in WTW hardmask CD, despite intentionally-created disturbances in incoming lithography and reactor conditions, demonstrated that tool-level IM is a robust capability for WTW CD control in the SADP scheme.

Keywords: Double Patte rning, SADP, Integrated Metrology, Advanced Process Control (APC), Overlay Error

There are two main double patterning approaches: double exposure (DE), which uses two masks, each containing half the features of the f inal pattern; and SADP, which generates identical pairs of features from a single mask. Our SADP scheme uses two layers of APF hardmask and nitride spacers to create dense, sub-32nm line CD circuit patterns using a 65nm photomask and non-immersion optical lithography.[1] If immersion lithography is used, the SADP scheme can be extended to the 22nm node. This line-by-space process f low (Figure 1) includes lithogra-phy resist trim, top APF etch, spacer for-mation (deposition and etch), strip of top APF (also referred to as core APF), and f inal pattern transfer from nitride spacers to bottom APF as a hardmask.

Two types of CD errors are commonly seen in double patterning. One is the line CD error, which refers to the CD variation of the lines from the design target after final pattern transfer. The other is the overlay error, which refers to the odd and even space between lines on the final pattern due to an offset between two patterning steps. In our SADP scheme, all the lines are derived from the same spacer deposition and etch process with good film thickness and CD uniformity control. As a result, the line CD error is greatly mini-mized. However, an overlay error can still occur in SADP. This is because of the dif-fering origins of the two types of spaces on the final pattern. The core space originates

from core APF, which is stripped later in the process f low. The gap space originates from the gap formed during spacer deposi-tion and etch. If the core APF CD deviates from the design target, then the core space and gap space will differ in CD and cause overlay error (Figure 2). Therefore, a very important objective of process control for the line-by-space SADP scheme is to deliver core APF CD within the upper (UCL) and lower (LCL) control limits and thus minimize the overlay error in the final pattern.

Core APF CD Control MethodThe exact overlay error specif ication is a matter of debate. The double expo-

Figure 1. SADP line-by-space process flow.

Final Pattern Transfer

Trim and Etch Core APF

STI Etch and Ash

Form Spacers

Strip Core APF

Patterning

Core APF

PR

Bottom APF


■ CD control for SADP

sure double patterning (DEDP) approach has demonstrated an overlay error of 5nm.[2] The SADP approach can signif i-cantly reduce the overlay error to 3-4nm because all features come from a single exposure. However, such overlay per-formance still may not meet the stringent requirement of DP, which some believe should be as low as 1nm. This level of control requires a good understanding of the process response function and the uti-lization of WTW APC.

For th is study, an integrated metrol-ogy (IM) system provided WTW APC with both feedforward (FF) and feed-back (FB) closed loop control. The IM system is at tached to the process tool so wafer s can be measured immedi-ately before and after processing. The most commonly used technology for CD measurement i s opt ica l scat ter-ometry, or opt ica l cr it ica l d imension (OCD). This type of control scheme is well established for control l ing gate length in logic devices in high-volume manufacturing.[3] In this study, a ful ly integrated run-to-run (R2R) control system was used to provide nanome-ter-level control of gate CD,[4] show-ing that this technology can be readily adopted for SADP CD control. Our APC cont rol ler i s integ rated on the process system, which inter faces with the IM, fab host and endpoint systems to provide f lexibil ity for various APC control schemes.

To improve CD control with an IM system, two criter ia must be satisf ied. First, the post-etch CD must be related to a recipe-controllable process parame-ter. For core APF CD control, this pro-cess parameter is the BARC trim time. The BARC tr im is t ypica l ly appl ied a f ter BARC open and before n it r ide hardmask etch to br ing the core APF CD to design target. The longer the BARC tr im step, the smal ler the core APF CD. The relationship between the tr im t ime and the amount of the CD

trim needed is cal led the trim curve. It is determined by measuring the wafer before and af ter etch for a var iety of t r im t imes. The t r im amount i s the difference between these two measure-ments and is a function of the trim time. Such trim process control has been well established for gate CD control in logic devices. Because of the learning from gate etch, the etch chamber and etch process are now ready to provide stable CD control for SADP.

Second , the core APF CD cont rol should not affect the f inal l ine CD and

its uniformity. This criterion is satis-f ied for our SADP scheme since the line CD and its uniformity is mainly deter-mined by the spacer deposition, while the core APF etch determines the space between adjacent l ines. This has a lso been proven by process results, where a 12 second trim time dif ference led to a core APF CD difference of ~8nm with no difference in the f inal line CD, uni-formity and roughness.

A f lowchart of the proposed core APF CD control method is shown in Figure 3. FF control takes place by making a set

Figure 2. Ilustration of spacer mask patterning overlay error (overlay error = core space - gap space).

CoreSpace

GapSpace

Target CD

Calculate Trim Time

Recipe

Process ModuleLitho CDIM

Core APF CDIM

TrimCurve

WTW

FF

WTW

FB

Wafer Movement

Data Flow

Figure 3. WTW APC process flow.



of CD measurements across the wafer using IM before the wafer is sent to the process module. The mean CD on that wafer is then calculated. The amount of tr im needed is then computed based on the mean pre-etch CD on that wafer, target CD, the trim curve, the current feedback of f set , and any add it iona l offset needed. The recipe settings for

that wafer are then changed based on this newly calculated trim time. After the wafer is etched, it is sent to the IM module for post-etch CD measurement. The measurement is performed at a set of sites across the wafer and the mean CD is computed. The feedback offset is calculated from the difference between the measured and expected CD values,

and then further adjusted by using an exponentially weighted moving average (EWMA) f i lter. The feedback offset is then applied to the FF calculation for the next wafer.

SADP APC DemonstrationTo test the funct iona l it y of the etch system and demonstrate the benef it of applying WTW APC to core APF etch, an APC demonstration was carried out on Applied’s 32nm SADP wafers by using the AdvantEdge G5 chamber.

OCD Modeling The f irst step in implementing IM for core APF CD cont rol was to create scatterometry models and libraries that provide precise CD measurement on pre- and post-etch wafers. An optimized OCD model represents the expected var iat ion seen in normal product ion while minimizing the contr ibution of insensitive parameters to critical output such as CD and sidewal l ang le. The OCD metrology tool on the etch sys-tem used in this demo was the NOVA 3090. The OCD models and l ibraries were created off line on a NOVA MARS station. Figure 4 shows the l itho and post-core APF etch f ilm structures used in the OCD models, with the measured parameters.

The libraries created from both models were va l idated by compar ing the CD va lues repor ted by OCD with those repor ted by CD-SEM a s shown in Figures 5(a) and 5(b). There are strong correlations between results from these two dif ferent CD measurement tech-nologies over a wide range of CD varia-tion, which validates the OCD models and libraries. Once instal led on the IM module the libraries were available for WTW APC.

Trim Curve Characterization Once the OCD l ibr a r ie s were c re-ated and va l idated, the next step was to character ize the tr im curve, which

Width (nm)

Heig

ht (n

m)

630

60 120 180

PR CD

PR Height

Nitride Thickness

Core APFThickness

240 300 360 420 480 540

560

490

420

350

280

210

140

70

0

400

40 80 120 160 200 240 280 320 360 400

Top CDSidewallAngle

Core APF Height

Bottom APFThickness

350

300

250

200

150

100

50

0

Width (nm)

Heig

ht (n

m)

Figure 4. OCD model of the SADP film stacks (top) before patterning and (bottom) after core APF etch.



represent s the rel at ionsh ip between trim amount and trim time. Six wafers were etched, with the trim time vary-ing from 3 to 12 seconds. Each wafer was measured before and after core APF etch in the IM module. The dif ference between these two measurements was calculated and plotted against the trim time applied (Figure 6). The relation-ship between the trim amount and trim time was very well described by a lin-ear function. Based on this l inear tr im

curve, the FF ca lcu lat ion dur ing the APC test was such that

CDfeedback is given by:

where l= 0.4 , CDo f f s e t = 8.44n m, CDtarget =38.0nm, trim rate =0.78nm/s. CDoffset accounts for the sum of CD bias

induced from all other etch steps except BARC trim.

IM Data Collection Plan The impact of IM on wafer through-put is always a concern in WTW APC. The goal of the IM data collection plan was to minimize the IM measurement time while stil l measuring enough sites on the wafer to have true mean CD. In order to achieve this goal, a total of 92 dies were measured on the whole wafer. Then 17 dies were selected as shown in Figure 7, which yielded very simi lar mean CD and standard deviation as that of all 92 dies. These 17 dies were later measured on every wafer before and after etch in the IM module during the APC demonstration to provide input for FF and FB control.

Design of the APC Test Unl ike the situat ion in a product ion fab where large wafer populations are available for monitoring and testing of an APC scheme, the number of SADP wafer s ava i l able for th i s s tudy were l imited. Therefore, the APC test was designed to demonstrate WTW APC behavior under var ious expected pro-duction variations with only 22 SADP demonstration wafers.

In order to simulate lot-to-lot lithogra-phy CD variation and demonstrate the benef it of FF control, the 22 SADP dem-onstration wafers were patterned with different target CDs. The f inal litho CD variation in this group of wafers had a range of 6.2nm with a standard deviation of 1.49nm.

These 22 demonstrat ion wafers were split into three groups during the APC demo. Five wafers were etched with no APC appl ied , i .e. they were a l l etched using exact ly the same cham-ber and baseline recipes. The post-etch CD va lues of th is g roup would pro-vide a comparison for the WTW APC scheme. The second g roup had ten

Figure 5 (a). CD-SEM measurements vs. OCD measurements on litho CD.

Figure 5 (b). CD-SEM measurements vs. OCD measurements on core APF CD.

60

58

56

54

52

50

4848 50 52 54 56 58 60

CD-S

EM (n

m)

OCD (nm)

y = 1.1066x - 6.9242

R2 = 0.9705

50

49

48

47

46

45

44

43

42

41

4032 34 36 38 40 42

CD-S

EM (n

m)

OCD (nm)

y = 0.9521x + 9.9881R2 = 0.9562



wafers, etched with FF and FB closed loop control from WTW. The baseline process recipe was used with only the t r im t ime adjusted by the APC con-trol ler. Results from this group were used to demonstrate the benef it of FF control with minor process excursions. There were seven wafers in the third group. The O2 f low rate in the t r im step for this group was increased from 12sccm in the baseline recipe to 15sccm to simulate an unexpected disturbance in the process chamber. The O2 f low

increase could ef fectively increase the trim rate and result in smaller CDs on the wafer i f lef t uncorrected. Results f rom th i s g roup wou ld be u sed to demonstrate the benef it of WTW FB control.

SADP APC Demonstration Results The post-etch core APF CD va lues mea su red on a l l 22 demon s t r a t ion wafers are shown in Figure 8. Group one has the highest CD var iat ion, as expected. This indicates the ef fect of

litho CD variation on the post-etch CD if no process control is applied.

Although group two has similar l itho CD variation as that of group one, the post-etch core APF CD is wel l kept within the +/-1nm control band. This is because of the FF control applied to this group of wafers that effectively cor-rected the CD variation in the incom-ing wafers. The benef it of FB control is minimal for this group of wafers, as shown by the dif ference between the CD values in green (simulated results assuming no FB applied) and real CD values in pink. This was expected since the benef it of FB control is its capability to detect process excursions and make corrections. When the process is at a stable state, there is not much FB cor-rection needed.

The FB benef it is clearly demonstrat-ed by the CD va lues in g roup three. Only the f irst wafer in the group has a post-etch CD outside the control band. I f the FB control was not appl ied to th is g roup of wafer s, their post-etch core APF CD would have been ~1nm smaller than the design target as shown by the CD values in green in Figure 8. The abi l ity of tool level FB control to immediately detect and correct a pro-cess excursion and reduce the number of wafers at r isk is clearly demonstrated by these results.

Over a l l , t he W T W FF+F B c lo sed loop APC control was able to del iver a post-etch core APF CD wel l within the (design target +/-1nm) control band with a 3σ va lue of 1.7nm despite the wide incoming CD var iat ion (range: 6.2nm, 1σ : 1.49nm) and O2 f low dis-turbance in the etch process.

ConclusionThe WTW closed loop APC has been succes s fu l ly appl ied to 32nm SADP wafers to provide tight control of core APF CD and thus min imize overlay

Figure 7. The IM data collection plan for the SADP APC demo. Each die contains multiple 100x100μm 2-D gratings for OCD measurements (red circles).

0

-4

-8

-12

-16

-200 2 4 6 8 10 12 14

CD B

ias

(nm

)

Trim Time (s)

y = -7.7928x - 8.4406R2 = 0.9819

Wafer Map Die Map

Figure 6. The core APF etch trim curve shows a linear relationship between trim time and change in CD (CD bias).



error from DP schemes. Although the APC test conducted is relatively simple compared with similar APC tests in a product ion env ironment, the resu lt s clearly prove the functionality of OCD metrology as a solut ion for tool level APC and demonstrate the benef it of WTW APC control in an SADP pro-cess f low.

AcknowledgementsThe author s a r e e spec i a l l y g r a t e -fu l to Huix iong Dai of the Maydan Technolog y Center for per form ing l ithography on the SADP APC demo wafers to generate litho CD variation as designed. The authors would also like to thank Applied’s Yongmei Chen, Jessie Blanquet, Ming Xu, Opher Harel, and

Verlyn Fischer for their special contri-butions. ■

References [1] C.Bencher,“SADP:TheBestOptionfor32nm

NANDFlash”,NanochipTechnologyJournal,

IssueTwo,2007.

[2]“SADPmostcost-effectivefor32nmnode–

AppliedMaterials,”ElectronicsWeekly,March

11,2008.

[3]M.Sendelbach,etal,“Integratedscatterometry

inhigh-volumemanufacturingforpolysilicon

gateetchcontrol”,Proc.ofSPIEVol.6152,

61520F,2006.

[4]D.Muietal,“In-toolprocesscontrolfor

advancedpatterningbasedonintegrated

metrology”,Proc.ofSPIEVol.5378,2004.

Applied Centura® AdvantEdge™

G3 Silicon Etch

Process System Used in Study

• Exact CD control and CD uniformity to within 2mm of the wafer’s edge

• Run-to-run control with closed-loop feedback from optional integrated OCD metrology

• In situ resist trimming capability

Lei Lianisamemberofthetechnicalstaff

inAppliedMaterials’SiliconEtchDivision.

She iscurrentlyworkingonetchprocess

endpoint control, advancedprocess con-

trol for SADP, andplasma statemonitor-

ingandprocess chambermatching. She

has a Ph.D. in theoretical and applied

mechanics from theUniversityof Illinois

atUrbana-Champaign.

Jaklyn Jin isamemberofthetechnical

staff in Applied’s Silicon Etch Division.

She has a B.S. in materials science

from the Univers i ty of Sc ience and

TechnologyofChina.

Corne l Bozdog has he ld d i f ferent

ro les as appl icat ions sc ient ist and

applications group manager at Nova

Measuring Instruments. He is the 2007

recipient of the “Nova Expert” fellow-

sh ip and i s cur rent ly the product

manager of the NovaMARS sof tware

for scatterometry appl icat ions. He

receivedhisPh.D. insolidstatephysics

from Lehigh University and his B.S. in

physics from University of Bucharest,

Romania.

Article Contact: [email protected]

45

44

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41

40

39

38

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36

351 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

Post

-etc

h CD

(nm

)

Wafer Number

Group 2 FF and FBGroup 3 FF, FB

with Process ExcursionGroup 1 Baseline

Lith

o CD

(nm

)

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58

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52

51

50

49

48

Post-etch CDPost-etch CD with no FB

Target CDLitho CD

Authors

Figure 8. The SADP APC demonstration results for the three wafer groups showed improve-ment in CD control from the application of WTW APC.


Photomask Cleaning for 45nm and Beyond

Photomask C l ean ing

As the semiconductor industry moves to 45nm and beyond, the cleaning of advanced photomasks becomes much more challenging, requiring new technology solutions. The major challenges are particulate cleaning on blank masks, damage-free cleaning for post-etch and post-repair applica-tions, preserving film integrity, and sulfur-free cleaning to reduce haze growth. New photomask cleaning technologies have been developed to meet these demanding cleaning requirements.

Keywords: Photomask, Mask Cleaning, NanoDroplet Technology (NDT), Haze

The photomask manufacturing process is shown in Figure 1. Although this f low is less complex than a wafer f low, the defect requirements are much more stringent. On a wafer, a defect affects only a single die, whereas mask defects get printed on every die. Thus, a mask cleaning system must provide defect-free performance without altering optical properties or damaging the sensitive structures. Applied Materials developed the Tetra Reticle Clean system to meet the above challenges. In this paper, the technologies that enable phototresist strip and damage- free cleaning in the new clean system are presented.

Clean System DesignThe new clean system integrates dry and wet process chambers. The dry chamber is based on a remote plasma source and is used for photoresist strip and surface pre-treatment applications. The wet process-ing chamber is equipped with advanced damage-f ree clean ing technolog ie s including proprietary Uniform Cavitation Megasonics (UCM) and NanoDroplet Technology (NDT).

Damage-Free CleaningA viable cleaning technology has to remove defects without damaging the

Mask Blank

Order Information

Reticle layout

and data fracture

Resist Coat Pattern Generation Resist Develop Etch

Metrology Strip and CleanCleanDefect InspectionRepair

Final Inspection To Wafer FabApply PellicleCleanDefect Inspection

Figure 1. Typical phase shift mask process flow. Each mask is cleaned several times during manufacturing.


sensitive mask features. Table 1 shows the technology node and the corresponding sub-resolution assist feature (SRAF) sizes according to the 2007 ITRS. The SRAF size is very small for advanced technology nodes and it is critical to remove contami-nants without damaging these features during mask cleaning.

Megasonics is commonly used for parti-cle removal. Historically, “f inger-based” megasonics, where acoust ic energy is applied to the stream of a cleaning f luid at the delivery nozzle, is known to cause

localized SRAF damage. UCM technol-ogy has been demonstrated to have a large damage-free cleaning window and is in use for 45nm production. With UCM, the energy is transmitted uniformly from the back side of the mask to the front side of the mask where the critical features are located. By transmitting the energy from the back, the mask itself acts as an attenu-ator, thus reducing the delivered energy level to the top side of the mask. Besides energy control, this approach cleans both sides of the mask simultaneously, reduc-ing the total process time for improved throughput.

While UCM can be used for 45nm, a new mixed f luid jet nozzle technology called NanoDroplet was developed to further reduce the potential for SRAF damage without compromising particle removal

eff iciency (PRE) for 32nm and beyond. NDT is a momentum-based cleaning technique that delivers microscopic liquid droplets to the mask surface. As described by Haller et al. in their fundamental study of droplet impact onto a substrate, the impinging droplets create a pressure front at the impact zone resulting in a radial or lateral jetting f low of liquid.[2] The lateral liquid f low induces a drag force, FD, on particles, enabling their removal from the mask when this drag force exceeds the van der Waals interaction force, FvdW, between the particle and the substrate (Figure 2). For 65nm particles, FD is estimated to be an order of magnitude higher than FvdW with appropriate NDT parameters.

Prudent design of the mixed f luid jet nozzle is critical to obtain desired droplet characteristics for damage-free cleaning. One of the major limitations of conven-tional nozzles is that their droplet velocity/size distribution has a relatively signif icant tail of large diameter droplets (Figure 3). The kinetic energy of a droplet, Ek is pro-portional to the cube of its diameter, d, per the following equation:

where ρ is the f luid density and v is veloc-ity. These large diameter droplets result in a corresponding high energy tail in the droplet kinetic energy distribution, and

■ Advanced Photomask Cleaning

Table 1. Assist feature size and defect size for 65nm and below technology nodes.[1]

2007

65

85

52

2008

57

76

45

2010

45

60

36

2013

32

42

26

2016

22

30

18

Production Year

Technology Node (nm)

Sub-resolution Feature Size (nm)

Defect Size (nm)

Manufacturable solutions exist, and are being optimized

Manufacturable solutions are known

Manufacturable solutions are NOT known

Figure 2. NDT mechanism showing the drag and van der Waals forces exerted on a defect during cleaning.

NanodropletTechnology

Conventional Nozzle

Velo

city

(au)

Droplet Diameter (au)

Substrate

FVdW

FD

Vf

Defect

Figure 3. Conventional nozzles create damage-inducing large diameter outliers (circled area). NDT generates droplets with uniform small size distribution to enable damage-free cleaning.


can induce damage to sensitive mask fea-tures and erode the inside of the nozzle. Consequently, a new nozzle design was developed to eliminate the large drop-let size/high energy tail. Phase Doppler analysis was used as a diagnostic tool to characterize the nozzle droplet size and velocity distributions and to help guide the design optimization.[3]

Particle Removal EfficiencyPRE is the standard metric used to evalu-ate cleaning capability, and is def ined as the percentage of particles cleaned rela-tive to the original particle count.[4] To conduct PRE testing, unpatterned blank masks are “contaminated” with several thousand particles using a wet deposi-tion method. The blanks are comprised

of industry-standard f i lm stacks (e.g., NTAR7 binary masks and TF11 phase shift masks). Particle counts are measured before deposition, after deposition, and after cleaning using a Lasertec 2351 par-ticle counting system. This PRE testing simulates removal of actual particles that contaminate the mask during the fabri-cation process. Polystyrene latex spheres (PSL) and si l icon nitr ide (Si3N4) par-ticles are used to simulate organic and inorganic particles, respectively. Figure 4 shows the PRE performance obtained on un-patterned NTAR7 photomask blanks for Si3N4 particles. Similar PRE of >99% is achieved with PSL on NTAR7 blanks (Figure 5). Additional data on TF11 blanks, the most common phase shift mask type for 45/32nm applications, showed similar results.

Figure 6 shows data on the performance of NDT compared to conventional meth-ods. The particle measurement system sizes and classif ies particles in pixels. The correlation between pixel-sized binning and par t icle diameter var ies between metrology tools, but smaller pixel sizes correspond to smaller particle diameters. NDT-based cleaning shows superior per-formance across all bins compared to con-ventional PTOR clean.

As mentioned previously, the high PRE must be achieved without feature damage. Repeatable damage-free cleaning has been demonstrated using NDT on damage test masks for sub-50nm Cr/MoSi lines (32nm technology node) as shown in Figure 7. The same process was run on a set of PRE masks deposited with Si3N4 particles. The PRE was repeatable > 98% (Figure 7), demonstrating a robust window for dam-age-free cleaning with high PRE.

Photoresist RemovalPhotore s i s t s t r ipping i s per for med af ter mask etching steps and a l so for rework dur ing patterning. The over-a l l st r ip+clean process must remove photoresist and post-etch residues, and


Figure 4. Representative PRE performance (>99.9%) for >80nm Si3N4 particles with NDT cleaning shown by defect maps for a mask (left) before deposition, (center) after Si3N4 particle deposition, and (right) after NDT cleaning.

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Figure 5. Representative PRE performance (>99%) for >80nm PSL particles on NTAR7 masks with NDT cleaning as shown by defect maps for a mask (left) before deposition, (center) after Si3N4 particle deposition, and (right) after NDT cleaning.


leave the mask free of particle defects. In addition to the bulk photoresist layer, all photoresist on the vertical and hori-zontal edges of the mask must a lso be completely removed. Typically the edge photoresist is thicker and takes consider-ably longer to str ip than the bulk. For masks with negative photoresist or with posit ive photoresist plus an edge bead removal step after coating, the edge resist is less of a concern. However, there is still a bump of thicker resist at the outer perimeter of the bulk resist region.

Conventional photoresist stripping uses a sulfuric acid/hydrogen peroxide mix-ture (SPM) for both bulk and edge resist. In some cases, sulfuric ozone chemistry (SOM) has been used in which sulfuric acid and ozone is mixed instead of hydrogen peroxide.[5] Although fast and effective at removing organic photoresist, sulfuric acid-based chemistries leave chemical residuals on the surface of the mask that can lead to the formation of haze. Strategies have been implemented to minimize the residue, such as hot water rinsing, UV light, or thermal treatments,[5] but these have proven only partially effective. The complete removal of sulfuric acid from the process f low is desir-able for not only mask cleaning purposes but also for environmental reasons.

The Tetra Clean system enables the strip+clean process to be accomplished with either a dry/wet or an all-wet pro-cess, both of which are sulfur-free. For the dry/wet approach, stripping is performed in the dry remote plasma chamber. This chamber is equipped with multiple gases for str ipping dif ferent types of resists with high selectivity to underlying f ilms. For wet stripping, photoresist is removed in the wet chamber using an ozonated water (DIWO3) process. A f inal clean in the wet chamber is performed after dry stripping, or incorporated into the end of the all-wet process sequence.

Overall, the dry/wet approach is favored for str ip+clean appl icat ions. In addi-

tion to providing ~ 30% faster photore-sist strip rates, using remote plasma for stripping signif icantly reduces DIWO3 exposure time and potential feature ero-sion issues. An added benef it of dry pro-cess capability is for surface pretreatment in the cleaning of blank masks. Blanks typica l ly have an organic residue due to outgassing from shipping and storage containers, and high quality cleaning is dif f icult unless this organic residue is removed initial ly. A short plasma pre-treatment has proven to be very effective for removing these organic residues, and also offers higher productivity relative to conventional approaches such as UV treatment.

Representat ive part icle data after dry str ipping+wet cleaning are shown in Figure 8. The f ina l par t icle count is approximately twenty, and most of these defects are concentrated in the smaller particle size bins. Additional f inal clean-ing does not substantially reduce the par-ticles further, indicating that the dry/wet process performs resist removal and f inal particle cleaning as intended.

Haze ControlManaging haze is one of the most critical issues in the lithography process. There are three main causes of haze as described below.

• Sulfateionresiduesonthemasksur-


Conventional cleanNDT-based clean

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Figure 6. Bin by bin PRE performance on Si3N4 particles for NDT and conventional clean-ing processes.

Figure 7. Repeatability results using two sets of blank and sub-50nm line/space patterned masks (inset) subjected to the same NDT cleaning recipe. The average PRE was 99% with zero damage.

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face combine with ammonium ions in the presence of high energy light during stepper exposure (particularly ArF 193nm) to form ammonium sul-fate crystals. These are the most com-monly reported as progressive haze defects.

• Thebreakdownoforganic-containingpellicle gasket and adhesive materials also occurs during repeated exposure of the mask in the stepper. This results in outgassing of organics and subsequent reaction with moisture and ammonia on the mask active area to form haze.[6]

• Themaskstorageenvironmentaffectsthe residual mask contaminant level, even without photon exposure, and could cause haze issues.

The best solut ion to prevent and/or reduce haze problems is to avoid using sulfur-based chemistries such as sulfuric peroxide mixture (SPM) in mask clean-ing. The Tetra Clean uses ozone-based chemistr y for improved haze per for-mance. Figure 9 shows the sulfate and ammonium ion levels as measured by ion chromatography for conventional and Tetra Clean processes. It can be noted that the Tetra Clean process shows sig-ni f icant ly lower residua l ions lef t on the sur face of the mask compared to

conventional SPM processes. Figure 9 also shows haze threshold energy on the secondary y-axis for both conventional and Tetra Clean processes. These data were generated using a haze accelera-tion test bench where the cleaned mask is exposed to high laser energy to pro-mote haze g rowth in a shor t per iod of time. It is shown that the threshold energy for haze growth is much higher for masks processed with Tetra Clean

process using ozone-based chemistr y compared to SPM based cleaning chem-istry. Higher threshold energy results in increased mask lifetime in the wafer fab and reduced number of recleans.

Film IntegrityPreserving the f ilm integrity is a criti-ca l measure of a good cleaning pro-cess. Film integrity can be evaluated by measuring phase loss and transmittance change for attenuated phase shift pho-tomasks (APSM) and ref lect iv ity for binary masks (BM). For APSM masks the at tenuator layer induces a phase shift to enhance patterning resolution. Precise control of phase (change in opti-cal path length between two regions on the mask expressed in degrees) is essential for accurate patterning of small features. The mean value of phase is determined by averaging measurements for many features on the mask. Figure 10 shows the phase loss and transmittance change per clean for conventional and Tetra processes. As shown, the Tetra Clean ozone-based pro-cess is signif icantly better in preserving f ilm integrity than SPM chemistry.

Future Cleaning ChallengesThe next generation of masks wil l be more sensitive to damage due to smaller features and have even tighter defectivity


Figure 8. Post strip+clean particle map for FEP photoresist stripped from TF11 photomask.

Figure 10. Comparison of the phase and transmittance change per clean on APSM masks for conventional vs. Tetra Clean processes.

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Figure 9. Residual surface ions and haze threshold energy for conventional and Tetra Clean processes.

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requirements than current technologies. Therefore, control l ing contamination with effective cleaning technology will be critical. Extreme ultraviolet (EUV) l ithography is being considered as an alternative to current optical patterning methods and will be a signif icant depar-ture from the DUV lithography masks used today. The EUV masks will be com-posed of multilayer stacks of new materi-als which will bring new challenges in maintaining optical and topographical integr ity including dif ferent types of post-etch residues and material selectivity to cleaning chemistries. The Tetra Clean system is designed for extendibility and work is on-going to develop next genera-tion NDT and megasonics technologies.

ConclusionTetra Clean technology meets the strin-gent cleaning requirements for advanced

photomask cleaning for 45nm and below processing. The use of integrated dry and wet processing sequences enables fast pho-toresist stripping without the use of haze-promoting sulfuric-acid based chemistries thus extending mask lifetime. UCM has shown damage free cleaning while achiev-ing >99% PRE for 45nm technology node masks. A new mixed-jet f luid technology (NDT) has been developed and damage free cleaning was demonstrated for 32nm processing using masks with sub-50nm SRAFs and 32nm line and space features on nano-imprint masks. ■

References [1] Lithography – Optical mask requirements, avail-

able at http://www.itrs.net, ITRS 2007.

[2] Haller K.K. et al., “Computational study of high-speed liquid droplet impact”, J. Applied Physics, 92(5), 2821-2828, 2002.

[3] Bachalo W.D. et al., “Phase/Doppler spray ana-lyzer for simultaneous measurements of drop size and velocity distributions,” Opt. Eng. 23(5), pp. 583–590, 1984.

[4] Gouk, G. et al., “Advanced damage-free photo-mask cleaning for 45/32nm technology nodes” Photomask and Next Generation Lithography Mask technology XV, Proc. SPIE 7028, 702808-4, 2008.

[5] Kindt, Let al., “Sulfur-Free Cleaning Strategy for Advanced Mask Manufacturing”, Photomask Technology 2006, P.M. Martin and R.J. Naber, eds., Proc. SPIE 6349, 63491J, 2006.

[6] Kalk F. et al., “Photomask defectivity and clean-ing: A new Milieu,” Semiconductor International, (Sept-2007).

Applied Tetra™ Reticle Clean


• Delivers damage-free cleaning with 99% particle removal efficiency for 32nm and beyond

• Dry/wet technology offers maximum flexibility for applications including strip, post-etch clean, and final clean for all mask types

• Highest productivity due to simultaneous front/back cleaning, short process times, and 2-step mask processing

Evans Baiya is a global product manager for photomask cleans in Applied’s Etch and Cleans Unit. He is responsible for product strategy development, product marketing, and project management of all photomask cleaning activities. He has an MBA from Northwest Nazarene University.

Jim Papanu is a senior technology manager for photomask cleans in Applied’s Etch and Cleans unit. He has B.S. and M.S. degrees from Case Western Reserve University, and a Ph.D. from University of California, Berkeley, all in chemical engineering.

Ro m a n G o u k i s a m e m b e r o f t h e techn ica l s ta f f w i th App l ied ’s Etch and Cleans unit , working on process deve lopment for photomask c lean -i n g a p p l i c a t i o n s . H e re c e i v e d h i s B.S. and M.S. degrees in mechanical eng ineer ing f rom the Un ivers i ty of Minnesota.

Jason Jeon is a process engineer in Applied’s Etch and Cleans unit, focusing on process development metrology/inspection for mask clean applications. He received his Ph.D. in solid state physics from Moscow State University.

Tong Liu is a process engineer in Applied’s Etch and Cleans unit. She is responsible for process and technology development, customer demos and on-site support. Tong has a Ph.D from Rensselaer Polytechnic Institute, and M.S. and B.E. degrees from Tsinghua University, China, all in materials science and engineering.

Rao Yalamanchil i is the director of Applied’s Photomask Cleans group. He received his masters degree from the Indian Institute of Technology, Bombay, and a Ph.D. from the University of Utah, both in metallurgical engineering.

Brad Eaton is the global product market-ing manager in Applied’s Etch and Cleans unit. His responsibilities include managing global product marketing activities across etch and cleans for mask products. He has an MBA from Santa Clara University.

Ajay Kumar is the general manager of Applied’s Mask Etch and Cleans group. He received his Ph.D. in applied physics from the Indian Institute of Technology.


Authors




New Techno logy

Why is the industry adopting TSV, and what are the markets and applications driving this technique?Sesh Ramaswami: Let me start off by providing a context for TSV development. TSV is an evolution of 3-D packaging, com-bining the best aspects of system-on-chip (SOC), where different functional blocks are fabricated on the same substrate, and system-in-package (SIP) schemes. In TSV wafers or the chips are stacked on top of each other, and are connected using vertical pathways of interconnects (instead of wires) that run completely through the chips. The chips can be of the same type or of different types, referred to as homogenous or heterogeneous integration, respec-tively. For end-product companies, this approach opens up the supply chain and lowers their cost by enabling them to procure different components from various suppliers − and scale them at different rates, hence different costs curves – and integrate them using TSV.

In homogenous integration, there might be four or eight DRAM chips, for example, stacked up with tens of copper interconnect vias

running through them. This results in one chip with the memory equivalent of eight individual chips in a smaller form factor. Using these DRAM chips in a server would consume less board space and also reduce the latency and improve the bandwidth between the microprocessors and the DRAM.

For communications devices like Blackberries and iPhones, wire bonding is used today to connect chips of various types. These chips are mounted on multi-layer substrates. By using copper to intercon-nect devices in 3-D with several thousand vias interconnecting them, one can get more functionality from the same real estate.

An established application for TSVs is in CMOS image sensors, where manufacturers have already implemented TSVs at 200mm and will be migrating to 300mm starting next year. Although the technical requirements here are less challenging, cost is a major issue. In a nutshell. we expect significant growth in the design-in of TSV in communication and DRAM chips in 2009 and 2010 with significant growth to begin around 2011.

Through-SiliconViaTechnologieS— ChallengesandSolutions

SPECIAL FOCUS : TSV


TSV i s emerg ing as a c r i t i ca l techn ique

f o r s c a l i n g , p a c ka g i n g a n d c o n t i n u i n g

the d r i ve to h i ghe r dens i ty and h i ghe r

pe r fo rmance ICs . We assemb led a pane l

o f A p p l i e d ’s l e a d i n g t e c h n o l o g i s t s i n

t h i s f i e l d t o d i s c u s s t h e c h a l l e n g e s

and so lu t i ons needed to imp l ement and

acce lerate new TSV integrat ion schemes.

Panelists include Sesh Ramaswami, Brad Eaton, John Dukovic, Nitin Khurana, Sherry Xia, Balaji Chandrasekaran, and Kedar Sapre.


■ TSV Etch Technology

What are some of the key challenges for TSV applica-tions?Sesh Ramaswami: Challenges associated with EDA tools and mod-els, device reliability, cost-effective unit processes and process integra-tion on thinned wafers need to be solved to enable the adoption of TSV technology into high volume devices. We are mitigating process risks for customers by integrating proven materials, films and equip-ment into the TSV scheme. Key unit processes are etch, dielectric oxide liners, PVD barrier/seed, low temperature oxide/nitride films, plating and CMP.

There are two main choices for TSV processing. Chipmakers that choose to introduce TSV at the FEOL use the via-first scheme that requires the most changes to interconnect circuit layout. A simpler way to introduce TSV is at the back end of line – via-last. In the via-last approach, the vias are formed after BEOL or bonding, on a full thickness wafer from the front-side or from the backside on a thinned wafer. Also, the via size and aspect ratio are important to understand since they drive the integration schemes.

CMOS image sensors have via sizes >40 um with>2:1 aspect ratio. For other devices, the vias range from 3-20μm, with wafer thickness (which determines aspect ratio) ranging from 30-125μm.

Device wafers are typically bonded to carriers (glass or dummy silicon) prior to thinning down to the 30-125μm range. Bonding, grinding, wafer processing on bonded/thinned wafers and subsequent de-bond-ing are hence very important steps in the wafer f low. Once bonded,

processing temperatures cannot exceed 200°C. Since significant ‘value’ is added by the business entity that processes these wafers, we see a ‘value tussle’ between foundries and packaging houses, which in turn drives integration requirements. One can well imagine that a packag-ing house does not want to be tagged with breaking valuable thinned wafers coming to them from a wafer fab.

John Dukovic: There are various dimensions to TSV technology that will have to come together before it can go into mainstream vol-ume production. While CMOS image sensors have led the way in unit volume, they do not constitute high volume in terms of new 300mm wafer starts. The volumes are expected to be large for stack-ing memory chips and for joining logic and memory chips together to achieve faster bandwidth and lower latency. You could combine two chips using conventional wire bonds, but the inductive losses will make the data exchange too slow. These types of TSV applications present new design challenges, especially if a logic chip is married to a memory chip. Designers will have to work off of the same plan and line up the connection points between the two chips. There is also the thermal question: will this chip now be too hot and is there a good way to release the heat? Finally, we also need new automatic test capability compatible with 3-D integration.

What is the cost factor for TSV? Sesh Ramaswami: For TSV to be adopted in high volume, cost is an over-riding factor. For example, there are early indications that a 30% cost increase relative to wire-bond can be tolerated since TSV enables a much higher return in value at the system level. However, this needs to be watched carefully, since the economics on the value side may change rapidly. A couple of years ago, the TSV process added

Through-SiliconViaTechnologieS— ChallengesandSolutions

■ TSV Challenges and Solutions

SESH RAMASWAMI is senior director of Strategy and Marketing in Applied’s Silicon Systems Group.

JOHN DUKOVIC is a distinguished member of technical staff in the Silicon Systems Group.



about $300 or $400 per wafer. There are roadmaps to get it to the sub-$150 range. The biggest contributors to cost are bonding/de-bonding and copper fill. Applied’s joint work with suppliers in these areas will help reduce cost.

What processing tools will be required for TSV? John Dukovic: Certain new process systems will be needed depending on how the TSV technology is implemented. One area that will change is the formation of via holes, which was origi-nally done with laser ablation. As the number of vias grows and the damage-free requirements increase, this method will soon be unworkable. Instead, the vias will be formed using deep reactive ion etch technology.

After the hole is etched, if the via was immediately lined and filled with metal, it would be shorted to the body of the silicon. So the hole must first be lined with an insulating layer of oxide. Assuming copper is the metal for the via, a second liner that is a barrier to copper diffusion is also needed. Alternatives to copper have been explored. Tungsten is a possibility, especially for the via-first f lows, and polysilicon has also been tried. Copper is likely to prevail in mainstream applications for reasons of conductivity and cost.

Suitable barrier materials for copper TSVs are the same as those deposited for advanced logic devices: titanium or tantalum. Deposition uniformity is critical since very-high-aspect-ratio struc-tures are historically tricky for PVD. However, we’ve had some excellent results with extensions of our PVD technology and we are encouraged by the possibilities there.

Filling the via with copper will almost certainly be done by electro-plating. We are partnering with Semitool on plating, and conducting integrated process-sequence development together to co-optimize the etch, dielectric liner, barrier/seed and plating steps..

An additional step in the sequence, in some applications, is CMP. Currently, three process schemes using CMP in TSV devices have been identified. They are pre-transistor via , post-transistor via first and post-transistor via last schemes. The former scheme requires an oxide CMP processing step while the latter post-transistor schemes can use copper CMP for both via-first and via-last approaches

It’s notable that all processes performed after the wafer has been bonded to a carrier and thinned must be below 200°C. These include PVD and dielectric CVD oxide and nitride films, stress-relief Si CMP and copper CMP.

What progress has Applied made with technologies for TSV? Brad Eaton: On the wafer, the smallest CDs for via-first schemes tend to be 5-10μm. Via-last CDs are 25-100μm, typically with 5:1 to 10:1 aspect ratios. We have a lot of experience with these types of materials and aspect ratios and we have a long history of deep silicon etch, from very high aspect ratios. Our HART system is used for etching trench capacitors with aspect ratios as high as 80:1. Also, we have a 200mm DPS system running TSV in production for CMOS image sensors.

The biggest challenge is to etch very, very fast and maintain a low cost of ownership. Etch profile is another technical challenge. With the traditional Bosch process approach that consists of rapidly alternating etch and deposition steps, there is a significant trade-off between the quality of the profile and the etch rate. You can etch very quickly but have poor quality profiles or you can etch very slowly and have excellent profiles.

We have found a way to the profile requirements with etch rate to get the smoothest sidewall to ensure that subsequent deposition steps are of high quality and have good electrical characteristics. To achieve this, we have modified a proprietary process in our new Silvia etch system. This will have a substantial impact on cost of ownership and provides the fastest silicon etch rate on the market.

There is another method that others are pursuing, utilizing a steady-state process. It’s not a multi-step etch/dep process, but rather a sim-pler single-step deep etch. However, it has very poor tapers and undercut, so it’s generally not the favored approach where high aspect ratios and high selectivity to resist are required. The approach has proven sufficient for low via density and low aspect ratio applications such as CMOS image sensors. However, the high plasma density of Silvia’s ICP reactor makes it ideal for both approaches.

BRAD EATON is global product manager of Applied’s Etch and Cleans Business Group.




Kedar Sapre: Our solution includes SA and PE CVD processes that are ideal for TSV dielectric liner applications. SACVD processes are highly conformal while PECVD processes are capable of deposit-ing films at very low temperatures. Conformality is critical for the subsequent titanium barrier and copper seed step coverage. SACVD processes use O3/TEOS chemistry at high pressure in a non-plasma environment which is beneficial for TSV trench profiles where a uni-form oxide film is desired along the sidewall. These processes have demonstrated 70-80% conformality in high aspect ratio TSVs. While plasma-based processes are ideal for via-last integration schemes where thermal budget considerations may be critical, current SACVD ther-mal oxides can be deposited at temperatures as low as 400°C with good breakdown voltage and leakage current properties. Both the SACVD and PECVD processes in conjunction with the Producer high-productivity platform, enable a low-cost-of-ownership solution for our customers. The Producer platform also supports up to three types of twin chambers for optimal f lexibility. So, in addition to liners mentioned above, low temperature (<200°C) oxide and nitride films can be deposited, thereby supporting the complete TSV dielectric film portfolio for via first and via last Integration schemes.

Nitin Khurana: There are multiple approaches for barrier and seed deposition with PVD technology being pursued for both the via-first and via-last technology schemes. We are leveraging our extensive wafer fab experience with both ionized and non-ionized sources to provide solutions for TSV. We also have extensive experience with tantalum- and titanium-based barriers. Using titanium, cost can be significantly reduced. We also have unique pre-clean capability that allows us to remove oxides and nitrides from the base of the via with very low defect

density and high mean time between cleans. Our systems also have very high uptime compared to the competition, who have minimal 300mm expertise.

Balaji Chandrasekaran: For CMP, the key challenge lies in develop-ing cost effective solutions without compromising wafer topography performance. For both oxide and copper CMP processes, we are devel-oping solutions that offer high productivity, low cost of consumables, and good dishing performance.

How will Applied’s tools differ from what’s out there now? Brad Eaton: The equipment companies that served niche markets, such as MEMS and similar processes, saw TSV as an obvious adjacent

market for them. Combined, they have several hundred chambers in the installed base and they already have experience doing this, but they lack the credibility for having a reli-able tool for a front-end wafer fab. To my knowledge, none of these companies have systems at 300mm wafer fabs.

Nitin Khurana: Yes, one of the key questions that comes up whenever you talk to customers is how reliable is your product? How many wafers have you broken? At Applied, we talk about wafers broken per mil-lion processed through our tools. Millions of wafers are processed through our tools on a weekly basis all over the world and you can count the number of broken wafers,

if any, on one hand. But for many of

NITIN KHURANA director of technology in the packaging and productiv-ity unit of the Silicon Systems Group.

KEDAR SAPRE (left) is product marketing engineer in Applied’s Gapfill division.BALAJI CHANDRASEKARAN (right) is a global product manager in Applied’s CMP division.



the other companies that are trying to penetrate this market maybe with a tool here or a tool there (at <20k wspm capacity), a similar number of wafers are broken each month on each tool.

Sherry Xia: For oxide CMP, our Reflexion LK tools feature three platens that allow platen balancing for higher throughputs. Process control technology offers look-ahead endpointing capability and higher removal rates. Alternative oxide CMP processes that use slurries with higher removal rates can also be developed.

For metal CMP, the three-platen architecture is more beneficial for thick copper film removal. We have developed new consumables that enable much higher copper removal rates to better handle thick copper film than traditional BEOL applications. Real-time-process-control technol-

ogy is also available and it provides good within-wafer profile control in real time to get uniform removal and overall good dishing performance. Other advanced process control technologies like FullVision are available if required for superior wafer-to-wafer performance.

TSV wafers are often supported on substrates. What challenges does that introduce? Sesh Ramaswami: Temperature control, electrostatic chucking, chemical compatibility and mechanical handling are the key factors that need to be fully characterized prior to TSV reaching high volume. We are working closely with the other equipment suppliers and customers to ensure success across the TSV value chain.

Nitin Khurana: For almost all of our products, handling these substrates is not an issue, both in terms of thickness and diameter. Results of testing show no impact to either handling or to processes. The process valida-tion still needs to take place at a detailed level in the months ahead, but at least on the wafer handling level it’s relatively easy.

Brad Eaton: These materials aren’t dramatically different from what we usually handle; they are similar to common materials that we handle in our chambers. Of course, as we work with customers, we will character-ize the processes on their unique substrates and to their requirements.

Sherry Xia: The incoming wafers for TSV CMP are usually mounted on wafer carrier systems such as glass substrates. Changes in wafer weight and thickness can pose some challenges for mechanical handling and transfer in the CMP tools through heads load and unload while retaining high throughputs. Wafer sensing mechanisms in the tool may need new setups or new calibrations to handle transparent materials accordingly.

Another challenge would be in the area of chemical compatibility of bonding material to the exposure of slurry, chemistry and other clean-ing chemicals. Shear force and mechanical integrity of the bonding material during CMP will also be an important factor. We may need to do compatibility testing and selection of suitable bonding material by working closely with our customers.

Why are packaging companies interested working with Applied? Sesh Ramaswami: One of the major comments from our existing customers and from packaging companies, is that they are looking at us to bring our 300mm capability into their process f low to reduce product risk. There are suppliers in the 200mm space who supply tools for etch, PVD, etc., but they lack the integration capability, resources and 300mm expertise that is expected in the industry today. We are leveraging our equipment and technical competency in the Maydan Technology Center to solve industry problems. As mentioned earlier, we are also collaborating with other suppliers to qualify unit processes and successful end-to-end process-sequence integration.

Is Applied working with SEMI on a the TSV roadmap? Sesh Ramaswami: We are working with SEMI on the ITRS roadmap for packaging. It’s being revised now, with the next revision at the end of the year. The main clarity we are providing is to segment the market, so that by application and product type, we can develop the right equip-ment and processes and help set the technology roadmap. The increased granularity is vital to improve the understanding of what is involved.

Will Applied support both 200 and 300mm? Sesh Ramaswami: Packaging houses use 200mm in early products and as a learning platform for 300mm scaling. We have a complete line of 200mm tools that these companies are using for TSV, packaging and MEMS applications.

Anything new that requires process integration or new module develop-ment for 300mm applications. For 300mm TSV, most unit processes are currently being defined by our customers. So we are developing unit processes and integration f lows for them, the packaging houses and our customers’ customers. ■

SHERRY XIA is a global product manager in Applied’s CMP division.



■ TSV Etch TechnologyNew Techno logy

Deep Silicon Etch for TSV Increases Performance and Productivity

Through-silicon via (TSV) is an emerging technology used in 3D packaging for integrating stacked ICs. Establishing a vertical electrical interconnect that passes completely through the die, the TSV approach can deliver increased device performance through shorter interconnect lengths and more compact form factors. This article examines the etch technology required for implementing TSV in via-first and via-last integration schemes.

Keywords: Etch, Through-Silicon Via, Deep Reactive Ion Etch

Consumer demand for smaller, lighter electronic devices with higher perfor-mance and more features is putting con-tinuous pressure on chipmakers to increase the functionality of ICs while reducing their cost and size in both footprint and thickness. This requirement has resulted in innovative, cost-effective 3-D packag-ing schemes.

The technology being adopted to form 3-D packages is TSV to link individual chips by employing vertical connections etched through a silicon wafer and f illed with metal to directly attach multiple dies. A basic f low involves the via etched through the silicon using a deep reactive ion etching (DRIE) process. This hole is then typically lined with a dielectric depos-ited by CVD. Then, much as with copper dual damascene processes, a diffusion bar-

rier and copper seed layer is deposited by physical vapor deposition (PVD), and the hole is filled by electroplated copper.

The formation of the metal-f illed holes is only part of the TSV process. The TSVs are opened at the wafer backside by aggressively thinning the silicon wafer to allow dies to be attached and electrically interconnected to a Cu/dielectric landing substrate. Thinning is done by grinding, chemical mechanical planarization (CMP) or by a wet chemical process.

Typically, the wafer is reduced in thick-ness by backgrinding after device fabrica-tion, TSV features need only be etched to the f inal die thickness. Currently, a f inal thickness of 50μm is typical, but this is

expected to be reduced to 30μm in the near future, with a f inal goal of 15μm.[1] DRIE is the preferred technology choice for TSV etch. TSV is implemented at dif-ferent phases of the manufacturing f low. There are two main categories: before front end of line (FEOL) which is the via-f irst scheme and back end of line (BEOL) called the via-last scheme. Since process requirements vary for each approach the TSV etch reactor must be f lexible enough for a range of applications. This study dis-cusses key requirements for TSV etch as well as applications that employ deep sili-con etch outside the regime of TSVs.

Deep silicon etch can be performed today by two signif icantly different modes of operation. In one mode, passivation to

Via-First

Via-Last

TSV etch TSV fill

TSV etchDevicefabrication

Devicefabrication

Grinding Stacking

TSV fill

Figure 1. TSV integration falls into two categories: via-first and via-last.



the sidewalls of the trenches is provided by heavily polymerizing chemistries such as C4F8. For TSV etch applications, an etch reactor can use alternating gases that f irst etch silicon then deposit a protective coating on the newly etched feature. The process is repeated making a series of iso-tropic etch bubbles in the silicon to form through-silicon vias. This technique of using alternating deposition and etch steps for etching is known as the Bosch or time multiplexed gas modulation (TMGM) process.

The second mode is called the “steady state process.” In this mode, etch is dominated by halogen chemistries such as f luorine, bromine or chlorine. Passivation to the trench sidewalls is provided by introduc-tion of oxidizing chemistries such as O2, N2, etc. The majority of deep Si etch processes included in our study were per-formed using etch gases such as SF6, NF3, Cl2, and HBr.

The steady state process is a clear favorite for applications where absolutely no side-wall attack is allowed such as deep trench isolation, RF power devices, opto-MEMS, etc. It is possible that via-first applications may adopt this method at a future date as via CDs continue to shrink. Although the steady state process has excellent sidewall integrity, it lacks the higher etch rates and

higher selectivity seen today with Bosch or derivative processes.

Laser drilling is another approach used for forming TSV features. The disadvantages of laser drilling are large minimum hole size and, because each via must be drilled separately, limited throughput. As TSV CDs continue to shrink, and via count per die continues to increase, laser drill-ing is expected to be supplanted by DRIE technology.

TSV Integration SchemesThe entry point for TSV etch varies for dif-ferent device requirements. Some manu-

facturers will introduce TSV at the FEOL. This via-f irst scheme requires the most changes to interconnect circuit layout, but may ultimately offer the greatest benefits. The simplest way to introduce TSV with minimum circuit layout impact is to intro-duce TSV formation at the BEOL (via-last). These schemes are shown in Figure 1 and explored in more detail below.

Via-First SchemeIn this approach, vias are etched during FEOL processing. The via-f irst approach typically has smaller CDs allowing for higher via density, with a typical via CD in the range of 0.5-5.0μm. Along with the smaller CD, depth is generally shal-lower, on the order of 20-50μm. This approach has advantages in that when vias are formed before the device, only good wafers are used to form the f inal device, minimizing yield impact of TSV forma-tion. This approach is favored where high via density is required such as in logic.

Via-Last SchemeIn the via-last approach, the vias are formed after BEOL or bonding, on a full thick-ness wafer from the front-side or from the backside on a thinned wafer. The biggest difference is the larger features and more complicated f ilm stacks. Via-last will involve etching silicon and oxide stack in one chamber in order to provide the lowest cost. In the case of via-last, the process-ing can be done by the IDM or packaging house. Currently, via-last is in production today for CMOS image sensors.

Experimental WorkApparatusAll experiments were conducted in an inductively-coupled plasma (ICP) etch reactor using the TMGM approach (Figure 2). The source has a dual coil design that enables radial control of plasma den-sity across the wafer by varying the current ratio between the inner and outer coils.[2]

The wafer to be etched sits on a ceramic electrostatic chuck (CESC) that can oper-

Tunable Gas Nozzle- Gas flow rate- Radial flow distribution

Dual Tunable RF Source- Source RF power- Radial Plasma Uniformity

Low Frequency RF Bias- Ion energy

Ceramic ESC- Wafer temp. control- RF bias power

Throttling GateValve- Pressure control

Turbo Pump

Figure 3. Test pattern with four via CD sizes (4μm, 10μm, 25μm, 50μm) with three differ-ent pitches and corresponding trenches.

Figure 2. ICP reactor layout showing adjustable parameters.



ate between 20-60°C with <1°C wafer temperature uniformity. Effective heat transfer between the ESC and the wafer is established by f lowing He into chan-nels between the wafer back side and the ESC surface.

Test MethodThe test wafer used for etch process tests had 4-50μm via features patterned in 2.8μm thickness i-line photoresist (PR). Each CD was laid out with different pitch-es to examine the impact of pitch on etch rate and selectivity. The pattern also con-tained trench lines with the same CDs as above with varying pitch (Figure 3).

Results and Discussion Bias power used in this application is relat ively low when compared to the source power. High PR-Si selectivity, approximately 200:1 was achieved for an i-l ine PR mask (Figure 4). This is almost as high as the 300:1 selectivity achieved using the same process with an oxide hardmask. The high PR-Si selec-tivity offers the opportunity to simplify the integration scheme by eliminating the need for hardmasks.

One percent prof ile non-uniformity was achieved and maintained. The non-uni-formity is calculated using measurements

of the CDs t aken at dif ferent depths for the s ame s i ze vias across multiple point s ac ro s s the wa fer, w ith 3mm edge exclusion.

As seen in Figure 5, for a given pressure and f low of the etch spec ie s , a s source power is increased, higher Si etch rates w e r e a c h i e v e d , c o r r e s p o n d i n g to h igher F r ad i-cal density. Si etch rate and selectivity increase with source power up to about 1,500W. This is a point of inf lexion beyond which any gain in silicon etch rate is achieved at a loss in the resist mask selectivity. This can be adjusted by modulating bias power levels, etch and deposition chemistries. At higher source power levels, for example, lower etch step time can be used because of the suf-f iciently high F dissociation. Reducing the etch time per cycle boosts etch rate because the etch step is now more eff i-cient. An alternative method to boost Si etch rate i s to reduce deposit ion

cycle time, but the reduced deposition can al low the PR mask to be eroded. To counter this, the bias power can be lowered to reduce PR bombardment. The lower bias power does not signif i-cantly affect etch rate because the etch mechanism is predominantly chemical in nature.

Figure 6 shows there is no limit to etch depth in this reactor. Trench depth was increased from 175μm to 520μm using the same process by the addition of time and no signif icant drop in etch rate was observed. Older reactor technologies suffer from an exponential decrease in etch rate over time, leading to erosion of the upper part of the via, manifested as widening or faceting. This reactor can be used to etch completely through the wafer if desired. A similar reactor design is used for high-volume, 750μm deep, through-substrate etching in inkjet printer head manufacturing, a common MEMS application.

Improving Sidewall Roughness and Etch RateIn the TMGM process, with each change from etch step to deposition step, several process parameters change depending on the process under review. Some of the

Figure 4. Cross-sectional view of typical TSV with top CD of 10μm, etched without oxide hardmask. SEM shows post-dielectric deposi-tion with conformal coverage due to smooth sidewall. Trench depth is 100μm. Scallop size averages <25nm with >100:1 PR-Si selectivity.

Source Power (W)

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tch

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Figure 5. Effect of source power on silicon etch rate and resist mask selectivity.



parameters that change are reactor pres-sure, gas f low, gas type and RF power levels for source and bias.

In a traditional TMGM process, any sig-nif icant reduction in sidewall scallop is almost always accompanied by a trade-off such as a reduction in the Si etch rate. By using a new hardware scheme and a new process regime, plasma eff iciency was increased for this TMGM process. In doing so, we achieved a signif icant improvement in the sidewall roughness for a given etch rate. We were able to break this industry-accepted trade-off of etch rate vs. scallops. This hardware is able to reduce sidewall roughness from 280nm to below 80nm without any loss in etch rate, as shown in Figure 7. It is expected that the process improve-ment should be extendable to a sidewall roughness below 50nm without any adverse impact on Si etch rate.

This concept will be most valuable for v ia-f i r st appl icat ions where sidewal l integ r it y i s es sent ia l for subsequent integration steps such as liner and metal deposition.

ConclusionsSome of the basic processes for via-f irst and via-last applications have been dis-cussed. An increase in silicon etch rate was seen with an increase in the source power. This process trend appl ies to both via-f irst and via-last applications. Also, a novel concept was introduced where excellent sidewall roughness can be achieved without any trade-off in sili-con etch rate. ■

References[1] ITRS 2007 Edition Interconnect. Table INTC6,

page 46.

[2] John Holland et al., 48th AVS Symposium, San

Francisco, CA, 2001.

Jon Farr is a senior process engineer responsi-ble for process development in through-silicon via technology and is part of the Etch business unit of Applied Materials. He received his B.S. in physics from Arizona State University.

Khalid Sirajuddin is a key account tech-nologist at Applied, currently focused on TSV process development. He received his B.S. in chemical engineering from the University of Texas at Austin.

Sharma Pamarthy is a senior process manager at Applied and program manager for TSV Etch. He received his masters in chemical engineering from Oklahoma State University and his M.B.A. from Santa Clara University.

Ajay Kumar is general manager of Applied’s Mask Etch and Cleans group. He holds a Ph.D. in applied physics from the Indian Institute of Technology. Article Contact: [email protected]

Total Etch Time (min)

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300

200

100

0

600

30.0 40.0 50.00 10.0 20.0 60.0

275mTorr/2000Ws/300sccmSF6

Si E

tch

Dept

h (µ

m)

Figure 7. (Left) Scalloping from a standard, unoptimized TMGM process; (right) modifica-tions to the process regime achieved significant reduction in scalloping.

Figure 6. Effect of etch time on silicon etch depth.

Authors


■ running headRTP

Virtual Metrology Improves Thermal Uniformity forCritical Anneals

For transistors with gate lengths of 32nm and below, it is important to maximize uniformity in rapid thermal processing (RTP) spike anneals while minimizing variations across the wafer. Established of f-line methods of monitoring process and tool performance are costly and not time-efficient. An advanced analysis package featuring a virtual metrology module analyzes and transforms process data that can be used wafer-to-wafer to improve thermal uniformity. This innovative new method can significantly reduce wafer processing errors, enhance yield, and minimize production cost.

Keywords: RTP, Virtual Metrology, WISR, Metrology, Wafer Uniformity, Advanced Process Control

The control software of modern RTP sys-tems can acquire process data with high resolution and at high data rates. In this article, we explore how this information, in particular wafer rotation angle and wafer rotation speed, can be used to pre-dict on-wafer process results using WISR (wafer interdiction and scrap reduction) advanced analysis.

WISR is an advanced process control plat-form for the collection, storage, visualiza-tion, and analysis of process parameters from production tools. One of the key analysis features of WISR is the ability to create virtual sensors. Virtual sensors are calculated parameters derived from physical sensors that can provide real-time

and statistical representations of process health.

We focus here on the WISR platform’s capability to transform time series cham-ber parameters from the pyrometers and the magnetic levitation controller into thermal wafer images. This information would be available any time during the recipe execution and provide wafer-to-wafer handoff correction. We describe the implementation of WISR analysis and show how temperature maps and han-doff corrections correlate with off-line metrology in RTP critical anneals.

RTP ChallengesThe variability of the thermal properties of wafers during RTP has always challenged the control performance of the system. As gate lengths shrink to 32nm and 22nm, there is an increased need to address smaller scale variability within the wafer. There are several root causes for this variability. The issue of “pattern effect” has been described, where the presence of dopants and thin film layers in the patterned product area of the wafer significantly affects the thermal and optical properties of that wafer.[1] Also, the properties of the bulk of the substrate can introduce variations in photon absorp-tion across the wafer, which contributes to temperature variations.[2] Thus, tempera-ture measurements made while annealing implanted wafers can result in errors that can be incorrectly interpreted as tempera-ture non-uniformity.

As a consequence, a signif icant portion of process work on an RTP tool involves processing expensive, specialized monitor wafers using production recipes to antici-pate the uniformity of product wafers. These monitor wafers are analyzed to measure sheet resistance (Rs) using the 4-point probe method, and f ilm thick-ness using an ellipsometer. By optimiz-ing process parameters, variations on the monitor wafers are minimized, which results in improved uniformity on product wafers. Subsequently, periodic processing of monitor wafers is necessary to ensure product yield.

Although the use of monitor wafers is the establ ished method for checking process health and tool per formance, it is expensive and not time-eff icient. Process tools must wait for metrology results to be verif ied before processing product wafers, which hinders wafer throughput and impacts tool ut i l iza-t ion. Monitor wafers are only ef fec-tive indicators of process health if the frequency of their measurement is suf-f icient ly high. With more aggressive thermal processing requirements, faster and more cost-eff icient approaches are needed to monitor process health, such as faster ramp rates, minimal t ime at peak temperature, and higher demands for uniformity and repeatability.

In other f ields of semiconductor process-ing, particularly in chemical mechanical


■ Improving Thermal Uniformity

planarization (CMP), methods of utiliz-ing relevant process parameters to predict wafer-to-wafer data for use in advanced process control (APC) have been devel-oped and appl ied successfu l ly. New demands in thermal processing and the high cost of monitor wafers give RTP tremendous potential to benefit from this type of information.

The magnet ic lev it at ion cont rol ler (MagLev) on RTP tools is able to pro-vide high resolution (100Hz) data of the wafer rotation angle and rotation speed as a function of time. WISR collects, analyzes, and displays this information. The virtual metrology (VM) module in WISR reads and analyzes the temperature readings and MagLev data to compute contour maps of temperature variation at any point during the recipe and provides a suggested robot handoff correction to improve the ther-mal uniformity of the wafer. By focusing on these critical parameters for 300mm wafers, we were able to generate the wafer-to-wafer data needed for APC.

Experimental SetupThe RTP chamber used consists of three main parts: light source, wafer support mechanism and temperature measurement system. The light source is a tightly-packed honeycomb array of tungsten f ilament lamps with an integrated ref lector for each

lamp. The wafer rests on a susceptor capable of withstanding high temperature. This is mounted to a metal rotor that is magnetical-ly coupled to an external motor for rotation and levitation control. The wafer support design and all materials are chosen carefully to shield the lamp radiation from the wafer backside, where pyrometers measure the wafer temperature. Seven fiber optic probes situated at f ixed radii within the bottom ref lector plate transmit the wafer radiation readings to the pyrometers below.

The rotation speed is controlled very tightly, and the rotational angle is mea-sured with an accuracy of approximately 1°. The high rate of temperature read-

ings from the pyrometer probe allows the transformation of the stream of tempera-ture data to points (x,y) on the wafer to be calculated with high accuracy. Figure 1 shows the temperature data for a typical spike anneal. The inset focuses on the peak temperature and shows the temperature for each probe.

Experimental Results and AnalysisThe primary capability of VM is the ability to produce wafer temperature contour maps for any given time during recipe execution. Using the fast fourier transform (FFT) and filtering algorithms contained within the VM module of WISR, we were able to separate temperature averages from the rotational oscillation.[3] To validate our algorithm, this investigation was limited to spike anneal reci-pes due to their high sensitivity to tempera-ture variation. Among the factors influencing the effectiveness of a spike anneal, the peak temperature is the most important. Therefore, only the contour map corresponding to the peak temperature in VM was compared to off-line metrology.

Figure 2 shows peak temperature contours from an implant wafer derived from two sources. The VM data is shown on the left and off-line Rs measurements from the same wafer are shown on the right. Significant correlation between the two distributions is observed.

Time (s)

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(°C)

1100

1000

900

800

700

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40050 55 60 65 70 75 80 8545

T1T2T3T4T5T6T7Set

Figure 1. RTP spike anneal temperature profile.[4]

dT-17 Peak Fit

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dT-17 Metrology

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dT(°C)

Figure 2. Comparison of spike anneal peak temperature contours from an implant monitor wafer (left) from VM and (right) from off-line Rs measurements demonstrate significant correlation.



During high temperature processing of short duration applications such as spike anneals, wafer centering is crucial to pro-cess performance. In an experiment per-formed in a 300mm RTP chamber, f ive wafers were processed using a spike anneal recipe. The first wafer was processed at the center of the chamber. For the remaining four wafers, the robot parameters were changed to place the wafers signif icantly off-center in four different directions: posi-tive and negative tracking (left and right)

and extension (forward and backward) from chamber center.

The metrology results were compared to the VM contour maps at the peak temperature of the recipe (Figure 3). The temperature distributions on all f ive wafers indicate a strong correlation between VM and off-line metrology.

The results above gave us confidence to per-form further analysis on factors contributing

to wafer uniformity. The contour maps generated by VM when the wafers were intentionally placed off-center have a distinctive thermal signature (Figure 3, left). The region of the wafer edge farthest away from the chamber center was cooler than the rest of the wafer. Similarly, the region of the wafer edge closest to the chamber center was hotter than the rest of the wafer. These results demonstrate that temperature

variation at the edge of the wafer at the peak temperature is directly related to the place-ment of the wafer. This suggests that VM temperature measurements can be used to provide wafer-to-wafer handoff correction.

Calculation of the handoff correction is split into three main computational blocks, begin-ning with generating the contour maps. Using the contour map, the location of the center of the wafer is computed based on the tempera-ture variation throughout the wafer. Lastly,

Figure 5. Absolute value of the difference between VM and Optitune tracking coordinate values. The average difference is 0.036mm, including the wafer 9 outlier point.

Ext = +0.2mm

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Figure 3. Comparison of temperature contours showing the effect of offset wafer placement, (left) from VM calculations and (right) from off-line metrology (Optitune).

Figure 4. Tracking values reported by VM and off-line metrology (Optitune).



the difference between the calculated center of the wafer and the center of the susceptor is converted to polar coordinates and used to correct the placement of the next wafer.

The VM-based wafer placement capabil-ity was verified using monitor wafers on a production RTP system. Similar to VM, the Optitune tuning algorithm provides input for handoff corrections by performing a pro-cess-based tuning algorithm on the 121-point metrology data. Monitor wafers were cycled and Rs measurements taken. Sixteen monitor wafers were processed over 32 days in a high-volume production environment.

A comparison of VM and Optitune val-ues for angular placement, referred to as

tracking, is shown in Figure 4. It was observed that the VM data is in good agreement with Optitune tracking with a correlation coefficient of 0.96. Wafer number 9 in this plot is shown to be at least 0.4mm away from the chamber cen-ter in the tracking direc-tion. Virtual metrology detected this gross mis-placement, and the robot was manually adjusted to place subsequent wafers closer to thermal zero,

i.e. centrally placed on the susceptor.

Figure 5 shows the absolute value of the difference between VM and Optitune for the tracking-coordinate. The differences between the reported tracking-correction values of VM and Optitune are minimal with an average difference of 0.036mm including the outlier data-point corresponding to wafer number 9.

Figure 6 shows extension coordinate values for VM and Optitune for the same 16 monitor wafers. While VM data follows the same trend as its metrology counterpart for the exten-sion coordinate, it does not match as well as tracking does. Similarly, the absolute value of the difference between VM and Optitune is

shown in Figure 7. The maximum difference in the extension-coordinate is not as severe as the tracking coordinate, but there is more significant f luctuation in the extension value with an average difference of 0.05mm.

The decoupled analysis of extension and tracking for VM and metrology shows a very strong correlation. In order to further con-firm the accuracy of VM, the radial distance of VM and metrology must be compared. Figure 8 shows the radial distance from the center of the chamber for VM and Optitune. Similar to the results shown for extension and tracking individually, VM data exhibits strong correlation with metrology.

DiscussionPlacement corrections from metrology mea-surements and VM correlate well. However, there are differences that seemingly limit the applicability of VM. It must be noted that in off-line metrology, aerial resolution is on the order of a few square millimeters com-pared to 5-6cm2 for VM. The discrepancy in the measurement scale between these two methods does not automatically discount the accuracy of VM. Off-line metrology takes a coarser measurement: the thermal conduc-tion properties of bulk silicon minimize thermal gradients, making them no more sensitive than VM data for a 300mm wafer.

Also, by measuring temperature directly, VM is less affected by inconsistencies in the

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Figure 8. Radial distance from chamber center for VM and Optitune.

Figure 7. Absolute value of the difference between VM and Optitune for the extension coordinate.


Victor Vitale is a process engineer with

Applied’s Front End Products (FEP) core

engineering unit. He received his B.S. in

electrical engineering from Santa Clara

University.

Wolfgang Aderhold is a senior member

of the technical staff in Applied’s FEP divi-

sion and a process technologist with the

RTP core engineering unit. He received

his Dipl.-Ing. and Dr.-Ing. degree in elec-

trical engineering from the University of

Erlangen-Nuernberg, Germany.

Aaron Hunter leads the core technology

unit of Applied’s RTP division. He received

his B.A. in physics from the University of

California, Santa Cruz.

Natalia Kroupnova is a member of techni-

cal staff with the Special Projects/com-

mon systems software (CSS) division.

She received her M.Sc. from the Moscow

Institute of Energy, Russia and her Ph.D. in

electrical engineering from the University

of Twente, The Netherlands.

Aleksey Yanovich is a member of the tech-

nical staff with Applied’s Special Projects/

CSS division. He is the project manager

and architect of the WISR application.

He received his M.S. in computer science

from the Moscow Engineering Physical

Institute, Russia.

Nir Merry is the managing director of

Applied’s core engineering unit and a mem-

ber of Applied’s engineering governance

board. He earned his B.S and M.S. in mechani-

cal engineering controls and heat transfer

from the University of California, Berkeley.

monitor wafers. Implant variations, espe-cially around the wafer edge, can lead to misinterpretation of placement errors. The relationship between temperature variation at the edge of the wafer and the displaced distance from the chamber enter (placement sensitivity) is process-dependent and inf lu-enced most strongly by peak temperature and ramp rate. The placement sensitivity must be experimentally obtained using a sequence of test wafers in a similar way as that shown in Figure 3.

ConclusionTo support the development and manufactur-ing of transistors with smaller gate lengths, it is important to maximize uniformity in RTP spike anneals while minimizing variations across the wafer. The established methods of monitoring process health and tool perfor-mance are costly and time-consuming. The VM module of the WISR platform presents the opportunity to analyze and transform the high resolution process data into mean-

ingful information that can be used wafer-to-wafer to improve thermal uniformity. Having demonstrated suitable accuracy with metrology readings, VM provides an effec-tive and cost-efficient alternative to using monitor wafers in RTP critical anneals. Virtual metrology can be rapidly imple-mented to increase tool performance. It also enables significant cost savings by providing an alternative to running monitor wafers.

AcknowledgementsThe authors thank Ilias Iliopoulos and Mikhail Kozine for their contributions to this paper.

References[1] Aderhold et al., “Reduction of pattern effects

in RTP Centura system”, 10th IEEE International

Conference on Advanced Thermal Processing

of Semiconductors – RTP 2002, pp. 69-73,

September 2002.

[2] B. Lojek, “Wafer Temperature Non-uniformity

due to Volumetric Absorption of Radiation,”

12th IEEE International Conference on Advanced

Thermal Processing of Semiconductors,

September 28 - 30, 2004.

[3] I. Iliopoulos et al., “Use of Virtual Metrology

and APC for RTP Critical Anneals,” 8th European

Advanced Equipment Control/Advanced Process

Control (AEC/APC) Conference, Dresden, 18 - 20

April 2007.

[4] W. Aderhold et al, “Virtual Metrology in

RTP with WISR,” 15th IEEE International

Conference on Advanced Thermal Processing

of Semiconductors – RTP 2007, pp. 101-104,

October 2007.

© 2008 IEEE. Published with permission from the proceedings of the IEEE/SEMI Advanced Semiconductor Manufacturing Conference.

Authors


Applied Vantage® RadiancePlus® RTP


• Optimized for superior spike anneal uniformity and low-temperature salicide processing

• Virtual metrology module analyzes data to improve thermal uniformity for RTP critical anneals

• Honeycomb lamp head, zoned in situ tuning and patented multi-point temperature sam-pling maximize heating effi-ciency and thermal process uniformity



Aerial Imaging — the Optimal Classifier of Photomask Defect Printability

Mask I nspec t i on

The tight linear correlation between defect signal and CD effect in aerial inspection systems allows for optimized and effective mask inspection for all mask types and technologies. By tuning the detection threshold to avoid false defects, this technique allows a straightforward migration from the 65nm node to the 45nm and 32nm nodes with double patterning.

Keywords: Photomask Inspection, Aerial Imaging, Double Patterning, Double Exposure, CD Variation

Advanced photomasks for low k1 lithog-raphy are prone to defects from various sources such as: contamination, geometry, transmission, phase, etc. There is a com-plex relationship between a defect, the signal from an imag ing detector and the impact of the defect on the wafer. This has important consequences for the per-formance of the detection scheme under conditions where there are a large num-ber of small defects that will not print on the wafer, known as nuisance defects. We studied several imaging schemes numeri-

cally, with respect to their defect detection signal and its relation to the effect on the associated CD. We show that for actinic (i.e. the same wavelength employed by the exposure tool) aerial imaging detec-tion the signal is tightly correlated and l inearly sca led with the induced CD variation regardless of defect source and location. Conversely, the correlation of a non-actinic and/or non-aerial (high-resolution based) detection signal with printing effect is poor. Whereas the linear behavior characterizing aerial imaging is independent of the distribution of defect attributes, the statistics of the non-aerial defect signal are shown to be highly sen-sitive to defect distribution. Such non-aerial detection schemes generally have to compromise detection sensitivity in order to maintain a manageable nuisance false alarm rate. Aerial imaging is therefore the optimal discriminator between printing and non-printing defects.

A serious concern of low k1 lithography is the large typical mask error enhancement factor (MEEF) values.[1, 2] A large MEEF is

an indicator that defects on the mask will behave in complex way s , a nd t h a t sm a l l changes on the mask can

result in significant deviations of the printed pattern from the intended design – devia-tions that are diff icult to predict without complicated analysis. Of the different clas-sification schemes of mask defects, the one most relevant to the successful operation of the lithography process is the assignment of a printability strength to each defect, in order to estimate how a photomask defect impacts the printed pattern on the wafer. The printability metric used in this paper (and common throughout the industry) is CD variation.

Two very different inspection strategies can be employed for mask defect detec-tion: in the first, the maximum number of defects are identified, irrespective of their printability content, and are later classi-fied using a different method. In the sec-ond strategy, the focus of the inquiry is on those defects that eventually lead to print-able errors on the wafer. The first inspec-tion strategy therefore typically employs high resolution optics, not necessarily at the actinic wavelength, and the defects are subsequently classif ied according to their printable impact using optical modeling or aerial automatic defect review (ADR). Conversely, since the second strategy aims at finding precisely those defects that result in printing deviations when exposed under the stepper conditions, it necessarily uses the actinic wavelength, and the same illu-mination and collection optics as employed by the stepper, including aperture shapes

Block Divot Bump

Figure 1. Illustration of the three defect types considered.


and polarization. As the second approach adheres to the expo-sure conditions of the stepper, it is termed “aerial imaging” inspect ion, whi le the f i r st approach is referred to as “high-resolution” inspection.

High-resolution inspection is typically sensitive to smaller defects, which is desirable for the purpose of process con-trol of mask manufacturing. Nevertheless, it unavoidably results in enormous amount of data, most of which are associ-ated with detection events that are essentially nuisance from the print-ability point of view. Thus, determination of defect disposition of high-resolution inspection data is typically a multi-step process, involving modeling and simula-tions, and usually requiring an additional review step using an AIMS tool, and often involving operator intervention as a f inal f ilter.[3] The optical charachteristics of a typical high resolution inspection system are drastically different from the optics used for projecting the mask pattern on the photoresist. Therefore, one does not expect a tight correlation between the signal of a particular defect and its consequences in terms of deviation of the eventual latent image in the photoresist from the intended one. The inverse is true for an aerial imag-ing inspection, because of the matching of the optics of the inspection tool to the exposure conditions of the stepper.

This study describes a series of numerical simulations that demonstrate a linear scal-ing and a tight correlation between aerial CD variation and the aerial imaging defect signal, and the lack of such correlation when defects are inspected by non-aerial, resolution-based techniques. We consid-ered a wide variety of defects on line/space photomasks of various half-pitch nodes, and examined the effect of the distribu-tion of defect attributes (such as size) on the detectability-printability correlation,

and its consequences for the performance of the detection technique in terms of sen-sitivity and immunity to nuisance-related false alarms. We demonstrated the indepen-dence of the performance of aerial imaging detection on the underlying defect distribu-tion. This makes aerial imaging an optimal discriminator between printing and non-printing mask defects, unlike high resolu-tion non-aerial detection. Furthermore, we showed that this property of aerial imaging detection enables simple migration from the 65nm to the 45nm and the 32nm (by means of double patterning) technology nodes by a simple tuning of the detection line, with-out compromising the nuisance-induced false alarm rate.

CD Variation and Defect SignalModern photomasks, equipped with features smaller than the exposure wavelength, pres-ent a formidable modeling challenge. Many of the approximations that are well-ground-ed for larger feature sizes cease to be valid in this regime. However, simple mask patterns still allow some analytic insight. We used a scalar toy model of a two-beam image for-mation to show [4] that aerial CD error and the associated aerial defect signal are tightly correlated and linearly related:

Here Sd is the defect signal, i.e. the inten-

sity difference between a pattern with and without a defect; kAI is a linear constant; and dCD = ∆CD/CDnom is the relative CD variation, normalized by the nominal CD. The proportionality factor depends on the derivative of the pattern intensity at the nominal position of the PR wall (xth). We showed that if the defect is small (compared to l /NA), and is located inside a dense pattern or close (compared to l /NA) to a bright/dark transition edge, then the proportionality constant kAI is independent of all defect attributes (size, type, shape, phase and location). If, addi-tionally, the dense mask pattern is charac-terized by a single pitch value, and the resist development intensity threshold is chosen independent of pitch, then one may easily show that the proportionality Sd∝|dCD | is also insensitive to the pattern pitch.[4] This is demonstrated by the numerical results. A corollary of the derivation of the above equation implies that this linear relation is the hallmark of aerial imaging detec-tion alone, and does not characterize non-aerial, high resolution-based detection.[4]

This is the primary result demonstrated numerically in the current paper.

Experiments and AnalysisSix percent MoSi attenuated phase shift masks (APSM) were simulated with 1:1 line/space patterns on 520nm and 360nm full pitches, corresponding to 65nm and

■ Aerial Imaging

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Figure 2. Defect signal vs. CD variation for various defect types (combined) for line/space arrays on APSMs at 65nm, 45nm and 32nm nodes.


45nm half-pitch values on a wafer. Also considered was a 32nm wafer equivalent l ine/space ha l f-pitch image, through double pa t ter n ing ( DP) f rom dua l 65nm masks. These patterns were cho-sen because they offer a technologically relevant, easi ly modeled and analyzed example where aerial imaging employ-ing off-axis dipole il lumination results in nearly 100% contrast. Moreover, such masks of fer the opportunity to model and study the behavior of a wide range of defect types, such as Cr over MoSi, pinholes, pindots, dark and clear exten-sions, and par t ia l ly under- and over-etched bumps and divots (Figure 1). In addition to their relevance to everyday defects encountered on state-of-the-art masks, these defects, and their conse-quences under various optical imaging conf igurations, exhibit a rather rich phe-nomenology, including (e.g., for the latter two defect types) the effect of combined variation of transmission and phase at the defect location. Various defect sizes, as well as defect locations, were simulated.

For the 65nm and 45nm masks (single exposure lithography, 50% printed duty

cycle), the resist development intensity threshold Ith was chosen to maximize the image log-slope (ILS), namely

However, for the 32nm DP lithography masks, we used

to obtain 32nm wafer features from a 65nm mask with 25% printed duty cycle and a negative photoresist.

Three different imaging schemes were studied: aerial imaging, where the masks were illuminated with a dipole illumination at the actinic wavelength (l = 193 nm); high-resolution (collection NA 0.75) at the actinic wavelength; and high-resolution (collection NA 0.85) at a higher wavelength (l = 248 nm). From the resulting simu-lated images we extracted the defect signal (defined as the maximum difference from the image of a defect-free mask) and the CD variation at the position of the defect (with the appropriate resist development intensity threshold).

Simulation ResultsThe fundamental difference between aerial and non-aerial (high resolution) detection is illustrated in Figure 2. In this figure, the defect signals obtained with the three different optical settings we considered were plotted as functions of the aerial CD error associated with the defect, for all defect types combined, on a mask with a particular pitch. We found a tightly correlated linear scaling between the aerial imaging defect signal and CD variation. In contrast, the defect signals of high resolution non-aerial detection were widely scattered and correlated poorly with CD variation.

The simulation results show that the propor-tionality factor of aerial imaging defect signal on CD variation (i.e. the slope ) is essentially independent of defect type, and of all defect attributes (such as size, position, shape, phase and transmittance). Furthermore, the slope depends only on the value of the resist development threshold: defects on single exposure 65nm and 45nm masks exhibit essen-tially the same slope, in agreement with the analysis above. In contrast, the smaller slope of the DE/DP pattern is a direct consequence of the different resist threshold employed for this mask.

DiscussionThe results reported in the previous section bear important practical consequences for defect detection on modern photomasks. A stable lithographic process requires CD variations below some threshold dCDth, typically ~10%. The detection process, on the other hand, being subject to noise of various sources, is limited to signals above some detection threshold, Sth. Given a dis-tribution of defects with associated print-ing impact, the value of minimal detectable defect signal has direct implications for the limitations of CD error detection (Figure 3). The printability and detection thresh-old lines separate the printability/detection plane into four domains. For these values of detection and printability threshold, defects in the top-right sector are defects that must be detected because they induce a CD error above specification, and that can be detected,

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Figure 3. Defect signal vs. CD variation using three detection schemes for all defect types on a 65nm half-pitch mask overlaid with a typical value of printability and detection thresholds. The value of the detectability threshold is set such that all printing defects are detected and all nuisance defects are ignored.


in principle (because they have a signal above the detection threshold). The defects on the top-left domain represent nuisance, as they are detectable but non-printing (namely, have dCD < dCDth). Defects on the bottom-right domain are printing but undetectable with this value of detection threshold; and defects on the bottom-left domain do not print and remain undetected.

If mask defect detection is considered as a “classif ier,” discerning between printing and non-printing defects, then the per-formance of a particular detection scheme can be quantitatively analyzed by com-puting how the different domains of the signal-dCD plane are occupied, given a certain defect distribution, CD error and detection thresholds. For a pair (dCDth, Sth) of printability-detectability thresh-old values, let Rnuis be the “nuisance rate”, which is the rate of false alarms (detectable but non-printing defects), and let Rmiss be the “miss rate”, which is the rate of defects that induce CD variation above spec, but cannot be detected. Simply put:

where P denotes the probability. Fixing the printability threshold at a certain value, one may plot Rnuis and Rmiss as functions of the detection threshold. Clearly, when Sth → 0, we have Rnuis → 1, Rmiss → 0, while in the other extreme, when Sth → ∞, we have Rnuis → 0, Rmiss → 1. A viable detection scheme, however, must avoid these extreme regimes, and should strive to minimize simultaneously both the frac-tion of missed defects and the “false alarm” rate. We consider then these two rates at intermediate values of Sth.

In Figure 4, Rnuis and Rmiss are plotted as functions of the detection threshold for a log-normal size distribution [ log(A/(1000nm)2 ~ N(-3,0.7)] of defects on a 65nm mask. With dCDth f ixed at the 10%

level, the plot shows that in aerial imag-ing detection a correct choice of detection threshold can simultaneously minimize Rnuis and Rmiss to approximately 0. This striking characteristic of aerial imaging detection, which is independent of pitch and defect types, stems directly from the linear scal-ing between CD variation and defect sig-nal, and is a manifestation of the fact that the signal in aerial imaging detection provides the natural scale of defect printability. This is in sharp contrast to high-resolution, non-aerial detection schemes, where one may be forced to sacrif ice detection sensitivity in order to maintain an acceptable nuisance rate.

We conclude this section with examin-ing mask defect detection from another complementar y aspect adopted f rom detection theory – the receiver operation characteristics curve (ROC).[5] A ROC curve is obtained when f ixing the CD variation threshold, and gradually chang-ing the detection threshold. As the detec-tion threshold is changed, the performance of the detection scheme follows a curve in the (Rnuis, Rhit) plane, where Rhit = 1 - Rnuis is the detection rate. This is the ROC curve. Evidently, an optimal classi-

f ier would operate in the regime Rnuis → 0, Rhit → 1 for then it would not have to sacrif ice sensitivity in order to maintain acceptable false alarm rate. In Figure 5 we plot the ROC curves of aerial imaging and high-resolution, non-aerial detection schemes, for 32nm (via DE/DP), and for two log-normal defect area distributions. These plots demonstrate very vividly our assertion that aerial imaging is an optimal classif ier: it is not limited by the underly-ing defect distribution, and is not limited to a certain mask pitch value, provided that the appropriate detection threshold is used. In contrast, non-aerial detection would not, in general, operate near the optimal point, and is highly susceptible to changes of the defect distribution parameters.

ConclusionWe simulated and analyzed a large variety of photomask defects on line-and-space masks of various pitch values. We examined the resulting CD variation and signal defect in an aerial imaging detection scheme, as well as in high-resolution, non-aerial, actinic and non-actinic detection schemes. We showed that for aerial imaging at the actinic wave-length, the defect signal scales linearly, and is tightly correlated with the CD variation

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Figure 4. Nuisance rate (dashed line) and miss rate (solid line) as function of detection threshold. The rates are computed for all defect types combined. The bottom panels give expanded views.


on the target wafer. Remarkably, this qual-ity of aerial imaging detection was shown to be independent of all defect attributes (such as type, size, area, phase, transmit-tance and position), as well as of the under-lying defect distribution. We showed that when the resist development threshold is chosen independent of the pitch value, then the linear relation between aerial imaging defect signal and the associated defect dis-position is also independent of the value of the mask pitch. In contrast, the defect signal in non-aerial detection schemes correlates poorly with CD variation.

The performance of aerial and non-aerial detection schemes was analyzed in terms of nuisance, hit and miss rates. We showed that the linear relation between aerial CD varia-tion and aerial imaging defect signal makes aerial imaging detection the optimal clas-sif ier between printing and non-printing defects. It allows a very high “true” detec-tion rate without being subject to an unac-ceptably high nuisance rate. This hallmark of the aerial imaging concept is insensitive to defect attributes and defect distribution, and may in principle be valid for all pitch values. The migration to advanced technol-ogy nodes is made particularly simple with

aerial imaging inspection tools, requiring simply an adequate tuning of the detection threshold.

Conversely, we showed that non-aerial detection schemes would, in general, have to sacrifice sensitivity in order to maintain an acceptable nuisance rate. Furthermore, their performance in terms of nuisance and miss rates was shown to be extremely sus-ceptible to changes of the underlying defect distribution. Consequently, the performance of a non-aerial detection scheme as a print-ability classifier is necessarily inferior to that of an aerial imaging scheme. ■

References [1] C.A.Mack,“AnalyticApproachtoUnderstanding

theImpactofMaskErrorsonOpticalLithography”,inOpticalMicrolithographyXIII,C.J.Progler(Ed.),Proc.SPIE4000,pp.215-227,2000.

[2]R.Schenckeretal.,“TheMEEFDivergenceforLow-k1Lithography”,inPhotomaskTechnology2007,R.J.Naber&H.Kawahira(Ed),Proc.SPIE6730,67301M,2007.

[3]P.Fiekowsky,“DefiningDefectSpecificationstoOptimizePhotomaskProductionandRequalification”,inPhotomaskTechnology2006,P.M.Martin,R.J.Naber(Ed),Proc.SPIE6349,63493R,2006.

[4]H.J.Baiketal.,“RelationshipBetweenDefectSignalandCDVariationinAerialImagingMaskInspection”,inPhotomaskJapan2008:PhotomaskandNGLMaskTechnologyXV,2008.

[5]T.Fawcett,“AnIntroductiontoROCAnalysis”,PatternRecognitionLetters,27,8,861-874,ROCAnalysisinPatternRecognition,2006.


Applied Aera2™ Mask Inspection

Inspection System Used in Study

• Uses true aerial imaging for inspecting reticle

• Predicts defect printability

• Automatic defect classifica-tion

• Maps CD uniformity concur-rently with inspection

Figure 5. ROC curves of detection statistics for 32nm DE/DP masks, where defect areas are log-normally distributed. (Left) A/(1000nm)2~lognormal(-6,0.5); (right) A/(1000nm)2~lognormal(-3,0.7). The legend specifies the AUC (area under the ROC curve) for the three optical settings considered. The aerial imaging ROC curve is essentially optimal, as is also reflected by the ~1 value of the corresponding AUC. Also the aerial imaging ROC and AUC is practically independent of defect size distribution and of mask pitch, provided the threshold is changed accordingly.

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AI : 0.998HiRes (193) :0.983HiRes (248) :0.975

AI : 1.000HiRes (193) :0.989HiRes (248) :0.936

Amir Sagiv isanR&DphysicistwithApplied'sMaskInspectionDivision.HeholdsaB.Sc.inphysicsandmathfromtheHebrewUniversityinJerusalem,andanM.Sc.andaPh.D.inphys-icsfromtheWeizmannInstituteofScience.

Shmoolik Mangan ismanagerofApplied'sMaskInspectiondivision.HereceivedhisPh.D.attheWeizmannInstituteofScience,andM.Sc.attheTechnionInstituteofTechnology,Israel.

Authors

Republished with permission from Photomask and Next-Generation Lithography Mask Technology XV, Proc. SPIE 7028, 70281E (2008)


■ running head

Gridded Design Rules — 1-D Approach Enables Scaling of CMOS Logic

DFM

One-dimensional (1-D) gridded design rule (GDR) cells have demonstrated a number of advantages over 2-D complex design rule (CDR) cells, including smaller area, better gate CD con-trol, and elimination of hotspots. Because of their regularity, 1-D GDR-style cells are expected to scale to 32nm with single pass exposure using optimized exposure conditions.

Keywords: Gridded Design Rules, SADP, CD Control

The semiconductor industry has benefited from the relatively straightforward lateral and vertical scaling of integrated circuit dimen-sions for the past 50 years. The main chal-lenges of each new technology node have been in the photolithography and device/interconnect processing steps. However, for the randomly-arranged logic circuits used in CMOS system-on-chip (SOC) devices, a paradigm shift in design style is required to permit continued scaling. GDR-LC, which uses a “line” plus “cut” approach is proposed

as a design solution. Combined with a spa-tial frequency multiplying technique such as self-aligned double patterning (SADP) and a sparse pattern exposure approach such as multiple e-beam (MEB), GDR-LC should allow continued scaling to the 16nm logic node and beyond. GDR can also be applied to older logic nodes to reduce die cost.

The continual improvements in photolithog-raphy resolution have enabled the dramatic scaling of IC feature sizes. The k1 factor is used in the Rayleigh equation as:

where CD is the critical dimension or mini-mum feature size, l is the wavelength of light used in the stepper and NA is the numerical aperture of the stepper lens as seen from the wafer.

In spite of improvements in the optical source related to the photon wavelength, and concur-rent improvements in numerical aperture, the

k1 value has been on a downward trend for several technology nodes. With l/NA limited to 143nm, low k1 will continue to be the focus for reducing feature sizes.

If we examine the trend in k1 for logic technol-ogy nodes extending from 180nm to 16nm, wavelengths are 248nm for the KrF excimer laser, 193nm for the ArF excimer laser, 133nm for water-immersion ArF, and 13.5nm for soft x-rays or EUV. NAs range from 0.25 to 1.35 and different combinations of increasing NA, decreasing wavelength, immersion, and double patterning are available. At 22nm, the k1 value is below the theoretical minimum of 0.25, illustrating the requirement for double patterning.

Until the 45nm node, the choice of a cost-effec-tive lithography solution was fairly consistent across the industry. Each node had a higher lithography cost, but the area reduction from scaling also lowered die cost. The decrease in k1 was accommodated by the increased use of resolution enhancement techniques (RETs)

Figure 1a. Two dimensional logic cell layout.

Figure 1c. Another one dimen-sional logic cell layout.

Figure 1b. One dimensional cell layout.

metal-1 level gate level


■ CMOS scaling with GDR

such as attenuated phase shift masks (att-PSM), off-axis illumination, and optical proximity correction (OPC).

At the 45nm node, two approaches are being taken. One, using dry lithography, requires a change in design style to a more 1-D physical layout with straight lines. The other, using immersion lithography, allows a conventional 2-D design style with bends, but with many complex design rules.

Design StylesA partial physical layout of a commonly used logic standard cell, the scan-D f lip-f lop (SDFF), is shown in Figures 1a and 1b. Another functional logic cell is shown in Figure 1c. The solid green polygons are the gate level, and the dashed outline red polygons are the metal-1 level. Figure 1a shows the conventional 2-D layout style, in which lines are drawn with bends and have multiple pitches. Figure 1b shows the Tela Canvas™ 1-D GDR layout style, in which the lines on each level are straight, without bends, and on a f ixed pitch. The orthogonal gate and metal-1 lines define an x-y grid which is propagated through-out a block of logic cells.

The appearance of the layouts in 1b and 1c is virtually the same, even though the logic functions are completely different. This uniformity of layout patterns, inde-pendent of logic function, is a critical fac-

tor in the benefits of the 1-D GDR layout style. Figure 2 shows a portion of a logic block after standard cells have been placed and routed. The uniform vertical gate lines and horizontal metal-1 lines make the overall block extremely regular.

The conventional 2-D design style has been used since the beginnings of logic IC design. For recent technology nodes, the number of design rules per mask layer has doubled from 180nm to 45nm. The percentage of “complex” design rules, i.e. rules with multiple dependencies or restrictions, has increased from ~20% to >60% of the rules during the same period.[1,2,3,4] The additional rules, and the com-plexity of the rules, are directly related to the problem of patterning 2-D shapes with lower and lower k1 lithography.

Because of the lower fidelity of the lithog-raphy process at advanced technology

nodes, attempts have been made to produce design with acceptable yields using design rule check (DRC) tools. Addit ional rules, var iously named rest r icted or rad ica l design ru les (RDRs), have been added to existing rule decks to help designers address the pattern f idelity problem.[5] Additional efforts have been made to systemati-cally create layout patterns, then evalu-ate them in simulation and patterned wafer s to develop rest r ict ions on allowed combinations of shapes, sizes, and spaces.[6]

A change in design style was demonstrated by Intel in its 45nm CMOS process in which dry lithography was used to reduce cost and risk.[7] This resulted in a lower k1 value than if immersion lithography had been selected. To maintain pattern f idel-ity, the design style was 1-D for critical layers like the gate. One benef it of the regular layout style was a 37% reduction in number of logic rules for 45nm com-pared to 65nm. The benef its of regular layout styles have been discussed by other groups as well.[8]

Another feature of the Intel 45nm process was the use of lines and cuts for the gate level. The 1-D features were formed from long lines that were selectively cut using a second photomask – resulting in the f inal gate shapes on a wafer. This approach improves gate CD control and reduces the line-end overlap for contacts and the overhang of transistor channels. The logic and SRAM layouts have unlanded gate contacts, i.e. those where the contact does not completely sit on the active area, fur-ther improving the CD uniformity.

1-D vs. 2-D ComparisonWe compared 1-D GDR layouts to 2-D CDR layouts for several circuit designs at technology nodes f rom 90nm to 45nm. In each case, the 1-D cells were 5-17% smal ler than the conventional 2-D cells for allowed design rules. This is a signif icant area improvement that

Figure 2. Portion of a logic block after place and route showing the regularity of 1-D GDR.

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Figure 3. Gate CD distribution for 1-D and 2-D layout styles under worst-case simulated exposure process.


translates directly into cost and yield improvements.

Improved CD UniformityThe most critical process parameter in a CMOS technology is the gate electrode l i new id th , o f t en c a l led g a t e CD. Historically, through the impact on tran-sistor saturation current, gate CD was controlled to keep product speed distri-butions within a yielding range. More recently, with transistor scaling halted by the atomic limits of the gate dielectric thickness, transistor sub-threshold leakage has become another reason for improving gate CD uniformity.

Gate CD uniformity can be split into three components: wafer-to-wafer, with-in-wafer, and within-die. Wafer-to-wafer uniformity is improved by using advanced process control (APC) in process equip-ment such as that employed by the Applied Centura AdvantEdge Silicon Etch system. This system makes gate CD measurements on each wafer, then trims the resist or advanced patterning f ilm (APF) to center the resist CD on target. Within-wafer and within-die gate CD can be improved by die-to-die exposure compensation and by optimizing the etch reactor conf igura-tion and process conditions. Within-wafer etch CD uniformity and etch microload-ing, which affects within-die uniformity, may be challenging to optimize simul-taneously. By contrast, a regular circuit layout pattern with uniform density such as that produced using the Tela Canvas application is expected to reduce within-wafer non-uniformity by ~50% because it is no longer necessary to optimize for microloading.

The greater impact of 1-D GDR on gate CD uniformity is on the within-die component. Figure 3 shows the gate CD distribution for both 1-D and 2-D logic cells under worst-case simulated exposure conditions. As in real, i.e. non-ideal opti-cal lithography, although the drawn gate length is 50nm, the f inal CDs are shorter.

The 1-D case maintains a tight distribu-tion, whereas the 2-D case has a broad distribution with greater CD loss. Besides being a reliability concern, shorter gate lengths also create higher sub-threshold leakage currents. We measured the 1-D

leakage to be 50% smaller compared to 2-D leakage on a 45nm test device.

Using aerial image simulations, gate CD was compared for six different logic cells and four different layout styles/environ-


M1 layer Contact hole Gate Area Contact hole

How Gridded Design Works

Process engineers have a three dimen-sional view of the chip through cross-section and top-down SEMs. Design engineers only have a top-down view, which they create in a layout editor. The layout is built up with multiple levels, which represent the masking lay-ers to be used in the wafer fab.

A portion of a conventional layout is show in Figure S-1 (left) for a 2-D design style. 2-D in this case refers to shapes on the same level that can be oriented in the x or y direction, or bent to have sections aligned in both x and y. Because of the bends and jogs, complex design rules are needed to communicate processing limitations from the fab to the designers. The additional complexity in the rules has also been described as restricted design rules (RDR).

The figure shows three problem areas in the layout. 1 is a gate line which is isolated and will have a different process window than a gate line surrounded by a more dense array of lines; 2 shows a gate in a dense pattern, but the pitch is different on each side of the line, again

causing a reduced process window; 3 shows a congested region with bent gate shapes that require additional de-sign rules and also reduce the process window.

Figure S-1 (right) shows a similar portion of a layout, but in this case 1-D GDR is used. 1-D refers to shapes on critical levels without bends or jogs. “Gridded” refers to a fixed pitch used for shapes in the x and y directions (not necessarily the same pitch in x and y). With the gate and metal-1 levels on a grid, the contacts be-tween them also fall onto a grid. GDRs become very simple, since there are no 2-D shapes to deal with.

Once a layout is done in the 1-D GDR style, it becomes straightforward to build the line segments by pattern-ing longer lines on grid, then cutting the lines to form the segments using a second photomask. This 1-D GDR-LC approach allows the use of less advanced lithography tools for the lines. The same lithography tools can then be used for the cuts to form the hole patterns for contacts and vias.

Figure S-1. (Left) 2-D complex design rule layout and (right) 1-D gridded design rule layout.


ments. Aerial image simulation follows the same steps as in the physical world: The DRC deck is applied to a circuit design to ensure manufacturability as far as pos-sible. OPC features are then applied and the aerial optical simulation is peformed on the resulting pattern. The f idelity of the resulting aerial image is expressed by the dimensionless coeff icient of variation (CoV), which is given by the ratio of the standard deviation from the mean CD to the mean CD:

Table 1 summarizes the gate CD CoV results for the different layouts. The 2-D columns are for cells with different sur-rounding cel ls. “Self ” means that the surrounding cells have the same layout as the cel l being measured. “Simple”

means that the surrounding cells are less complex and is essential ly the case for which the image would be of the high-est f idelity. By contrast, “complex” is the most diff icult to image, with more complex cells surrounding the cell being measured. The 1-D column has the 6 cells surrounded by the same 1-D cell. For the 2-D cases, almost independent of sur-rounding layout context, the CoV ranged from about 1% to over 15%. For the 1-D case, all cells had a CoV of less than 0.5%. The 1-D GDR cells have a signif icantly better gate CD uniformity than any of the 2-D cells.[9]

The cells evaluated for Table 1 were in relatively small layout blocks, with three rows of cells and three to four columns of cells. In order to pose a more severe test for the 1-D layout, a larger, more repre-

sentative block of cells was constructed and simulated to get aerial image contours. The CoV results for a 270μm wide by 250μm tall block are shown in Figure 4. Each point represents the CoV for a group of cells in that row of the standard cell block. The cell groups and their placement in the block represent all the permutations of a group of ~300 standard cells in a 45nm library. We were unable to determine any systematic special correlation in the data, indicating that the gate CD uniformity is relatively independent of context and in the worst cases still very small compared to 2-D results.

Improved Hotspot PredictionAnother criterion for logic cell quality is the number of hotspots, or regions in the aerial image of the layout that may have narrow linewidths (necking) or smal l inter-l ine spaces (br idging). Hotspot checking tools have become widely used at the 65nm logic node and below in order to improve yield by early identif ication of potential failing sites. Unfortunately, the hotspot checking is normally done on a f inished block or chip, since 2-D layouts are sensitive to the context of surround-ing cells.

The SDFF cell metal-1 layer was evalu-ated with the ASML-Brion simulation tool for hotspots. The results for a 7x10 design space, i.e. all combinations of 7 pitches and 10 end-gaps, are shown in Figure 5. In this plot, the x-axis is the end-gap in the metal-1, while the y-axis is the metal-1 pitch with approximately equal width and space. Several key points are shown in this f igure. First, the 2-D version of the cell, drawn at the design rules and passing the DRC, had several hotspots, indicating that the DRC failed to predict layout f laws that would result in non-functional devices. These would have to be evaluated and potentially cor-rected after place and route, slowing down the design f low. The result of this uncertainty is that more relaxed design rules are often used to attempt to avoid


Table 1. Aerial image simulation of gate CD for various layouts shows consistently low coefficient of variation for 1-D patterns.

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Figure 4. Gate CD uniformity for a logic block generated using aerial image simulation.


manufacturability problems, despite wast-ing 10% or more of the die area.

The second key factor illustrated by Figure 5 is that the 1-D cell layout could be gen-erated for seventy (7x10) points in the design space, and there is a large region in which there are no bridging hotspots. These results show that a 1-D GDR cell can be evaluated over a large region of design space, and smaller rules could be used with better quality results compared to a 2-D cell. Given the uniformity of the GDR layout, the hotspot results are expected to extend across blocks of logic cells, meaning that hotspot checking can take place entirely at the design stage.

The ability to create and analyze design spaces should not be underest imated. The evaluation of such design spaces will allow faster development of design rules and more conf idence that rules selected have a known margin from yield prob-lems. This permits logic cell development to be more like SRAM cell development, which can be carried out concurrently with the process stabilization.

The scalability of 1-D GDR should be clear, given the lithography k1 trend and the uniformity and hotspot results pre-

sented. Optimization of patterning condi-t ions , such a s the use of dipole illumi-nat ion, wi l l a l low single pass pattern-ing to be used for the 32nm node.

T h e 1 - D G D R design style a l lows t he u s e o f l i n e s and cuts to extend beyond single pass op t i c a l l i t hog r a -phy. Log ic node s at 22nm and below wil l use the GDR-LC approach fo r

logic and memories in SOCs. Pitch-halving by LELE (litho-etch-litho-etch) or SADP can form the lines at pitches for 16nm logic.[10] The cut patterns can be done with whatever lithography process is used for the contact and via hole pat-terns. Options include optical lithography with source-mask-optimization (SMO) and direct write e-beam. Because cuts are effectively 2-D structures, multiple e-beam (MEB) tools may be required for contact hole cuts at 22nm, replacing the optical cut mask. At low, 3-6% effective pattern density, an MEB tool is expected to be able to process 30-40 wafers per hour, keeping pace with an immersion lithography scanner.

The GDR-LC approach can be extended into the interconnect layers of an SOC. The design style can be applied to both orthogonal Manhattan layouts and X diagonal layouts.[11]

Conclusion1-D GDR cel l s have been shown to have a number of advantages over 2-D CDR cells, including smaller area, bet-ter gate CD control, and elimination of hotspots. Because of their regular ity, 1-D GDR style cel ls are expected to scale to 32nm with single pass exposure

using optimized exposure conditions. Further scaling to 22nm and below can be achieved by combining GDR-LC with pitch-halving for l ines and MEB for cuts and holes.

AcknowledgmentsThe author wishes to thank the Tela engineering and executive teams, expe-cia l ly Jon Quandt and Daryl Fox for creation of the cell design space and the large block with an exhaustive permuta-tions of cells. The lithography simula-tions by Hua-Yu Liu and Lynn Cai of ASML-Brion were especially helpful for cell evaluations.

References[1] C.Webb,Proc.ofSPIE,Volume6156,2006.

[2] M.Mason,BACUS,2006.

[3] M.Levittetal.,NanochipTechnologyJournal,v4.1,pp12-17,2006.

[4] M.Smaylingetal.,NanochipTechnologyJournal,v4.1,pp18-21,2006.

[5] L.Liebmann,ISPD,2003.

[6] L.Capodieci,EDPS,2006.

[7] C.Webb,Proc.ofSPIEAdvancedLithography,6925-2,2008.

[8] J.Wangetal.,MicrolithographyWorld,2003.

[9] M.Smayling,etal.,Proc.ofSPIEAdvancedLithography,6925-68,2008.

[10]M.Smaylingetal.,Proc.ofSPIEAdvancedLithography,6925-48,2008.

[11] M.Smaylingetal.,Proc.ofSPIEMicrolithography,2004.

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Figure 5. Metal-1 bridging hotspots. The diameter of the data point indicates the number of hotspots detected.


Mike Smayling is a senior vice-presi-

dent at Tela Innovations responsible for

technology development, and integra-

tion. He received a B.S. degree from the

University of Minnesota, and M.S. and

Ph.D. degrees from Rice University, all

inelectricalengineering.

Author



Innovative Endpoint Technology OptimizesCMP Process Control

CMP

At advanced technology nodes, controlling varia-tions in film thickness that result from upstream processes such as film deposition or the CMP process itself is requiring more advanced process control techniques. In situ monitoring is a pow-erful tool to control the final thickness of a pol-ished film. This article explores a new endpoint system that uses optical ref lectance technology to achieve impressive results in dielectric CMP applications.

Keywords: CMP, Endpoint Monitoring, STI, PMD, Process Control

Variation in the CMP process can be the result of polished f ilm properties or the consumables—such as rate drift over pad life, lot-to-lot differences in the polishing slurry, etc. Variation can also be caused by the CMP hardware, such as head-to-head or tool-to-tool differences. Automated process control (APC) systems can make adjustments for these without operator intervention, eliminating the need for manual monitoring of statistical process control charts.

For dielectric CMP processes, two approach-es to process control have been implemented: inline control (feed forward/feed back con-trol) and in situ control (endpoint). For inline control, adjustments to polish time are made between wafers based on measurements made with metrology systems that are integrated into the factory interface (FI) of the polisher. For in situ endpoint, polishing is stopped based on a measurement made with an embedded sensor during the polish cycle.

Several monitoring methods have been devel-oped over the past two decades. Each method measures a material property of the film—optical, electrical, chemical, or mechanical (frictional). For measurement of dielectric films, optical methods are superior because they are fast, non-contact, and are capable of monitoring absolute thickness. Optical methods are not limited to the detection of transitions between films of different mate-rials—which is the case for measurements of friction or chemical properties.

The recently developed FullVision end-point system employs an in situ sensor to measure broad-spectrum optical ref lec-tance. The system has been widely adopted for real-time film thickness monitoring in

high volume production for 300mm CMP processing.

System DescriptionThe FullVision endpoint system uses a xenon f lash lamp light source—an electric glow discharge lamp designed to produce extremely intense, incoherent, full-spec-trum white light for very short durations. The light source and spectrograph are located inside the platen assembly which rotates during polishing. The light emit-ted by the lamp is delivered to the wafer along one leg of a bifurcated f iber optic cable. The light ref lected from the wafer is carried by the second leg of the f iber optic cable to the detector. An optical path between the fiber and wafer is formed by

Figure 1. Stop-in-oxide endpoint performance for CMP of PMD films.

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a specially designed optical head assembly integrated into the polishing pad. A sealed pad window prevents polishing debris, e.g., slurry and polishing by-products, from reaching the optical head assembly.

Signal ProcessingModel-based determination of absolute thickness for each layer of a patterned film stack is possible using measured ref lec-tance spectra when properties of the f ilms stacks are known. However, real-time, in situ CMP measurements are more com-plex for the following reasons:

1) Patterned films have adjacent micro-scopic reg ions composed of d i f-ferent materials. Interpretation of optical measurement of such compli-cated structures would require accurate determination of the position of each measurement—which is impractical for in situ monitoring.

2) The spot size required for optical, in situ interrogation is large relative to the microscopic features. This requires the analysis of signals that contain a mix-ture of information from different film stacks that change from measurement to measurement.

3) The complex calculations required for many measurements per rotation can-not be made in real time due to the high data rate generated by the high platen velocities used for dielectric CMP.

The endpoint system avoids the difficulties of model-based thickness measurements by employing an empirical technique for detecting the target thickness of patterned dielectric f i lms. The technique makes use of a single set-up wafer to generate a library of spectra wherein each spectrum corresponds to a different thickness of a given dielectric f ilm. A target spectrum is selected from the library according to the desired thickness at endpoint. As sub-sequent f ilms are polished, the software makes a mathematical comparison of each measured spectrum to all of the spectra in the library to determine the best match. As polishing continues, endpoint is called

when the measured spectrum matches the target spectrum from the library.

Results with Test WafersStop-in-Oxide Endpoint — PMD CMP The behavior of the endpoint system for stop-in-oxide endpoint is shown in Figure 1. Deliberate process perturbations were intro-duced to simulate real-world variation. The robustness of this endpoint method is clearly demonstrated by the tight post-polish wafer-to-wafer thickness range of 106Å despite the introduction of variation to the incoming thickness and the polishing rate. The end-point system adjusted the polish times over a range of 26s to compensate for the incoming thickness range of 534Å and the variation of polishing rate of 43-66Å/s.

Polishing was performed using an Applied Ref lexion CMP system and diluted high selectivity slurry with an IC1010 pad. Endpoint performance was measured over a 100 wafer run using DRAM test pat-terned films slotted between five dummy wafers. The incoming DRAM film stack was 12,300Å TEOS, 1,500Å silicon nitride, and 110Å pad oxide. Target thickness for TEOS at endpoint was 9,300Å (i.e. 3,000Å nominal removal of TEOS). Perturbation of incoming thickness was introduced prior to the 100 wafer run by touch-polishing (10s to 18s) five of the DRAM wafers to reduce the incom-

ing thickness by 200Å to 500Å compared to the virgin DRAM films. Perturbation of the removal rate over a range of +/-20% of the baseline process was introduced by polish-ing every third DRAM wafer at higher than baseline pressure, and every fourth DRAM wafer at lower than baseline pressure. The baseline process of 3.0psi downforce and plat-en/head velocities of 110/100rpm resulted in a removal rate of 50Å/s compared to 66Å/s for the high pressure process and 43Å/s for the low pressure process.

One set-up wafer was used to create a library of ref lectance spectra and create an endpoint algorithm. A second wafer was polished under active endpoint control to confirm accurate matching of actual post-thickness with end-point target thickness. No further adjustment to the endpoint algorithm was made.

Stop-on-Nitride Endpoint — STI CMP STI processes are typical ly performed in two steps: bulk oxide removal dur-ing which topography is planarized, and active oxide clearing with over-polish to ensure the elimination of oxide residue. Endpoint control for the over-polish step is critical to minimize dishing of trenches and optimize throughput. In the absence of a robust optical technique to detect clear-ing of active-oxide, motor torque endpoint has traditionally been used for the second

■ Optical Reflectance Endpoint

Figure 2. Remaining active oxide thickness as a function of polishing time.

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step. An optical endpoint system offers the advantage over the motor torque signal of determining when active-oxide is cleared on a specific region of the wafer rather than simply determining the average clearing time over the entire wafer.

Optical reflectance endpoint was used to con-trol both steps of an STI polish: stop-in-oxide endpoint was used for bulk oxide polish, and stop-on-nitride endpoint was demonstrated for clearing of active oxide. The bulk oxide polish was performed on the first platen of

polisher using Semi-Sperse® 12 slurry with an IC1010 pad and integrated endpoint win-dow. Stop-in-oxide endpoint was used to stop polishing with 1,600Å active oxide remaining. The residual oxide polish was performed on the second platen of the same polisher using diluted high selectivity slurry with an IC1000 pad and integrated window. Individual wafers were polished in a time series study for 30s, 40s, 60s, and 90s. The endpoint signal was passively collected for each wafer to deter-mine the endpoint signal corresponding to full clearing of oxide-to-nitride.

The results for remaining active oxide thickness as a function of polishing time are shown in Figure 2. Active-oxide thickness was measured using an all-die metrology recipe. The results show that oxide clear-ing occurred between 40s and 60s in the second polish step. The results also show that active oxide was cleared first from the center of the wafer at about 40s, and was cleared last in the annular region located 100-130mm from the center of the wafer.

The results of the analysis of the endpoint data are shown in Figure 3. The plots show the endpoint signal for wafers polished in a time series study. The endpoint signal was collected from the region of the wafer that cleared last (100-130mm from the center of the wafer). The target spectrum was selected from the sig-nal collected well after complete oxide clearing at about 90s. The oxide-to-nitride transition is indicated by a minimum in the trace where the best matching occurs between the col-lected spectra and the target spectrum. The plots indicate that the oxide-to-nitride tran-sition occurred at 54s and 49s for the wafers polished for 60s and 90s, respectively, and that clearing of oxide to nitride did not occur for the wafers polished for shorter times (30s and 40s). This is consistent with the measurements in Figure 2. The endpoint signals show little change after the oxide-to-nitride transition, when over-polishing to clear residual oxide leads to increased dishing in the trenches. This is due to the high selectivity of the slurry and consequent low polish rate of nitride on active sites following oxide clearing.


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Figure 4. Performance of endpoint for 65nm PMD films. Results for thickness at endpoint are shown relative to the target thickness. For each wafer, all measurement points are shown (4mm edge exclusion). Mean thickness for each wafer is indicated by the large circle. Post-thickness range was 88Å calculated for two lots of wafers polished on subsequent days.

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Figure 3. Endpoint signals collected for the second step of an STI CMP process in a time series experiment for a) 30s, b) 40s, c) 60s, and d) 90s. The endpoint signal for clearing of active oxide-to-nitride is indicated by the minimum in the endpoint traces.


Production Wafer ResultsOur endpoint system was evaluated at a pro-duction fab using 65nm and 45nm device wafers. Both PMD and STI wafers were used for the evaluation. For both types of wafers, polishing was performed using Semi-Sperse D112 slurry with an IC1010 pad and integrated window. The within-wafer non-uniformity for post-thickness was optimized using the polishing heads which incorporate multiple independently controlled polishing zones.

Stop-in-Oxide Endpoint — PMD CMP PMD short-loop wafers, i.e. wafers with test structures representative of fully functional wafers, were polished in a single step on one platen. One setup wafer was used to create the library and setup the endpoint algorithm. The remaining wafers were polished under endpoint control. The results for two lots of 65nm PMD films are shown in Figure 4. The wafer-to-wafer range for both lots was 88Å and the average within-wafer range was 201Å (measured to 4mm edge exclusion). Both metrics met the performance specifica-tions. Average endpoint time was 74s for the first lot, and 68s for the second lot, which was polished the next day. The shorter endpoint time for the second lot indicates increased polishing rate for that lot.

Stop-in-Dielectric Endpoint — STI CMP FullVision endpoint was demonstrated for two different STI wafer types: HARP

oxide f ilm on bulk s i l i con ( H A R P/Si) and HDP-CVD oxide f i lm on si l-icon-on-insu lator ( H D P/ S O I ) . I n both cases, stop-in-oxide endpoint was used for the bulk oxide removal step. Different endpoint algorithms were used for the two wafer types. Perturbations to polish rate were introduced by pol-

ishing some wafers at pressures that were ~18% lower than the basel ine recipe. Results for both types of STI wafers are shown in Figure 5. Results for thickness at endpoint are shown relative to the target thickness (post-thickness – target thick-ness). The wafer-to-wafer range was 45Å for remaining oxide for both wafer types under pressure perturbation which met the performance specification. Endpoint time was ~ 83s for HARP/bulk Si f ilms and ~ 38s for HDP/SOI films.

ConclusionOptical ref lectance endpoint technology has been shown to be a robust real-time film thickness monitor and endpoint system suitable for high volume manufacturing. It has been demonstrated for both stop-in-film endpoint and stop-on-film endpoint for oxide, nitride, and dielectric CMP. The system employs multiple wavelength spec-troscopy with patented window-in-pad technology to monitor real-time thickness change across the full wafer. ■

AcknowledgementsThe authors wish to thank Gary Lam, Sean Cui, Nathan Bohannon, Iqbal Ali, Harry Lee and Gregory Menk of Applied Materials for process engineering and software.


Jun Qian is a member of technical staff with the CMP division of Applied Materials. She holds a Ph.D. in electri-cal engineering from the University of Illinois at Urbana-Champaign.

Siva Dhandapani is a member of tech-nical staff with Applied’s CMP division. He received his Ph.D. in mechanical engineer ing f rom the Univers i ty of Michigan, Ann Arbor.

Dominic Benvegnu is a systems engi-neer with Applied’s CMP Division. He received a B.S. in physics from the University of Utah and a Ph.D. in bio-physics from Stanford University.

Jeff David is a systems engineer with Applied’s CMP division. He received a B.S. in electrical engineering and a M.S. in interdisciplinary engineering from Purdue University.


Authors

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Figure 5. Performance of stop-in-oxide endpoint on 45nm STI wafers.

Applied Reflexion® LK CMP


• FullVision endpoint system for real-time process control

• Patented window-in-pad technology with multiple-wavelength spectroscopy supports in situ endpoint for a variety of applications, includ-ing oxide, STI and poly

• Improves measurement accu-racy with 50% higher reliabil-ity for dielectric applications


Novel Approach Extends PVD Ta Barrier Technology to 32nm and Below

PVD

A new PVD tantalum (Ta) barrier process has been developed for 32nm and below copper/ low k dual damascene interconnect structures. The novel process preserves the delicate low k trench integrity, while demonstrating excellent stability, manufacturability, electrical and reli-ability performance.

Keywords: Ta, PVD, Barrier Process

The punch-through process involves the removal of barrier material from the via bottom during the etch/re-sputter step,

intentionally gouging into the underly-ing copper (Cu) line. This process has been widely used in Cu back-end-of-line (BEOL) 65nm production because it produces high per formance devices with superior reliability, [1-5] especially compared to non-punch-through pro-cesses. [6] However, the conventional punch-through process can cause physi-cal damage to porous low k dielectrics, leading to reliability implications such as roughening of the trench bottom in dual damascene structures or microtrenching in the bottom of single trenches.

This article reports on the use of of f-angular Ta neutral f lux during the re-sputter process to improve the selectivity between the via and trench bottom. This protects the trench bottom and via bevel, while stil l al lowing suff icient gouging into the underlying Cu line. In addition, the plasma density and ion energy are adjusted to further optimize selectivity and avoid micro-trenching. The result is a high deposit/etch selectivity PVD pro-cess, validated using TEM and electrical test results. This approach has extended the PVD Ta barrier process to at least the 32nm node.

Experimental WorkThe structures used in this study were etched in a low k dielectric (k≈2.7) f ilm. The structures contained dual dama-scene via chains and single trench lines with an approximate 2:1 aspect ratio. The structures were deposited with a TaN/Ta bi layer init ia l ly, fol lowed by Ar+ sputtering on the bilayer and a f inal barrier layer deposition step. The PVD reactor used was able to achieve high-ionization deposit ion and in situ Ar+

sputtering capability. The step coverage performance was evaluated using TEM cross-section images and reliability was evaluated using electrical test wafers.

Results and DiscussionSelectivity depends on the difference in aspect ratio between trenches and vias.

Target

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Figure 1. Diagram represents the new selective re-sputtering reactor and process. Increasing DC power on the Ta coil generates more off-angular neutral flux.


During the deposition step, source DC power applied to the target and AC bias power applied to the pedestal were opti-mized to maximize the selectivity.

Increasing the DC source power while keeping the AC bias power low increases the non-directional neutral f lux and min-imizes the directionality of the ion f lux at the wafer. This leads to higher bottom coverage in the trenches than in the vias and improves the deposition selectivity. High re-sputter ing selectivity is more diff icult to achieve since Ar+ ions arriv-ing normal to the substrate will affect the bottom of the trenches and vias equally, regardless of aspect ratio. Lower wafer bias power reduces Ar+ ion energy which al lows re-sputtering of the via bottom, but with reduced bevel damage.

Increasing the DC power on the Ta coil attached on the side of the reactor can generate more off-angular neutral f lux, as shown in Figure 1. The off-angular Ta neutral deposition protects the bevel area and enhances trench bottom coverage during the re-sputter etch step. The coil voltage will also increase proportionally, but, according to plasma simulations, this has no deleterious effect on the process (Figure 2). The DC coil power is the key parameter to increase the re-sputtering selectivity.

Dur ing the re-sputter ing process, the DC source power must be opt imized to maintain a stable plasma and to keep the Ta+ ion fraction as low as possible to minimize via bottom deposition. Plasma stability is also assisted by increasing the pressure in the reactor, which raises the plasma density and al lows a lower coil voltage to be used.

We def ine the net deposition rate during the sputtering step as the rate of Ta neutral/ion deposition minus the absolute rate of Ar/Ta ions sputtering away. This is always a minus number. Low Ta+ ion fraction dur-ing sputtering minimizes the net deposition

effect on the via bottom, while high neutral fraction leads to a higher Ta net deposition rate on the trench bottom compared to the

via bottom. Low Ta+ ion fraction also leads to lower line resistance (Figure 3) and good device yield (Figure 4).

■ PVD Barriers for 32nm

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Figure 3. Electrical results for different etch regimes show that low Ta+ ion fraction during the re-sputtering process reduces line resistance.


With higher DC coil power, more off-angular Ta f lux from the coil strikes the wafer, possibly increasing overhang for-mation. Therefore, both target DC power and coil DC power need to be optimized for proper trade-off between overhang and selectivity. Increasing the RF coil power improves the plasma stability and decreases the re-sputter ing energy, as shown in Figure 5. Proper adjustment of the RF coil power and AC bias power can keep the re-sputter/deposition ratio close to 1 (net deposition rate during sputter-ing is close to 0), thereby maximizing the re-sputtering selectivity. Also, increasing Ar f low improves plasma stabil ity and lowers the coil DC voltage, which is ben-ef icial for hardware stability.

In Figure 6, TEM images f rom our study show that the dua l damascene bevel/t rench bot tom is damage-f ree with suff icient Cu gouging depth into the via after re-sputtering. In addition, there is no microtrenching in the single trench bottom and excellent center-to-edge uniformity is achieved, as seen in Figure 7.

This new PVD tanta lum barr ier pro-cess has shown good manufacturability during an extended run (>1,900kWh), achieving good process stability and good defect performance.


Figure 7. TEM cross-section of a trench on low k dielectric showing no micro-trenching damage in the bottom and excellent center-to-edge uniformity.

99.9

99 Low Source DC/High CoilDC power etch

ConventionalEtch

High DC Etch959080705030201052

.5.1

1 50 100 150 200Line Resistance

Perc

ent

160

140

120

100

80

60

401000500 1500 2000 2500 3000

Volta

ge (V

)

9.00

8.50

8.00

7.50

7.00

6.50

6.00

RF Power (W)

Real

Etc

h Ra

te (Å

/s)

Vbias

Real Etch Rate

Figure 4. Electrical results show that low Ta+ ion frac-tion during the re-sputtering process produces good device yield.

Figure 5. RF power vs. wafer bias voltage (proportional to ion energy) and real etch rate.

Figure 6. TEM cross-section of a dual damascene via with low k dielectric showing (left) trench bottom damage using the conventional process, while (right) the new selective etch preserves the trench bottom intact.


ConclusionA new Ta barrier process has been devel-oped to address low k dielectric damage issues in advanced dual damascene inter-connect structures. As well as preserving the delicate low k trench integrity, the process demonstrates excellent electrical and reliability performance. This approach has extended the PVD Ta barrier process to at least the 32nm node. ■

AcknowledgmentsThe authors would like to thank Applied’s Philip Wang for TEM support and Tza-Jing Gung for technical and management support. This work has been supported by Applied’s Maydan Technology Center.

References [1] H.Yangetal.,”OffAngularDeposition

CompensationforPVDSelectiveRe-Sputtering

Process,”MaterialsResearchSociety

ConferenceProceedings,Volume1079E-N03-05,

2008.

[2]K.Inoetal.,“Ionenergy,ionflux,andionspe-

cieseffectsoncrystallographicandelectrical

propertiesofsputter-depositedTathinfilms,”

JournalofVacuumScience&TechnologyA

15(5),2627,1997.

[3]P.Cataniaetal.,“Lowresistivitybody-centered

cubictantalumthinfilmsasdiffusionbarriers

betweencopperandsilicon,”JournalofVacuum

Science&TechnologyA10,3318,1992.

[4]C.-CYangetal.ExtendibilityofPVDBarrier

SeedforBEOLCuMetallization,”Proceedingsof

theIEEEInternationalInterconnectTechnical

Conference,p.135,2005.

[5]D.Edelsteinetal.“AHighperformancelinerfor

Copperdamasceneinterconnects,”Proceedings

InternationalInterconnectTechnical

Conference.p.9,2001.

[6]N.Kumaretal,“ImprovementinParametric

andReliabilityPerformanceof90nmDual-

damasceneInterconnectsUsingAr+Punch-

ThruPVDTa(N)BarrierProcess,”Advanced

MetallizationConf.2004,p.247.


Applied Endura® CuBS PVD


• PVD deposition of Ta(N) barrier and Cu seed

• Ultra-thin and conformal barri-ers enable low line resistance with robust SM/EM performance

• Robust integration with low k dielectrics

• Aktiv Preclean delivers efficient removal of residue and CuO while minimizing ILD k value change

Hsien-Lung Yang is a senior processengineer with Appl ied ’s Cu Barr ier/Seed division, responsible for productdevelopment on the Endura system.He received his M.S. in electrical andcomputer engineer ing f rom Cornel lUniversity.

Fuhong Zhang is a process engineerwith Applied’s Silicon Systems Group,responsible for process developmentand improvement of metal deposition.He received his Ph.D. and M.S. degreesfromPurdueUniversity.

Jennifer Tseng is a program managerw i th App l i ed ’s Maydan Techno logyCenter BEOL integrat ion group. Shereceived hermaster’s degree fromUtahState University and her B.S. degreefromNationalTaiwanUniversity.

John Forster isadistinguishedmemberof technicalstaff in theMetalDepositionProducts (MDP) unit , special iz ing inRF/p l a sma p rocess ing . He ho lds aPh.D. in electr ical engineering fromRensselaerPolytechnicInstitute.

Arv ind Sundarra jan heads PVD Cubarrier seed process development inApplied’s MDP unit. He has a Ph.D. inmaterials science fromMITandaB.Tech.

in metallurgical engineering from IITBombay,India.

Ajay Bhatnagar is a global productmanager w i th App l i ed ’s D i e l ec t r i cGapfill division. He was previously theGPM for the PVD division. He receivedhis M.S. and Ph.D. degrees in materialsscience and engineering from StanfordUniversity.

Niranjan Kumar isaglobalproductmar-ket ing manager with Appl ied ’s MDPunit.He receivedhisB.Tech. inelectricalengineering from IITKanpur, Indiaandacertificatedegree inelectricalengineer-ingfromStanfordUniversity.

Prabu Gopalraja is thegeneralmanagerof theMDPunit atAppliedMaterials.HehasaPh.D.inplasmaphysics.

In Memoriam: The late Kim Nelsonworked as a process engineer with theMDP productivity enhancement teamresponsible for the products on theEndura2 platform. She received herM.S. inmaterials science from StanfordUniversity.

Authors


(Republished from the Proceedings of the Materials Research Society, 2008 Spring Conference, Vol.1079E-N03-05)


Reducing Low kDamagewith CO2 Plasma Etch

Low k

Porous low k dielectrics are subject to degradation during plasma etch and ash processing. We stud-ied the effects of CO2 plasma, as a replacement for O2 plasma, in the etching of porous organo-silicate (OSG) low k dielectrics. We found that the damage induced by CO2 plasma was lower, depending on the plasma density, ion energy and low k film chemistry used.

Keyword s : L ow k D ie l e c t r i c , Po rou s Organosilicate (OSG), CO2 Plasma, Etch.

Beyond the 45nm technology node, porous low k dielectrics with k≈2.3 will be required to reduce the RC delay for Cu interconnects. Porous low k dielec-trics tend to degrade when subjected to plasma processing such as etching and ashing.[1-8] The result of plasma dam-age is the formation of a carbon-depleted surface layer on the sidewall (Figure 1). This increases the dielectric constant and the leakage current, causing signif icant d i f f icu lty for the implementat ion of porous low k dielectrics.

Prev ious stud ies revea l that damage formation in low k dielectrics is a com-plicated phenomenon, involving both physical and chemical effects. Physical bombardment depends on the plasma densit y and energ y whi le chemica l ef fects are a result of reactions of the plasma with the low k constituents.[9] In this study, we investigated the impact

of CO2 plasma on porous organosilicate (OSG) low k dielectr ics as a potential replacement for O2 plasma in the ashing processes.

We f irst studied the damage caused by CO2 plasma compared to O2 plasma. This was fol lowed by a study of the plasma damage mechanism using both capacitively-coupled plasma (RIE) and inductively-coupled plasma (ICP) sourc-es to vary the plasma density and energy. Using a combination of analytical tech-niques, the changes in the material due to plasma damage were quantitatively evaluated. These techniques included spectroscopic ellipsometry (SE), FTIR,

XPS, XPS depth prof i l ing, and C-V measurements. Finally, we explored the possibility of mitigating the CO2 plasma damage in OSG by increasing carbon doping in OSG.

Comparison of CO2 and O2 PlasmasThe OSG can be schematically represent-ed by a network of base siloxane struc-tures that form an aggregate of Si-O-Si bonds incorporated with methyl(-CH3)and H bonds(Figure 2). After plasma treatment, the bonding changes were determined by analyzing XPS and FTIR spectra. For XPS, of particular interest is the C1s peak, which can be separated

Position (nm)

17nm

100 150 200500

Carbon K Copper L2,3Silicon L2,3 Fluorine K

Oxygen KNitrogen K

Figure 1. (Left) TEM-EELS analysis of a metalized porous low k trench structure shows (right) sidewall carbon depletion to 17nm depth along line 1.


into four peaks representing C-H/C-C, C-O-H/C-O-C, C=O, and O-C=O bonds.[10] The intensity changes of these peaks were used to evaluate the chemi-cal changes caused by plasma treatment. With FTIR, di f ferent ia l spectra can reveal changes in the bonding conf igu-ration,[11] and this technique was used to compare the pristine OSG with the OSG after plasma treatment. The FTIR analy-ses for OSG exposed to ICP CO2 and O2

plasmas as a function of treatment time are compared in Figure 3. It is clear that plasma treatment itself causes a decrease in the Si-(CH3)x/Si-O bond ratio together with an increase in the Si-OH/Si-O ratio, indicating methyl depletion and an increase of the silanol bonds. These damages result in moisture uptake and a hydrophilic dielectric surface. Compared to CO2, the damage is clearly more severe for O2 plasma. In addition to the bond-ing changes, shrinkage of the OSG f ilm thickness was observed by ellipsometry suggesting a collapse of the nanopores. Moreover, O2 plasma induced more car-bon depletion (Figure 4, left).

The effect of the plasmas on the dielec-tric constant was investigated. The results obtained after a 40 second plasma treat-ment are summarized in Figure 5 (top). The dielectric constant measured by the CV method showed a value of 3.42 at

1MHz for CO2 plasma as compared to 3.57 for O2 plasma. The polarization compo-nents were extracted from the dielectric response at different frequencies using C-V, SE and FTIR combined with the Kramers-Kronig dispersion relation.[12] The polarization analysis showed that the dielectric loss was caused primarily by a change in the dipolar component while the sum of the electronic and the ionic compo-nents remained unchanged at about 2.10. Quantum chemistry calculations were per-formed for the bonding clusters observed by XPS and FTIR and we found that the dipolar component is primarily due to the moisture uptake.

Test st ructures of 125nm l ine/space formed in k=2.4 OSG were used to com-

pare O2 and CO2-based photoresist strip processes. After etch and resist strip in an Applied Materials Enabler Etch chamber, a capacitively-coupled plasma oxide etch reactor, the structure wafers were metal-ized and measured to extract RC delays. Results showed that the CO2-based strip process gave 17% lower RC delay com-pared to O2 based strip process at the same RF power and pressure. At higher plasma density, CO2 resulted in higher RC delay, which was still lower than that of O2 as shown in (Figure 5, bottom).

These dif ferences might be attr ibuted to a smaller oxygen radical concentra-tion during CO2 plasma treatment. Two possible mechanisms can be proposed. First, the bond energy for C=O bond is 799kJ/mol, considerably higher than 495kJ/mol for O=O bond. So the disso-ciation of CO2 plasma was more difficult than O2 plasma. Second, optical emission spectroscopy (OES) revealed the presence of various radicals and ions in the CO2 plasma, such as CO2

+, CO, CO+, C2, C, O, and O2

+,[13-14] some of which can recombine with oxygen to reduce the oxy-gen radical concentration.

Effect of Plasma ParametersThe effect of plasma parameters was f irst studied with an ICP plasma source as a function of power. The results are plot-

■ Reducing Low k Damage

CH2

CH2

CH3

CH3

CH3

CH3

CH3

CH3

SiSi

SiSi Si

Si

SiSi

SiSi Si

Si

Si

Si

SiSi

Si

Si

H

H

O

OO

O

O

O

OO OOO

O

O

OO

OO O

O O

OO

O O O

O

CH=0

CH=0

OH

OHOH

OHOH

OH

OH

OH

OH

OH

H20

H20

H20

H20

H20

PristineOSG

DamagedOSG

Figure 2. Bonding configuration of OSG.

0.04

0.05

0.03

0.02

0.01

0.00

Plasma Treatment Time (s)

150 200 2500 50 100 300FTIR

Pea

k Ar

ea R

atio

: Si-(

CH3)

x/Si

-O ICP CO2, 300W 5mTorrICP CO2, 150W, 5mTorrICP CO2, 150W, 150mTorr

ICP O2, 150W, 5mTorrRIE CO2, 150W, 5mTorr

0.20

0.25

0.15

0.10

0.05

0.00150 200 2500 50 100 300

Plasma Treatment Time (s)

FTIR

Pea

k Ar

ea R

atio

: -OH

/Si-O

Figure 3. FTIR peak area ratio for (left) Si-CH3/Si-O and (right) –OH/Si-O for OSG treated by plasma.


ted in Figure 3. With increasing source power, the ICP plasma damage became more severe, as indicated by decreasing Si- (CH3)x/Si-O ratio and increasing Si-OH/Si-O. The result can be attrib-uted to an increase in plasma density for bond breaking and sputter desorp-tion of low k constituents in OSG due to an increase in the source power.[15] The high density correlation with f ilm

damage is conf irmed by tests that show a larger Si- (CH3)x/Si-O rat io and a smaller Si-OH/Si-O ratio under condi-tions of lower source power or higher pressure, both of which will reduce plas-ma density.

Film damage tests performed in an RIE plasma show an advantage in damage, relative to the ICP plasma, as evidenced

by a larger Si- (CH3)x/Si-O ratio and a smaller Si-OH/Si-O rat io and less f ilm shrinkage. XPS depth prof iling showed a much higher C/Si rat io for OSG subjec ted to RIE pl a sma t reatment than ICP plasma treat-ment ( F igu re 4, le f t ) . I n add i t ion , t he R I E plasma induced a smaller dielectric constant, 2.72 at 1MHz, a s compared to 3.42 by ICP pla sma (Figure 5, top) . These resu lt s can be at t r ibut-ed to the lower pla sma densit y and h igher ion energy for the RIE plas-ma compared to the ICP plasma. Under physica l bombardment of ions and radicals, the surface layer wa s den s i f ied and the

pore size reduced. This blocked the dif-fusion of oxygen radicals. Under these plasma conditions, the Knudsen diffu-sion dominated the transport of oxygen radical in the OSG low k dielectrics and the Knudsen diffusivity is proportional to the pore size.[7] This ion energy effect was a lso witnessed in the ICP cham-ber. A reduction in f i lm damage was observed when bias power was applied to increase the ion energy.[16-17]

Effect on Low k DielectricsFinal ly, we invest igated the ef fect of plasma damage on low k dielectr ics. The results are summarized in Figure 4 (r ight). For the lower k va lues, the depth of carbon depletion layer induced by CO2 plasma increased. This can be at t r ibuted to the fact that increased porosit y and/or pore s ize i s usua l ly found in dielectrics with lower k values. In contrast, increasing the carbon dop-ing of the k≈2.2 OSG f ilm was found to improve the material resistance to plas-ma damage.[8] This high carbon doping increased the reaction between oxygen radical and carbon species in OSG sur-face, inducing more pore col lapse or more densif ication on the f ilm surface, blocking the oxygen radical diffusion. These resu lt s suggest the interest ing possibi l ity of tuning the carbon con-centration to reduce the plasma damage on low k dielectrics.


Thickness (Å)

0.2

0.4

0.6

08

1.0

1.2

0.0300 400100 200 500 6000XP

S At

omic

Con

cent

ratio

n Ra

tio: C

/Si

ICP CO2RIE CO2ICP O2

0.2

0.4

0.6

08

1.0

1.2

0.04002000 600 800

Thickness (Å)

XPS

Atom

ic C

once

ntra

tion

Ratio

: C/S

i

RIE, CO2, k=2.2, high carbonRIE, CO2, k=2.2, low carbonRIE, CO2, k=2.5

ICP CO2Pristine RIE CO2 ICP O2

0

1

2

3

4

Recipe

Diel

ectr

ic C

onst

ant

DipolarIonicElectronicVacuum

1.61.41.21.00.80.60.40.20.0

B

1.21 1.151

A C

Recipe

RC R

atio

(RIE

CO 2

Ash

)

RIE O2RIE CO2RIE CO2high density

Figure 5. (Top) Dielectric constants and (bottom) normalized RC at 1MHz for OSG treated by O2 and CO2 strip processes.

Figure 4. XPS depth profile for (left) same OSG with different plasma and (right) different OSG treated by same RIE CO2 plasma.


ConclusionIn this study, we investigated the damage formation and its mechanism for CO2 plas-ma and compared it with O2 plasma. The damage induced by CO2 plasma was found to be lower, although this effect is depen-dent on the plasma density and ion energy and low k f ilm chemistry. With increas-ing plasma density, the plasma damage increased as measured by methyl depletion and moisture uptake. Film damage perfor-mance can be improved for an ICP plasma by decreasing the plasma density through lowering source power or increasing pres-sure. Increased ion energy was also shown to improve f ilm damage performance. RIE chambers, which generally operate at lower plasma densities and higher ion energies, show improved film damage per-formance relative to ICP chambers. The advantage of etching and ashing in an RIE chamber has been shown with electrical tests using an Applied Materials Enabler Etch chamber. Low k damage capability through k≈2.2 value films have been dem-onstrated in this chamber. ■

AcknowledgementsThe authors wish to thank G. F. Doyle of Molecular Impr ints in Aust in for the use of the test bench plasma cham-ber. This work was per formed at the Microelectronics Research Center and at the Center for Nano & Molecular Science & Technology (CNM) at UT Austin sup-ported by NSF.

References[1]K.Maexetal.,J.Appl.Phys.,V93,8793-8840,

2003.

[2]J.Sunetal.,Appl.Phys.Lett.,81,1447,2002.

[3]D.Shamiryanetal.,J.Vac.Sci.Technol.B,20(5),1923,2002.

[4]M.A.Worsleyetal.,J.Vac.Sci.Technol.B,23(2),395,2005.

[5]X.Huaetal.,J.Vac.Sci.Technol.B,24,1238,2006.

[6]N.Possemeetal.,J.Vac.Sci.Technol.B,25(6),1928,2007.

[7]M.R.Baklanovetal.,N2.6,2008MRSSpringMeeting,2008.

[8]E.T.Ryanetal.,N2.7,MRSSpringMeeting,2008.

[9]J.Baoetal.,J.Vac.Sci.Technol.B,26(1),2008.

[10]Y.Uchidaet.al,Surf.InterfaceAnal.36,p677-680,2004.

[11]A.Grilletal.,J.Appl.Phys.,94,6697,2003.

[12]H.Shietal.,theAdvancedMetallizationConference2007,VB.3.

[13]P.Yangetal.,AppliedSpectroscopy,Volume44,No.3,531,1990.

[14]P.G.Reyesetal.,Phys.Stat.Sol.(c)5,No.4,907,2008.

[15]R.J.Shuletal.,Solid-stateElectronicsVol.42,No.12,p2269-2276,1998.

[16]E.Kondohetal.,J.Vac.Sci.Technol.B,18(3),1276,2000.

[17]S.Hwangetal.,SurfaceandCoatingsTechnology,174-175,835,2003.


Paul S. Ho isaprofessorofmaterialssci-ence and engineering at the Universityof TexasatAustin. He receivedhisPh.D.in physics from Rensselaer PolytechnicInstitute.

Hualiang Shi is working on his Ph.D.d e g r e e w i t h t h e L a b o ra t o r y f o rInterconnect and Packaging at theUniversityofTexasatAustin.Hisresearchincludes mechanistic study of plasmadamagetoporouslowkdielectrics.

Huai Huang isagraduateresearchassis-tantwith theLaboratory for InterconnectandPackagingat theUniversityof Texasat Austin. He received his B.S. degree inapplied physics from the University ofScienceandTechnologyofChina.

Junjing Bao isanadvisoryengineerwithIBM and is currently involved in 45nmBEOLandairgap integration.He receivedhis Ph.D. degree in physics from theUniversityofTexasatAustin.

Yangming Sun is a research scientist atthe Center forNano&Molecular Science

& Technology (CNM) at University ofTexasatAustin.

Yifeng Zhou isaseniorprocessengineerwith the Etch and Cleans Product divi-sionatAppliedMaterials. YifengholdsaPh.D. in chemical engineering fromTexasA&MUniversity.

Jeremiah T. P. Pender isaseniorprocessmanager with Applied’s Etch and Cleansdivision. He received his B.S. in physicsfrom the University of Virginia, and hisM.S. and Ph.D. in nuclear engineeringfromtheUniversityofMichigan.

Michael D. Armacost is theseniordirec-tor of Applied’s Customer Technologygroup forDielectric Etch.HeholdsaB.A.in chemistry from Western MarylandCollege and aM.S. in chemical engineer-ingfromClarksonUniversity.

Kathryn Keswick isanetchglobalprod-uct manager wi th Appl ied ’s S i l iconSystems Group. She received her B.S. inchemistry from the University of TexasatAustin.

Applied Centura® Enabler® Etch


• Demonstrates no resist poison-ing and minimal low k ashing damage

• High frequency source and decoupled plasma design

• Independent tunability and control parameters for opti-mizing performance across the wafer


Authors

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