Manifestations of faults in single- and double-BJT BiCMOS logic gates

S.M. Menon A.P. Jayasumana Y.K. Malaiya

Indexing terms: Delay faults, Design for testability, VLSI

Abstract: Combining the inherent advantages of bipolar and CMOS, BiCMOS is emerging as a major technology for high-speed, high- performance, digital and mixed-signal applica- tions. Logic behaviour of single- and double-BJT BiCMOS devices under transistor-level shorts and opens is examined. In addition to sequential behaviour, some stuck-open faults exhibit increased delay. While most stuck-on faults can be detected by logic level testing, some of them can only be detected by monitoring the power supply current (IDDQ monitoring). A stuck-open fault in double-BJT BiCMOS device manifesting as enhanced dynamic I,, current is shown. The faulty behaviour of bipolar (TTL) and CMOS logic families is compared with BiCMOS. Test- ability of both single- and double-BJT BiCMOS devices are discussed along with a design for a testability approach for detecting stuck-open faults in S-BJT BiCMOS devices.

1 Introduct ion

BiCMOS technology, which combines the advantages of CMOS and bipolar, is emerging as a major technology for many high performance digital and mixed signal applications. The main advantages of CMOS technology over bipolar are lower power dissipation and higher packing density. Bipolar technology offers better output current drive, switching speed, 1/0 speed and analogue capability. Combining the advantages of bipolar and CMOS, BiCMOS offers the following advantages [ 11 : improved speed over CMOS, lower power dissipation compared to bipolar, flexibility in 1/0 (TTL, ECL, CMOS compatibility), high-performance analogue capa- bility and latchup immunity. Compared with the CMOS counterparts, BiCMOS circuits can be faster by a factor of up to two for the same level of technology. Access times of less than 10 ns have been reported for 0.8 pm BiCMOS ECL input/output 256K and 1 Mbit SRAMs [2]. l00K gate arrays operating at 100 MHz clock rates

0 IEE, 1995 Paper 1644E (E3, EIO), first received 14th January and in revised form 9th August 1994 S.M. Menon is with the Department of Electrical Engineering Color- ado State University, Fort Collins, CO 80523, USA A.P. Jayasumana is with the Department of Electrical & Computer Engineering, South Dakota School of Mines, Rapid City, SD-57701, USA Y.K. Malaiya is with the Department of Computer Science, Colorado State University, Fort Collins, CO 80523, USA

I E E Proc.-Comput. Digit. Tech., Vol. 142, No. 2, March 199s

have also been reported [2]. BiCMOS is even being con- sidered for high-performance microprocessors and dynamic RAMS, and it is felt that it will be one of the main technologies to drive almost all functions in the decade ahead [3].

Most of the defects and failures in present day inte- grated circuits can be abstracted to shorts and opens in the interconnects and degradation of devices [4]. Transistor-level shorts and opens model many of the physical failures and defects in ICs [SI. The major fault models at transistor level are stuck-at faults, and shorts and opens of transistors and interconnects [SI. It has been shown [7-121 that the stuck-at model does not cover many df the manufacturing defects in BiCMOS devices and that most open faults manifest themselves as delay faults. Analysis on the effects of bridging faults in BiCMOS is given in References 8 and 13. Reference 12 presents testability analysis and fault modelling of BiCMOS circuits in which the behaviour of BiCMOS under faults is compared with CMOS. Comparative studies of fault coverage among various BiCMOS logic families, and with CMOS and ECL can be found in Ref- erences 14 and 15. In this paper, we investigate the mani- festations of faults in single BJT (S-BJT) and double BJT (D-BJT) BiCMOS NAND device, and we compare the faulty behaviour of BiCMOS with CMOS and bipolar technologies. Testability aspects of BiCMOS devices are also presented.

2 BiCMOS devices

BiCMOS circuits employ one or two bipolar junction transistors (BJTs) to perform the function of driving output loads and CMOS to perform logic functions. In this Section, the operation of S-BJT and D-BJT NAND devices and its logic levels are presented.

2.1 S-BJT BiCMOS device A single-BJT BiCMOS NAND realisation is shown in Fig. 1. The functioning of the BiCMOS NAND can be explained by first applying logic 0 to one or both of the inputs which would cause at least one P-device to be on and at least one N-device in each serial N-pairs to be off. With the P-devices (P, and/or P2) on, the base of the bipolar NPN transistor would be about 5 V supplying base current and turning on the bipolar transistor (Q,) providing logic 1 at the output. With both the inputs at logic 1, the P-devices (P, and P z ) would be turned off,

This research was supported by a BMDO-funded project monitored by ONR.

135

and the N-devices N,, N,, N , and N , would be turned on causing a conduction path from output node to ground. This will cause the output to be a logic 0. Thus the circuit realises the NAND function. A block diagram of a general S-BJT BiCMOS device is shown in Fig. 2.

+

Fig. 1 S-BJT BiCMOS N A N D gate

p-part

I I

*I

input

I I AVss (grid)

I I CMOS p-and n-parts bipolar and pull-down n-part

Fig. 2 General S-BJT BiCMOS device

t -0

output ( X ) - n - part n-part

An S-BJT BiCMOS gate consists of CMOS p- and n-parts to perform logic function, and a BJT and a pull- down n-part for driving the output node.

S-BJT BiCMOS devices do not have the full VDD-to- ground logic swing of CMOS devices. The output-high voltage (V,,,) is limited to VDD - V B E ( Q 1 ) . However, output-low voltage (VoL) is E O V. qtmX and qHmin were determined to be 1.5 and 1.9V, respectively [ll]. The logic levels for S-BJT BiCMOS are 0 to 1.5 V for logic level 0 and 1.9 to 4.4 V for logic level 1 [ll]. Any voltage between 1.5 and 1.9 V is considered indeterminate. The device characteristics given for Fujitsu BiCMOS gate array devices [16] are VIHmin = 2 V, VoHmin = 2.4 V, V,,,, = 0.8 V and VOLMx = 0.5 V. CMOS devices exhibit rail-to-rail logic swing resulting in V,,,, of ~5 V and V,Lmin of -0 v. 2.2 D-BJT BiCMOS device A double-BJT BiCMOS NAND realisation is shown in Fig. 3. The logical operation of this gate is similar to S-BJT BiCMOS gate, but the transistor Q, provides a higher drive capability for high-to-low transition. During

136

( 1 )

output high-to-low transition, transistor N, turns off as a result of transistors N, and N , discharging Q, base, causing the gate of N, to be low [17], this results in all the current through N , and N , to be provided as base

* ( 2 )

0 A

0 5 a

Fig. 3 D-BJT BiCMOS NAND gate

current to transistor Q2. During output low-to-high tran- sition, transistor N , turns on to discharge the base of Q2 quickly to speed up the transition. The static power con- sumption of the circuit is negligible, neglecting reverse biased leakage currents. A block diagram of a general D-BJT BiCMOS device is shown in Fig. 4. A D-BJT

BiCMOS gate consists of CMOS p- and n-parts to perform logic function, and two output BJTs for driving the output node.

D-BJT BiCMOS devices do not have the full VDD-to- ground logic swing of CMOS devices. The output-high voltage (V,,) is limited to VDD - V',,,,, and output-low voltage (VoL) is limited to Gnd + V,,,,,,. V,,,, and QHmin were determined to be 2.2 and 2.7 V, respectively [ll]. The logic levels for BiCMOS are 0.6 to 2.2 V for logic level 0 and 2.7 to 4.4 V for logic level 1 [ll]. Any voltage between 2.2 and 2.7 V is considered indeter- minate. The device characteristics given for Fujitsu BiCMOS gate array devices [16] are qHmin = 2V, VOHmin = 2.4 V, VILmx = 0.8 V and VoLmx = 0.5 V.

IEE Proc.-Comput. Digit. Tech., Vol. 142, No. 2, March 1995

3

In this Section, the response of the S-BJT BiCMOS NAND is evaluated in the presence of stuck-om, and stuck-opens of transistors. The output of the BiCMOS gate is examined by simulating one failure at a time for all possible stuck-on and stuck-open failures of all the transistors. Stuck-on faults and stuck-open faults were simulated by turning on and turning off the correspond- ing transistors. Open (OP) in bipolar transistor terminals (emitter, base and collector) were simulated by connect- ing a resistance of R > 1 MR in series with the respective node and short (SH) were simulated by connecting a hard short of R < 0.01 C2 between the respective terminals. The BiCMOS gate outputs obtained analytically have been compared with SPICE simulation outputs to ensure cor- rectness.

The fault-free and faulty behaviour (stuck-on and short faults) of BiCMOS NAND are summarised in Table 1 and the faulty behaviour with stuck-open faults are summarised in Table 2. The length and width of PMOS (L,, W,) and nMOS (La, W,) transistors used for BiCMOS devices in this study are (L, = 1.5 pm, W, = 30 pm, L, = 1.5 pm, W, = 26 pm) similar to the values used in Reference 7. Simultaneous current monitoring was performed using SPICE simulation and the observed lDqP values are listed in the Tables along with the output logc levels. In Tables 1 and 2, the subscript represents the transistor number for the BiCMOS circuit shown in Fig. 1 and superscript represents the type of hard failure

Analysis of physical failures in S-BJT B i C M O S devices

under consideration where on indicates stuck-on failure and OP indicates stuck-open failure. For example, NYN indicates transistor N, stuck-on, NY indicates transistor N, stuck-open, QY: indicates transistor Q, collector open and QsZ indicates transistor collector-to-emitter short.

To make the analysis a true representative of circuit conditions, CMOS inverters were used to drive the BiCMOS device and CMOS inverters were used as loads to the BiCMOS device as shown in Fig. 5. The dimen- sions of PMOS and nMOS transistors used as CMOS

BiCMOS NAND CMOS inv

CMOS inv

Fig. 5 S-BJT BiCMOS N A N D with CMOS inuerter load and driver

driver devices in this study are (L, = 5 pm, W, = 60 pm) and (L, = 5 pm, W, = 20 pm), respectively. The sizes for the CMOS load devices used are (L, = 5pm, W, = 40 pm) and (L, = 5 pm, W, = 15 pm). To study the effects of output fan-out on BiCMOS devices, analysis was con- ducted with one CMOS load alone and also with an RC load [7] along with a CMOS load as shown in Fig. 5. R = 100 C2 and C = 1 p F were chosen for this study and

Table 1 : Behaviour of S-BJT BiCMOS NAND for stuck-on o r short faul ts between terminals fo r a t ransistor

Single BJT BiCMOS NAND stuck-on and short results

Input ff PP" P:" NP" N:" N$" N:" PS& P::,, P:Es P:& P::o Pg& N:gS

A B X i X i X i X i X i X i X i X i X i X i X i X i X i X i

0 0 I n I n I n I n I n I n I n l a l a I n l a l a I n I n 0 1 I n I n I n l a I n l a I n I n I n I n Oa Oa I n I n 1 0 I n I n I n I n / *a I n l a Oa Oa I n I n I n I n I n 1 1 On Oa Oa On On On On On / *a l a On l a l a l a

0 0 l a I n I n I n I n I n l a I n I n I n I n I n I n D,.,n 0 1 Oa l a l a l a I n I n l a l a l a l a I n I n I n D,_,n 1 0 I n I n I n / *a Oa I n I n I n I n l a l a I n I n D,_,n 1 1 l a On l a l a On l a l a On l a l a On l a l a On

X = output; i = current drawn by device; 0" = previous state; on = stuck-on; SH =short; (G, S, D =gate, source, drain); ff = fault free, I' = indeterminate (1 52.0 V); e, b, c = eminer, base, collector; n (normal current) = 2 x lo - ' A ; a (abnormal current) > 2 x A; Do-, = low-to-high transition delay; D,-o = high- to-low transition delay

Table 2: Behaviour of S-BJT BiCMOS NAND with stuck-open faul ts fo r a l l transistors

0 0 1 1 1 1 1 1 1 R R Do-, 0 1 1 1 Q" 1 1 1 1 R R Do-1 1 0 1 0" 1 1 1 1 1 R R Do-, 1 1 0 0 0 D... D... S S 0 0 0

~

X = output, Q* = previous state, e, b, c =emitter, base, collector, O f = open, ff = fault tree, Do-, = low-to-high transition delay, D, ., = high-to-low tran- sition delay. R = stuck-at-0 after initialisation, S = stuck-at-1 after initialisation

137 I E E Proc.-Comput. Digit. Tech., Vol. 142, No. 2, March 1995

RC load referred to henceforth in this paper refers to the values given.

would detect this failure mode. Delay fault caused by transistor Qffe can be detected by delay test.

3.1 Stuck-on faults in S-BJT BiCMOS NAND Stuck-on faults in S-BJT BiCMOS NAND generally result in a fault-free logic level, faulty logic level or inde- terminate logic level. However, in all the cases, it results in enhanced Z D o Q . The logic behaviour and the current drawn by an S-BJT NAND for different stuck-on faults and shorts is summarised in Table 1. Based on these results, it can be seen that 1 7 out of 27 faults considered may be detected by logic-level testing. However, all the faults (except one) can be detected by current monitoring, and one fault affects neither the logic level nor IoDQ but the delay.

As an example, consider the S-BJT BiCMOS NAND shown in Fig. 1, for the physical failure PY", the device behaves similar to fault-free gate for all input vectors except for input vector 11. Input vector 11 causes all the N-devices to be on providing a conduction path from V,, to V,, (Gnd), resulting in enhanced IDDQ. The current drawn by the device with this vector for the fault under consideration is -2 mA instead of the normal -0.2 PA. The current testing technique can be employed to detect this fault. SPICE simulation indicates the output voltage level to be -1 .16 V, which is logic 0 level for S-BJT BiCMOS devices indicated as 0 in Table 1.

Transistor NI stuck-on fault results in enhanced IDDQ for input vector 0 1 . SPICE simulation indicates output voltage to be -2.42 V, which is logic 1 level for S-BJT BiCMOS devices. Similarly, enhanced IDDQ is observed for transistor N, stuck-on fault with input vector 10. SPICE simulation indicates the output voltage level to be - 1.7 V, which is an indeterminate (I*) voltage level for BiCMOS devices. At a first glance, one would expect the output voltage level to be the same for NYN and N:". On careful analysis, it can be seen that the channel resistance will be different owing to the nonlinear characteristics of the nMOS transistor for the individual stuck-on failures NYN and N:N, leading to the different output voltage levels.

Stuck-on failures of transistors N, and N, would result in enhanced IDoQ for input vectors 01 and 10, respectively. However, the fault-free and faulty output is logic 1 for input vectors 01, 10 and 11. Since fault-free and faulty logic levels are the same, only current testing can detect their failures. Transistor QfE and QfE shorts also result in enhanced IDDO and cause a faulty output logic level 1 for input vector 11. Transistor Qffe results in delay faults for output low-to-high transitions as the base to emitter junction does not get forward biased and hence the transistor does not get turned on. The low-to- high transition delay observed for transistor Qffe short with RC output load is 2.08 ns compared to the fault-free delay of 0.90 ns.

Current testing can be very effective for testing failures which result in elevated IDDQ from a normal -0.2 pA to be enhanced to =2 mA, an increase by a factor of Y l o 4 . Conventional logic testing cannot be used to detect stuck-on failure N:" as the fault causes an indeterminate output. However, current testing can detect the above stuck-on faults. Since stuck-on failures PY", P:", NYN, N:" and Nf" provide same logic level for faulty as well as fault-free operations, current testing alone can detect the failures. Conventional logic testing can detect the fail- ures Q f E and QfE as the logic output is different for fault-free and faulty operations, however, current testing

3.2 Stuck-open faults in S-EJT BiCMOS NAND Stuck-open faults in S-BJT BiCMOS NAND result in either sequential behaviour or delay faults. The logic behaviour of S-BJT BiCMOS NAND with stuck-open faults for all transistors is given in Table 2. Based on these results, it can be seen that 1 8 out of 27 faults exhibit sequential behaviour and nine faults exhibit delay in the output response. Two faults (PI and P , stuck-open) in the S-BJT BiCMOS NAND exhibit sequential behaviour (QJ, similar to the behaviour seen in CMOS circuits.

Stuck-open failures of transistors N, and N, cause unique delay faults. A first glance would lead one to expect that with input vectors 11, the output parasitic capacitance would be discharged by turning on of tran- sistors N, and N,. However, due to the open fault of transistor N, or N, under consideration, the vectors 00, 0 1 or 1 0 would charge up the parasitic capacitors at the base as well as the emitter nodes of the bipolar tran- sistors. With the application of input vector 11, the series path of N, and N4 will be turned on but the series path of N, and N, will not be turned on due to the fault. This will cause transistor Q , to remain on for sometime because of the charge stored at the base of the bipolar transistor. Transistor Q , would be discharged slowly through the on resistance of N, and N4 alone causing delay in the output response. The slow to fall delay fault is shown in Fig. 6a and b. This type of fault has also been observed in Reference 7 for a different implementation of a BiCMOS NAND.

-5 o 10-9 o 5 0 10-9 1 o 10-8 15 io-* 2010-8 t ime. s

(I

- 2 5 10-9 o 2 5 10-9 50 10-9 7 5 10-9 1 o 10-9 t1me.s

b

Fig. 6 B t m = 10 ns and one CMOS load b I,. = 4 ns and RC load

BiCMOS response to NYpEN

138 IEE Proc.-Comput. Digit. Tech., Vol. I42, No. 2, March 1995

RC load referred to henceforth in this paper refers to the values given.

would detect this failure mode. Delay fault caused by transistor Qffe can be detected by delay test.

3.1 Stuck-on faults in S-BJT BiCMOS NAND Stuck-on faults in S-BJT BiCMOS NAND generally result in a fault-free logic level, faulty logic level or inde- terminate logic level. However, in all the cases, it results in enhanced Z D o Q . The logic behaviour and the current drawn by an S-BJT NAND for different stuck-on faults and shorts is summarised in Table 1. Based on these results, it can be seen that 1 7 out of 27 faults considered may be detected by logic-level testing. However, all the faults (except one) can be detected by current monitoring, and one fault affects neither the logic level nor IoDQ but the delay.

As an example, consider the S-BJT BiCMOS NAND shown in Fig. 1, for the physical failure PY", the device behaves similar to fault-free gate for all input vectors except for input vector 11. Input vector 11 causes all the N-devices to be on providing a conduction path from V,, to V,, (Gnd), resulting in enhanced IDDQ. The current drawn by the device with this vector for the fault under consideration is -2 mA instead of the normal -0.2 PA. The current testing technique can be employed to detect this fault. SPICE simulation indicates the output voltage level to be -1 .16 V, which is logic 0 level for S-BJT BiCMOS devices indicated as 0 in Table 1.

Transistor NI stuck-on fault results in enhanced IDDQ for input vector 0 1 . SPICE simulation indicates output voltage to be -2.42 V, which is logic 1 level for S-BJT BiCMOS devices. Similarly, enhanced IDDQ is observed for transistor N, stuck-on fault with input vector 10. SPICE simulation indicates the output voltage level to be - 1.7 V, which is an indeterminate (I*) voltage level for BiCMOS devices. At a first glance, one would expect the output voltage level to be the same for NYN and N:". On careful analysis, it can be seen that the channel resistance will be different owing to the nonlinear characteristics of the nMOS transistor for the individual stuck-on failures NYN and N:N, leading to the different output voltage levels.

Stuck-on failures of transistors N, and N, would result in enhanced IDoQ for input vectors 01 and 10, respectively. However, the fault-free and faulty output is logic 1 for input vectors 01, 10 and 11. Since fault-free and faulty logic levels are the same, only current testing can detect their failures. Transistor QfE and QfE shorts also result in enhanced IDDO and cause a faulty output logic level 1 for input vector 11. Transistor Qffe results in delay faults for output low-to-high transitions as the base to emitter junction does not get forward biased and hence the transistor does not get turned on. The low-to- high transition delay observed for transistor Qffe short with RC output load is 2.08 ns compared to the fault-free delay of 0.90 ns.

Current testing can be very effective for testing failures which result in elevated IDDQ from a normal -0.2 pA to be enhanced to =2 mA, an increase by a factor of Y l o 4 . Conventional logic testing cannot be used to detect stuck-on failure N:" as the fault causes an indeterminate output. However, current testing can detect the above stuck-on faults. Since stuck-on failures PY", P:", NYN, N:" and Nf" provide same logic level for faulty as well as fault-free operations, current testing alone can detect the failures. Conventional logic testing can detect the fail- ures Q f E and QfE as the logic output is different for fault-free and faulty operations, however, current testing

3.2 Stuck-open faults in S-EJT BiCMOS NAND Stuck-open faults in S-BJT BiCMOS NAND result in either sequential behaviour or delay faults. The logic behaviour of S-BJT BiCMOS NAND with stuck-open faults for all transistors is given in Table 2. Based on these results, it can be seen that 1 8 out of 27 faults exhibit sequential behaviour and nine faults exhibit delay in the output response. Two faults (PI and P , stuck-open) in the S-BJT BiCMOS NAND exhibit sequential behaviour (QJ, similar to the behaviour seen in CMOS circuits.

Stuck-open failures of transistors N, and N, cause unique delay faults. A first glance would lead one to expect that with input vectors 11, the output parasitic capacitance would be discharged by turning on of tran- sistors N, and N,. However, due to the open fault of transistor N, or N, under consideration, the vectors 00, 0 1 or 1 0 would charge up the parasitic capacitors at the base as well as the emitter nodes of the bipolar tran- sistors. With the application of input vector 11, the series path of N, and N4 will be turned on but the series path of N, and N, will not be turned on due to the fault. This will cause transistor Q , to remain on for sometime because of the charge stored at the base of the bipolar transistor. Transistor Q , would be discharged slowly through the on resistance of N, and N4 alone causing delay in the output response. The slow to fall delay fault is shown in Fig. 6a and b. This type of fault has also been observed in Reference 7 for a different implementation of a BiCMOS NAND.

-5 o 10-9 o 5 0 10-9 1 o 10-8 15 io-* 2010-8 t ime. s

(I

- 2 5 10-9 o 2 5 10-9 50 10-9 7 5 10-9 1 o 10-9 t1me.s

b

Fig. 6 B t m = 10 ns and one CMOS load b I,. = 4 ns and RC load

BiCMOS response to NYpEN

138 IEE Proc.-Comput. Digit. Tech., Vol. I42, No. 2, March 1995

Table 3: Behaviour of D-BJT BiCMOS NAND with stuck-on and short between terminals for all transistors

Double-BJT BiCMOS NAND with stuck-on and shon results

Input ff Pp" P,"" NPN N,ON N,ON N,ON NgN Nf& Pf& NfZs N::, N : L NZ&

A B X i X i X i X i X i X i X i X i X i X i X i X i X i X i X i X i X i X i

0 0 I n I n I n I n I n I n I n I n l a l a I n l a l a I n I n l a I n I n 01 I n I n I n Oa I n l a I n I n I n I n I n O a O a I n I n O a Oa l a 1 0 I n I n I n l n O a I n l a I n Oa O a I n I n I n I n I n I n I n I n 1 1 O n O a O a O n O n On On D,-,n On /*a l a On /*a l a l a / * a On l a

Input f f NZE, NZgs NZ& NZgD Nf:, N::, N:& N:;, N::, NE& Of:# Ofre Of:. Os,", Qsf- A B X i X i X i X i X i X i X i X i X i X i X i X i X i X i X i X i X i X i

00 I n I n I n I n l a I n I n I n I n O a Oa I n I n I n D,-,n O a Oa I n 01 I n l a I n I n /*a /*a l a l a I n Oa O a I n I n I n D,-,n O a O a I n 1 0 I n Oa O a I n I n I n I n l a l a O a O a I n I n I n D,.,n Oa Oa I n 1 1 O n /*a O n l a /*a O n l a / * a On O n O n D,.,n l a l a O n On O n D,.o n

X = output; i = current drawn by device; 0" = previous state; ON = stuck-on; SH =short; G, S. D =gate, source, drain; ff = fault free, I' = indeterminate (2.2-2.7 V); e, b, c = emitter, base, collector; n (normal current) = 2 x lO-'A; a (abnormal current) > 2 x lO-'A; Do-, = low-to-high transition delay; D, ~o = high-to-low transition delay

Table 4: Behaviour of D-BJT BiCMOS NAND with stuck-oDen faults for all transistors

Single-BJT BiCMOS NAND results

Input ff P7:GD PflGD NY:GD N:lGD N::Go Nf:GD N;lGD 07: 07: 0:; 0:; 0:: A B X X X X X X X X X X X X X X

Pp' P p NPP N:P N!P NYP NY

0 0 1 1 1 1 1 1 1 Do-, R R Do., 1 1 1 0 1 1 1 0" 1 1 1 1 D,-, R R D,-, 1 1 1

X = output; 0" = previous state; e. b. c =emitter, base, collector, OP = open; ff = fault free, I' = indeterminate (2.2-2.7 V); G, S. D =gate. source, drain, Do-, = low-to-high transition delay; D, .o = high-to-low transition delay; R = stuck-at-0 after initialisation; S = stuck-at-1 after initialisation

Current testing can be very effective for testing failures which result in elevated loDa from a normal -0.2 pA to enhanced -2 mA, an increase by a factor of ir lo4. Since stuck-on failures PyN, P f N , NYN and N:N provide same logic level for faulty as well as fault-free operations, current testing alone can detect the failures. Transistor N, and N , stuck-on as well as Qf:, Qfz, QZE, and failures exhibit dissimilar outputs under faulty and fault- free conditions, conventional logic testing can detect the failure. However, current testing would detect this failure mode. Transistor Q, and Q, base-to-emitter shorts mani- fest as low-to-high and high-to-low transition delays respectively and hence delay test alone would detect the failure modes.

4.2 Stuck-open faults in D-BJT BiCMOS NAND Stuck-open faults in D-BJT BiCMOS NAND result in either sequential behaviour or delay faults. The logic behaviour of D-BJT BiCMOS NAND with stuck-open faults for all transistors is given in Table 4. Based on these results, it can be seen that only 10 out of 34 faults exhibit sequential behaviour and 24 faults exhibit delay in the output response.

Response of stuck-open failure of N , are shown in Fig. 8a and b. For the stuck-open failure of N , shown in Fig. 80, with input vector 11 exhibits a delay thlZ of 1.204 ns and output logic level of 1 V instead of the normal pro- pagation delay of 0.256 ns and logic level of 0.6 V, with one CMOS load and input pulse width t,, of 10 ns. With RC load and input pulse width t,, of 4ns, the output logic level does not fall below the logic threshold as shown in Fig. 8b. Hence, the fault appears as stuck-at-1 for logic testing purposes.

Bipolar transistor Q1 emitter- and base-open faults manifest as stuck-at-0 after initialisation (shown as R in Table 4). With bipolar transistor Q, collector open, the 140

output exhibits low-to-high transition delay (Do - as shown in Fig. 9a and b. Fig. 9a shows the response of BiCMOS NAND to Q, collector open with one CMOS

5 5 ' , I , , ,., I ,

< - - - - - _ _ _ _ _

- 2 5 10-9 o z 5 10-9 5010-9 7 5 10-9 1 o 10-8 time. s

b

BiCMOS response to N F E N Fig. 8 a tpw = 10 ns and one CMOS load b I, = 10 ns and RC load

I E E Proc.-Cornput. Digit . Tech., Vol. 142, No. 2, March 199s

load connected to the BiCMOS output and with input pulse width t,, of 10 ns shows low-to-high transition tlhZ delay of 1.08 ns instead of the normal low-to-high tran- sition t,,, of 0.823 ns. Fig. 9b shows the response of the

5 5 , , 1 , I , ,, ,., , , 4

0.002 I I , , I , 1 ' I " ' _

0 -

..---- I F \ -0.002 I i fault-free . . ...er .. ,/'.\ 'r i

2 - 0 .- 004: i 1, i ', .e'* N5 open V f -0 006- ': "

-0 008- i 1

-0.010- I j I I , , I ' ' 1 ' '

- 0 . 5 F 1 x I 1 I I I I I 3 -5 .0 10-9 o 5.010-9 io 10-8 1.5 10-8 2.0 10-8

t1me.s a

-2 .5 10-9 o 2.5 10-9 5.0 10-9 7.5 10-9 1.0 10-8 time,s

b

Fig. 9 P t p = 10 ns and one CMOS load b t,, = 4 ns and RC load

BiCMOS response to QIZPEN and Q2gLEN

BiCMOS NAND with input t,, = 4 ns and RC load where the faulty output exhibits a larger delay for the low-to-high transition. The faulty low-to-high transition delay is seen to be tlhZ = 2.3 ns instead of the normal low-to-high transition delay oft,,, = 0.91 ns.

Bipolar transistor Q , emitter-, base- and collector- open faults manifest as high-to-low delay faults. Response of D-BJT BiCMOS NAND base and emitter opens are shown in Figs. 9a, b and e. With one CMOS load and input t,, of 10 ns shows a delay (tthl,) of 1.059 ns instead of the normal propagation delay (thIt) of 0.526 ns for Q , base open. However, Q2 emitter exhibits a lower delay compared to Q2 base open. With input t,, of 4 ns and with one CMOS load, the output exhibits a delay t,,, of 1.68 ns instead of the normal propagation delay thll of 0.58 ns. With RC load at the output of the BiCMOS NAND input t,, of 4 ns, the output exhibits a delay t,,, of 3.22 ns instead of the normal propagation delay t,,, of 0.79 ns, for transistor Q , base open. Transistor Q , emitter open with input t,, of 4 ns exhibits stuck-at-1 behaviour since before the input can make a transition to output low, the input undergoes transition to opposite logic level. If the input pulse width t,, is made wider, the output would go to the other side of the logic threshold.

4.2.1 Enhanced dynamic I,, current: A phenomena resulting in enhanced dynamic I,, current observed under transistor N, open in D-BJT BiCMOS devices is mentioned below.

IEE Proc.-Comput. Digit. Tech., Vol. 142, No. 2, March I995

Transistor N, serves the purpose of discharging the base of Q , quickly to speed up the output low-to-high transition [lq. Stuck-open failure of transistor N, can be expected to result in delayed low-to-high transition.

There is an interesting observation during output high-to-low transition. During output high-to-low tran- sition with N, stuck-open, it is observed that the output transition speeds up and causes enhanced dynamic current (I,,) as shown in Fig. 10. This can be explained

open 0.43 ns, resulting in 0.47 ns early transition than that of fault-free. A built-in current sensing scheme using dynamic supply current monitoring for analogue circuits is described in Reference 18.

5 Comparison of l T L , C M O S , B i C M O S

Summary of faulty behaviour of single and double-BJT BiCMOS, CMOS and TTL NAND and NOR devices are given in Tables 5 and 6, respectively. While analysis of single and double BJT BiCMOS NAND devices are presented in Sections 3 and 4, analysis of BiCMOS as well as CMOS and TTL NAND and NOR are given in Reference 11. Response of the respective devices is evalu- ated for hard failures of the components (MOS and bipolar transistors and resistors). AI1 possible failures such as, stuck-on and stuck-open of transistors, opens and shorts between terminals are considered.

From Tables 5 and 6, the conclusions that can be drawn are given below. While faults in TTL devices manifest either as logic testable or indeterminate output, faults in CMOS devices manifest either as logic-testable or current-testable faults. 25% of the faults in CMOS devices manifest as stuck-at and 25% as sequential behaviour. Out of the 50% of the faults in CMOS NAND and NOR which manifest as current-testable faults, 44% in CMOS NAND and 34% in CMOS NOR are logic testable. However, 6 and 16% of the current testable faults in CMOS NAND and NOR devices are not logic testable, which means that only IDDQ testing would detect the faults in a definite way. About 48 and 44% of the faults in single and double BJT NAND as well as NOR devices manifest as current-testable faults, out of which almost 11 to 17% of the faults are not loeic testable and hence,

Y

for these faults, only I D D p monitoring

would ensure detection. For D-BJT BiCMOS devices, transistor N, open fault manifesting as enhanced dynamic I,, current is not included as current testable fault in Tables 5 and 6. However, the enhanced dynamic I,, current can be detected using I , , monitoring tech- niques. 19% of the faults in S-BJT NAND and NOR and 42 and 29% of the faults in D-BJT NAND and NOR are delay fault testable.

From this summary on the behaviour of S-BJT and D-BJT BiCMOS devices vis-a-vis CMOS and TTL devices, it can be seen that a major portion of the faults in S-BJT and D-BJT devices manifest either as current- testable fault or as delay-testable fault. This makes IoDp testing as well as delay testing methodologies important for BiCMOS devices. Current monitoring techniques [20, 21, 81 can be used to detect such faults. A scheme for current monitoring (IDDQ) for BiCMOS devices is pre- sented in Reference 10. In addition to current testable faults, BiCMOS devices exhibit delay-testable faults too. Hence, the strategy for BiCMOS devices are much more complicated than CMOS and TTL devices. Testability and testing issues in BiCMOS are addressed in the fol- lowing Section.

6 Testabil i ty of B i C M O S devices

In S-BJT and D-BJT BiCMOS devices, apart from sequential behaviour, current-testable as well as delay- testable faults are present.

Stuck-on faults in BiCMOS devices result in either the same logic level as fault-free or a different logic level from that of fault-free. In all cases, enhanced ZDDp results due to a direct path from V,, to V,, (Gnd). Hence, current testing (IDDQ monitoring) techniques can be implemented to detect such failures. When the logic level under faulty

Table5: Summary of faulty behaviour in BiCMOS. CMOS and bipolar (TTL) NAND gates

Summary of BiCMOS, CMOS and TTL NAND gates

Type of faulty behaviour BiCMOS BiCMOS CMOS TTL

Fault-free

Indeterminate output -

NAND (S-BJT) NAND (D-BJT) NAND NAND

- - - 12 (30%)

- - 4 (10%)

Logic testable faults 18 (33%) 10 (14%) 16 (50%) 25 (60%) 8 (25%) 25 (60%)

Sequential behaviour 8 (1 5%) 8 (11%) 8 (25%) - Stuck-at-0 or 1 10 (1 8%) 2 (3%)

- Delay testable faults 10 (1 9%) 28 (42%) - 16 (50%) Current testable faults 26 (48%) 30 (44%)

Logic testable 17 (32%) 22 (32%) 14(44%) - Not logic testable 9 (17%) 8 (12%) 2(6%) -

Table 6: Summary of faulty behaviour in BiCMOS, CMOS and bipolar (mL) NOR gates

Summary of BiCMOS. CMOS and TTL NOR gates

Type of faulty behaviour BiCMOS BiCMOS CMOS TTL

Fault-free - - - 14 (27%)

Indeterminate output - - - 7 (13%)

NOR (S-BJT) NOR (D-BJT) NOR NOR

Logic testable faults 18 (33%) 18 (27%) 16 (50%) 31 (60%) Stuck-at-0 or 1 2 (3%) 2 (3%) 8 (25%) 31 (60%) Sequential behaviour 16 (30%) 16 (24%) 8 (25%) -

Delay fault 10 (19%) 20 (29%)

Current testable faults 26 (48%) 30 (44%) 16 (50%) -

Not logic testable 6 (11%) 10 (1 5%) 5(16%) -

- -

Logic testable 20 (37%) 20 (29%) 11 (34%) -

142 I E E Proc.-Comput. Digit. Tech., Vol. 142, No. 2, March 1995

conditions are different from that of fault-free, logic mon- itoring as well as current testing will detect the fault. However, when the logic level under faulty conditions is the same as fault-free, current testing alone can detect the fault.

Stuck-open faults in BiCMOS devices can exhibit sequential behaviour or delay fault [7-101. Detection of such sequential behaviour due to s-open faults in CMOS requires two pattern tests instead of a single pattern [22- 251. The first pattern is applied to initialise the output of the gate and the second pattern to detect the fault. For detection of an s-open fault in the p-part (n-part), the first pattern sets the output to logic zero (logic one). The second pattern then attempts to provide a low-resistance path between the output and the power supply (ground) through the faulty transistor. To avoid invalidation of tests in the presence of timing skews, robust two-pattern tests have been suggested. In such robust sequences, the Hamming distance between the initialisation pattern and the second test pattern is kept at unity [26-281, so as to avoid the possible intermediate state.

Stuck-open failures in n-part (1) in both S-BJT and D-BJT NAND devices manifest as delay faults. Test gen- eration for detection of delay faults are more difficult. One method of detecting faults manifesting as sequential behaviour is by applying two-pattern tests or multi- pattern sequences. A design for testability (DFT) tech- nique [30] has been developed for detection of such faults in S-BJT circuits. The DFT scheme developed uses only two additional transistors and only a single vector instead of the two- or multipattern sequences to detect stuck-open failures in the presence of timing skews/ delays, glitches or charge sharing among internal nodes.

Since the n-parts and the combination of p-part and bipolar are complementary to each other, when a vector turns the n-part on, the combination of p-part and bipolar are turned off and vice-versa. The proposed test- able design uses two DFT transistors, either two PMOS transistors or two nMOS transistors can be used as shown in Fig. l l a and b. One of the transistors is con- nected to the CMOS output of the BiCMOS device (base of bipolar transistor) and the other to the output of the BiCMOS device (emitter of the bipolar transistor). The switching of these pass transistors are controlled by an external signal C, and the value passed is provided exter- nally by the signal C,. Two external control signals (C, and C,) and two p- or n-transistors are used in the pro- posed design as shown in Fig. 1 l a and b.

I I p-part

U Vss(g nd 1 Vss w (gnd) ct Lp

a b

Fig. 11 a PMOS DF? b nMOS DIT

Proposed testable design for testable BiCMOS gate

The extra transistors provide a static load at the output. The dimensions of the extra transistors should be chosen such that the on resistance of the transistors are considerably higher than the on resistances of the p-part

IEE Proc.-Cornput. Digit. Tech., Vol. 142, No. 2, March 1995

as well as the n-parts. With the use of PMOS transistor, for example, when C , = 0, the gate is essentially trans- formed to a pseudo-nMOS gate [19]. Therefore, the stan- dard rules in designing pseudo-nMOS (pseudo-PMOS) type structures can be used to determine the size of the extra transistors. In general, a minimum size transistor, which offers a resistance of about 5-6 times that of the on resistance of the p- or n-parts are sufficient to provide the correct voltage levels. Table 7 summarises the input

Table 7: Summary of input vectors needed under normal and test conditions

Summary

PMOS DFT nMOS DFT Mode

"&' C,C# Normal operation o x Testing n-parts 0 1 1 1 Testino o-Dart 0 0 1 0 _____ ~ ~ _ _ _ _ _ _

vectors needed under normal and test modes with pMOS/nMOS transistors as DFT transistors.

Power dissipation was computed for a BiCMOS NAND device with and without the implementation of the proposed testable design. The power dissipation without the implementation of the proposed testable design was computed to be -1.36 mW. Testable design was implemented for the BiCMOS NAND and power computation was performed under fault-free and all pos- sible single stuck-open failure. The worst-case power dis- sipation in the presence of a fault was computed to be N 8.07 mW.

Hardware overhead of a BiCMOS device with the proposed testable design was estimated using a typical design rule. If the size of an nMOS transistor is In unit. The size of PMOS transistor is normally chosen to be 2 to 2.5 times of nMOS transistor resulting in 2.5n units. The size of BJT implementation is normally 3-4 times that of an nMOS transistor, resulting in a size of 4n units. The hardware overhead is higher when the testable design is implemented for primitive gates such as two- input NAND or NOR gate. The hardware overhead was computed and found to be 14% for a two-input BiCMOS NAND device. The hardware overhead is much less when the testable design is implemented on complex BiCMOS devices as only two extra transistors are needed per gate to implement the testable design irrespective of the function being implemented. A detailed discussion on the testable design developed for detecting stuck-open faults in BiCMOS circuits can be found in References 29 and 30.

With the bipolar transistor collector open, there would still be a conduction path from V,, to the output through the p-part and the base to emitter diode of the bipolar transistor and hence this fault may not be detected. The open faults in additional transistors cannot be tested in this design.

Summarising the results, stuck-at behaviour, sequen- tial behaviour, delay faults as well as faults that can be detected only by monitoring the current are present in BiCMOS devices. Schemes to detect such failure modes were also presented.

7 Conclusions

Physical failures causing transistor stuck-open in single- and double-BJT BiCMOS devices were examined. In addition to sequential behaviour observed in CMOS devices, BiCMOS devices also exhibit delay faults. Some

143

of the stuck-on faults can be detected by observing voltage level, however, power supply current ( IDDp) moni- toring would definitely detect the fault. A stuck-open faults in double-BJT BiCMOS device exhibiting enhanced dynamic I,, current was presented. Faulty behaviour of the three different families, namely, TTL, CMOS and BiCMOS were compared to bring out the testability differences between the three logic families. Since many stuck-open faults manifest as delay faults, this failure needs to be considered as an important cri- teria for testing/test generation of BiCMOS devices. Test- ability of both single and double-BJT BiCMOS devices were discussed. A design-for-testability approach for detecting stuck-open faults in S-BJT BiCMOS devices was discussed.

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