Mani Srivastava UCLA - EE Department [email protected] VLSI Design Methodologies EE116B (Winter 2001): Lecture # 4

Mani SrivastavaUCLA - EE [email protected]

VLSI Design Methodologies

EE116B (Winter 2001): Lecture # 4

Copyright 2001 Mani Srivastava2

Reading for this Lecture

Chapter 11 of Rabaey’s book


Four Phases in Creating a Chip

ThisLecture

Previous Lecture

FutureLecture


The Design Problem

Source: sematech97

A growing gap between design complexity and design productivity[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]


Profound Impact on the way VLSI is Designed

The old way: manual transistor twiddling expert “layout designers” entire chip hand-crafted okay for small chips… but cannot design billion

transistor chips in this fashion The new way: using CAD tools at high level

tools do the grunge work… high levels of abstractions

– synthesis from a description of the behavior libraries of reusable cores, modules, and cells

Chip design increasingly like object-oriented software design![Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]


Designing a VLSI

Economic viability affected by design time Design time affected by the efficiency of

concept requirements architecture logic/memory circuit layout

Continuous trade-off between performance (speed, area, power) size of die (hence cost of die and packaging) time of design (hence cost of engineering & schedule) ease of test generation and testability


VLSI-design Tools & Methodologies

Goal is to reduce complexity, increase productivity, and increase chances of a working chip

Key is the use of Constraints and Abstractions Constraints

– help automate the procedure by simplifying the problem Abstractions

– collapse detail and arrive at a simpler problem to deal with

Different design methodologies different types of constraints and trade-offs choice driven by economics!


Design Domains

Behavioral what a system does

Structural how entities are connected together to perform the

behavior

Physical (geometrical) how to build a structure that has the required

connectivity to implement the prescribed behavior


Levels of Design Abstractions for Each Design Domain

Architectural Algorithmic Module or functional block Logical Switch Circuit Device

etc.


Design Abstraction Levels

n+n+S

GD

+

DEVICE

CIRCUIT

GATE

MODULE

SYSTEM

[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]


Design Methodology

Design process traverses iteratively between behavior, structure, and geometry abstractions

CAD tools providing more and more automation


A More Simplified Flow


Principles of Structured Design Techniques

Hierarchy

Regularity

Modularity

Locality


Hierarchy

Divide and conquer compose system from simpler widgets

Analogy with software break large programs into threads and subroutines

Hierarchy can be there in all domains behavior, structural, physical

The hierarchy in different domains may not correspond

e.g. a structural hierarchy may not map well to physical


Example of Structural Hierarchy


Example of Physical Hierarchy


Example of Structural Hierarchy


Example of Physical Hierarchy


Repartitioning Structural Hierarchy to Fit Physical Hierarchy


Regularity

Hierarchy breaks a system into submodules but this may not solve the complexity problem there may not be any regularity in the subdivision

– we just end up with a large # of different submodules

Regularity as a guide subdivide into a set of similar building blocks

– e.g. RAM composed of identical cells

Regularity means that the hierarchical decomposition of a large system should result in not only simple, but also similar blocks, as much as possible


Regularity (contd.)

Regularity can be at all levels circuit: use identically sized transistors gate: similar gate structures higher level: architectures with identical processors

Regularity helps in many ways correct by construction reuse of design simplify verification of correctness


Circuit-level Regularity Example

A 2-1 Mux D-type edge triggered

flipflop One-bit full add

All designed using inverter and tristate buffer


Modularity

Condition that submodules have “well-defined” functions and interfaces

in addition to regularity and hierarchy ‘Well-formed” modules allow their interaction with others

to be “well-characterized” Depends on the situation

e.g. in s/w a subroutine has a well-defined interface– argument list with typed variables

e.g. in IC a well-defined physical, structural, and behavioral interface

– pin position, layer, size, signal type, electrical characteristics, logic function


Why Modularity?

Allows the design of system to be broken up with confidence that the system will work as specified when the parts are combined

Allows team design by a number of designers Examples:

bad use: use of transmission gates as inputs– internal signals now depend on source impedance

bad use: use dynamic CMOS logic but fail to latch or register the inputs

– timing of each module will have to be checked


Example of Poor Modularity


Locality Modularity provided “well-characterized” interfaces

internals of modules unimportant to exterior interface• internal details remain at the local level

a form of “information hiding”• reduces apparent complexity of the module

Locality ensures that connections are between neighboring modules, avoiding long-distance connections

Example: timing locality so that time critical operations are local• clock generation and distribution network

• entire clock cycle for global signals to traverse chip

• placement so that global wiring is minimized Analogy with software

• global variables are to be avoided


Parallels between H/W & S/W Design

Strong parallels in the way VLSIs are designed and the way complex software is

HDLs used to describe hardware systems in essence merge these two disciplines

software methods used to define hardware Hardware-software Co-design But, can’t ignore hardware aspects entirely

important since a physical chip is the end product


Typi

cal V

LSI D

esig

n Fl

ow


Types of Tools

Analysis and verification

Implementation and synthesis

Testability techniques


Design Analysis and Verification

Accounts for largest fraction of design time More efficient when done at higher levels of

abstraction select of correct analysis level can reduce

verification time by orders of magnitude Two approaches:

simulation: depends on choice of excitation verification: extracts desired results directly from

circuit description[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]


Simulation Approaches

Key distinction is how are data & time represented? Circuit-level simulation (e.g. Spice) Switch-level simulation (e.g. IRSIM)

– transistors as switches with resistance

Gate-level (logic) simulation– now obsolete due to logic synthesis

Functional simulation (e.g. VHDL, Verilog)– primitives of arbitrary complexity

Behavioral simulation (e.g. VHDL)– only mimic I/O functionality– hardware delay loses its meaning


Digital Data as Analog Signals

Vo

ut (

V)

5.0

3.0

1.0

–1.0

t (nsec)

21.510.50

Vin Vout

tpHL

Gn,p

In Out

VDD

Bp

Bn

Dn,p

Sn

Sp

Circuit Simulation

Both Time and Data treated as Analog QuantitiesAlso complicated by presence of non-linear elements

(relaxed in timing simulation). Impractical for large circuits



Representing Data as Discrete Entity

V

t

VM

t1 t2

0 1 0 VD D

Rn

Rp

CL

Discretizing the data usingswitching threshold

{0,1,X} representation of data

The linear switch modelof the inverter



Discretizing Time

Evaluate circuits only at “interesting” times Event-driven simulation

evaluate gates only at a future time of interest– current time + gate delay– for more accuracy

gate delay = function of load still, events can happen at any time

Further simplification: unit-delay model events only at multiples of a unit time

Even further simplification: zero-delay model events at clock a.k.a. clock or cycle based simulation


Circuit vs. Switch Level Simulation

0 5 10 15 20time (nsec)

–1.0

1.0

3.0

5.0

CIN

OUT[3]

OUT[2]

Circ

uit

Sw

itch



Structural Description of Accumulator

entity accumulator isport ( -- definition of input and output terminals

DI: in bit_vector(15 downto 0) -- a vector of 16 bit wideDO: inout bit_vector(15 downto 0);CLK: in bit

);end accumulator;

architecture structure of accumulator iscomponent reg -- definition of register ports

port (DI : in bit_vector(15 downto 0);DO : out bit_vector(15 downto 0);CLK : in bit

);end component;component add -- definition of adder ports

port (IN0 : in bit_vector(15 downto 0);IN1 : in bit_vector(15 downto 0);OUT0 : out bit_vector(15 downto 0)

);end component;

-- definition of accumulator structuresignal X : bit_vector(15 downto 0);begin

add1 : addport map (DI, DO, X); -- defines port connectivity

reg1 : regport map (X, DO, CLK);

end structure;

Design defined as composition ofregister and full-adder cells (“netlist”)

Data represented as {0,1,Z}

Time discretized and progresses withunit steps

Description language: VHDLOther options: schematics, Verilog



Behavioral Description of Accumulator

entity accumulator isport (

DI : in integer;DO : inout integer := 0;CLK : in bit

);end accumulator;

architecture behavior of accumulator isbegin

process(CLK)variable X : integer := 0; -- intermediate variablebegin

if CLK = '1' thenX <= DO + D1;DO <= X;

end if;end process;

end behavior;

Design described as set of input-outputrelations, regardless of chosen implementation

Data described at higher abstractionlevel (“integer”)



Behavioral Simulation of Accumulator

Integer data

Discrete time

(Synopsys Waves display tool)



Timing Verification

(Synopsys-Epic Pathmill)

Critical path

Enumerates and rankorders critical timing paths

No simulation needed!



Issues in Timing Verification

b yp a ss

4-b it a d d e r

MU

X

O u t

In

False Timing Paths



Design Verification

Simulation only tells how circuit reacted to input excitation that was specified

Verification tools analyze design and find problems Example:

electrical verification– transistor sizing for rise/fall time constraints

timing verification– find critical path

functional (formal) verification– compare circuit behavior against designer’s specification– proof that the two are “equivalent”, i.e. proof that the circuit

will work– e.g. prove that two state machines are equivalent


Implementation MethodologiesDigital Circuit Implementation Approaches

Custom Semi-custom

Cell-Based Array-Based

Standard Cells Macro Cells Pre-diffused Pre-wired(FPGA)Compiled Cells (Gate Arrays)



Economics of Implementation

Decision depends on Non-recurring engineering cost

– engineering design cost (personnel, support etc.)– prototype manufacturing cost

Production cost (Recurring cost)– wafer cost, processing cost– die per wafer– die yield per wafer, packaging yield, final test yield

Fixed costs– data sheets, cost of sales

Important to estimate design time and design cost guide to select the design method


Choosing a Design Style

Custom Cell-based Prediffused PrewiredDensity Very High High High Medium-LowPerformance Very High High High Medium-LowFlexibility Very High High Medium LowDesign Time Very long Short Short Very ShortManufacturing Time Medium Medium Short Very ShortCost – low volume Very High High High LowCost – high volume Low Low Low High


Custom Circuit Design

When performance & design density important High cost and long time-to-market

justified only if– high volumes– design will be reused (e.g. library cell)– cost no concern

due to CAD tools, custom design is minimal


Tools for Custom Design

Layout editor (e.g. Virtuoso) Symbolic layout

relative positioning followed by compactor Design rule checking

technology file, hierarchical DRC Circuit extraction

schematic from layout transistors, caps, resistances, inductances

Netlist comparison and netlist isomorphism Back annotation from layout to schematic


Custom Design - Layout Editor

Magic Layout Editor(UC Berkeley)



Symbolic Layout

1

3

In O ut

VDD

GND

Stick diagram of inverter

• Dimensionless layout entities• Only topology is important• Final layout generated by “compaction” program



Cell-based Design Methodology

Why? Shorter design time! but, larger penalty

Array-based design (later) cuts process steps and reduces time even further…

Standard cell library of logic gate (nand, and, or etc.) design as a schematic or netlist of cells from library layout is generated automatically in rows design and composition of library is the main issue

– what fanout to design for?– Alternative versions of cells with different drive


Standard Cell Libraries Typically contain a few hundred cells

inverters, NAND gates, NOR gates, complex AOI, OAI gates, D-latches, and flip-flops

Each gate type can have multiple implementations to provide adequate driving capability for different fanouts

e.g the inverter gate can have standard size transistors, double size transistors, and quadruple size transistors

the chip designer can choose the proper size to achieve high circuit speed and layout density

Cells characterized for various metrics, such as delay time vs. load capacitance Circuit, timing, and fault simulation models cell data for place-and-route mask data

Cells designed such that they can be abutted to form rows


Standard Cell Based Design

FunctionalModule(RAM,multiplier, )

Row

s of

Cel

ls

Logic Cell

RoutingChannel

Feedthrough Cell

Routing channel requirements arereduced by presenceof more interconnectlayers



Standard Cell - Example

[Brodersen92]



Standard Cell - Example

3-input NAND cell(from Mississippi State Library)characterized for fanout of 4 andfor three different technologies



Automatic Cell Generation (Compiled Cells)

Random-logic layoutgenerated by CLEOcell compiler (Digital)



Module Generators

Logic gate okay for random logic But, inefficient for regular structures

e.g. carry chain capacitance in N-bit adder Standard cells do not exploit regularity Structured custom design

macrocell generators, e.g. memories, multipliers– interconnects by abutment in both dimensions

datapath compilers– abutment in one dimension, routing in the other

usually “parameterizable”


Datapath Compilers: Linear Placement

add

er

bu

ffer

reg0

reg1

mu

x

bus0

bus2

bus1

bit-slicerouting area feed-through

Advantages: One-dimensional placement/routing problem



Datapath Layout


Macrocell Design Methodology

Macrocell

Interconnect Bus

Routing Channel

Floorplan:Defines overalltopology of design,relative placement ofmodules, and global routes of busses,supplies, and clocks



Channel Routing


Macrocell-based Design Example

Video-encoder chip[Brodersen92]

SRAM

SRAM

Rou

ting

Cha

nnel

Data paths

Standard cells



Array-based Design

Cuts process steps and reduces time even further…

Several types: Mask programmable arrays

– pre-diffused so that several masks are eliminated– typically, only top metalization needs to be done– standard packages to keep packaging cost low– e.g. gate array, sea of gates

Pre-wired arrays– avoid detailed manufacturing totally– analogy with memory


Processing Steps in Gate Array Implementations


Gate Array - Sea-of-gates

rows of

cells

routing channel

uncommitted

VD D

GND

polysilicon

metal

possiblecontact

In1 In2 In3 In4

Out

UncommitedCell

CommittedCell(4-input NOR)



Sea-of-gate Primitive Cells

NMOS

PMOS

Oxide-isolation

PMOS

NMOS

NMOS

Using oxide-isolation Using gate-isolation



Sea-of-gates

Random Logic

MemorySubsystem

LSI Logic LEA300K(0.6 m CMOS)



Pre-wired Arrays

Categories of pre-wired arrays (or, field programmable gate arrays)

fuse based (program once) non-volatile EPROM or EEROM based RAM based



Programmable Logic Devices

PLA PROM PAL



EPLD Block Diagram

Macrocell

Courtesy Altera Corp.

Primary inputs



Antifuse

Normally high resistance (> 100 M)

on application of appropriate voltage, the antifuse is changed permanently to a low resistance structure (200-500)


Antifuse-based Actel FPGAsI/O Buffers

P rogram/Test/Diag nostics

I/O Buffers

I/O B

uffe

rs

I/O B

uffe

rs

Vertical ro utes

Rows o f logic m odule s

Routing channels

Standard-cell likefloorplan



Detailed Interconnect

Cell

Horizontaltracks

Vertical tracks

Input/output pin

Antifuse

Programmed interconnection

Programming interconnect using anti-fuses



Basic Block in Actel FPGA


RAM-based FPGAs

CLB CLB

CLBCLB

switching matrixHorizontalroutingchannel

Vertical routing channel

Interconnect point



Basic Block (CLB) in RAM-based FPGAs

R

Q1D

CE

R

Q2D

CE

F

G

F

G

F

G

R

D in

Clock

CE

F

G

A

B/Q1/Q2

C/Q1/Q2

D

A

B/Q1/Q2

C/Q1/Q2

D

E

Combinationa l logic Sto ra ge eleme nts

Any function of up to 4 variables

Any function of up to 4 variables

Courtesy of Xilinx



RAM-based FPGA

Xilinx XC4025



General Architecture of Xilinx FPGAs


Switch Matrices & Interconnection between CLBs


XC2000 CLB of the Xilinx FPGA


Overview of VLSI Design Styles


Design synthesis

Behavior Structure


Taxonomy of Synthesis TasksA rc hite ctural Le ve l Logic Le ve l C irc uit Lev el

Be

ha

vio

ral

Vie

wS

tru

ctu

ral

Vie

w

Archi tec tu reSynthe sis

LogicSy nthe sis

C irc uitSy nthes is

0

1

3

2

state(i: 1 ..1 6) ::sum = su m*z–1 +coe ff[i]* In*z–1

ab

c x

a

bc1

2

2

4

tp

ab

cx

D

me m

*

fsm



Circuit Synthesis

Logic equations transistor schematics selection of circuit style

– complementary static, pass-transistor, dynamic etc. construction of logic network

– e.g. Euler path techniques

Transistor sizing to meet performance constraints

– major impact on area, power, timing subtle process… sensitive to parasitics

– usually circuit modeled by equivalent RC circuit– detailed knowledge of subsequent layout process needed

for estimation of parasitic capacitances


RTL or Logic Synthesis

Generate structural view of a logic level network Many ways of specifying:

FSMs, schematics, boolean equations, HDL etc. Two step process:

technology independent phase– logic optimized using boolean & algebraic manipulation

technology mapping phase


Evolution of RTL Synthesis

2-Level logic minimization Espresso from Berkeley Suited for PLAs & PALs which were used a lot in 80s

Sequential and state-machine synthesis state minimization, state encoding

Multilevel logic synthesis Mis-II from Berkeley standard-cell and FPGA

Full blown RTL synthesis from HDL e.g. Synopsys’s VHDL compiler, Berkeley’s SIS


Example: Multi-level Logic Synthesis

Adder:S = (A B) Ci Co = A.B + A.Ci + B.Ci


Architecture Synthesis

Also called behavior or high-level synthesis Generate architecture from task description

under constraints on area, speed, power etc. Three phases

allocation: figures out busses, execution units etc. assignment: binds behavior operations to hardware

resources scheduling: order of operations

Also, transformations that manipulate input behavior to obtain superior solution

pipelining, parallelization etc.


Example of Architecture Synthesis

;


Alternative Solution


Design-Evaluation Space


Design-Evaluation Space for a Logic Function


Area, Latency, Cycle-time Design Evaluation Space


Another Example of Architecture Synthesis


Alternative Implementations

Documents

Mani Srivastava UCLA - EE Department [email protected] VLSI Design Methodologies EE116B (Winter 2001): Lecture # 4