12/8/2002 1

Lecture 13

ADVANCED DESIGNEXAMPLE

Manchester EncoderSlides ofMark Schulzused

12/8/2002 2

Manchester2 Encoder/Decoder◆◆ Short specificationShort specification◆ Manchester encoding scheme is used in communication to convert

binary data streams into electrical signals that are suitable forsending over long wires.This method makes the average value of a digital signal close to 0 andthus prevents the electrical bias of a transmission line.

◆ It also allows to embed the clock information into the data signal, sothere is no need to send the clock by a separate line.

1 1 1 1- 12V

+12V bias voltage

- 12V

+12Vbias voltage 0 1 0 1 0 1 0 1

12/8/2002 3

Manchester2 Encoder/Decoder◆◆ Short specificationShort specification◆ Principles of Manchester encoding

0 11

0 1 0

1 1 1 1

0 0 0 0

1 0 0 1

0 1 0 1 0 1 0 1

1 0 1 0 1 0 1 0

0 1 1 0 1 0 0 1

12/8/2002 4

Manchester2 Encoder/Decoder

◆◆ Short specificationShort specification◆ Structure of a simple communication link

data source

DataReady

ReadyToSend

8bit data Man2E encoder

line

driv

er

data sink

DataReady

8bit data Man2D decoder

line receiver

clock recover

12/8/2002 5

◆◆ Short specificationShort specification◆ Handshake protocol ManEncoder <-> DataSource

data source

DataReady = DR

RTSReadyToSend

8bit data Man2E encoder

0 1 2 6 7 0 1 6 7

DR

8bit data - A

RTS

8bit data - B

serial data serial data - A

C

B

bit

bitClk

Manchester2 Encoder

12/8/2002 6

Manchester2 Encoder

◆◆ Short specificationShort specification◆ Handshake protocol ManEncoder <-> DataSource

data source

DataReady = DR

RTSReadyToSend

8bit data Man2E encoder

0 1 2 6 7 0 1 6 7

DR

8bit data - A

RTS

8bit data - B

serial data serial data - A

C

B

bit

bitClk

12/8/2002 7

◆◆ Short specificationShort specification◆ Handshake protocol ManEncoder <-> DataSource

data source

DataReady = DR

RTSReadyToSend

8bit data Man2E encoder

0 1 2 6 7 0 1 6 7

DR

8bit data - A

RTS

8bit data - B

serial data serial data - A

C

B

bit

bitClk

Manchester2 Encoder

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◆◆ Short specificationShort specification◆ Handshake protocol ManDecoder <-> DataSink

Manchester2 Decoder

data sink

DataReady

8bit data Man2D decoder

clock recover

DR

8bit data

serial data - Z serial data - A

bitClk

6 7 610 7 05

6 7 610 75 5 0

12/8/2002 9

◆◆ Short specificationShort specification◆ Handshake protocol ManDecoder <-> DataSink

data sink

DataReady

8bit data Man2D decoder

clock recover

DR

8bit data

serial data - Z serial data - A

bitClk

6 7 610 7 05

6 7 610 75 5 0

Manchester2 Decoder

12/8/2002 10

Manchester2 Encoder◆◆ Block StructureBlock Structure

LastBit

Data Ready

ReadyToSend

Clk

LatchEnable

Shift

Bit(i)

COUNTER mod 16

CO

NT

RO

LLER

LATC

H &

SH

IFT

CEn

8 Bi

t Dat

a

Enable

SDat

12/8/2002 11

Manchester2 Encoder◆◆ Block StructureBlock Structure How it works How it works

SDat

LastBit

Data Ready

ReadyToSend

Clk

LatchEnable

Shift

Bit(i)

COUNTER mod 16

CO

NT

RO

LLER

LATC

H &

SH

IFT

CEn

8 Bi

t Dat

a

Enable

8DatBit(i)

SDat

En

RTS

DR

LEn

Clk

LBit

Sh

CEn

xAC

12/8/2002 12

How it works How it works

Manchester2 Encoder◆◆ Block StructureBlock Structure

En

RTS

DR

LEn

8DatBit(i)

SDat

Clk

LBit

Sh

CEn

xAC

LastBit

Data Ready

ReadyToSend

Clk

LatchEnable

Shift

Bit(i)

COUNTER mod 16

CO

NT

RO

LLER

LATC

H &

SH

IFT

CEn

8 Bi

t Dat

a

Enable

SDat

12/8/2002 13

Manchester2 Encoder◆◆ Block StructureBlock Structure How it works How it works

SDat

LastBit

Data Ready

ReadyToSend

Clk

LatchEnable

Shift

Bit(i)

COUNTER mod 16

CO

NT

RO

LLER

LATC

H &

SH

IFT

CEn

8 Bi

t Dat

a

Enable

En

RTS

DR

LEn

8DatBit(i)

SDat

Clk

LBit

Sh

CEn

xAC

12/8/2002 14

Manchester2 Encoder◆◆ Block StructureBlock Structure How it works How it works

En

RTS

DR

LEn

8DatBit(i)

SDat

Clk

LBit

Sh

CEn

xAC 0 0

LastBit

Data Ready

ReadyToSend

Clk

LatchEnable

Shift

Bit(i)

COUNTER mod 16

CO

NT

RO

LLER

LATC

H &

SH

IFT

CEn

8 Bi

t Dat

a

Enable

10101100

SDat

12/8/2002 15

Manchester2 Encoder◆◆ Block StructureBlock Structure How it works How it works

En

RTS

DR

LEn

8DatBit(i)

SDat

Clk

LBit

Sh

CEn

xAC 0 0

LastBit

Data Ready

ReadyToSend

Clk

LatchEnable

Shift

Bit(i)

COUNTER mod 16

CO

NT

RO

LLER

LATC

H &

SH

IFT

CEn

8 Bi

t Dat

a

Enable

10101100

SDat

12/8/2002 16

Manchester2 Encoder◆◆ Block StructureBlock Structure How it works How it works

En

RTS

DR

LEn

8DatBit(i)

SDat

Clk

xAC

LBit

Sh

CEn

0 0 1 1 0 1 0 1

LastBit

Data Ready

ReadyToSend

Clk

LatchEnable

Shift

Bit(i)

COUNTER mod 16

CO

NT

RO

LLER

LATC

H &

SH

IFT

CEn

8 Bi

t Dat

a

Enable

10101100

SDat

12/8/2002 17

Manchester2 Encoder◆◆ Block StructureBlock Structure How it works How it works

En

RTS

DR

LEn

8DatBit(i)

SDat

Clk

xAC

LBit

Sh

CEn

0 0 1 1 0 1 0 1

SDat

LastBit

Data Ready

ReadyToSend

Clk

LatchEnable

Shift

Bit(i)

COUNTER mod 16

CO

NT

RO

LLER

LATC

H &

SH

IFT

CEn

8 Bi

t Dat

a

Enable

10101100

12/8/2002 18

Manchester2 Encoder◆◆ Block StructureBlock Structure How it works How it works

8DatBit(i)

SDat

SDat

LastBit

Data Ready

ReadyToSend

Clk

LatchEnable

Shift

Bit(i)

COUNTER mod 16

CO

NT

RO

LLER

LATC

H &

SH

IFT

CEn

8 Bi

t Dat

a

Enable

10101100

En

RTS

DR

LEn

Clk

xAC

LBit

Sh

CEn

0 0 1 1 0 1 0 1

12/8/2002 19

SDat

Manchester2 Encoder◆◆ Block StructureBlock Structure How it works How it works

LastBit

Data Ready

ReadyToSend

Clk

LatchEnable

Shift

Bit(i)

COUNTER mod 16

CO

NT

RO

LLER

LATC

H &

SH

IFT

CEn

8 Bi

t Dat

a

Enable

10101100

0 0 1 1 0 1 0 1

En

RTS

DR

LEn

8DatBit(i)

SDat

Clk

xAC

LBit

Sh

CEn

12/8/2002 20

Manchester2 Encoder◆◆ Block StructureBlock Structure Counter timing Counter timing

En

RTS

LEn

CQ3

CQ2

Clk

CQ1

Sh = CQ0

CEn

LBit

SDat

Data Ready

ReadyToSend

Clk

LatchEnable

Shift

Bit(i)

COUNTER mod 16

CO

NT

RO

LLER

LATC

H &

SH

IFT

CEn

8 Bi

t Dat

a

Enable

10101100

LBit

12/8/2002 21

Manchester2 Encoder◆◆ CONTROLLERCONTROLLER Timing Timing

Q0 Q1 SdatS0

S3S2S1

S4

0 0 1

0 1 10 1 01 0 1

1 0 0

0

1

S0

S3 S2

S1S4

!LEn

LEn&B(0) LEn& !B(0)

1 1

!B(i) B(i) B(i) !B(i)

!LEn # !En

0 0 1 1 0 1 0 1

En

RTS

DR

LEn

8DatBit(i)

SDat

Clk

xAC

LBit

Sh

CEn

12/8/2002 22

Manchester2 Encoder◆◆ CONTROLLERCONTROLLER Timing Timing

H0!En

!En

H3

!LBit

H1!DR

H2

En

DR

1LBit

Q0 LEn RTSH0

H3H2H1

0 0 0

1 0 00 1 00 0 1

CEn = 0

CEn =1!C15

!LEn

C15LEn

0 0 1 1 0 1 0 1

En

RTS

DR

LEn

8DatBit(i)

SDat

Clk

xAC

LBit

Sh

CEn

12/8/2002 23

Q0 Q1 SdatS0

S3S2S1

S4

0 0 1

0 1 10 1 01 0 1

1 0 0

0

1

S0

S3 S2

S1S4

!LEn

LEn&B(0) LEn& !B(0)

1 1

!B(i) B(i) B(i) !B(i)

!LEn # !En

H0!En

!En

H1

!LBit

H1!DR

H1

En

DR

1LBit

Q0 LEn RTSH0

H3H2H1

0 0 1

0 1 10 1 01 0 1

CEn = 0

CEn =1!C15

!LEn

C15LEn

Clk

DR

LBit

En

Bit(i)

LEn

RTS

SDat

CEn

Manchester2 Encoder◆◆ CONTROLLERCONTROLLER

12/8/2002 24

What have we learnt?◆ Top down design methods suite well design of digital

systems.◆ State diagrams are efficient tools in design of sequential

logic.A controller can be defined as a set of interacting FSMs.

◆ Timing diagrams are important to understand interactions inmore complex designs.

◆ Synchronous systems are safe and relatively easy to design.