by Anantha R. Sethuraman, Ph.D.,CMP Solutions, KLA-Tencor

hemical Mechanical Polishing(CMP) has become one of the

most widely-accepted and practicedplanarization methods in IC fabrica-tion in less than two decades. Theexplosive growth of this segment ofsemiconductor process technologyhas been remarkable in an industrythat has been credited with rapidgrowth. In an industry that aspiresto reach six sigma process controlbased on scientific first principles,CMP is still being used and devel-oped by artisans. The rigor in thedesign of experiments held as gospelby the semiconductor industry hasnot been applied in the developmentof CMP consumables. After morethan ten years of widespread assimi-lation of this technology, users needan integrated process control solu-tion for their CMP needs. This articlediscusses some of the history of thematuration of the technology, notescurrent challenges facing the indus-try and presents some views on thetimeliness of an integrated processcontrol solution for CMP.

Current status and emerging trendsWhen viewed as a process modulewithin a fab, CMP is comprised of anumber of elements from a numberof different suppliers (see figure 1).1

C

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CMP TECHNOLOGY TRENDS: IMPLEMENTATION

Each user assembles a selection ofcomponents from this list and inte-grates the process in manufacture. Itis quite likely that each of these com-ponents are available from a relative-ly limited group of vendors who spe-cialize in products unique to CMPwhich are guarded by high levels ofsecrecy and intellectual property pro-tection. In contrast, for the moremature sectors such as plasma etch orthin film chemical vapor deposition(CVD), an equipment supplier canmore than likely provide the userwith the tool, best-known-methods(BKMs), endpoint detection, processconsumables, delivery systems andeven exhaust treatment systems.With the broadening of knowledgeand expertise in CMP, the technicalcommunity is driving towardsachieving the maturity level thatthey have become accustomed toexpect in widely accepted processes.However, due to the consumable-specific nature of CMP itself, the factremains that all slurries and pads willstill be specialty materials, controlledby one or two vendors. By its verynature — its multiple vendors andspecialty material requirements—CMP has developed into a niche mar-ket technology that demands gener-ous amounts of “black magic” andfolklore to achieve success!

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SSttoorryyFROMTO IMPROVEMENT

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starts per week that would needCMP, this number is in the thou-sands. This implies that the processhas emerged as a critical part of thearchitecture of an integrated circuitand is therefore needed for integratedcontrol of the process to achieve yieldgoals.

Emerging trends in equipment alsosupport the need. A typical layout ofa polishing area in the fab is shown infigure 4. As one can imagine, a waferfab with more than 10,000 waferstarts per week would have severalpolishers. Currently each polish andclean tool is intrinsically connectedwith the input and output device. Inthe future, a robot will be used toallow two or more polishers to beattached to a single input/outputsource and a single cleaning station.This arrangement will optimize tooluse and increase processing speed.

The development of the infrastruc-ture needed to support an efficientoperation is drawn from all the ven-dors that supply into the area. SinceCMP is a relatively new area forsemiconductor manufacture, theexpertise on the user side is sparsealthough growing. Larger organiza-tions such as IBM, Intel, MicronTechnology, Motorola and AMDhave over the years developed a rea-sonable methodology to manage thetechnology. The development of such

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The rapid growth in the use of CMPtechnology is shown in figure 2.Between 1994 and 1998, CMP usemore than doubled — use of CMP oninterlayer dielectrics (ILD) grewfrom three to five layers, and polish-ing of metal contacts and the intro-duction of the damascene process cre-ated the need for CMP on metal. Forexample in a four metal layer processwith shallow trench isolation (STI),ILD and tungsten CMP: 15-25 pol-ishers would be needed at 60 percentutilization, with 20 wafers per hour,in a fab with 5000 wafer starts perweek.

Furthermore, the extension of CMPto the front-end in order to enableSTI integration has triggered theneed for innovation. STI has becomean architectural requirement for sub-0.25 micron device rules, as localizedoxidation of silicon (LOCOS) doesnot deliver the critical transistorproperties. The challenge of STI istypically to planarize a high densityplasma oxide over silicon nitride.The objective is to remove the over-burden without damaging thenitride excessively, while preservingthe integrity of the circuit. Althoughthis is a formidable requirement, itpresents a great opportunity. Theresult has been development of exot-ically exciting technical solutions inCMP consumables, especially high-selectivity slurries. In addition,process solutions using better end-pointing have also enabled STI CMP.

In the memory area (specificallyDRAM), polysilicon polish has beenin implementation for about a year.The volume is expected to increase asmore manufacturers adopt poly CMP.

Figure 3 describes the evolution ofCMP applications in chip manufac-ture. About two-thirds of the 93semiconductor fabs producingdevices with sub-0.5 micron geome-tries require some form of CMP.When considered in number of wafer

Figure 1. Elements of a CMP process

module.1

Figure 2. Growth of CMP utilization.2

Figure 3. Current and future

Planarization Metrology

Equipment Equipment EquipmentConditioner PVA Brush ThicknessEndpoint detect Tanks UniformityProcess Spin/rinse/dry ParticlesSlurry Hot DI water ScratchesPad Cold DI water DefectsInsert Process Electrical qualityTemplate Chemistry Setup standardsSlurry delivery Chemical deliverySlurry replenishing Chemical disposalSlurry recyclingSlurry disposal

ILD polishMetal polish

# of

Lay

ers

Polis

hed

1994 (0.8 - 0.5) 1998 (0.35 - 0.25 µm)

Application

1st Generation0.8-0.5 µm

2nd Generation<0.5 µm

3rd Generation< 0.25 µm

Post-CMPCleaning

Oxide (ILD)

Above + ILD0W CMP + STI

Above + Cu, Al & low kCMP + new applications

(both FE & BE, e.g. Poly Si)

methodologies has been evolutionary.The conventional control that asemiconductor engineer would liketo have over the various aspects of theprocess has not been possible withCMP, primarily due to the continu-ing and rapid metamorphosis of theprocess itself.

A history of CMP developmentLet us examine a little bit of history.The chronology described in figure 5shows the initial rollout of CMP3.Conceived and developed at IBMunder strictest secrecy during theearly 1980’s, the process was not wellpublicized. Vendors who suppliedequipment such as IPEC Westech, R.Howard Strasbaugh and process con-sumable suppliers with pads/carrierfilms from Rodel and slurry fromCabot were not told the end result oftheir involvement. This was a typicalpractice in early semiconductorprocess development, as intellectualproperty issues were not well workedout between vendors and chipmak-ers. The concept of joint develop-ment projects (JDPs) between ven-dors and chipmakers was alien in theera of big company research anddevelopment activities. The resultwas that early understanding of theintricacies of the process rested solelywith the users and an infrastructurefor development of an ideal solution

integrating both equipment andmaterials was not developed. Afterall, the concept of polishing a waferwith expensive circuitry that hadbeen developed and manufactured ina clean room environment using“dirty” particle-laden slurry wasstarted as an “experiment”. Given thedramatic shift in thinking requiredto accept such an idea, there were amultitude of skeptics who did notexpect CMP to survive, let alone bewhere it is today.

As with every breakthrough we havewitnessed in the technology sector,what was once deemed improbable,or even impossible, has become areality and is now accepted as anessential step. Until depth of focusrequirements necessitated morestringent planarity as the shift to0.35 micron devices occurred, CMPwas never seriously viewed as a long-range solution. Due to the secrecywith which it was developed, under-standing both the power and thechallenges of CMP has taken longerto achieve than many other processesin our industry’s history.

Following on the heels of IBM, Intellaunched CMP via technology trans-fer in the 1987-88 timeframe fol-lowed by Micron Technology in1989. The SEMATECH program onCMP was conceived in 1989 andthen began the pursuit of rigorouscharacterization of the process asadoption rose quickly. Member com-panies dispatched their best talent tocollaborate in this “sand box” calledSEMATECH. Technical advisoryboards were formed and vendors wereinitiated into the “inner circle”,although again restrictions againstdisclosing the JDP progress to non-member companies were imposed inan effort to ensure better return oninvestment for the member compa-nies. Figure 6 presents the number ofprocess areas that were involved inthe CMP sector in 1992 and theincrease to date. It depicts a 5-10

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Figure 4. Trends in equipment layout in the

CMP area.2

Figure 5. CMP development at IBM.

trends in CMP applications.

CMP Post-CMPCleaning

Single Platen/Single Head1-step polish

Multi-Platen/Multi-Head 2-step polish (buff step)

End-point detection On-board metrology

Integrated Dry-in/Dry-outMulti-Platen/Multi-HeadNon-Rotary (e.g. Orbital,Linear CMP) multi-step

polish, End-point detectionOn-board metrology

Conventional wafer cleaning(wet stations)

Wafer scrubbing/DI water

Wafer scrubbing/DI waterNH4OH

Integrated Dry-in/Dry-outMulti-Platen/DIW

NH4OH, HFNew cleaning methods &

New chemistries

Polish 1

I/O Clean

Polish 2

Robot

CleanPolish

I/O

East Fishkill Base Technology (83)East Fishkill Pilot Line (86)

Logic (Oxide, Al) (89)Logic (Oxide, W) (89)

Burlington Pilot Line (86)

4MB DRAM (89)

current future

dielectric applications makes controlof CMP more critical in achievingappropriate device yield and perfor-mance.

What are the core competencies thatwill be needed in a supplier to win in the integrated process control solution game? To begin with, thishighly complex technology willrequire an understanding of polymerchemistry, colloid chemistry, powdersynthesis, electrochemistry, and sur-face chemistry, none of which aremainstream competencies in anindustry that makes electricaldevices. So who would be most suc-cessful in delivering an integratedprocess control solution for CMP?The most likely case would be acoalition of capital equipment ven-dors and consumable vendors whocan service the market with all that isneeded to run the process. Unlikemany other semiconductor processes,CMP is unique in its requirement forboth chemical and mechanical supe-riority, making the coordination oftools and materials considerablymore important to a successful effort.

This industry is largely dominatedby electrical engineers and, to a cer-tain extent by mechanical engineers,due to equipment needs, so the fewchemists or physical sciences engi-neers available have not been ade-quate to drive the creation of an inte-grated solution scenario. Furthermore,the newness of the technology has led to a “rat race” to file patents (figure 7). Propelled by the need tobe the “first-to-file” company, mostof the users have been unwilling todisclose or “share” the secrets withvendors who might then have beenin a position to provide better solu-tions. This thinking is changing, butit has left a legacy of slow change inits wake.

Only now, as CMP has finallyemerged as not just an accepted butan essential practice in the majority

times increase in the number of sup-pliers, each filling a specific needwith a tailored solution. These sup-pliers now vie for nearly a billion dol-lars in total revenue available today.3Considering the unusual complexitycreated by both the very nature ofCMP and its idiosyncratic develop-ment, an integrated process controlsolution provider has not emerged.

What does the futurehold?With the advent of copper intercon-nect, the influence of CMP on finalyield has increased even more. Thesuccess of copper dual damasceneinterconnect technology lies squarelyon the film deposition, CMP andpost-CMP clean steps. Along withthe enabling characteristics of CMPfor copper, there also is a hidden dan-ger. Flaking of copper during or as aresult of the CMP process createsdefects that might be insignificant inother processes, but are considered“killers” in these highly sensitiveapplications. The thin layers andmultiple levels used in copper inter-connect structures will requireincreased CMP use, yet little isunderstood about the criticality ofthe defects seen there. The principalchallenge in copper CMP is optimiz-ing copper polish rate with respect tobarrier layers (typically Ta or TaN).Currently this is being achieved by atwo or three stage process wherein anew slurry is employed for barrierpolish. Although not fully opti-mized, the challenge has openeddoors for technology development.For this reason, the introduction ofcopper presents a huge inspectionchallenge and thereby a valuableopportunity for innovation.

We are currently approaching a pointin time when there is a definite needto provide an integrated process con-trol solution for CMP. Copper inter-connect and a continuation of thechallenges in areas such as shallowtrench isolation and other interlayer

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Figure 6. Growth in the number of CMP

vendors to date.3

Figure 7. Number of CMP patents filed.

Number of CMP Vendors

Number of CMP Patents Filed

1. M.A. Fury, Solid State Technology, April 1995and July 1995.

2. M. Moinpour, Proc.NCCAVS CMPUG AnnualSymposium., 1997.

3. K. A. Perry, VLSI Conference., June 1997.

4. A.R. Sethuraman, Future Fab International, Vol. 5, pp.261, 1998.

5. A.R. Sethuraman, Proc. of CMP 98, NCCAVS,1998.

About the AuthorAnantha Sethuraman has a Ph.D. in Materials Science with a metallization specialization. He is a Senior Director in CorporateMarketing focused on CMP strategy. He has held managerial positions in technology development at Cypress Semiconductorand Rodel Inc. He was involved in the development of CMP technology for several years at Rodel, primarily responsible for slurry and process development for advanced CMP processes. Anantha has published more than 70 papers and holds several patents in CMP technology.

Contact informationKLA-Tencor • 160 Rio Robles • San Jose, CA. 95134Tel 408.875.4374 • Fax 408.875.4144Email: anantha.sethuraman@kla-tencor.com

C O V E R S T O R Y

of fabs, is the industry turning from“implementing” to “improving” theuse of this technology. An integratedsolution utilizing the best tools,materials and techniques will be crit-ical in achieving the high level ofdevice performance and productionyield required for the advanced prod-ucts of the next millennium.

Acknowledgments The author would like to acknowledgethe helpful discussions with Mike Furyof Allied Signal, Mansour Moinpour ofIntel Corporation and Kathleen Perry of Obsidian Inc. for the theme of thisarticle.

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