Maciej Ciesielski Electrical & Computer Engineering University of Massachusetts, Amherst, USA

2004 Ciesielski Taylor Expansion Diagrams 1

Taylor Expansion Diagrams:A Compact Canonical Representationfor Symbolic Verification and Synthesis

Maciej Ciesielski

Electrical & Computer EngineeringUniversity of Massachusetts, Amherst, USA

[email protected]


Motivation – RTL Verification

• Complex RTL designs: – data flow and – control

• Interaction– Arithmetic and Boolean– Data flow and control

BA

s1

10

F1

Dak

bk

>

+*-

• Check equivalence of two RTL designs

A

B

s2

01

F2

bk

ak

*

*-

D


Common Representations

• Boolean functions ( f : B B )– Truth table, Karnaugh map– SoP, PoS, ESoP– Reed-Muller expansions (XOR-based)– Decision diagrams (BDD, ZDD, etc.)

• Arithmetic functions ( f : B Int )– Binary Moment Diagrams (*BMD, K*BMD, *PHDD)– Multi-terminal, Algebraic Decision Diagrams (ADD)

• Arithmetic functions (f : Int Int )– Taylor Expansion Diagrams (TED)


Canonical Representations

• Each minimal, canonical representation is characterized by– Decomposition type

• Shannon, Davio, moment decomposition, Taylor exp., etc.

– Reduction rules• Redundant nodes, isomorphic sub-graphs, etc.

– Composition method (“Apply”, composition rule)

• What they represent– Boolean functions (f : B B)

– Arithmetic functions (f : B Int )

– Algebraic expressions (f : Int Int )


Decomposition Types

• Shannon expansion

f = x fx + x’ fx’

• Moment decomposition: replace x’=1-x

f = x fx + (1-x) fx’ = fx’ + x fx

where fx = fx - fx’

– also called positive Davio decomposition


Binary Decision Diagrams (BDD)

• Based on recursive Shannon expansion

f = x fx + x’ fx’

• Compact data structure for Boolean logic– can represents sets of objects (states) encoded as

Boolean functions

• Canonical representation– reduced ordered BDDs (ROBDD) are canonical– essential for verification


Binary Moment Diagrams (*BMD)

• Devised for word-level operations, arithmetic

• Based on modified Shannon expansion (positive Davio)

f = x fx + x’ fx’ = x fx + (1-x) fx’ = fx’ + x (fx - fx’ ) = fx’ + x fx

where fx’ = fx=0, is zero moment

f x = (fx - fx’ ) is first moment

• Additive and multiplicative weights on edges (*BMD)


*BMD - Construction

• Unsigned integer: X = 8x3 + 4x2 + 2x1 + x0

• X(x3=1) = 8 + 4x2 + 2x1 + x0

• X(x3=0) = 4x2 + 2x1 + x0

• Xx3 = 8 x3

8

x2

x1

x0

4210

10

x0

x1

x2

12

4

x3

8

BMD

*BMD

Multiplicative edges


*BMD - Word Level Representation• Efficiently modeling symbolic word-level operators

Word level

4

10

x0

x1

x2

12

4

y0

y1

y2

2

1

10

x0

x1

x2

y0

y1

y2

12

4

24

1

Word level

X+Y X Y


Properties of BDDs and *BMDs

• Both are canonical for fixed variable order

• BDDs– Good for equivalence checking and SAT– Inefficient for large arithmetic circuits (multipliers)

• BMDs– Efficient for word-level operators– Less compact for Boolean logic than BDDs– Good for equivalence checking, but not for SAT – Insufficient for high-order arithmetic expressions


Symbolic Level Representation• Can we devise a truly symbolic representation?

– more general representation than “word-level” *BMD

X + Y

10

X

Y

Symbolic level

X Y

10

X

Y

Symbolic level


Taylor Expansion Diagram (TED)

• Let F be a continuous, differentiable function

• Taylor Expansion (around x=0):

F(x) = F(0) + x F’(0) + ½ x2 F’’(0) + …

• Notation

– F0(x) = F(x=0) 0-child - - - - - -

– F1(x) = F’(x=0) 1-child ----------

– F2(x) = ½ F’’(x=0) 2-child ======

– etc.

F(x) = F0(x) + x F1(x) + x2 F2(x) + …

x

F0(x) F1(x) F2(x) …

F(x)


Construction - Your First TED

F = A2B + 2C + 3A F0(A) = F|A=0 = 2C + 3

F1(A) = F’|A=0 = 2AB|A=0 = 0

F2(A) = ½ F’’|A=0 = B

B

10

A

G= 2C + 3

H0(B) = B|B=0 = 0

H1(B) = B’ = 1

C G0(C) = (2C+3)|C=0 = 3

G1(C) = (2C+3)’ = 2

B

C

*BMD : requires bit-level expansion!

23

H

(before normalization)


TED vs *BMD

• *BMD representation of F = X2 , X={x2, x1, x0}

• *BMD requires bit-level expansion– works on bit level– modeled with constant and first moment only

10

x0

x1

x2

x1

x0 x0

2

4

8F = (4x2 + 2x1 + x0)2 = 16x2+ 16x2x1+ 8x2x0+4x1+ 4x1x0+ x0


TED – a few Examples

1

x0

x1

x2

x3

2

4

1

0

1x0

x1

x2

1

1

1

44

816

16

64

11

(A+B)C +1

10

B

C

A

1

(A+B)(A+2C)

10

B

C

A

B

1

2

2)0x12x24x3(8x2X


TED Reduction Rules # 1

a) Nodes with all empty edges

1. Eliminate redundant nodes:

b) with only a constant term

0

f = 0 a2 + 0 a + g(b) = g(b), independent of a

f = 0 a2 + 0 a + 0 = 0

a

0

fa

b 0

f

g

bg


TED Reduction Rules # 2

2. Merge isomorphic subgraphs (identical nodes)

(A2 + 5A + 6)(B + C)A

B

C

10 0 11

BB

CC

6 51

A

B

C

01

6 5 1


TED Normalization

• TED is normalized if– there are no more than two terminal nodes: 0 and 1– weights of edges of a given node must be relatively

prime (to allow sharing isomorphic graphs)

26

B

A

2

2A + 2B + 6

normalized3

B

A

1

2

2

1 3

B

A

1

2

11

2(A + B + 3)


Normalization - Example

(A2 + 5A + 6)(B + C)

A

B

C

50 0 16

BB

CC

A

B

C

01

6 5 1

A

B

C

10 0 11

BB

CC

6 51


TED: Composition

• Operation depends on relative order of variables x, y – if x = y, then z = x, and

h(x) = f(x) OP g(x)

= f0(x) OP g0(y) + x [f1(x) OP g1(y)] + x2 [f2(x) OP g2], …– if x > y, then z = x, and

h(x) = f0(x) + g(y) + x f1(x) + x2 f2(x) + … (for OP = +)

h(x) = f0(x) • g(y) + x [f1(x) • g(y)] + x2 [f2(x) • g(y)] … (for OP = •)

u

f

x v

g

yOP =

• Recursive composition of nodes, starting at the top

h = f OP gqz

OP = (+, - , •)


COMPOSE Operator – ADD/SUB

• Nodes indexed by same variable

• Nodes indexed by different variable (x > y)

u

u0 u1

x v

v0 v1

x+ =

u

u0 u1

xv

v0 v1

y+ =

u + v

u0+v0 u1+v1

x

u + v

u0+ v

x

u1


COMPOSE Operator – MULT

• Nodes indexed by same variable

• Nodes indexed by different variable (x > y)

u

u0 u1

x v

v0 v1

x• =

u

u0 u1

xv

v0 v1

y• = u • v

u0 • v u1 • v

x

u • v

u0•v0

x

u0•v1+u1•v0

u1•v1


COMPOSE Operation - Example

*

A+B

0 1

4

3

A

B= 3•5

4•6A

0•5

C

A+2C

0 1

6

5

A

21•5

B

0•0 0•2 1•0 1•2

C C1•5

1•0 1•2

+

1•1

B3•1

0•1 1•1

C

0

7

2

B

0

8

1

+=0+7

8+7B

0+0 0+2 1

C

(A+B)(A+2C)

20 1

C

A

B B

2


Properties of TED

• Canonical• Compact• Linear for polynomials of

arbitrary degree– TED for Xk, k = const, with

n bits, has k(n-1)+1 nodes.

• Can contain symbolic, word-level, and Boolean variables

• It is not a Decision Diagram1

x0

x1

x2

x3

2

4

1

0

1x0

x1

x2

1

1

1

44

816

16

64

11

X2=(8x3+4x2+2x1+x0)2

n = 4, k = 2


TED for Boolean logic

AND

10

x

y

x y = x y

10

x1 -1

x’ = (1-x)

NOTOR

x y = (x + y – x y)

10

x

yy

-11

XOR

x

10

yy

-21

x y = (x + y – 2 x y)

• Needed to model arithmetic-Boolean interface • Same as *BMD for Boolean logic


TED for Arithmetic Circuits

• Arithmetic circuits contain related word-level (A, B) and Boolean (ak, bk) variables

A = [ an-1, …, ak , …,a0 ] = 2(k+1)Ahi + 2k ak + Alo

BA

s1

10

F1

Dak

bk

>

+*-

s1 = ak (1-bk)

Ahi Alo

0 1

2k

2(k+1)

Ahi

ak

Alo


Applications to RTL Verification

• Equivalence checking with TEDs– interacting word-level and Boolean variables

A

B

s2

01

F2

bk

ak

*

*-

D

BA

s1

10

F1

Dak

bk

>

+*-

F1 = s1(A+B)(A-B) + (1-s1)Ds1 = (ak > bk) = ak (1-bk)

F2 = (1-s2) (A2-B2) + s2 Ds2 = ak’ bk = 1 - ak + ak bk

A = [an-1, …,ak,…,a0] = [Ahi,ak,Alo], B = [bn-1, …,bk,…,b0] = [Bhi,bk,Blo]


RTL Equivalence Checking

BA

s1

10

F1

Dak

bk

>

+*-

A

B

s2

01

F2

bk

ak

*

*-

D

1

ak

0

Ahi

D

ak

bk bk

Bhi

Alo

Blo

0

1

22k+2

2k+

2

^2

-2k+

2

2k2k

-22k+2

1-1

-1

1

F1 = F2

^2 = power edge


Verification of Algorithmic Specifications

x

x

x

xFAB1

FAB2

FAB2

FAB3

IFFT0

IFFT1

IFFT3

IFFT2InvFFT(FAB)

A[0:3]

B[0:3]

C0C1

C2

C3

Conv(A,B)

A0A1

A3

A2

B0B1

B2

B3

FFT(A)

FFT(B)


Equivalence: Checking for TED Isomorphism

4{ A0*B0 + A1*B3 + A2*B2 + A3*B1}

In general, this proves: IFFT(i) Conv(i)

0 4

A0

A2

A1

A3

B1 B3 B2 B0

IFFT0 = C0


Complex and GF Computations

X

Y

0 1

2

4

X

Y

0 1

1

3

* =

X

Y

0 1

3

0

X

Y

132 +4 1 = 0

=

043 =

• Works for complex values and Galois Field (GF) operators

• Assume Galois Field GF[8], let 0 be primitive element of GF(8)

Q[XY] = (4 X + 2 Y)(3 X + 1 Y)R[XY] = 0 X + 3 Y

• Q and R are equivalent, have isomorphic TEDs


Limitations of TED Representation

• Non-linear design blocks (comparators, etc)– Cannot be represented as polynomials in Integer domain– Require decomposition at bit level– Complexity comparable to BDD’s

• Partial expansion of vectors (bit select)– Example: carry-out in adders, sign bit, etc

B

A +Sum

Cout

A, B, Sum – word level variables


Limitation: Internal Partial Fanout

• Internal partial fanouts: problem

Z = A+BA

B+A

B+

Z=A+B

F(Z,B[4:3])

B[4:3]G(A, BHI, B[4:3], BLO)

• Computations w/out internal partial fanouts: “nice” polynomials

• Cannot represent subvectors as continuous functions (polynomials), cannot model them as TED

A

B+

Z=A+B

Z[4:3]


Modeling Multiple-Output Discrete Functions

• Consider the output sub-vectors as individual functions- Discrete functions, arbitrary

A

B+

Z=A+B

Z[k:l]

Z[n] = F1(A,B)

Z[..] = F2(A,B)

Z[k:l] = F3(A,B)?

• Problem: can we model these discrete functions as polynomials in terms of input symbolic variables, without going down to bit level ?

• We recently attempted to model those signals as characteristic polynomials in GF, based on GF decomposition• Problem: high order polynomials (2k for k bits)


Modeling Discrete Functions in GF(N)

• Consider a multi-valued variable A, integer [0,…,N]

Let Ak = 1 if A = k, and Ak = 0 otherwise• For two-input function F(A,B) a term Ak Bi can be written as

Ak Bi= [1 – (A – k)N] [1 – (B – i)N]

• For example, in GF(N=4):

A1 Bα = [1 – (A – 1)3] • [1 – (B – α)3] = 1 if and only if A=1 and B=α

For all other values of A, B, this term = 0

• This is a property of GF(N)

Based on decomposition in GF(N) [Pradhan’78]


Conclusions• Features of TED

– Canonical– Compact – Represents arithmetic (word-level) blocks + Boolean logic

• Applications– Symbolic simulation (representation)– Equivalence checking, RTL verification – Algorithm verification– Varied computational domains: integer, binary, complex, GF, etc.– DSP, error correction coding, cryptography….– Other potential applications


Discussion• Limitations

– Increase in Boolean logic increases TED complexity– Problem: internal fanouts and multiple-output functions

• Cannot break outputs into sub-vectors• Functions cannot be modeled as low order polynomials

• Open problems– Satisfiability, functional test generation– Finite precision arithmetic


Taylor Expansion Diagrams

Application to Behavioral Synthesis


High Level Synthesis

Architectural solution minimized for given objective, constraints

Architecture

Specification (HDL)Specification (HDL)

...

Data Flow Graph

Objectives, constraints:

PowerPowerAreaArea LatencyLatency


High Level Synthesis ExampleInputs: A, B, C, DOutput: F ………

assign F = A*B + A*C ……….

Single Data Flow Graph (DFG)

Architecture 2:

1 Mult, 1 Add, L = 3 cycles

Cycle 1

Cycle 2x

+

x

Cycle 3

A

CA

B

F

Architecture 1:


x x

+

Cycle 1

Cycle 2

A CAB

F


High Level Synthesis - currentF = A*B + A*CF = A*B + A*C

x x

+

Specification

Singledata flow graph

Algorithms:

• Scheduling

• Allocation

• Resource binding

LatencyLatencyLatencyLatency

x x

+

Cycle 1

Cycle 2

A B A C

AreaAreaAreaArea

Cycle 1

Cycle 2 x

+

x

Cycle 3

A B

A C


Alternative solution

• The data flows are derived directly from user’s specification

• There is a need for a higher level of synthesis:

• Transformation A*B + A*C = A*(B+C)

• Abstract level synthesis should provide

Canonical representation

Basis for optimal solutions for different objectives

To derive alternative solutions, need different Data Flow Graph• user must rewrite the initial specification (HDL)• replace (A B + A C) by A (B + C)

Alternative architecture:


+

x

Cycle 1

Cycle 2

C

A

B

F


Current HL Transformation Methods

• Ad-hoc methods (algebraic)– Commutativity: A + B = B + A

– Associativity: A + (B +C) = (A + B) + C

– Distributivity: A * (B +C) = (A * B) + (A * C)

• Term rewriting, etc.

• Tools– Matlab, Maple– Mathematica

• Problems: – not canonical– cannot scale with design size– require manual intervention


TEDs for Behavioral Synthesis

• Given an algorithm, derive several implementations using common (canonical) structure of TED

F1 = AB + AC

+

AB C

F2 = A (B + C)

+

A B CA

B

C

0 1

F = AB + ACHLD


Alternative Architecture

F = A*(B+C)F = A*(B+C)

AreaAreaAreaArea

Specification

Data flow graph+

x

Cycle 1

Cycle 2

+

x

C

A

B


Current and Future Work• Current work

– Interface with GAUT (architectural synthesis system)• Behavioral VHDL front-end

– TEDs automatically generated from behavioral descriptions– TED ordering (static, dynamic)

• Future work– Fully integrate with GAUT system

• Derive TED from behavioral input• Decompose TED guided by some objective:

– generate best DFG for given objective (patent pending)

• Interface with SystemC (Univ. Bremen?)

• Open problems– Satisfiability, functional test generation– Finite precision arithmetic

Documents

Maciej Ciesielski Electrical & Computer Engineering University of Massachusetts, Amherst, USA