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MACD HOMEWORK 3

Figure1. The schematic of the circuit that is analyzed

During the analysis below, simulations will be done using LEVEL 1 MOSFET PSpice

parameters. Also, for NMOS KP=135u, VTO=0.7, LAMBDA=0.05 and for PMOS KP=40u,

VTO=-0.8V, LAMBDA=0.1. Transistor sizes found in the hand calculations are also used.

Applying the values determined in the solution of the circuit, first step is to analyze the

DC bias points. Using a sine wave input with a frequency of 10khz (which is sensed to be a

proper value for medium frequency for the circuit) following values determined:

VD1=1.502V, ID1=21.38uA, ID2=20.47uA. Also PDC=185.5uW. Schematics related to

these results can be seen in Figure2, 3 and 4.

Figure2. Bias voltages of the circuit

852.0mV

VIN

M3

MbreakP

0V

I120uAdc

VB

V1

FREQ = 10kVAMPL = 1mVOFF = 0.852

0V

1.502V

VB

M6

MbreakN

VIN

3.000V

567.0mV

0V

567.0mVVB

0.567Vdc

852.0mV

0V

0

M4

MbreakN

0V

1.384V

0

M5

Mbreakp

0

894.5mV

VDD

3Vdc

0V

0

0

2.009V

M2

MbreakP

0

VDD

3.000VVDD

M1

Mbreakn

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Figure3. Bias currents of the circuit

Figure4. Power consumptions of the circuit

Overdrive voltages (which is defined as VGS-VT) of M5 and M6 can easily be

determined from Figure2. VodM5=(3-2.009)-|0.8|=0.191V and VodM6=894.5mV-

0.7V=0.1945V.

When it comes to the calculation of small signal voltage gain, it is determined using a

1mV amplitude sinusoidal input. Frequency is chosen 1khz. Thus, it is long enough to run the

simulation 5 periods which is equal to 5ms. The output is depicted in the Figure5.

VI

M

M

P

A

.

A

-

.

A

.

A

I

A

.

AVB

V

E

=

VAMP

=

mV

!

=

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A

VB

M"

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-

.

A

A

.

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-#

.

f A

VI

VB

. " $

V

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M

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.

$

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A

.

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%

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M

A

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-

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.

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%

V & &

V

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%

%

M

M

P

A

.

$

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-

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.

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%

V& &

V& &

M

M

'

-

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A

A

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A

VI

M

M

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W

I

A

.

W

VB

V

E

=

VAMP = mV

!

=

.

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VB

M"

M

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W

VI

VB

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W

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Figure5. Output voltage for 10khz, 2mVpp input

In order for us to calculate the small signal voltage gain, we must use the max and min

values signed in the graph. The peak to peak value of output is 1.4799-1.1087=0.3712V.

Since the input is 2mVpp, the gain is determined as Av=185.6.

The next step is the determination of the maximum output voltage swings. As in

Figure6 and 7, proper sinus waves are expected at maximum 1.3968V and at minimum

0.245V.

Figure6. The output just before the top limit above

Figure7. The output just before the bottom limit

T i me

0 s 0 . 5ms 1 . 0ms 1 . 5ms 2 . 0ms 2 . 5ms 3 . 0ms 3 . 5ms 4 . 0ms 4 . 5ms 5 . 0ms

V(VOUT)

1 . 1 V

1 . 2 V

1 . 3 V

1 . 4 V

1 . 5 V

( 7 4 3 . 4 7 8 u , 1 . 4 7 9 9)

( 1 . 2 4 7 8m, 1 . 1 0 6 7 )

T i me

0 s 0 . 5ms 1 . 0ms 1 . 5ms 2 . 0ms 2 . 5ms 3 . 0ms 3 . 5ms 4 . 0ms 4 . 5ms 5 . 0ms

V(VOUT)

1 . 3 6 V

1 . 3 7 V

1 . 3 8 V

1 . 3 9 V

1 . 4 0 V( 7 4 5 . 6 1 4 u , 1 . 3 9 5 6)

( 1 . 2 5 0 0m, 1 . 3 6 7 4)

T i me

0 s 0 . 5ms 1 . 0ms 1 . 5ms 2 . 0ms 2 . 5ms 3 . 0ms 3 . 5ms 4 . 0ms 4 . 5ms 5 . 0ms

V(VOUT)

0V

0 . 5 V

1 . 0 V

1 . 5 V

2 . 0 V

( 2 4 7 . 8 2 6 u , 2 4 8 . 5 6 1 m)

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DISCUSSION

Examining the values we get from the simulation and comparing them with hand

calculations, we can see that the small signal gain is not 250 at all. Pspice gives a 185.6 gain

which is a quite different value. The first thing that comes to our mind is to check the input

DC level which is calculated as 0.852V. One can say that this biasing level fails to supply

such a gain. In further analyses, weve changed this value by 2mV only (0.854V) and see an

approximate gain of 270. This result shows that the input DC level is not adequate for such

gain. If we check all transistors to make sure that they are in saturation (Figure1), we see that

they are actually in the saturation and the lack of this gain is not about any of them entering

into the triode region. Another subject is the power consumption. The circuit consumes 5mW

more power according to PSpice, this means more current is driven. According to the

simulation results ID1 is not actually equal to ID2. This raises the question of the ideality of the

current mirror. The mismatch in the currents also makes VD1 vary from 1.5V exactly by 2mV.

The output voltage swing boundaries seem to be close enough to be considered equal in both

cases. Overdrive voltages are also in this manner. To sum up, the simulation and the hand

calculations match except for small signal gain. This is caused by the minor lack of DC input

level which is dictated in the solution beforehand. Finally, Id like to explain why I did not

simulate the circuit in AC Sweep Analysis in order to obtain the frequency response of the

structure. Since there is no capacitance information given in the model (parasitic capacitances

like CGD) and no other series capacitances at the input and the output of the circuit we dontexpect any poles. This means there are no such points on which gain falls 3db. This will cause

the frequency-gain graph look as if an infinite bandwidth amplifier with maximum and equal

gain at every frequency value. This wouldnt make any sense at all.