of 86 /86
ANGLES 3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ. 2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. 1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. DATE APPD ENG DATE APPD CK ECN ZONE REV DO NOT SCALE DRAWING X.XXX X.XX XX DIMENSIONS ARE IN MILLIMETERS THIRD ANGLE PROJECTION D SIZE APPLICABLE NOTED AS MATERIAL/FINISH NONE SCALE DESIGNER MFG APPD DESIGN CK RELEASE QA APPD ENG APPD DRAFTER METRIC OF SHT DRAWING NUMBER TITLE NOTICE OF PROPRIETARY PROPERTY I TO MAINTAIN THE DOCUMENT IN CONFIDENCE III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART II NOT TO REPRODUCE OR COPY IT AGREES TO THE FOLLOWING PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY Apple Computer Inc. 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 B C D A B C D A REV. DESCRIPTION OF CHANGE DESCRIPTION REFERENCE DES BOM OPTION QTY PART NUMBER CRITICAL DRAWING (6.0.0) DVT 3/3/2006 Schematic / PCB #’s M9 MLB Sully ALIASES RESOLVED FireWire Port Power 45 (M1_MLB) 43 (11/03/2005) FW PHY Power Supply 44 (MASTER) 42 (MASTER) Yukon Power Control 43 M1_MLB 41 02/10/2006 Ethernet Connector 42 M1_MLB 40 02/10/2006 ETHERNET CONTROLLER 41 M1_MLB 39 02/10/2006 FireWire PHY (TSB83AA22) 40 (MASTER) 38 (MASTER) FireWire Link (TSB83AA22) 39 (MASTER) 37 (MASTER) PATA Connector 38 M1_MLB 36 02/10/2006 Mobile Clocking 37 M1_MLB 35 02/10/2006 Clock Termination 34 M1_MLB 34 02/10/2006 CLOCKS 33 M1_MLB 33 02/10/2006 DDR2 VRef 32 M1_MLB 32 12/19/2005 Memory Vtt Supply 31 M1_MLB 31 02/10/2006 Memory Active Termination 30 (M1_MLB) 30 (11/07/2006) DDR2 SO-DIMM Connector B 29 M1_MLB 29 02/10/2006 DDR2 SO-DIMM Connector A 28 M1_MLB 28 02/10/2006 M1 SMBus Connections 27 M1_MLB 27 01/04/2006 SB Misc 26 M1_MLB 26 02/10/2006 SB Decoupling 25 M1_MLB 25 02/10/2006 SB: 4 OF 4 24 M1_MLB 24 02/10/2006 SB: 3 OF 4 23 M1_MLB 23 02/10/2006 SB: 2 of 4 22 M1_MLB 22 02/10/2006 SB: 1 OF 4 21 M1_MLB 21 02/10/2006 NB Config Straps 20 M1_MLB 20 02/10/2006 NB (GM) Decoupling 19 M1_MLB 19 02/08/2006 NB Grounds 18 M1_MLB 18 02/10/2006 NB Power 2 17 M1_MLB 17 02/10/2006 NB Power 1 16 M1_MLB 16 02/10/2006 NB DDR2 Interfaces 15 M1_MLB 15 02/10/2006 NB Misc Interfaces 14 M1_MLB 14 02/10/2006 NB PEG / Video Interfaces 13 M1_MLB 13 02/10/2006 NB CPU Interface 12 M1_MLB 12 02/10/2006 CPU ITP700FLEX DEBUG 11 M1_MLB 11 02/10/2006 CPU MISC1-TEMP SENSOR 10 M1_MLB 10 02/10/2006 CPU Decoupling & VID 9 M1_MLB 9 02/08/2006 CPU 2 OF 2-PWR/GND 8 M1_MLB 8 02/10/2006 CPU 1 OF 2-FSB 7 M1_MLB 7 02/10/2006 Signal Aliases 6 (M1_MLB) 6 (11/11/2005) Functional / ICT Test 5 (MASTER) 5 (MASTER) BOM Configuration 4 (MASTER) 4 (MASTER) Power Block Diagram 3 (MASTER) 3 (MASTER) System Block Diagram 2 (MASTER) 2 (MASTER) 86 104 M1_MLB 02/10/2006 M1 Net Properties 85 103 M1_MLB 02/10/2006 M1 Spacing & Physical Constraints 84 102 M1_MLB 02/10/2006 More System Constraints 83 101 M1_MLB 02/10/2006 Napa Platform Constraints 82 100 (MASTER) (MASTER) Revision History 81 99 M1_MLB 12/19/2005 LVDS Interface Pull-downs 80 98 (MASTER) (MASTER) M9 Specific Connectors 79 97 M1_MLB 11/18/2005 External Display Connector 78 94 M1_MLB 01/09/2006 Internal Display Connectors 77 93 M1_MLB 02/10/2006 ATI M56 Video Interfaces 76 91 M1_MLB 02/10/2006 ATI M56 GPIO/DVO/Misc 75 90 M1_MLB 02/10/2006 GDDR3 Frame Buffer B 74 89 M1_MLB 02/10/2006 GDDR3 Frame Buffer A 73 88 M1_MLB 02/10/2006 GPU Straps 72 87 M1_MLB 02/10/2006 ATI M56 Frame Buffer I/F 71 86 M1_MLB 02/10/2006 ATI M56 Core Power 70 85 M1_MLB 02/10/2006 GPU (M56) Core Supplies 69 84 M1_MLB 02/10/2006 ATI M56 PCI-E 68 83 M1_LIO 12/19/2005 PBus Supply & Batt. Charger 67 82 (MASTER) (MASTER) DC-In & Battery Connectors 66 81 M1_MLB 12/19/2005 Power Aliases 65 80 M1_MLB 02/10/2006 3.3V G3Hot Supply & Power Control 64 79 M1_MLB 02/10/2006 3.3V / 1.05V Power Supplies 63 78 M1_MLB 02/10/2006 1.8V Supply 62 77 M1_MLB 02/10/2006 2.5V & 1.2V Regulators 61 76 M1_MLB 02/10/2006 5V / 1.5V Power Supply 60 75 M1_MLB 02/08/2006 IMVP6 CPU VCore Regulator 59 67 M1_MLB 02/10/2006 TPM 58 66 M1_MLB 02/10/2006 Sudden Motion Sensor (SMS) 57 65 M1_MLB 02/10/2006 Fan Connectors 56 64 M1_MLB 02/10/2006 ALS Support 55 63 M1_MLB 02/10/2006 SPI BOOTROM 54 62 M1_MLB 01/05/2006 Current & Voltage Sensing 53 61 M1_MLB 02/10/2006 Thermal Sensors 52 60 M1_MLB 02/10/2006 LPC+ Debug Connector 51 59 M1_MLB 02/10/2006 SMC Support 50 58 M1_MLB 02/10/2006 SMC 49 57 M1_MLB 02/10/2006 PCI-E Connections 48 56 (MASTER) (MASTER) Current & Thermal Sensors 47 55 (MASTER) (MASTER) Left I/O Board Connector 46 52 M1_MLB 02/10/2006 External USB Connector 45 49 M1_MLB 02/10/2006 Internal USB Connections Page Contents (.csa) Date Sync Table of Contents 1 N/A 1 N/A Contents Date (.csa) Sync Page 44 46 (MASTER) (MASTER) FireWire Ports TITLE=SULLY ABBREV=DRAWING LAST_MODIFIED=Fri Mar 3 17:59:45 2006 PCBF,SULLY,FINAL,M9 820-2023 CRITICAL PCB 1 CRITICAL SCH 1 051-7023 SCHEM,SULLY,M9 ? ? ? ? ? 86 1 051-7023 SCHEM,SULLY,M9 06

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8

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3REV

2ZONE ECN DESCRIPTION OF CHANGE

1CK APPD ENG APPD DATE DATE

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. 2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. 3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

SullyM9 MLB 3/3/2006 SyncN/A Date

DVT(6.0.0)

?

?

?

?

?

DTABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_ITEM

D

PageTABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

(.csa)

ContentsTable of Contents System Block Diagram Power Block Diagram BOM Configuration Functional / ICT Test Signal Aliases CPU 1 OF 2-FSB CPU 2 OF 2-PWR/GND CPU Decoupling & VID CPU MISC1-TEMP SENSOR CPU ITP700FLEX DEBUG NB CPU Interface NB PEG / Video Interfaces NB Misc Interfaces NB DDR2 Interfaces NB Power 1 NB Power 2 NB Grounds NB (GM) Decoupling NB Config Straps SB: 1 OF 4 SB: 2 of 4 SB: 3 OF 4 SB: 4 OF 4 SB Decoupling SB Misc M1 SMBus Connections DDR2 SO-DIMM Connector A DDR2 SO-DIMM Connector B Memory Active Termination Memory Vtt Supply DDR2 VRef CLOCKS Clock Termination Mobile Clocking PATA Connector FireWire Link (TSB83AA22) FireWire PHY (TSB83AA22) ETHERNET CONTROLLER Ethernet Connector Yukon Power Control FW PHY Power Supply FireWire Port Power

PageTABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

(.csa)

ContentsFireWire Ports Internal USB Connections External USB Connector Left I/O Board Connector Current & Thermal Sensors PCI-E Connections SMC SMC Support LPC+ Debug Connector Thermal Sensors Current & Voltage Sensing SPI BOOTROM ALS Support Fan Connectors Sudden Motion Sensor (SMS) TPM IMVP6 CPU VCore Regulator 5V / 1.5V Power Supply 2.5V & 1.2V Regulators 1.8V Supply 3.3V / 1.05V Power Supplies 3.3V G3Hot Supply & Power Control Power Aliases DC-In & Battery Connectors PBus Supply & Batt. Charger ATI M56 PCI-E GPU (M56) Core Supplies ATI M56 Core Power ATI M56 Frame Buffer I/F GPU Straps GDDR3 Frame Buffer A GDDR3 Frame Buffer B ATI M56 GPIO/DVO/Misc ATI M56 Video Interfaces Internal Display Connectors External Display Connector M9 Specific Connectors LVDS Interface Pull-downs Revision History Napa Platform Constraints More System Constraints M1 Spacing & Physical Constraints M1 Net Properties

Sync(MASTER)

Date

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

C

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

B

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

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TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 37 38 39 40 41 42 43 44 45

N/A(MASTER)

(MASTER)(MASTER)

(MASTER)(MASTER)

(MASTER)(MASTER)

(MASTER)(11/11/2005)TABLE_TABLEOFCONTENTS_ITEM

(M1_MLB)02/10/2006TABLE_TABLEOFCONTENTS_ITEM

M1_MLB02/10/2006TABLE_TABLEOFCONTENTS_ITEM

M1_MLB02/08/2006TABLE_TABLEOFCONTENTS_ITEM

M1_MLB02/10/2006TABLE_TABLEOFCONTENTS_ITEM

M1_MLB02/10/2006TABLE_TABLEOFCONTENTS_ITEM

M1_MLB02/10/2006TABLE_TABLEOFCONTENTS_ITEM

M1_MLB02/10/2006TABLE_TABLEOFCONTENTS_ITEM

M1_MLB02/10/2006TABLE_TABLEOFCONTENTS_ITEM

M1_MLB02/10/2006TABLE_TABLEOFCONTENTS_ITEM

M1_MLB02/10/2006TABLE_TABLEOFCONTENTS_ITEM

M1_MLB02/10/2006TABLE_TABLEOFCONTENTS_ITEM

M1_MLB02/10/2006TABLE_TABLEOFCONTENTS_ITEM

M1_MLB02/08/2006TABLE_TABLEOFCONTENTS_ITEM

M1_MLB02/10/2006TABLE_TABLEOFCONTENTS_ITEM

M1_MLB02/10/2006TABLE_TABLEOFCONTENTS_ITEM

M1_MLB02/10/2006TABLE_TABLEOFCONTENTS_ITEM

M1_MLB02/10/2006TABLE_TABLEOFCONTENTS_ITEM

M1_MLB02/10/2006TABLE_TABLEOFCONTENTS_ITEM

M1_MLB02/10/2006TABLE_TABLEOFCONTENTS_ITEM

M1_MLB02/10/2006TABLE_TABLEOFCONTENTS_ITEM

M1_MLB01/04/2006TABLE_TABLEOFCONTENTS_ITEM

M1_MLB02/10/2006TABLE_TABLEOFCONTENTS_ITEM

M1_MLB02/10/2006TABLE_TABLEOFCONTENTS_ITEM

M1_MLB(11/07/2006)TABLE_TABLEOFCONTENTS_ITEM

(M1_MLB)02/10/2006TABLE_TABLEOFCONTENTS_ITEM

M1_MLB12/19/2005TABLE_TABLEOFCONTENTS_ITEM

M1_MLB02/10/2006TABLE_TABLEOFCONTENTS_ITEM

M1_MLB02/10/2006TABLE_TABLEOFCONTENTS_ITEM

M1_MLB02/10/2006TABLE_TABLEOFCONTENTS_ITEM

M1_MLB02/10/2006TABLE_TABLEOFCONTENTS_ITEM

M1_MLB(MASTER)TABLE_TABLEOFCONTENTS_ITEM

(MASTER)(MASTER)TABLE_TABLEOFCONTENTS_ITEM

(MASTER)02/10/2006TABLE_TABLEOFCONTENTS_ITEM

M1_MLB02/10/2006TABLE_TABLEOFCONTENTS_ITEM

M1_MLB02/10/2006TABLE_TABLEOFCONTENTS_ITEM

M1_MLB(MASTER)TABLE_TABLEOFCONTENTS_ITEM

(MASTER)(11/03/2005)TABLE_TABLEOFCONTENTS_ITEM

(M1_MLB)TABLE_TABLEOFCONTENTS_ITEM

44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86

46 49 52 55 56 57 58 59 60 61 62 63 64 65 66 67 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 93 94 97 98 99 100 101 102 103 104

(MASTER)02/10/2006

M1_MLB02/10/2006

M1_MLB(MASTER)

(MASTER)(MASTER)

(MASTER)02/10/2006

M1_MLB02/10/2006

M1_MLB02/10/2006

M1_MLB02/10/2006

M1_MLB02/10/2006

M1_MLB01/05/2006

M1_MLB02/10/2006

M1_MLB02/10/2006

M1_MLB02/10/2006

M1_MLB02/10/2006

M1_MLB02/10/2006

M1_MLB02/08/2006

C

M1_MLB02/10/2006

M1_MLB02/10/2006

M1_MLB02/10/2006

M1_MLB02/10/2006

M1_MLB02/10/2006

M1_MLB12/19/2005

M1_MLB(MASTER)

(MASTER)12/19/2005

M1_LIO02/10/2006

M1_MLB02/10/2006

M1_MLB02/10/2006

M1_MLB02/10/2006

M1_MLB02/10/2006

M1_MLB02/10/2006

M1_MLB02/10/2006

M1_MLB02/10/2006

M1_MLB02/10/2006

M1_MLB01/09/2006

B

M1_MLB11/18/2005

M1_MLB(MASTER)

(MASTER)12/19/2005

M1_MLB(MASTER)

(MASTER)02/10/2006

M1_MLB02/10/2006

M1_MLB02/10/2006

M1_MLB02/10/2006

M1_MLB

TABLE_TABLEOFCONTENTS_ITEM

ALIASES RESOLVEDA

DIMENSIONS ARE IN MILLIMETERS

XX

METRICDRAFTER DESIGN CK

Apple Computer Inc.NOTICE OF PROPRIETARY PROPERTYTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

X.XX

A

X.XXX ENG APPD MFG APPD

Schematic / PCB #sPART NUMBER051-7023 820-2023DRAWING

ANGLES

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART QA APPD DO NOT SCALE DRAWING DESIGNER TITLE

QTY1 1

DESCRIPTIONSCHEM,SULLY,M9 PCBF,SULLY,FINAL,M9

REFERENCE DESSCH PCB

CRITICALCRITICAL CRITICAL

BOM OPTION

RELEASE

SCALE NONE SIZE

SCHEM,SULLY,M9DRAWING NUMBER

TITLE=SULLYABBREV=DRAWINGLAST_MODIFIED=Fri Mar 3 17:59:45 2006 THIRD ANGLE PROJECTION

MATERIAL/FINISH NOTED AS APPLICABLE

D

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6GDDR3 Frame Buffer 128MB/256MB P.74-75 CPU THERMAL SENSOR P.10

5

4

3ITP700FLEX CPU Debug Connector P.11

2

1

Core Duo (Yonah)479 BGA P.7-9

INVERTER CONNECTOR

D

P.78LCD Panel

DJ2800

PWM Dual-Channel LVDS S-Video/Composite Dual-Channel TMDS

P.78,81DVI-I/DL Connector w/TV-Out Support

ATI M56P GPUP.69-73,76-77

FSB PCIe x16 CH.A

DDR2 SO-DIMM ALower Connector

P.28J2900

P.79

945GM NB1466UFCBGAP.12-20

CH.B

DDR2 SO-DIMM BUpper Connector

DDR2 VTT& REGULATOR

RJ45 (Ethernet) Connector

ENET

Yukon Gig-E Controller

Yukon Power

P.29

DDR2 VREFBUFFER

P.30-31

P.401394a/b (FireWire)

P.39

P.41

FWPort Power

DMI x4TSB83AA22 FireWire

P.32

C

Connectors

Controller

P.44

P.37-38PHY Power

P.43Right USB 2.0 Connector

PCIe x1 PCI

C

ICH7-MPCIe x1 PCIe x1Left I/O & Audio Board Connector P.47

USB

P.42

P.46 HDD/BT/IR Connectors P.80 Camera Connector P.45

SATA USB x2

SB

USB x2 USB Azalia (HD-Audio)

USB

609 BGAP.21-26

BGeyser KB / TP Connector P.45 ODD Connector P.36CK410 Clock Controller

USB SMBusBatt Chgr/ PBUS Supply P.68 LPC 33MHZ BootROM P.55SB SMBus

B

PATA

66MHZ 16BITS

SPI

TPMH8S/2116P.59

LPC Debug Connector

Power Supplies P.60-67,70

P.33-34

P.27SMC SMBus

P.52RT ALS

A

Temperature Sensors

SMBus x5

SMCPWM/TachP.50-51

System Block DiagramSYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)NOTICE OF PROPRIETARY PROPERTY

P.56SMS

A

P.48,53Battery SMBus Connector

P.27Fan Connectors

P.58 P.57Analog Sensors

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER REV.

P.82

P.54

APPLE COMPUTER INC.

DSCALE NONE

051-7023SHT OF

06 86

2

8

7

6

5

4

3

2

1

8J5500 LIO Flex Connector PPDCIN_G3H 18.5V - 9V

7U8000 ENABLE 3.425 G3Hot (LT3470)

6

5

4Q7610

3

2

1

PP3V42_G3H 3.425V 5V 1.5V SMC_PM_G2_ENABLE PM_SLP_S3_L U7600 PP5V_S5 5.0V PP1V5_S0 1.5V

PP5V_S3 5.0V

D

DPM_SLP_S4_LS5V Q7615 PP5V_S0 5.0V

ENABLES J8200 LIO Power Connector PPBUS_G3H_B 12.6V - 9V PPBUS_G3H_A 12.6V - 9V 5V/1.5V S5/S0 (LTC3728) PGOOD NC SMC_PM_G2_ENABLE U7900 ENABLE 3.3V S5 (ISL6269) PPVCORE_S0_CPU ?V PGOOD RSMRST_PWRGD PM_SLP_S3_L U7950 ENABLE PGOOD 1.05V S0 (ISL6269) PGOOD IMVP_PWRGD_IN/ALL_SYS_PWRGD PM_SLP_S3_L U8500 ENABLE GPU VCore S0 (ISL6269) PGOOD PM_SLP_S3_L U3100 NC PM_SLP_S3_LS5V Q7845 0.9V (Vtt) S0 (BD3533FVM) PP0V9_S0 0.9V PP1V8_S0 1.8V Q4565 PPBUS_S5_FWPORT 12.6V - 9V ENABLE PPVCORE_S0_GPU 1.2V - 1.0V PP1V05_S0 1.05V NC U7750 ENABLE Q7770 1.2V S3 (LTC3412) PGOOD NC PGOOD NC Q7947 PP3V3_S0 3.3V PM_SLP_S3_LS5V_L PP1V2_S3 1.2V PP1V2_S0 1.2V PM_SLP_S3_LS5V_L ENABLE Q7720 2.5V S3 (LTC3411) PP2V5_S3 2.5V PP2V5_S0 2.5V PP3V3_S5 3.3V PM_SLP_S4_LS5V U7700 Q7945 PP3V3_S3 3.3V

PM_SLP_S3_LS5V

IMVP_VR_ON IMVP_PWRGD_IN

CENABLES

U7530 CPU VCore S0 (ISL6262) "IMVP6" PGOOD

C

VR_PWRGOOD_DELAY J5500 Inverter Connector PM_SLP_S4_L

BENABLE

U7800 1.8V S3 (ISL6269)

B

PP1V8_S3 1.8V

Power Block DiagramSYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)NOTICE OF PROPRIETARY PROPERTYTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER REV.

A

A

PM_SLP_S3_LS5V_L

APPLE COMPUTER INC.

DSCALE NONE

051-7023SHT

06 86

FWPWR_EN

3

OF

8

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5

4

3

2

1

8BOM NUMBER 630-7404 630-7406 BOM NAME PCBA,SULLY,2.0GHz,M9 PCBA,SULLY,2.16GHz,M9

7

6TABLE_BOMGROUP_HEAD

5TABLE_BOMGROUP_ITEM

4QTY1 1 1 1 1 1 1 1 1 1

3REFERENCE DESU4101 U5800 U5800 U5800 U4102 U6301 U6301 U6301 U7530 U3301

2BOM OPTION

1

BOM OPTIONS VRAM_256SAM,M9_COMMON,CPU_2_0GHZ,EEE_UNZTABLE_BOMGROUP_ITEM

PART NUMBER338S0270 338S0274 341S1876 341S1876 341S1797TABLE_BOMGROUP_HEAD

DESCRIPTIONIC,88E8053,GIGABIT ENET XCVR,64P QFN, NO

CRITICALCRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL

VRAM_256SAM,M9_COMMON,CPU_2_16GHZ,EEE_UP1

IC,SMC,HS8/2116 IC,SMC,PRGRM,M9 IC,SMC,PRGRM,M9 IC,EEPROM,SERIAL IIC,8KBIT,SO8IC,16MBIT 8-PIN SPI SERIAL FLASH,SOIC8 IC,EFI,BOOTROM DEVELOPMENT,M9 IC,EFI,BOOTROM FINAL,M9 IC,CPU VOLTAGE REGULATOR,IMVP,TWO PHASE

SMC_BLANK SMC_DEVEL SMC_FINAL

BOM GROUP

BOM OPTIONSTABLE_BOMGROUP_ITEM

335S0384 341S1828TABLE_BOMGROUP_ITEM

BOOTROM_BLANK BOOTROM_DEVEL BOOTROM_FINAL

D

VRAM_128SAM VRAM_256SAM VRAM_128HY VRAM_256HY BOM GROUP M9_COMMON M9_COMMON1 M9_COMMON2 M9_COMMON3 M9_COMMON4 M9_DEBUG

VRAM_128_SAMSUNG GPU_MEM_256M,VRAM_256_SAMSUNGTABLE_BOMGROUP_ITEM

D

341S1829 353S1235TABLE_BOMGROUP_ITEM

GPU_MEM_HYNIX,VRAM_128_HYNIX GPU_MEM_HYNIX,GPU_MEM_256M,VRAM_256_HYNIXTABLE_BOMGROUP_HEAD

359S0101

IC,CY28445-5,CLOCK GEN,68PIN QFN

BOM OPTIONSTABLE_BOMGROUP_ITEM

ALTERNATE,COMMON,M9_COMMON1,M9_COMMON2,M9_COMMON3,M9_COMMON4,M9_DEBUGTABLE_BOMGROUP_ITEM

PART NUMBER341S1789TABLE_BOMGROUP_ITEM

QTY1

DESCRIPTIONIC, TPM, 28-PIN TSSOP

REFERENCE DESU6700

CRITICALCRITICAL

BOM OPTION

ENET_LOM_DISABLE,ENETPWR_S3AC,GPUTHM_A_GPU,GPU_BB_CTL,HSTHMSNS_HAS,INVERTER_BUF,ONEWIRE_PU KBDLED_HAS,MEMVREF_S3,MEMVTT_EN_PU,RTUSB_ESD,USB_C_OC_PU,USB_D_OC_PU,USB_E_OC_PUTABLE_BOMGROUP_ITEM

LVDS_PD,M56_REV_B24_LP,FW_B_BILINGUAL,FW_A_DS_ONLY,FW_PORT_FAULT_PU,FW_PLTRST_UNGATEDTABLE_BOMGROUP_ITEM

LIO_TEMP,BOOTROM_DEVEL,SMC_DEVELTABLE_BOMGROUP_ITEM

PART NUMBER337S3282 337S3267 337S3268 338S0269 343S0385

QTY1 1 1 1 1

DESCRIPTIONIC,CPU,479 BGA IC,CPU,479 BGA IC,CPU,479 BGA IC,945GM,SOUTHBRIDGE IC,SB,652BGA

REFERENCE DESU0700 U0700 U0700 U1200 U2100

CRITICALCRITICAL CRITICAL CRITICAL CRITICAL CRITICAL

BOM OPTIONCPU_1_83GHZ CPU_2_0GHZ CPU_2_16GHZ

ITP,ITPCONN,LPCPLUS

C

C

Bar Code Labels / EEE #sPART NUMBER826-4393 826-4393 826-4393 826-4393 826-4393

QTY1 1 1 1 1

DESCRIPTIONLBL,P/N LABEL,PCB,28MM X 6 MM LBL,P/N LABEL,PCB,28MM X 6 MM LBL,P/N LABEL,PCB,28MM X 6 MM LBL,P/N LABEL,PCB,28MM X 6 MM LBL,P/N LABEL,PCB,28MM X 6 MM

REFERENCE DES[EEE:UNZ] [EEE:UP0] [EEE:UP1] [EEE:UP2] [EEE:UYU]

CRITICALCRITICAL CRITICAL CRITICAL CRITICAL CRITICAL

BOM OPTIONEEE_UNZ EEE_UP0 EEE_UP1 EEE_UP2 EEE_UYU64 63 61 60 54 47 43 41 5 4 78 70 68 66

M9 Specific AliasesPPBUS_G3H PPDCIN_G3H PPBUS_G3H PPDCIN_G3H PPDCIN_G3H50 37 4 4 5 41 43 47 54 60 61 63 64 66 68 70 78 4 65 66 67 68 68 67 66 65 4

Module PartsPART NUMBER338S0266 338S0302 338S0309 338S0315 338S0316 333S0354

QTY1 1 1 1 1 4 4 4 4

DESCRIPTIONIC,ATI,M56P,GRPHSCTRL,880BGA,LF IC,ATI,M56P,GRPHSCTRL,880BGA,LF IC,ATI,M56P,GRPHSCTRL,880BGA,LF IC,ATI,M56P,GRPHSCTRL,880BGA,LF IC,ATI,M56P,GRPHSCTRL,880BGA,LF IC,SGRAM,GDDR3,8MX32,700MHZ,136 FBGA IC,SGRAM,GDDR3,16MX32,700MHZ,136 FBGA IC,SGRAM,GDDR3,8MX32,700MHZ,136 FBGA IC,SGRAM,GDDR3,16MX32,700MHZ,136 FBGA

REFERENCE DESU8400 U8400 U8400 U8400 U8400 U8900,U8950,U9000,U9050 U8900,U8950,U9000,U9050 U8900,U8950,U9000,U9050 U8900,U8950,U9000,U9050

CRITICALCRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL

BOM OPTIONM56_REV_B24_LL M56_REV_B24_HL M56_REV_B24_LP M56_REV_B26_LP M56_REV_B26_P VRAM_128_SAMSUNG VRAM_256_SAMSUNG

4 65 66 67 68

SMC_RSTGATE_LMAKE_BASE=TRUE

SMC_RSTGATE_L PPFW_PORTA_VP_UF PPFW_PORTB_VP_UF PP3V3_S0 PP3V3_S0 PP3V3_S0

4 37 50

44 43 4

PPFW_PORTA_VP_UFMAKE_BASE=TRUE

4 43 44

44 43 4

PPFW_PORTB_VP_UFMAKE_BASE=TRUE

4 43 44

B

333S0350 333S0358 333S0351PART NUMBER

64 60 59 57 56 53 51 48 43 23 22 21 20 19 17 14 10 5 4 37 36 34 33 29 28 27 26 25 24 79 78 70 66 65

PP3V3_S0

VRAM_128_HYNIX VRAM_256_HYNIX50 48 27 10 4

48 51 53 56 57 59 60 64 65 66 4 5 10 14 17 19 20 21 22 23 24 25 26 27 28 29 33 34 36 37 43 70 78 79 48 51 53 56 57 59 60 64 65 66 4 5 10 14 17 19 20 21 22 23 24 25 26 27 28 29 33 34 36 37 43 70 78 79 48 51 53 56 57 59 60 64 65 66 4 5 10 14 17 19 20 21 22 23 24 25 26 27 28 29 33 34 36 37 43 70 78 79 4 10 27 48 50

B

SMBUS_SMC_B_S0_SCL SMBUS_SMC_B_S0_SDA PCI_ADMAKE_BASE=TRUE

SMBUS_SMC_B_S0_SCL SMBUS_SMC_B_S0_SDA =FW_PCI_IDSEL PP5V_S0

IS ALTERNATE FOR PART NUMBER 338S0266 338S0309 338S0309 376S0445 128S0073 128S0092 128S0094 128S0094 128S0061

TABLE_ALT_HEAD

50 48 27 10 4

4 10 27 48 50

BOM OPTION

REF DES

COMMENTS:37 22TABLE_ALT_ITEM

37

338S0309 338S0266 338S0315 376S0448 128S0083 128S0093 128S0060 128S0095 128S0081

M56_REV_B24_LL U8400 M56_REV_B24_LP U8400 M56_REV_B24_LP U8400 ALL C2516 ALL ALL ALL ALL

LP is alt to LLTABLE_ALT_ITEM

56 54 52 47 42 36 31 25 5 4 80 79 78 70 67 66 65 61 60 57

PP5V_S0

4 5 25 31 36 42 47 52 54 56 57 60 61 65 66 67 70 78 79 80

LL is alt to LPTABLE_ALT_ITEM

B26_LP is alt to B24_LPTABLE_ALT_ITEM

66 43 42 38 4

PPBUS_S5_FW_FET

PPBUS_S5_FW_FET PPBUS_S5_FW_FET PPBUS_S5_FW_FET

4 38 42 43 66

Vishay 2nd sourceTABLE_ALT_ITEM

4 38 42 43 66

1.86 max alt to 1.9 maxTABLE_ALT_ITEM

4 38 42 43 66

Kemet is alt to SanyoTABLE_ALT_ITEM

44 43 42 38 5 4

PP3V3_FWPHY

44 43 42 38 5 4

PP3V3_FWPHYVOLTAGE=3.3V MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm MAKE_BASE=TRUE

PP3V3_FWPHY PP3V3_FWPHY PP3V3_FWPHY PP3V3_FWPHY PP3V3_FWPHY

4 5 38 42 43 44

Sanyo is alt to PanasonicTABLE_ALT_ITEM

4 5 38 42 43 44

330uF,2V,6MOHM,D2TABLE_ALT_ITEM

4 5 38 42 43 44

C2 package is alt to C34 5 38 42 43 44

4 5 38 42 43 44

42 38 5 4

PP1V95_FWPHY

42 38 5 4

PP1V95_FWPHYVOLTAGE=1.95V MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm MAKE_BASE=TRUE

PP1V95_FWPHY PP1V95_FWPHY PP1V8_S3 LT2USB_OC_L

4 5 38 42

BOM ConfigurationSYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)NOTICE OF PROPRIETARY PROPERTY

A37 32 31 29 28 19 16 14 5 4 66 63 54 47 22 5 4

4 5 38 42

A

PP1V8_S3 LT2USB_OC_L

4 5 14 16 19 28 29 31 32 37 54 63 66

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING4 5 22 47

MAKE_BASE=TRUE

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

37 22 4

PCI_GNT3_L PCI_REQ3_L

MAKE_BASE=TRUE MAKE_BASE=TRUE

PCI_GNT3_L PCI_REQ3_L

SIZE4 22 37

DRAWING NUMBER

REV.

37 26 22 4

4 22 26 37

APPLE COMPUTER INC.

DSCALE NONE

051-7023SHT

06 86

4

OF

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

Functional Test PointsPower Supply NO_TESTsNO_TEST TRUE TRUE TRUE EXPOSED_VIA IMVP6_RBIAS P5VS5_RUNSS P1V5S0_RUNSS P2V5S3_MODE P2V5S3_SHDNRT P1V2S3_RT P1V2S3_RUNSS P1V8S3_COMP P1V8S3_FSET P3V3S5_COMP P3V3S5_FSET P1V05S0_COMP P1V05S0_FSET P3V42G3H_FB GPUVCORE_COMP GPUVCORE_FSET GPUBBP_ADJ60

Power NetsFUNC_TESTI179 I17861 65

Fan ConnectorsFUNC_TEST30 31 65 66 5 7 8 9 11 12 13 16 17 19 21 24 25 34 54 64 66 62 65 66 69 76 5 39 62 66 5 8 9 13 16 17 19 24 25 47 65 66 63 65 66 4 5 14 16 19 28 29 31 32 37 54 63 66 17 19 62 65 66 76 77 39 62 66 5 70 78 79 48 51 53 56 57 59 60 64 65 66 4 5 10 14 17 19 20 21 22 23 24 25 26 27 28 29 33 34 36 37 43 27 32 37 41 45 51 56 58 59 62 63 64 66 80 11 22 23 24 25 26 55 62 64 65 66 78 78 79 80 4 5 25 31 36 42 47 52 54 56 57 60 61 65 66 67 70 5 45 51 61 66 80 5 25 46 51 61 63 64 65 66 67 70 4 5 41 43 47 54 60 61 63 64 66 68 70 78

Battery ConnectorFUNC_TEST66 67 70 78 79 80 4 5 25 31 36 42 47 I134 52 54 56 57 60 61 65

I18261 65

D

I183

TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE

62 62

I184 I185 I186

62

I18741 62

I18863 63

I189 I190 I191

64

I19264

I19364 64

I194 I195 I197

TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE

PP0V9_S0 PP1V05_S0 PP1V2_S0 PP1V2_S3 PP1V5_S0 PP1V8_S0 PP1V8_S3 PP2V5_S0 PP2V5_S3 PP3V3_S0 PP3V3_S3 PP3V3_S5 PP5V_S0 PP5V_S3 PP5V_S5 PPBUS_G3H GND

TRUE TRUE TRUE TRUE TRUE

PP5V_S0 FAN_LT_PWM FAN_LT_TACH FAN_RT_PWM FAN_RT_TACH

I13557 57

TRUE TRUE TRUE TRUE TRUE

BATT_POS BATT_NEG SMC_BS_ALRT_L SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA

67 68 67 68

50 51 67 27 50 67 27 50 67

D

57 57

LPC+ Debug ConnectorFUNC_TEST TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE PP3V42_G3H PP5V_S0 LPC_AD LPC_AD LPC_FRAME_L PM_CLKRUN_L BOOT_LPC_SPI_L SMC_TMS DEBUG_RST_L SMC_TRST_L SMC_TDO SMC_MD1 SMC_TX_L FWH_INIT_L PCI_CLK_PORT80_LPC LPC_AD LPC_AD INT_SERIRQ PM_SUS_STAT_L SMC_TDI SMC_TCK SMC_RST_L SMC_NMI SMC_RX_L SV_SET_UP

Left I/O Data ConnectorFUNC_TEST68 5 26 27 35 45 50 51 52 54 65 66 67 66 67 70 78 79 80 4 5 25 31 36 42 47 52 54 56 57 60 61 65 21 50 52 59 21 50 52 59 21 50 52 59 23 50 52 59

TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE

PP1V5_S0 PPBUS_G3H PP3V42_G3H PP5V_S0_AUDIO GND_AUDIO ALS_GAIN LTALS_OUT ACZ_SDATAIN ACZ_SDATAOUT ACZ_BITCLK ACZ_RST_L EXCARD_OC_L LTUSB_OC_L LT2USB_OC_L PM_SLP_S3_LS5V PM_SLP_S4_L SYS_ONEWIRE MINI_CLKREQ_L SMC_EXCARD_CP EXCARD_CLKREQ_L SMC_EXCARD_PWR_EN LIO_PLT_RESET_L ACZ_SYNC USB2_LT_N USB2_LT_P USB2_EXCARD_N USB2_EXCARD_P PCIE_EXCARD_R2D_C_N PCIE_EXCARD_R2D_C_P PCIE_EXCARD_D2R_N PCIE_EXCARD_D2R_P PCIE_CLK100M_EXCARD_P PCIE_CLK100M_EXCARD_N USB2_LT2_N USB2_LT2_P PCIE_MINI_R2D_C_N PCIE_MINI_R2D_C_P PCIE_MINI_D2R_N PCIE_MINI_D2R_P PCIE_CLK100M_MINI_P PCIE_CLK100M_MINI_N SMBUS_SB_SCL SMBUS_SB_SDA PCIE_WAKE_L SMC_BC_ACOK

25 47 65 66 5 8 9 13 16 17 19 24 68 70 78 4 5 41 43 47 54 60 61 63 64 66 5 26 27 35 45 50 51 52 54 65 66 67 68 47 47

65

Request for at least 10 GND TPs70 70

I16522 50 52

6 47 50 47 56 21 47 86 21 47 86 21 47 86 21 47 86 6 22 47 51 6 22 47 4 22 47 47 61 65 5 23 41 46 47 50 63 65 47 50 51 33 34 47 47 50 51 33 34 47 47 50 26 47 21 47 86 6 22 47 6 22 47 6 22 47 6 22 47 47 49 47 49 22 47 49 22 47 49 34 47 34 47 6 22 47 6 22 47 47 49 47 49 22 47 49 22 47 49 34 47 34 47 23 27 28 29 33 45 47 23 27 28 29 33 45 47 23 39 47 47 50 51 67 68

I16650 51 52 26 52 50 52 50 51 52 50 52 50 51 52 21 50 51 52

Characterization TPsFUNC_TESTI198 I200

70

CPU FSB NO_TESTsNO_TEST TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE EXPOSED_VIA FSB_A_L FSB_ADS_L FSB_ADSTB_L FSB_BNR_L FSB_BREQ0_L FSB_D_L FSB_DBSY_L FSB_DINV_L FSB_DRDY_L FSB_DSTBN_L FSB_DSTBP_L FSB_HIT_L FSB_HITM_L FSB_LOCK_L FSB_REQ_L7 12 86 7 12 86

I199 I201 I202 I2037 12 86

TRUE

I2047 12 86

C

I2057 12 86

I2067 12 86

I2077 12 86

TRUE TRUE TRUE

I2087 12 86

I2097 12 86

I2107 12 86

I2117 12 86

I2127 12 86

I2137 12 86

I2157 12 86

I2147 12 86

I216

EXPOSED_VIA property indicates that the net should have a via with 10-mil soldermask opening for use as engineering probe point.

I217 I219 I218 I221 I220

Misc EXPOSED_VIA NetsEXPOSED_VIA TRUE TRUE TRUE TRUE DMI_N2S_P DMI_N2S_N SB_CLK100M_SATA_P SB_CLK100M_SATA_N14 22 14 22 21 34 21 34

I222 I223 I224 I225

TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE

IMVP_VR_ON IMVP_DPRSLPVR PM_SLP_S3_L PM_SLP_S3BATT PM_SLP_S4_L PM_SLP_S5_L P1V5P1V05S0_PGOOD CPU_DPRSTP_L IMVP6_VID FSB_CLK_CPU_N FSB_CLK_CPU_P PLT_RST_L PLT_RST_L PEG_RESET_L SMC_LRESET_L TPM_LRESET_L CPU_STPCLK_L FSB_CLK_NB_P FSB_CLK_NB_N CLK_NB_OE_L NB_CLK100M_GCLKIN_P NB_CLK100M_GCLKIN_N GND GND GND GND CPU_THERMTRIP_R TP_SB_SUS_CLK

50 60 60 86 23 32 39 43 50 54 64 65 41 5 23 41 46 47 50 63 65 23 50 51 60 64 65 7 21 60 9 60 7 34 7 34 5 14 22 26 5 14 22 26 26 69 26 50 26 59 7 21 86 12 34 12 34 14 33 14 34 14 34

I13834 52 21 50 52 59 21 50 52 59 23 50 52 59 23 50 51 52 59 50 51 52 50 51 52 50 51 52 50 52 50 51 52 23 52

C

Resistor CalibrationFUNC_TESTI142 I141

I140 I139 I143 I16421 6 23

TRUE TRUE TRUE TRUE TRUE TRUE TRUE

PP5V_S0 PP1V8_S3 PP1V05_S0 PPVCORE_S0_CPU PPVCORE_S0_GPU ISENSE_CAL_EN GND

66 67 70 78 79 80 4 5 25 31 36 42 47 52 54 56 57 60 61 65 64 66 5 7 8 9 11 12 13 16 17 19 21 24 25 34 54 8 9 54 60 66 54 66 70 71 76 50 54

Request for at least 2 GND TPs per resistor

Camera Connector MAC-1 TPsFUNC_TESTI168 I167 I227 I228 I229 I230 I231 I232 I233 I235 I234 I236 I237 I238 I239 I240 I241 I242 I243 I244 I245 I246 I247 I248 I250 I249 I251

FUNC_TEST TRUE TRUE TRUE TRUE TRUE PP5V_S3 USB2_CAMERA_N USB2_CAMERA_P SMBUS_SMC_0_S0_SDA SMBUS_SMC_0_S0_SCL5 45 51 61 66 80 6 22 45 6 22 45 27 45 50 53 27 50 53

B

A

I253 I252 I254 I256 I255 I257 I258 I259 I260 I261 I263 I262 I264

TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE

CPU_PWRGD 7 21 86 I169 TP_CPU_CPUSLP_L 21 I171 PM_DPRSLPVR 14 23 60 86 I170 CPU_DPSLP_L 7 21 86 PM_LAN_ENABLE 23 50 PCI_RST_L 22 37 PM_RSMRST_L 23 50 FUNC_TEST PM_SB_PWROK 23 26 TRUE I173 SB_RTC_RST_L 21 26 TRUE I174 PM_STPCPU_L 23 33 TRUE I172 PM_STPPCI_L 23 33 TRUE I175 VR_PWRGD_CK410 23 26 VR_PWRGOOD_DELAY 14 26 60 FSB_CPURST_L 7 11 12 86 FSB_SLPCPU_L 7 12 FUNC_TEST FSB_DPWR_L 7 12 86 NB_SB_SYNC_L 14 22 TRUE I177 PP2V5_S0_GPU_TPVDD TRUE 77 I176 PP2V5_S0_GPU_TXVDDR 77 PP2V5_S0_GPU_AVDD 77 PP2V5_S0_GPU_A2VDD 77 PP2V5_S0_GPU_LPVDD 77 PP2V5_S0_GPU_LVDDR 59 60 64 65 66 70 78 79 28 29 33 PP3V3_S0 4 5 10 14 (=PP3V3_S0_CK410) 17 19 20 21 22 23 24 25 26 27 34 36 37 43 48 51 53 56 57 PP3V3_S0_CK410_VDD48 33 PP3V3_S0_CK410_VDD_PCI 33 PP3V3_S0_CK410_VDD_REF 33 PP3V3_S0_CK410_VDD_CPU_SRC 33 PP3V3_S0_CK410_VDDA 33 PP3V3_FWPHY 4 38 42 43 44 PP3V3_FWPHY_AVDD 38 PP3V3_FWPHY_PLLVDD 38 PP1V95_FWPHY 4 38 42 PP1V95_FWPHY_PLLVDD 38 PP1V2_S3 5 39 62 66 (=PP1V2_S3_ENET) PP3V3_S3AC 39 41 66 (=PP3V3_S3_ENET) PP2V5_S3 5 39 62 66 (=PP2V5_S3_ENET) PP2V5_S3_ENET_AVDD 39 40

I226

B

Left I/O Power ConnectorFUNC_TEST TRUE TRUE TRUE TRUE TRUE PP18V5_DCIN PP5V_S5 PP5V_S0_AUDIO_PWR GND_AUDIO_PWR GND67 5 25 46 51 61 63 64 65 66 67 70 67 67

Thermal SensorsHSTHMSNS_DX_P HSTHMSNS_DX_N RSFSTHMSNS_D_P RSFSTHMSNS_D_N53 53 53 53

Request for at least 10 GND test points

SMC TPsPM_SYSRST_L SMC_ONOFF_L23 26 50 45 50 51 54

Functional / ICT TestSYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)NOTICE OF PROPRIETARY PROPERTYTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER REV.

A

APPLE COMPUTER INC.

DSCALE NONE

051-7023SHT

06 86

5

OF

8

7

6

5

4

3

2

1

8

7

6

5

4

346 22 6

2USB2_RT_P USB2_RT_N RTUSB_OC_L46 22 6

1USB2_RT_P USB2_RT_N RTUSB_OC_L

USB Port "A" (Debug Port) = Right USB 2.0 PortUSB2_RT_PMAKE_BASE=TRUE46 22 6 6 22 46 46 22 6

USB2_RT_NMAKE_BASE=TRUE

6 22 46

7 6

NC_CPU_A32_LMAKE_BASE=TRUE NO_TEST=TRUE

NC_CPU_A32_L NC_CPU_A33_L NC_CPU_A34_L NC_CPU_A35_L NC_CPU_A36_L NC_CPU_A37_L NC_CPU_A38_L NC_CPU_A39_L NC_CPU_APM0_L NC_CPU_APM1_L NC_CPU_EXTBREF NC_CPU_HFPLL NC_CPU_SPARE0 NC_CPU_SPARE1 NC_CPU_SPARE2 NC_CPU_SPARE4

6 7

28

NC_MEM_A_AMAKE_BASE=TRUE NO_TEST=TRUE

MEM_A_A MEM_B_A NB_CFG NB_CFG NB_CFG NB_CFG NB_CFG NB_CFG14 14 50 47 5

46 22 6

R0600ALS_GAIN1

46 22 6

RTUSB_OC_LMAKE_BASE=TRUE

6 22 46

7 6

NC_CPU_A33_LMAKE_BASE=TRUE NO_TEST=TRUE

6 7

29

NC_MEM_B_AMAKE_BASE=TRUE NO_TEST=TRUE

0

2

RTALS_GAINMAKE_BASE=TRUE

RTALS_GAIN

6 56

USB Port "B" = Trackpad (Geyser)45 22 6

7 6

NC_CPU_A34_LMAKE_BASE=TRUE NO_TEST=TRUE

6 7

TP_NB_CFGMAKE_BASE=TRUE

5% 1/16W MF-LF 402

USB_TRACKPAD_P USB_TRACKPAD_N UNUSED_USB_B_OC_LMAKE_BASE=TRUE

45 22 6

USB_TRACKPAD_PMAKE_BASE=TRUE

USB_TRACKPAD_P USB_TRACKPAD_N UNUSED_USB_B_OC_L

6 22 45

45 22 6

45 22 6

USB_TRACKPAD_NMAKE_BASE=TRUE

6 22 45

D

7 6

NC_CPU_A35_LMAKE_BASE=TRUE NO_TEST=TRUE

6 7

TP_NB_CFGMAKE_BASE=TRUE

14

22 6

6 22

D

7 6

NC_CPU_A36_LMAKE_BASE=TRUE NO_TEST=TRUE

6 7

TP_NB_CFGMAKE_BASE=TRUE

14 39 6

USB Port "C" = Left USB 2.0 PortNC_ENET_CTRL12MAKE_BASE=TRUE NO_TEST=TRUE

7 6

NC_CPU_A37_LMAKE_BASE=TRUE NO_TEST=TRUE

NC_ENET_CTRL12 NC_ENET_CTRL25

6 39 47 22 6 5

6 7

TP_NB_CFGMAKE_BASE=TRUE14

USB2_LT_P USB2_LT_N LTUSB_OC_LMAKE_BASE=TRUE

47 22 6 5

USB2_LT_PMAKE_BASE=TRUE

USB2_LT_P USB2_LT_N LTUSB_OC_L

5 6 22 47

14 39 6

7 6

NC_CPU_A38_LMAKE_BASE=TRUE NO_TEST=TRUE

NC_ENET_CTRL25MAKE_BASE=TRUE NO_TEST=TRUE

47 22 6 5

6 39

47 22 6 5

USB2_LT_NMAKE_BASE=TRUE

5 6 22 47

6 7

TP_NB_CFGMAKE_BASE=TRUE

47 22 6 5

5 6 22 47

7 6

NC_CPU_A39_LMAKE_BASE=TRUE NO_TEST=TRUE

6 7

TP_NB_CFGMAKE_BASE=TRUE

USB Port "D" = Camera45 22 6 5

7 6

NC_CPU_APM0_LMAKE_BASE=TRUE NO_TEST=TRUE

6 7

NOTE: NB_CFG require test access TP_NB_CFGMAKE_BASE=TRUE

USB2_CAMERA_P USB2_CAMERA_N UNUSED_USB_D_OC_LMAKE_BASE=TRUE

45 22 6 5

USB2_CAMERA_PMAKE_BASE=TRUE

USB2_CAMERA_P USB2_CAMERA_N UNUSED_USB_D_OC_L

5 6 22 45

7 6

NC_CPU_APM1_LMAKE_BASE=TRUE NO_TEST=TRUE

6 7

NB_CFG

45 22 6 5

14

45 22 6 5

USB2_CAMERA_NMAKE_BASE=TRUE

5 6 22 45

7 6

NC_CPU_EXTBREFMAKE_BASE=TRUE NO_TEST=TRUE

22 6 6 7 23 6 5 6 7 47 22 6 5 6 7

6 22

TP_SB_SUS_CLKMAKE_BASE=TRUE

TP_SB_SUS_CLK

5 6 23

7 6

NC_CPU_HFPLLMAKE_BASE=TRUE NO_TEST=TRUE

USB Port "E" = ExpressCardUSB2_EXCARD_P USB2_EXCARD_N EXCARD_OC_LMAKE_BASE=TRUE47 22 6 5

USB2_EXCARD_PMAKE_BASE=TRUE

USB2_EXCARD_P USB2_EXCARD_N EXCARD_OC_L

5 6 22 47

7 6

NC_CPU_SPARE0MAKE_BASE=TRUE NO_TEST=TRUE

Ethernet Powr Management SupportENET_LOM_DISABLE

47 22 6 5

47 22 6 5

USB2_EXCARD_NMAKE_BASE=TRUE

5 6 22 47

7 6

NC_CPU_SPARE1MAKE_BASE=TRUE NO_TEST=TRUE

6 7

51 47 22 6 5

5 6 22 47 51

7 6

NC_CPU_SPARE2MAKE_BASE=TRUE NO_TEST=TRUE

6 7

R069022

USB Port "F" = IR Receiver80 22 6 39 80 22 6

7 6

NC_CPU_SPARE4MAKE_BASE=TRUE NO_TEST=TRUE

6 7

SB_GPIO30

1

0

2

ENET_LOM_DIS_L

USB_IR_P USB_IR_N

80 22 6

USB_IR_PMAKE_BASE=TRUE

USB_IR_P USB_IR_N

6 22 80

C

5% 1/16W MF-LF 402

80 22 6

USB_IR_NMAKE_BASE=TRUE

6 22 80

USB Port "G" = Bluetooth (M13P)80 22 6

C6 22 80 6 22 80

NOTE: BOM options "USB_G_OC_PU" and "ENET_LOM_DISABLE" are mutually-exclusive.

USB_BT_P USB_BT_N

80 22 6

USB_BT_PMAKE_BASE=TRUE

USB_BT_P USB_BT_N

80 22 6

80 22 6

USB_BT_NMAKE_BASE=TRUE

USB Port "H" = 2nd Left USB 2.0 Port47 22 6 5

USB2_LT2_P USB2_LT2_N

47 22 6 5

USB2_LT2_PMAKE_BASE=TRUE

USB2_LT2_P USB2_LT2_N

5 6 22 47

47 22 6 5

47 22 6 5

USB2_LT2_NMAKE_BASE=TRUE

5 6 22 47

Chassis connection to be made at the fan cutout near the right ALS GND_CHASSIS_FANFRAME

R06011

SH0601 EMI-SPRING 10G-502620R

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V

0

2

5% 1/16W MF-LF 402

Chassis connection to be made at the mounting hole northwest of the DVI connector

B

HOLE-VIA-P5RP25179 6

ZT0600

BGND_CHASSIS_DVI_TOP GND_CHASSIS_DVI_TOP GND_CHASSIS_DVI_TOP GND6 79 6 79

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V MAKE_BASE=TRUE

Chassis connection to be made on FW shell HOLE-VIA-P5RP25179 44 40 6

ZT0603

GND_CHASSIS_DVI_BOT GND_CHASSIS_DVI_BOT GND_CHASSIS_DVI_BOT GND_CHASSIS_DVI_BOT GND_CHASSIS_DVI_BOT GND_CHASSIS_DVI_BOT6 40 44 79 6 40 44 79 6 40 44 79 6 40 44 79 6 40 44 79

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V MAKE_BASE=TRUE

Chassis connection to be made at the mounting hole southwest of the USB connector HOLE-VIA-P5RP25146 44 6

ZT0601

GND_CHASSIS_USB GND_CHASSIS_USB GND_CHASSIS_USB GND_CHASSIS_USB6 44 46 6 44 46 6 44 46

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V MAKE_BASE=TRUE

Chassis connection to be made at the mounting hole east of the LVDS connector

A

HOLE-VIA-P5RP25178 6

ZT0602

Signal AliasesSYNC_MASTER=(M1_MLB) SYNC_DATE=(11/11/2005)NOTICE OF PROPRIETARY PROPERTYTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

GND_CHASSIS_LVDS GND_CHASSIS_LVDS GND_CHASSIS_LVDS GND_CHASSIS_LVDS GND_CHASSIS_LVDS6 78 6 78 6 78 6 78

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V MAKE_BASE=TRUE

A

1

78 6

GND_CHASSIS_INVERTER GND_CHASSIS_INVERTER6 78

SH0600 2OG-503040SHLD-SM-LF

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=0V MAKE_BASE=TRUE

SIZE

DRAWING NUMBER

REV.

APPLE COMPUTER INC.

DSCALE NONE

051-7023SHT

06 86

3

6

OF

8

7

6

5

4

3

2

1

886 12 5 86 12 5 86 12 5 86 12 5 86 12 5 86 12 5 86 12 5 86 12 5 86 12 5

7OMITBI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

6 U0700ADS* BNR* BPRI* DEFER* DRDY* DBSY* BR0* IERR* INIT* LOCK* RESET* RS0* RS1* RS2* TRDY* HIT* HITM* BPM0* BPM1* BPM2* BPM3* PRDY* PREQ* TCK TDI TDO TMS TRST* DBR* PROCHOT* THERMDA THERMDC THERMTRIP*

5PP1V05_S0BI BI BI BI BI BI BI5 12 86 5 12 86 12 86 5 7 8 9 11 12 13 16 17 19 21 24 25 34 54 64 66

4

3

2

1

ADDR GROUP0

D

86 12 5 86 12 5 86 12 5 86 12 5 86 12 5 86 12 5

FSB_A_L J4 A3* YONAH FSB_A_L L4 A4* CPU FSB_A_L M3 A5* BGA FSB_A_L K5 A6* (1 OF 4) FSB_A_L M1 A7* FSB_A_L N2 A8* FSB_A_L J1 A9* FSB_A_L N3 A10* FSB_A_L P5 A11* FSB_A_L P2 A12* FSB_A_L L1 A13* FSB_A_L P4 A14* FSB_A_L P1 A15* FSB_A_L R1 A16* FSB_ADSTB_L L2 ADSTB0*CONTROL

H1 E2 G5 H5 F21 E1 F1 D20 B3 H4 B1 F3 F4 G3 G2 G6 E4 AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20 D21 A24 A25 C786

86 12 5 86 12 5 86 12 5 86 12 5 86 12 5

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI IN OUT IN IN IN IN IN6 6 6 6 6 6 6 6 6 6

86 12 5 86 12 5 86 12 5 86 12 5 86 12 5 86 12 5 86 12 5 86 12 5 86 12 5 86 12 5 86 12 5 86 12 5 86 12 5 86 12 5

C

86 12 5 86 12 5

86 21 21 86 21

86 21 5 86 21 86 21 86 21

6

FSB_REQ_LK3 REQ0* FSB_REQ_LH2 REQ1* FSB_REQ_LK2 REQ2* FSB_REQ_LJ3 REQ3* FSB_REQ_LL5 REQ4* FSB_A_L Y2 A17* FSB_A_L U5 A18* FSB_A_L R3 A19* FSB_A_L W6 A20* FSB_A_L U4 A21* FSB_A_L Y5 A22* FSB_A_L U2 A23* FSB_A_L R4 A24* FSB_A_L T5 A25* FSB_A_L T3 A26* FSB_A_L W3 A27* FSB_A_L W5 A28* FSB_A_L Y4 A29* FSB_A_L W2 A30* FSB_A_L Y1 A31* FSB_ADSTB_L V4 ADSTB1* CPU_A20M_L A6 A20M* CPU_FERR_L A5 FERR* CPU_IGNNE_L C4 IGNNE* CPU_STPCLK_LD5 STPCLK* CPU_INTR C6 LINT0 CPU_NMI B4 LINT1 CPU_SMI_L A3 SMI* NC_CPU_A32_L AA1 RSVD1 NC_CPU_A33_L AA4 RSVD2 NC_CPU_A34_L AB2 RSVD3 NC_CPU_A35_L AA3 RSVD4 NC_CPU_A36_LM4 RSVD5 NC_CPU_A37_LN5 RSVD6 NC_CPU_A38_LT2 RSVD7 NC_CPU_A39_LV3 RSVD8 NC_CPU_APM0_L B2 RSVD9 NC_CPU_APM1_L C3 RSVD10 NC_CPU_HFPLL B25 RSVD11

FSB_ADS_L FSB_BNR_L FSB_BPRI_L FSB_DEFER_L FSB_DRDY_L FSB_DBSY_L FSB_BREQ0_L FSB_IERR_L CPU_INIT_L FSB_LOCK_L FSB_CPURST_L FSB_RS_L FSB_RS_L FSB_RS_L FSB_TRDY_L FSB_HIT_L FSB_HITM_L

1

12 86 5 12 86 5 12 86

1% 1/16W MF-LF 2402

R0702 54.9

5 12 86

IN BI IN IN IN IN IN BI BI

21 86

PLACE TESTPOINT ON FSB_IERR_L WITH A GND 0.1" AWAY

D

5 12 86

5 11 12 86 12 86 12 86 12 86 12 86

PP1V05_S01

5 7 8 9 11 12 13 16 17 19 21 24 25 34 54 64 66

5 12 86 5 12 86

DATA GRP0

11 26

86 12 5 12 5 86 86 12 5 86 12 5 86 12 5 86 12 5 86 12 5 86 12 5 86 12 5 86 12 5 86 12 5 86 12 5

DATA GRP2

XDP_BPM_L BI XDP_BPM_L BI XDP_BPM_L BI XDP_BPM_L BI XDP_BPM_L BI XDP_BPM_L XDP_TCK IN XDP_TDI IN XDP_TDO OUT XDP_TMS IN XDP_TRST_L IN XDP_DBRESET_L OUT

XDP/ITP SIGNALS

11 86 11 86 11 86 11 86 11 86

1% 1/16W MF-LF 2402

R0703 54.986 12 5 86 12 5 86 12 5 86 12 5 86 12 5 86 12 5 86 12 5

OMIT

BCLK0 BCLK1

A22 A21

RESERVED

RSVD12

T22 D2 F6 D3 C1 AF1 D22 C23 C24

RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20

B11 7

PP1V05_S0 XDP_TMS

5 7 8 9 11 12 13 16 17 19 21 24 25 34 54 64 66

R0720 54.91 2

YONAH D32* FSB_D_L E22 D0* CPU FSB_D_L F24 D1* D33* BGA FSB_D_L E26 D2* D34* (2 OF 4) BI FSB_D_L H22 D3* D35* BI 1 R0704 FSB_D_L F23 D36* D4* BI 68 FSB_D_L G25 D37* D5* 5% BI 1/16W FSB_D_L E25 D6* D38* MF-LF BI 2402 FSB_D_L E23 D7* D39* BI FSB_D_L K24 D40* D8* BI CPU_PROCHOT_L TO SMC CPU_PROCHOT_L FSB_D_L G24 D9* D41* OUT BI AND CPU VR TO INFORM CPU_THERMD_P OUT FSB_D_L J24 D10* D42* BI CPU IS HOT CPU_THERMD_N OUT FSB_D_L J23 D43* D11* BI FSB_D_L H26 D44* D12* BI PM_THRMTRIP_L OUT FSB_D_L F26 D13* D45* BI FSB_D_L K22 D14* D46* BI PM_THRMTRIP# FSB_D_L H25 D47* D15* BI SHOULD CONNECT TO FSB_DSTBN_L FSB_CLK_CPU_P H23 DSTBN0* DSTBN2* IN BI ICH7-M AND GMCH FSB_DSTBP_L FSB_CLK_CPU_N G22 DSTBP0* DSTBP2* IN BI WITHOUT T-ING (NO FSB_DINV_L J26 DINV0* DINV2* BI STUB) FSB_D_L N22 D16* D48* BI FSB_D_L K25 D17* D49* BI FSB_D_L P26 D18* D50* BI NC_CPU_EXTBREF FSB_D_L R23 D51* D19* BI FSB_D_L L25 D20* D52* BI NC_CPU_SPARE0 FSB_D_L L22 D21* D53* BI NC_CPU_SPARE1 SPARE[7-0],HFPLL: FSB_D_L L23 D54* D22* BI NC_CPU_SPARE2 ROUTE TO TP VIA AND FSB_D_L M23 D23* D55* BI TP_CPU_SPARE3 PLACE GND VIA W/IN 1000 MILS FSB_D_L P25 D24* D56* BI NC_CPU_SPARE4 FSB_D_L P22 D25* D57* BI TP_CPU_SPARE5 FSB_D_L P23 D26* D58* BI TP_CPU_SPARE6 FSB_D_L T24 D27* D59* BI TP_CPU_SPARE7 FSB_D_L R24 D28* D60* BI PP1V05_S0 FSB_D_L L26 D29* D61* BI FSB_D_L T25 D30* D62* BI FSB_D_L N24 D31* D63* BI 1 R0705 FSB_DSTBN_L M24 DSTBN1* DSTBN3* BI 1K FSB_DSTBP_L N25 1% DSTBP1* DSTBP3* BI 1/16W FSB_DINV_L M26 DINV1* MF-LF DINV3* BI 2402 CPU_GTLREF AD26 GTLREF COMP0BI BI BI11 86 7 11 7 11 11 7 11 11 10 10 14 21 51 5 34 5 34 86 12 5 86 12 5 86 12 5 86 12 5 86 12 5 86 12 5 86 12 5 86 12 5 86 12 5 86 12 5 86 12 5 86 12 5 86 12 5 86 12 5 86 12 5 86 12 5 86 12 5 86 12 5 86 12 5 6 6 6 6

U0700

AA23 AB24 V24 V26 W25 U23 U25 U22 AB25 W22 Y23 AA26 Y26 Y22 AC26 AA24 W24 Y25 V23 AC22 AC23 AB22 AA21 AB21 AC25 AD20 AE22 AF23 AD24 AE21 AD21 AE25 AF25 AF22 AF26 AD23 AE24 AC20 R26 U26 U1 V1 E5 B5 D24 D6 D7 AE686 86 86 86

6

21 19 17 16 13 12 11 9 8 7 5 66 64 54 34 25 24

86

1

1% 402

1% 1/16W MF-LF 240234 34 34

LAYOUT NOTE: 0.5" R0706 CPU_TEST1 2.0K

A2 NC MAX LENGTH C26 TEST1 D25 B22 B23 C21TEST2 BSEL0 BSEL1 BSEL2

MISC

COMP1 COMP2 COMP3 DPRSTP* DPSLP* DPWR* PWRGOOD SLP* PSI*

11 7

XDP_TDI

R0721 54.91 2

OUT OUT OUT

1% 402

CPU_TEST2 CPU_BSEL CPU_BSEL CPU_BSEL NOSTUFF

11 7

XDP_TCK

R0722 54.91 2

R0730 01 2 402 1 5% 1/16W MF-LF 2402 1 R0712 R0707 51 1K 5% 1/16W MF-LF 2402

FSB_D_L BI FSB_D_L BI FSB_D_L BI FSB_D_L BI FSB_D_L BI FSB_D_L BI FSB_D_L BI FSB_D_L BI FSB_D_L BI FSB_D_L BI FSB_D_L BI FSB_D_L BI FSB_D_L BI FSB_D_L BI FSB_D_L BI FSB_D_L BI FSB_DSTBN_L BI FSB_DSTBP_L BI FSB_DINV_LBI FSB_D_L BI FSB_D_L BI FSB_D_L BI FSB_D_L BI FSB_D_L BI FSB_D_L BI FSB_D_L BI FSB_D_L BI FSB_D_L BI FSB_D_L BI FSB_D_L BI FSB_D_L BI FSB_D_L BI FSB_D_L BI FSB_D_L BI FSB_D_L BI FSB_DSTBN_L BI FSB_DSTBP_L BI FSB_DINV_LBI CPU_COMP CPU_COMP CPU_COMP CPU_COMP CPU_DPRSTP_L IN CPU_DPSLP_L IN FSB_DPWR_L IN CPU_PWRGD IN FSB_SLPCPU_L IN CPU_PSI_L IN

ADDR GROUP1

5 12 86 5 12 86 5 12 86 5 12 86 5 12 86 5 12 86 5 12 86 5 12 86 5 12 86 5 12 86 5 12 86 5 12 86 5 12 86 5 12 86 5 12 86 5 12 86 5 12 86 5 12 86 5 12 86

THERM

C

HCLK

5 12 86 5 12 86 5 12 86 5 12 86 5 12 86 5 12 86 5 12 86 5 12 86 5 12 86 5 12 86 5 12 86 5 12 86 5 12 86 12 86 5

DATA GRP1

DATA GRP3

LAYOUT NOTE: COMP0,2 CONNECT WITH TRACE LENGTH SHORTER COMP1,3 CONNECT WITH TRACE LENGTH SHORTER

ZO=27.4OHM, MAKE THAN 0.5". ZO=55OHM, MAKE THAN 0.5".

R0716 27.41 2

R0717 54.95 12 86 5 12 86 5 12 86

402

1

2 1% 402

R0718 27.41 2

B

R0719 54.91 25 21 60 5 21 86 5 12 86 5 21 86 5 12 60

1% 402

NOSTUFF

1% 402

CHANGE THE PULLS RESISTOR VALUE PER NAPA PLATFORM DG REV 0.9

CPU 1 OF 2-FSB

A

WE THROUGH THE ITP700FLEX CONNECTOR CONNECT TO PDB XDP BUFFER BOARD--ECM*50 SO THE TDI PULL UP THROUGH 54.9 OHM,TMS PULL UP THROUGH 54.9 OHM TCK PULL DOWN THROUGH 54.9 OHM(FOLLOW UP XDP DESIGN REFERENCE)

SYNC_MASTER=M1_MLB

SYNC_DATE=02/10/2006

NOTICE OF PROPRIETARY PROPERTYTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER REV.

A

APPLE COMPUTER INC.

DSCALE NONE

051-7023SHT

06 86

7

OF

8

7

6

5

4

3

2

1

8

7

6

5

4OMIT A4 A8 A11 A14 A16 A19 A23 A26 B6 B8 B11 B13 B16 B19 B21 B24 C5 C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F5 F8 F11 F13 F16 F19 F2 F22 F25 G4 G1 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 P3VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81

3 U0700BGA(4 OF 4)VSS_82

2

1

PPVCORE_S0_CPUOMIT A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18VCC_1 VCC_2 VCC_3 VCC_5 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12 VCC_13 VCC_14 VCC_15 VCC_16 VCC_17 VCC_18 VCC_19 VCC_20 VCC_21 VCC_22 VCC_23 VCC_24 VCC_25 VCC_26 VCC_27 VCC_28 VCC_29 VCC_30 VCC_31 VCC_32 VCC_33 VCC_34 VCC_35 VCC_36 VCC_37 VCC_38 VCC_39 VCC_40 VCC_41 VCC_42 VCC_43 VCC_44 VCC_45 VCC_46 VCC_47 VCC_48 VCC_49 VCC_50 VCC_51 VCC_52 VCC_53 VCC_54 VCC_55 VCC_56 VCC_57 VCC_58 VCC_59 VCC_60 VCC_61 VCC_62 VCC_63 VCC_64 VCC_65 VCC_66 VCC_67 VCCSENSE VSSSENSE VCCA

5 8 9 54 60 66

YONAH VSS_83 CPU VSS_84 VSS_85VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162

YONAH VCC_70 CPU VCC_71 VCC_4BGA(3 OF 4)VCC_72 VCC_73 VCC_74 VCC_75 VCC_76 VCC_77 VCC_78 VCC_79 VCC_80 VCC_81 VCC_82 VCC_83 VCC_84 VCC_85 VCC_86 VCC_87 VCC_88 VCC_89 VCC_90 VCC_91 VCC_92 VCC_93 VCC_94 VCC_95 VCC_96 VCC_97 VCC_98 VCC_99 VCC_100 VCCP_1 VCCP_2 VCCP_3 VCCP_4 VCCP_5 VCCP_6 VCCP_7 VCCP_8 VCCP_9 VCCP_10 VCCP_11 VCCP_12 VCCP_13 VCCP_14 VCCP_15 VCCP_16

U0700

VCC_68 VCC_69

D

C

AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20 V6 G21 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21 B26 AD6 AF5 AE5 AF4 AE3 AF2 AE2

(CPU CORE POWER)

PP1V05_S0

25 34 54 64 66 5 7 9 11 12 13 16 17 19 21 24

(CPU IO POWER 1.05V)

(CPU INTERNAL PLL POWER 1.5V)CPU_VID OUT CPU_VID OUT CPU_VID OUT CPU_VID OUT CPU_VID OUT CPU_VID OUT CPU_VID OUT9 86 9 86 9 86 9 86 9 86 9 86 9 86

PP1V5_S0

VCCA=1.5 ONLY

VID0 VID1 VID2 VID3 VID4 VID5 VID6

B

VID FOR CPU POWER IF NO USE, NEED PULL-UP OR PULL-DOWN 1

PPVCORE_S0_CPU SUPPLY

5 8 9 54 60 66

R0802 1001% 1/16W MF-LF

2402

AF7 AE7

CPU_VCCSENSE_P CPU_VCCSENSE_N

OUT

60 86

1 LAYOUT NOTE: CONNECT R0803100 1% TO TP_VSSSENSE WITH NO 1/16W MF-LF STUB. 2402 LAYOUT NOTE: VCCSENSE AND VSSSENSE LINES SHOULD BE OF EQUAL LENGTH

R0803

LAYOUT NOTE: PROVIDE A TEST POINT (WITH NO STUB) TO CONNECT A DIFFERENCTIAL PROBE LAYOUT NOTE: BETWEEN VCCSENSE AND VSSSENSE AT THE CPU_VCCSENSE_P/CPU_VCCSENSE_N USE LOCATION WHERE THE TWO 54.9 OHM ZO=27.4 OHM DIFFERNTIAL TRACE ROUTING. RESISTORS TERMINATE THE 55 OHM TRANSMISSION LINE

OUT

60 86

P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 AF3 AF6 AF8 AF11 AF13 AF16 AF19 AF21 AF24

D

C

B

CPU 2 OF 2-PWR/GND

A

SYNC_MASTER=M1_MLB

SYNC_DATE=02/10/2006

NOTICE OF PROPRIETARY PROPERTYTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER REV.

A

APPLE COMPUTER INC.

DSCALE NONE

051-7023SHT

06 86

8

OF

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

DCPU VCORE HF AND BULK DECOUPLING66 60 54 8 5

D

PPVCORE_S0_CPU

4x 470uF. 20x 22uF 08051

C090022UF

1

C090122UF

1

C090222UF

1

C090322UF

1

C090422UF

1

C090522UF

1

C090622UF

1

C090722UF

1

C090822UF

1

C090922UF

CPU VCORE VID ConnectionsResistors to allow for override of CPU VID Will probably be removed before production

20% 2 6.3V CERM 805

20% 2 6.3V CERM 805

20% 2 6.3V CERM 805

20% 2 6.3V CERM 805

20% 2 6.3V CERM 805

20% 2 6.3V CERM 805

20% 2 6.3V CERM 805

20% 2 6.3V CERM 805

20% 2 6.3V CERM 805

20% 2 6.3V CERM 805

R099086 8

CPU_VID

1

0

2

IMVP6_VID

5 60

1

C091022UF

1

C091122UF

1

C091222UF

1

C091322UF

1

C091422UF

1

C091522UF

1

C091622UF

1

C091722UF

1

C091822UF

1

C091922UF86 8

20% 2 6.3V CERM 805

20% 2 6.3V CERM 805

20% 2 6.3V CERM 805

20% 2 6.3V CERM 805

20% 2 6.3V CERM 805

20% 2 6.3V CERM 805

20% 2 6.3V CERM 805

20% 2 6.3V CERM 805

20% 2 6.3V CERM 805

20% 2 6.3V CERM 805

CPU_VID

5% 1/16W MF-LF 402

R09911

0

2

IMVP6_VID

5 60

R099286 8

CPU_VID

1

0

2

5% 1/16W MF-LF 402

IMVP6_VID

5 60

CRITICAL1

CRITICAL1

CRITICAL1

CRITICAL1

C0950

C

20% 3 2 2.5V POLY D2TS

470uF-8MOHM

C0952

20% 3 2 2.5V POLY D2TS

470uF-8MOHM

C0953

20% 3 2 2.5V POLY D2TS

470uF-8MOHM

C0954

86 8

CPU_VID

5% 1/16W MF-LF 402

R09931

0

2

IMVP6_VID

5 60

20% 3 2 2.5V POLY D2TS

470uF-8MOHM86 8

R0994CPU_VID1

0

2

5% 1/16W MF-LF 402

IMVP6_VID

5 60

C

86 8

CPU_VID

5% 1/16W MF-LF 402

R09951

0

2

IMVP6_VID

5 60

R099686 8

CPU_VID

1

0

2

5% 1/16W MF-LF 402

IMVP6_VID

5 60

5% 1/16W MF-LF 402

VCCA (CPU AVdd) Decoupling65 47 25 24 19 17 16 13 8 5 66

PP1V5_S0

1x 10uF, 1x 0.01uFC0980 110uF20% 6.3V 2 X5R 603 1

C09810.01UF

20% 2 16V CERM 402

B

B

VCCP (CPU I/O) Decoupling24 21 19 17 16 13 12 11 8 7 5 66 64 54 34 25

PP1V05_S0

1x 470uF, 6x 0.1uF 0402C0935 120% 2.5V 2 3 POLY D2TS 1

C09360.1UF

1

C09370.1UF

1

C09380.1UF

1

C09390.1UF

1

C09400.1UF

1

C09410.1UF

470uF-9MOHM CRITICAL

20% 2 10V CERM 402

20% 2 10V CERM 402

20% 2 10V CERM 402

20% 2 10V CERM 402

20% 2 10V CERM 402

20% 2 10V CERM 402

NOTE: This cap is shared between CPU and NB

CPU Decoupling & VID

A

SYNC_MASTER=M1_MLB

SYNC_DATE=02/08/2006

NOTICE OF PROPRIETARY PROPERTYTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER REV.

A

APPLE COMPUTER INC.

DSCALE NONE

051-7023SHT

06 86

9

OF

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

D

D

CPU ZONE THERMAL SENSOR79 78 70 66 65 64 60 59 57 56 53 51 48 43 37 36 34 33 29 28 27 26 25 24 23 22 21 20 19 17 14 5 4

PP3V3_S0

CLAYOUT NOTE: ADD GND GUARD TRACE FOR CPU_THERMD_P AND CPU_THERMD_N LAYOUT NOTE: ROUTE CPU_THERMD_P AND CPU_THERMD_N ON SAME LAYER. 10 MIL TRACE 10 MIL SPACING 1

C1

C10020.1UF

R100510K

1

R100610K

PLACEHOLDER ADT7461A CRITICAL 1VDD

10% 2 16V X5R 402

5% 1/16W MF-LF 2 402

5% 1/16W MF-LF 2 402

R10017

OUT

CPU_THERMD_P

1

499

2

53 53

1% 1/16W MF-LF 402 (TO CPU INTERNAL THERMAL DIODE)

THRM_CPU_DX_P 2 THRM_CPU_DX_N 3

D+ D-

U1001ADT7461MSOP

ALERT*/ 6 THM2* THM* 4 SCLK 8 SDATA 7

THRM_ALERT_L THRM_ALERT SMBUS_SMC_B_S0_SCL SMBUS_SMC_B_S0_SDABI BI4 27 48 50 4 27 48 50

1

C10010.001uF

R10027

IN

CPU_THERMD_N

1

499

2

10% 50V 2 CERM 402

GND 5

1% 1/16W MF-LF 402

PLACE U1001 NEAR THE U1200

B

B

CPU MISC1-TEMP SENSOR

A

SYNC_MASTER=M1_MLB

SYNC_DATE=02/10/2006

NOTICE OF PROPRIETARY PROPERTYTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER REV.

A

APPLE COMPUTER INC.

DSCALE NONE

051-7023SHT

06 86

10

OF

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

D

D

CPU ITP700FLEX DEBUG SUPPORTCITPCONN21 19 17 16 13 12 11 9 8 7 5 66 64 54 34 25 24

CPP1V05_S0ITP1 1% 1/16W MF-LF 2402 1 R1101 R1103 54.9 54.9 1% 1/16W MF-LF 24027 7 7

CRITICAL 52435-2872 F-RT-SM29OUT OUT OUT

J1101

XDP_TDI XDP_TMS

XDP_TRST_L CPU_XDP_CLK_N CPU_XDP_CLK_P(FBO)

ITP7

IN

XDP_TDOITP

R1102 22.61 2 1% 1/16W MF-LF 402

11 7

OUT

(TCK) XDP_TCK ITP_TDO

IN (FROM CK410M HOST 133/167MHZ)86 34

IN

86 12 7 5

IN

22.6 1 2 FSB_CPURST_L1% 1/16W MF-LF 402

R1100

11 7

OUT86

XDP_TCK

ITPRESET_L

86 7

BI

86 7

BI

B

65 64 62 55 26 25 24 23 22 5 78 66

PP3V3_S586 7

BI

1

5% 1/16W MF-LF 2402

R1104 240

86 7

BI

86 7

BI

86 7

BI

XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L PP1V05_S0 1 C1100 0.1UF10% 2 16V X5R 4021

(AND WITH RESET BUTTON) OUT

XDP_DBRESET_L21 19 17 16 13 12 11 9 8 7 5 66 64 54 34 25 24

1 2 3 NC 4 5 NC 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 NC 24 25 26 27 28 30

B

(DBA#) INDICATE THAT ITP IS USING TAP I/F, NC IN 945GM CHIPSET SYSTEM. (DEBUG PORT ACTIVE) (DBR#) TO ICH7M SYS_RST*, AND WITH SYSTEM RESET LOGIC (DEBUG PORT RESET)

518S0320

680 ITP TCK SIGNAL LAYOUT NOTE: 5% MF-LF ROUTE THE TCK SIGNAL FROM ITP700FLEX CONNECTORS TCK PIN TO 1/16W CPUS 402 2 TCK PIN AND THEN FORK BACK FROM CPU TCK PIN AND ROUTE BACK TO ITP700FLEX CONNECTORS FBO PIN.

R1106

CPU ITP700FLEX DEBUG

A

SYNC_MASTER=M1_MLB SYNC_DATE=02/10/2006NOTICE OF PROPRIETARY PROPERTYTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER REV.

A

APPLE COMPUTER INC.

DSCALE NONE

051-7023SHT

06 86

11

OF

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

86 7 5

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

D

86 7 5 86 7 5 86 7 5 86 7 5 86 7 5 86 7 5 86 7 5 86 7 5 86 7 5 86 7 5 86 7 5 86 7 5 86 7 5 86 7 5 86 7 5 86 7 5 86 7 5 86 7 5 86 7 5 86 7 5 86 7 5 86 7 5 86 7 5 86 7 5 86 7 5 86 7 5

C

86 7 5 86 7 5 86 7 5 86 7 5 86 7 5 86 7 5 86 7 5 86 7 5 86 7 5 86 7 5 86 7 5 86 7 5 86 7 5 86 7 5 86 7 5 86 7 5 86 7 5 86 7 5 86 7 5 86 7 5 86 7 5 86 7 5 21 19 17 16 13 12 11 9 8 7 5 66 64 54 34 25 24

PP1V05_S0

86 7 5 86 7 5 86 7 5

R122054.9

1

1

R1225221

86 7 5 86 7 5 86 7 5 86 7 5 86 7 5 86 7 5 86 7 5 86 7 5

B

1% 1/16W MF-LF 402 2

1% 1/16W MF-LF 2 402

R122124.9

1

1

R1226100

86 7 5

1

C12260.1uF

86 7 5 86 7 5 86 7 5

1% 1/16W MF-LF 402 2

1% 1/16W MF-LF 2 402

10% 16V 2 X5R 402

FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L FSB_D_L NB_FSB_XRCOMP NB_FSB_XSCOMP NB_FSB_XSWING NB_FSB_YRCOMP NB_FSB_YSCOMP NB_FSB_YSWING

F1 J1 H1 J6 H3 K2 G1 G2 K9 K1 K7 J8 H4 J3 K11 G4 T10 W11 T3 U7 U9 U11 T11 W9 T1 T8 T4 W7 U5 T9 W6 T5 AB7 AA9 W4 W3 Y3 Y7 W5 Y10 AB8 W2 AA4 AA7 AA2 AA6 AA10 Y8 AA1 AB4 AC9 AB11 AC11 AB3 AC2 AD1 AD9 AC1 AD7 AC6 AB5 AD10 AD4 AC8

HD0* HD1* HD2* HD3* HD4* HD5* HD6* HD7* HD8* HD9* HD10* HD11* HD12* HD13* HD14* HD15* HD16* HD17* HD18* HD19* HD20* HD21* HD22* HD23* HD24* HD25* HD26* HD27* HD28* HD29* HD30* HD31* HD32* HD33* HD34* HD35* HD36* HD37* HD38* HD39* HD40* HD41* HD42* HD43* HD44* HD45* HD46* HD47* HD48* HD49* HD50* HD51* HD52* HD53* HD54* HD55* HD56* HD57* HD58* HD59* HD60* HD61* HD62* HD63*

OMIT

U1200945GM NBBGA(1 OF 10)

HA3* HA4* HA5* HA6* HA7* HA8* HA9* HA10* HA11* HA12* HA13* HA14* HA15* HA16* HA17* HA18* HA19* HA20* HA21* HA22* HA23* HA24* HA25* HA26* HA27* HA28* HA29* HA30* HA31*

H9 C9 E11 G11 F11 G12 F9 H11 J12 G14 D9 J14 H13 J15 F14 D12 A11 C11 A12 A13 E13 G13 F12 B12 B14 C12 A14 C14 D14

FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_A_L FSB_ADS_L FSB_ADSTB_L FSB_ADSTB_L NB_FSB_VREF FSB_BNR_L FSB_BPRI_L FSB_BREQ0_L FSB_CPURST_L FSB_DBSY_L FSB_DEFER_L FSB_DPWR_L FSB_DRDY_L

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

5 7 86 5 7 86 5 7 86 5 7 86 5 7 86 5 7 86 5 7 86 5 7 86 5 7 86 5 7 86 5 7 86 5 7 86 5 7 86 5 7 86 5 7 86 5 7 86 5 7 86 5 7 86 5 7 86 5 7 86 5 7 86 5 7 86 5 7 86 5 7 86 5 7 86 5 7 86 5 7 86 5 7 86 5 7 86

D

PP1V05_S01

5 7 8 9 11 12 13 16 17 19 21 24 25 34 54 64 66

C

R1210100

HADS* HADSTB0* HADSTB1* HAVREF HBNR* HBPRI* HBREQ0* HCPURST* HDBSY* HDEFER* HDPWR* HDRDY* HDVREF HDINV0* HDINV1* HDINV2* HDINV3* HDSTBN0* HDSTBN1* HDSTBN2* HDSTBN3* HDSTBP0* HDSTBP1* HDSTBP2* HDTSBP3* HHIT* HHITM* HLOCK* HREQ0* HREQ1* HREQ2* HREQ3* HREQ4* HRS0* HRS1* HRS2* HSLPCPU* HTRDY*

E8 B9 C13 J13 C6 F6 C7 B7 A7 C3 J9 H8 K13 J7 W8 U3 AB10 K4 T7 Y5 AC4 K3 T6 AA5 AC5 D3 D4 B3 D8 G8 B8 F8 A8 B4 E6 D6 E3 E7

BI BI BI

5 7 86 5 7 86 5 7 86

HOST

1% 1/16W MF-LF 2 402

BI OUT BI OUT BI OUT BI BI

5 7 86 7 86 5 7 86 5 7 11 86 5 7 86 7 86 5 7 86 5 7 86

C12110.1uF

1 1

R1211200

10% 16V X5R 2 402

1% 1/16W MF-LF 2 402

FSB_DINV_L FSB_DINV_L FSB_DINV_L FSB_DINV_L FSB_DSTBN_L FSB_DSTBN_L FSB_DSTBN_L FSB_DSTBN_L FSB_DSTBP_L FSB_DSTBP_L FSB_DSTBP_L FSB_DSTBP_L FSB_HIT_L FSB_HITM_L FSB_LOCK_L FSB_REQ_L FSB_REQ_L FSB_REQ_L FSB_REQ_L FSB_REQ_L FSB_RS_L FSB_RS_L FSB_RS_L FSB_SLPCPU_L FSB_TRDY_L

BI BI BI BI BI BI BI BI BI BI BI BI

5 7 86 5 7 86 5 7 86 5 7 86

5 7 86 5 7 86 5 7 86 5 7 86

5 7 86 5 7 86 5 7 86 5 7 86

B

BI BI BI

5 7 86 5 7 86 5 7 86

BI BI BI BI BI

5 7 86 5 7 86 5 7 86 5 7 86 5 7 86

E1 HXRCOMP E2 HXSCOMP E4 HXSWING Y1 HYRCOMP U1 HYSCOMP W1 HYSWING AG2 HCLKIN AG1 HCLKIN*

OUT OUT OUT

7 86 7 86 7 86

21 19 17 16 13 12 11 9 8 7 5 66 64 54 34 25 24

PP1V05_S034 5 34 5

R123054.9

1

1

R1235221

IN IN

FSB_CLK_NB_P FSB_CLK_NB_N

OUT OUT

5 7 7 86

1% 1/16W MF-LF 402 2

1% 1/16W MF-LF 2 402

NB CPU Interface

AR123124.91% 1/16W MF-LF 402 2 1 1

SYNC_MASTER=M1_MLB

SYNC_DATE=02/10/2006

R1236100

NOTICE OF PROPRIETARY PROPERTY1

A

C12360.1uF

1% 1/16W MF-LF 2 402

10% 2 16V X5R 402

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER REV.

APPLE COMPUTER INC.

DSCALE NONE

051-7023SHT

06 86

12

OF

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

PP1V5_S01

5 8 9 13 16 17 19 24 25 47 65 66

R131024.9

OMIT

U1200LVDS Disable19

D

OUT OUT OUT OUT BI BI BI

Can leave all signals NC if LVDS is not implemented Tie VCC_TXLVDS and VCCA_LVDS to GND. If SDVO is used VCCD_LVDS must remain powered with proper decoupling. Otherwise, tie VCCD_LVDS to GND also.

19 19 19 19 19 19

19 19 19

OUT IN IN OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

TP_LVDS_BKLTCTL TP_LVDS_BKLTEN TP_LVDS_CLKCTLA TP_LVDS_CLKCTLB TP_LVDS_DDC_CLK TP_LVDS_DDC_DATA NC_LVDS_IBG TP_LVDS_VBG TP_LVDS_VDDEN NC_LVDS_VREFH TP_LVDS_VREFL NC_LVDS_A_CLKN NC_LVDS_A_CLKP NC_LVDS_B_CLKN NC_LVDS_B_CLKP NC_LVDS_A_DATAN NC_LVDS_A_DATAN NC_LVDS_A_DATAN NC_LVDS_A_DATAP NC_LVDS_A_DATAP NC_LVDS_A_DATAP NC_LVDS_B_DATAN NC_LVDS_B_DATAN NC_LVDS_B_DATAN NC_LVDS_B_DATAP NC_LVDS_B_DATAP NC_LVDS_B_DATAP PP1V5_S0 PP1V5_S0 PP1V5_S0 PP1V5_S0 PP1V5_S0 PP1V5_S0 PP1V5_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 TP_CRT_DDC_CLK TP_CRT_DDC_DATA GND PP1V05_S0 GND

D32 L_BKLTCTL J30 L_BKLTEN H30 L_CLKCTLA H29 L_CLKCTLB G26 L_DDC_CLK G25 L_DDC_DATA B38 L_IBG C35 L_VBG F32 L_VDDEN C33 L_VREFH C32 L_VREFL A33 LA_CLK* A32 LA_CLK E27 LB_CLK*

945GM NBBGA(3 OF 10)

1% 1/16W MF-LF 2 402

EXP_A_COMPI EXP_A_COMPO EXP_A_RXN0 EXP_A_RXN1 EXP_A_RXN2 EXP_A_RXN3 EXP_A_RXN4 EXP_A_RXN5 EXP_A_RXN6 EXP_A_RXN7 EXP_A_RXN8 EXP_A_RXN9 EXP_A_RXN10 EXP_A_RXN11 EXP_A_RXN12 EXP_A_RXN13 EXP_A_RXN14 EXP_A_RXN15 EXP_A_RXP0 EXP_A_RXP1 EXP_A_RXP2 EXP_A_RXP3 EXP_A_RXP4 EXP_A_RXP5 EXP_A_RXP6 EXP_A_RXP7 EXP_A_RXP8 EXP_A_RXP9 EXP_A_RXP10 EXP_A_RXP11 EXP_A_RXP12 EXP_A_RXP13 EXP_A_RXP14 EXP_A_RXP15 EXP_A_TXN0 EXP_A_TXN1 EXP_A_TXN2 EXP_A_TXN3 EXP_A_TXN4 EXP_A_TXN5 EXP_A_TXN6 EXP_A_TXN7 EXP_A_TXN8 EXP_A_TXN9 EXP_A_TXN10 EXP_A_TXN11 EXP_A_TXN12 EXP_A_TXN13 EXP_A_TXN14 EXP_A_TXN15 EXP_A_TXP0

D40 D38 F34 G38 H34 J38 L34 M38 N34 P38 R34 T38 V34 W38 Y34 AA38 AB34 AC38 D34 F38 G34 H38 J34 L38 M34 N38 P34 R38 T34 V38 W34 Y38 AA34 AB38 F36 G40 H36 J40 L36 M40 N36 P40 R36 T40 V36 W40 Y36 AA40 AB36 AC40 D36 F40 G36 H40 J36 L40 M36 N40 P36 R40 T36 V40 W36 Y40 AA36 AB40

PEG_COMP SDVO Alternate Function PEG_D2R_N PEG_D2R_N PEG_D2R_N PEG_D2R_N PEG_D2R_N PEG_D2R_N PEG_D2R_N PEG_D2R_N PEG_D2R_N PEG_D2R_N PEG_D2R_N PEG_D2R_N PEG_D2R_N PEG_D2R_N PEG_D2R_N PEG_D2R_N PEG_D2R_P PEG_D2R_P PEG_D2R_P PEG_D2R_P PEG_D2R_P PEG_D2R_P PEG_D2R_P PEG_D2R_P PEG_D2R_P PEG_D2R_P PEG_D2R_P PEG_D2R_P PEG_D2R_P PEG_D2R_P PEG_D2R_P PEG_D2R_P PEG_R2D_C_N PEG_R2D_C_N PEG_R2D_C_N PEG_R2D_C_N PEG_R2D_C_N PEG_R2D_C_N PEG_R2D_C_N PEG_R2D_C_N PEG_R2D_C_N PEG_R2D_C_N PEG_R2D_C_N PEG_R2D_C_N PEG_R2D_C_N PEG_R2D_C_N PEG_R2D_C_N PEG_R2D_C_N PEG_R2D_C_P PEG_R2D_C_P PEG_R2D_C_P PEG_R2D_C_P PEG_R2D_C_P PEG_R2D_C_P PEG_R2D_C_P PEG_R2D_C_P PEG_R2D_C_P PEG_R2D_C_P PEG_R2D_C_P PEG_R2D_C_P PEG_R2D_C_P PEG_R2D_C_P PEG_R2D_C_P PEG_R2D_C_PIN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT69 69 69 69 69 69 69 69 69 69 69 69 69 69 69 69

D

SDVO_TVCLKIN# SDVO_INT# SDVO_FLDSTALL#

19 19 19 19

E26 LB_CLK C37 LA_DATA0* B35 LA_DATA1* A37 LA_DATA2* B37 LA_DATA0 B34 LA_DATA1 A36 LA_DATA2 G30 LB_DATA0* D30 LB_DATA1* F29 LB_DATA2* F30 LB_DATA0 D29 LB_DATA1 F28 LB_DATA2

19 19 19

LVDS

69 69 69 69 69 69 69 69 69 69 69 69 69 69 69 69

19 19 19

SDVO_TVCLKIN SDVO_INT SDVO_FLDSTALL

19 19 19

CTV-Out Signal Usage: Composite: DACA only S-Video: DACB & DACC only Component: DACA, DACB & DACC Unused DAC outputs must remain powered, but can omit filtering components. Unused DAC outputs should connect to GND through 75-ohm resistors. TV-Out Disable Tie DACx_OUT, IRTNx, and IREF to 1.5V power rail. Tie VCCD_TVDAC, VCCD_QTVDAC, VCCA_TVDACx, and VCCA_TVBG to 1.5V power rail. Tie VSSA_TVBG to GND. CRT Disable Tie R/R#/G/G#/B/B# and IREF to VCC Core rail, tie HSYNC and VSYNC to GND. Tie VCCA_CRTDAC to VCC Core rail, and tie VSSA_CRTDAC and VCC_SYNC to GND.

19 19 19

PCI-EXPRESS GRAPHICS

C

65 47 25 24 19 17 16 13 9 8 5 66 65 47 25 24 19 17 16 13 9 8 5 66 65 47 25 24 19 17 16 13 9 8 5 66 65 47 25 24 19 17 16 13 9 8 5 66 65 47 25 24 19 17 16 13 9 8 5 66 65 47 25 24 19 17 16 13 9 8 5 66 65 47 25 24 19 17 16 13 9 8 5 66

OUT OUT OUT OUT OUT OUT OUT

J20 TV_IREF B16 TV_IRTNA B18 TV_IRTNB B19 TV_IRTNC

TV

A16 TV_DACA_OUT C18 TV_DACB_OUT A19 TV_DACC_OUT

69 69 69 69 69 69 69 69 69 69 69 69 69 69 69 69

21 19 17 16 13 12 11 9 8 7 5 66 64 54 34 25 24 21 19 17 16 13 12 11 9 8 7 5 66 64 54 34 25 24 21 19 17 16 13 12 11 9 8 66 64 54 34 25 21 19 17 16 13 12 11 9 8 66 64 54 34 25 7 5 24 7 5 24

OUT OUT OUT OUT OUT OUT BI BI OUT

E23 CRT_BLUE D23 CRT_BLUE* C22 CRT_GREEN

21 19 17 16 13 12 11 9 8 7 5 66 64 54 34 25 24 21 19 17 16 13 12 11 9 8 7 5 66 64 54 34 25 24 19 19

C26 CRT_DDC_CLK C25 CRT_DDC_DATA G23 HSYNC J22 CRT_IREF H23 CRT_VSYNC

21 19 17 16 13 12 11 9 8 7 5 66 64 54 34 25 24

OUT OUT

VGA

B22 CRT_GREEN* A21 CRT_RED B21 CRT_RED*

SDVOB_RED# SDVOB_GREEN# SDVOB_BLUE# SDVOB_CLKN SDVOC_RED# SDVOC_GREEN# SDVOC_BLUE# SDVOC_CLKN

69 69 69 69 69 69 69 69 69 69 69 69 69 69 69 69

B

EXP_A_TXP1 EXP_A_TXP2 EXP_A_TXP3 EXP_A_TXP4 EXP_A_TXP5 EXP_A_TXP6 EXP_A_TXP7 EXP_A_TXP8 EXP_A_TXP9 EXP_A_TXP10 EXP_A_TXP11 EXP_A_TXP12 EXP_A_TXP13 EXP_A_TXP14 EXP_A_TXP15

SDVOB_RED SDVOB_GREEN SDVOB_BLUE SDVOB_CLKP SDVOC_RED SDVOC_GREEN SDVOC_BLUE SDVOC_CLKP

B

NB PEG / Video Interfaces

A

SYNC_MASTER=M1_MLB

SYNC_DATE=02/10/2006

NOTICE OF PROPRIETARY PROPERTYTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER REV.

A

APPLE COMPUTER INC.

DSCALE NONE

051-7023SHT

06 86

13

OF

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

65 64 60 59 57 56 53 51 48 43 23 22 21 20 19 17 14 10 5 4 37 36 34 33 29 28 27 26 25 24 79 78 70 66

PP3V3_S0

R1440110K

1

R144110K OMIT

D

5% 1/16W MF-LF 402 2

5% 1/16W MF-LF 2 402

U1200NC NC NC NC NC NC TP_NB_XOR_FSB2_H7 TP_NB_TESTIN_L NB_TV_DCONSEL0 NB_TV_DCONSEL1 NC19 19 19 19

DSM_CK0 SM_CK1 SM_CK2 SM_CK3 SM_CK0* SM_CK1* AY35 AR1 AW7 AW40 AW35 AT1 AY7 AY40 AU20 AT20 BA29 AY29 AW13 AW12 AY21 AW21 AL20 AF10 BA13 BA12 AY20 AU21 AV9 AT9 AK1 AK41 AF33 AG33 A27 A26 C40 D41 AE35 AF39 AG35 AH39 AC35 AE39 AF35 AG39 AE37 AF41 AG37 AH41 AC37 AE41 AF37 AG41

DDR MUXING

(D_PLLMON1#) (D_PLLMON1) (H_EDRDY#) (H_PCREQ#) (H_PLLMON1#) (H_PLLMON1) (H_PROCHOT#) (TESTIN#) (TV_DCONSEL0) (TV_DCONSEL1) (VSS_MCHDETECT) (LA_DATAN3) (LA_DATAP3) (LB_DATAN3) (LB_DATAP3)34 34 34 6 6 20 6 20

T32 RSVD1 R32 RSVD2 F3 RSVD3 F7 RSVD4 AG11 RSVD5 AF11 RSVD6 H7 RSVD7 J19 RSVD8 K30 RSVD9 J29 RSVD10 A41 RSVD11 A35 RSVD12 A34 RSVD13 D28 RSVD14 D27 RSVD15 K16 CFG0 K18 CFG1 J18 CFG2 F18 CFG3 E15 CFG4 F15 CFG5 E18 CFG6 D19 CFG7 D16 CFG8 G16 CFG9 E16 CFG10 D15 CFG11 G15 CFG12 K15 CFG13 C15 CFG14 H16 CFG15 G18 CFG16 H15 CFG17 J25 CFG18 K27 CFG19 J26 CFG20

945GM NBBGA(2 OF 10)

MEM_CLK_P MEM_CLK_P MEM_CLK_P MEM_CLK_P MEM_CLK_N MEM_CLK_N MEM_CLK_N MEM_CLK_N MEM_CKE MEM_CKE MEM_CKE MEM_CKE MEM_CS_L MEM_CS_L MEM_CS_L MEM_CS_L NC NC MEM_ODT MEM_ODT MEM_ODT MEM_ODT MEM_RCOMP_L MEM_RCOMP

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

28 28 29 29

28 28 29 29

RSVD

SM_CK2* SM_CK3* SM_CKE0 SM_CKE1 SM_CKE2 SM_CKE3 SM_CS0* SM_CS1* SM_CS2* SM_CS3* SMOCDCOMP0 SMOCDCOMP1 SM_ODT0 SM_ODT1 SM_ODT2

28 30 28 30 29 30 29 30

NC_NB_XOR_LVDS_A35 NC_NB_XOR_LVDS_A34 NC_NB_XOR_LVDS_D28 NC_NB_XOR_LVDS_D27 NB_BSEL NB_BSEL NB_BSEL NB_CFG NB_CFG NB_CFG NB_CFG NB_CFG NB_CFG NB_CFG NB_CFG NB_CFG NB_CFG NB_CFG TP_NB_CFG TP_NB_CFG NB_CFG NB_CFG NB_CFG NB_CFG NB_CFG PM_BMBUSY_L

28 30 28 30 29 30 29 30

IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN OUT

C

6 20 6 6 6 6 6 65 64 60 59 57 56 53 51 48 43 23 22 21 20 19 17 14 10 5 4 37 36 34 33 29 28 27 26 25 24 79 78 70 66

PP3V3_S0

6 20 6

R142015% 1/16W MF-LF 402 251 50 29 28 86 60 23 5

20 20 20

10K

IPU IPU IPU IPU IPU IPU IPU IPU IPU IPU IPU IPU IPU IPU IPU IPD IPD IPD

PP1V8_S3OUT OUT OUT OUT28 30 28 30 29 30 29 30

4 5 16 19 28 29 31 32 37 54 63 66

1

R141080.6

CFG

SM_ODT3 SMRCOMP* SMRCOMP SMVREF0 SMVREF1 G_CLKIN*

1% 1/16W MF-LF 2 402

CIN IN14 28 29 32 14 28 29 32

MEMORY_VREF MEMORY_VREF NB_CLK100M_GCLKIN_N NB_CLK100M_GCLKIN_P GND GND GND GND DMI_S2N_N DMI_S2N_N DMI_S2N_N DMI_S2N_N DMI_S2N_P DMI_S2N_P DMI_S2N_P DMI_S2N_P DMI_N2S_N DMI_N2S_N DMI_N2S_N DMI_N2S_N DMI_N2S_P DMI_N2S_P DMI_N2S_P DMI_N2S_PIN IN IN IN IN IN IN IN IN IN IN IN IN IN OUT OUT OUT OUT OUT OUT OUT OUT22 22 22 22 5 34 5 34

CLK

G_CLKIN D_REFCLKIN* D_REFCLKIN D_REFSSCLKIN* D_REFSSCLKIN DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 DMI_RXP0 DMI_RXP1 DMI_RXP2

C14150.1uF

1

1

C14160.1uF

1

R141180.6

20% 10V CERM 2 402

20% 10V 2 CERM 402

1% 1/16W MF-LF 2 402

23

IN IN

R143026 22 5

51 21 7 60 26 5

OUT IN

IN

PLT_RST_L

1

100

219 19 22 5 33 5

PM_THRMTRIP_L VR_PWRGOOD_DELAY NB_RST_IN_L_R TP_SDVO_CTRLCLK TP_SDVO_CTRLDATA NB_SB_SYNC_L CLK_NB_OE_L NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

G6 PW_THRMTRIP* AH33 PWROK AH34 RSTIN* H28 SDVO_CTRLCLK H27 SDVO_CTRLDATA K28 ICH_SYNC* H32 CLK_REQ* D1 NC0 C41 NC1 C1 NC2 BA41 NC3 BA40 NC4 BA39 NC5 BA3 NC6 BA2 NC7 BA1 NC8 B41 NC9 B2 NC10 AY41 NC11 AY1 NC12 AW41 NC13 AW1 NC14 A40 NC15 A4 NC16 A39 NC17 A3 NC18

PM

PM_EXTTS_L PM_DPRSLPVR

G28 PM_BM_BUSY* F25 PM_EXTTS0* H26 PM_EXTTS1*

22 22 22 22

BI BI OUT OUT

MISC DMI

5% 1/16W MF-LF 402

DMI_RXP3 DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3

5 22 5 22 22 22

B

5 22 5 22 22 22

B

NC

NB Misc Interfaces

A

SYNC_MASTER=M1_MLB

SYNC_DATE=02/10/2006

NOTICE OF PROPRIETARY PROPERTYTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER REV.

A

APPLE COMPUTER INC.

DSCALE NONE

051-7023SHT

06 86

14

OF

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2

1

D28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28

OMIT

OMIT

DSB_BS0 SB_BS1 SB_BS2 SB_CAS* SB_DM0 SB_DM1 SB_DM2 SB_DM3 SB_DM4 SB_DM5 SB_DM6 SB_DM7 SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 AT24 AV23 AY28 AR24 AK36 AR38 AT36 BA31 AL17 AH8 BA5 AN4 AM39 AT39 AU35 AR29 AR16 AR10 AR7 AN5 AM40 AU39 AT35 AP29 AP16 AT10 AT7 AP5 AY23 AW24 AY24 AR28 AT27 AT28 AU27 AV28 AV27 AW27 AV24 BA27 AY27 AR23 AU23 AK16 AK18 AR27

U1200BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

U1200SA_BS0 SA_BS1 SA_BS2 SA_CAS* SA_DM0 SA_DM1 SA_DM2 SA_DM3 SA_DM4 SA_DM5 SA_DM6 SA_DM7 SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 AU12 AV14 BA20 AY13 AJ33 AM35 AL26 AN22 AM14 AL9 AR3 AH4 AK33 AT33 AN28 AM22 AN12 AN8 AP3 AG5 AK32 AU33 AN27 AM21 AM12 AL8 AN3 AH5 AY16 AU14 AW16 BA16 BA17 AU16 AV17 AU17 AW17 AT16 AU13 AT17 AV20 AV12 AW14 AK23 AK24 AY14

C

28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28 28

B

28 28 28 28 28 28 28 28 28 28 28 28 28 28 28

MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ

AJ35 SA_DQ0 AJ34 SA_DQ1 AM31 SA_DQ2 AM33 SA_DQ3 AJ36 SA_DQ4 AK35 SA_DQ5 AJ32 SA_DQ6 AH31 SA_DQ7 AN35 SA_DQ8 AP33 SA_DQ9 AR31 SA_DQ10 AP31 SA_DQ11 AN38 SA_DQ12 AM36 SA_DQ13 AM34 SA_DQ14 AN33 SA_DQ15 AK26 SA_DQ16 AL27 SA_DQ17

945GM NBBGA(4 OF 10)

MEM_A_BS MEM_A_BS MEM_A_BS MEM_A_CAS_L MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DQS_P MEM_A_DQS_P MEM_A_DQS_P MEM_A_DQS_P MEM_A_DQS_P MEM_A_DQS_P MEM_A_DQS_P MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_N MEM_A_DQS_N MEM_A_DQS_N MEM_A_DQS_N MEM_A_DQS_N MEM_A_DQS_N MEM_A_DQS_N MEM_A_A MEM_A_A MEM_A_A MEM_A_A MEM_A_A MEM_A_A MEM_A_A MEM_A_A MEM_A_A MEM_A_A MEM_A_A MEM_A_A MEM_A_A MEM_A_A MEM_A_RAS_L NC NC MEM_A_WE_L

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

28 30 28 30 28 30

29 29 29 29

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

28 30 29 28 29 28 29 28 29 28 29 28 29 28 29 28 29 28 29 29

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

28 29 28 29 28 29 28 29 28 29 28 29 28 29 28 29 28 29 28 29 28 29 28 29 28 29 28 29 28 29 28 29 29

DDR SYSTEM MEMORY A

AM26 SA_DQ18 AN24 SA_DQ19 AK28 SA_DQ20 AL28 SA_DQ21 AM24 SA_DQ22 AP26 SA_DQ23 AP23 SA_DQ24 AL22 SA_DQ25 AP21 SA_DQ26 AN20 SA_DQ27 AL23 SA_DQ28 AP24 SA_DQ29 AP20 SA_DQ30 AT21 SA_DQ31 AR12 SA_DQ32 AR14 SA_DQ33 AP13 SA_DQ34 AP12 SA_DQ35 AT13 SA_DQ36 AT12 SA_DQ37 AL14 SA_DQ38 AL12 SA_DQ39 AK9 SA_DQ40 AN7 SA_DQ41 AK8 SA_DQ42 AK7 SA_DQ43 AP9 SA_DQ44 AN9 SA_DQ45 AT5 SA_DQ46 AL5 SA_DQ47 AY2 SA_DQ48 AW2 SA_DQ49 AP1 SA_DQ50 AN2 SA_DQ51 AV2 SA_DQ52 AT3 SA_DQ53 AN1 SA_DQ54 AL2 SA_DQ55 AG7 SA_DQ56 AF9 SA_DQ57 AG4 SA_DQ58 AF6 SA_DQ59 AG9 SA_DQ60 AH6 SA_DQ61 AF4 SA_DQ62 AF8 SA_DQ63

SA_DQS5 SA_DQS6 SA_DQS7 SA_DQS0* SA_DQS1* SA_DQS2* SA_DQS3* SA_DQS4* SA_DQS5* SA_DQS6* SA_DQS7* SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8 SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_RAS* SA_RCVENIN* SA_RCVENOUT* SA_WE*

AR36 SB_DQ18 AP36 SB_DQ19 BA36 SB_DQ20 AU36 SB_DQ21 AP35 SB_DQ22 AP34 SB_DQ23 AY33 SB_DQ24 BA33 SB_DQ25 AT31 SB_DQ26 AU29 SB_DQ27 AU31 SB_DQ28 AW31 SB_DQ29 AV29 SB_DQ30 AW29 SB_DQ31 AM19 SB_DQ32 AL19 SB_DQ33 AP14 SB_DQ34 AN14 SB_DQ35 AN17 SB_DQ36 AM16 SB_DQ37 AP15 SB_DQ38 AL15 SB_DQ39 AJ11 SB_DQ40 AH10 SB_DQ41 AJ9 SB_DQ42 AN10 SB_DQ43 AK13 SB_DQ44 AH11 SB_DQ45 AK10 SB_DQ46 AJ8 SB_DQ47 BA10 SB_DQ48 AW10 SB_DQ49 BA4 SB_DQ50 AW4 SB_DQ51 AY10 SB_DQ52 AY9 SB_DQ53 AW5 SB_DQ54 AY5 SB_DQ55 AV4 SB_DQ56 AR5 SB_DQ57 AK4 SB_DQ58 AK3 SB_DQ59 AT4 SB_DQ60 AK5 SB_DQ61 AJ5 SB_DQ62 AJ3 SB_DQ63

DDR SYSTEM MEMORY B

SA_DQS4

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

28 30 29 28 30 29 28 30 29 28 30 29 28 30 29 28 30 29 28 30 29 28 30 29 28 30 29 28 30 29 28 30 29 28 30 29 28 30 29 28 30 29 29

OUT

28 30 29 29 29

OUT

28 30 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29

MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ

AK39 SB_DQ0 AJ37 SB_DQ1 AP39 SB_DQ2 AR41 SB_DQ3 AJ38 SB_DQ4 AK38 SB_DQ5 AN41 SB_DQ6 AP41 SB_DQ7 AT40 SB_DQ8 AV41 SB_DQ9 AU38 SB_DQ10 AV38 SB_DQ11 AP38 SB_DQ12 AR40 SB_DQ13 AW38 SB_DQ14 AY38 SB_DQ15 BA38 SB_DQ16 AV36 SB_DQ17

945GM NBBGA(5 OF 10)

MEM_B_BS MEM_B_BS MEM_B_BS MEM_B_CAS_L MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DQS_P MEM_B_DQS_P MEM_B_DQS_P MEM_B_DQS_P MEM_B_DQS_P MEM_B_DQS_P MEM_B_DQS_P MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_N MEM_B_DQS_N MEM_B_DQS_N MEM_B_DQS_N MEM_B_DQS_N MEM_B_DQS_N MEM_B_DQS_N MEM_B_A MEM_B_A MEM_B_A MEM_B_A MEM_B_A MEM_B_A MEM_B_A MEM_B_A MEM_B_A MEM_B_A MEM_B_A MEM_B_A MEM_B_A MEM_B_A MEM_B_RAS_L NC NC MEM_B_WE_L

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

29 30 29 30 29 30

29 30 29 29 29 29 29 29 29 29

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

29 29 29 29 29 29 29 29 29 29 29 29 29 29 29 29

SB_DQS4 SB_DQS5 SB_DQS6 SB_DQS7 SB_DQS0* SB_DQS1* SB_DQS2* SB_DQS3* SB_DQS4* SB_DQS5* SB_DQS6* SB_DQS7* SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8 SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_RAS* SB_RCVENIN* SB_RCVENOUT* SB_WE*

C

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

29 30 29 30 29 30 29 30 29 30 29 30 29 30 29 30 29 30 29 30 29 30 29 30 29 30 29 30

OUT

29 30

OUT

29 30

B

NB DDR2 Interfaces

A

SYNC_MASTER=M1_MLB

SYNC_DATE=02/10/2006

NOTICE OF PROPRIETARY PROPERTYTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER REV.

A

APPLE COMPUTER INC.

DSCALE NONE

051-7023SHT

06 86

15

OF

8

7

6

5

4

3

2

1

8

7

6

5

4

3

2These connections can break without impacting part performance. OMITAD27 AC27 AB27 AA27 Y27 W27 V27 U27 T27 R27 AD26 AC26 AB26 AA26 Y26 W26 V26 U26 T26 R26 AD25 AC25 VCC_NCTF0 VCC_NCTF1 VCC_NCTF2 VCC_NCTF3 VCC_NCTF4 VCC_NCTF5 VCC_NCTF6 VCC_NCTF7 VCC_NCTF8 VCC_NCTF9 VCC_NCTF10 VCC_NCTF11 VCC_NCTF12 VCC_NCTF13 VCC_NCTF14 VCC_NCTF15 VCC_NCTF16 VCC_NCTF17 VCC_NCTF18 VCC_NCTF19 VCC_NCTF20 VCC_NCTF21 VCC_NCTF22 VCC_NCTF23 VCC_NCTF24 VCC_NCTF25 VCC_NCTF26 VCC_NCTF27 VCC_NCTF28 VCC_NCTF29 VCC_NCTF30 VCC_NCTF31 VCC_NCTF32 VCC_NCTF33 VCC_NCTF34 VCC_NCTF35 VCC_NCTF36 VCC_NCTF37 VCC_NCTF38 VCC_NCTF39 VCC_NCTF40 VCC_NCTF41 VCC_NCTF42 VCC_NCTF43 VCC_NCTF44 VCC_NCTF45 VCC_NCTF46 VCC_NCTF47 VCC_NCTF48 VCC_NCTF49 VCC_NCTF50 VCC_NCTF51 VCC_NCTF52 VCC_NCTF53 VCC_NCTF54 VCC_NCTF55 VCC_NCTF56 VCC_NCTF57 VCC_NCTF58 VCC_NCTF59 VCC_NCTF60 VCC_NCTF61 VCC_NCTF62 VCC_NCTF63 VCC_NCTF64 VCC_NCTF65 VCC_NCTF66 VCC_NCTF67 VCC_NCTF68 VCC_NCTF69 VCC_NCTF70 VCC_NCTF71 VCC_NCTF72 VCCAUX_NCTF0 AG27 VCCAUX_NCTF1 AF27 VCCAUX_NCTF2 AG26 VCCAUX_NCTF3 AF26 VCCAUX_NCTF4 AG25 VCCAUX_NCTF5 AF25 VCCAUX_NCTF6 AG24 VCCAUX_NCTF7 AF24 VCCAUX_NCTF8 AG23 VCCAUX_NCTF9 AF23 VCCAUX_NCTF10 AG22 VCCAUX_NCTF11 AF22 VCCAUX_NCTF12 AG21 VCCAUX_NCTF13 AF21 VCCAUX_NCTF14 AG20 VCCAUX_NCTF15 AF20 VCCAUX_NCTF16 AG19 VCCAUX_NCTF17 AF19 VCCAUX_NCTF18 R19 VCCAUX_NCTF19 AG18 VCCAUX_NCTF20 AF18 VCCAUX_NCTF21 R18 VCCAUX_NCTF22 AG17 VCCAUX_NCTF23 AF17 VCCAUX_NCTF24 AE17 VCCAUX_NCTF25 AD17 VCCAUX_NCTF26 AB17 VCCAUX_NCTF27 AA17 VCCAUX_NCTF28 W17 VCCAUX_NCTF29 V17 VCCAUX_NCTF30 T17 VCCAUX_NCTF31 R17 VCCAUX_NCTF32 AG16 VCCAUX_NCTF33 AF16 VCCAUX_NCTF34 AE16 VCCAUX_NCTF35 AD16 VCCAUX_NCTF36 AC16 VCCAUX_NCTF37 AB16 VCCAUX_NCTF38 AA16 VCCAUX_NCTF39 Y16 VCCAUX_NCTF40 W16 VCCAUX_NCTF41 V16 VCCAUX_NCTF42 U16 VCCAUX_NCTF43 T16 VCCAUX_NCTF44 R16 VCCAUX_NCTF45 AG15 VCCAUX_NCTF46 AF15 VCCAUX_NCTF47 AE15 VCCAUX_NCTF48 AD15 VCCAUX_NCTF49 AC15 VCCAUX_NCTF50 AB15 VCCAUX_NCTF51 AA15 VCCAUX_NCTF52 Y15 VCCAUX_NCTF53 W15 VCCAUX_NCTF54 V15 VCCAUX_NCTF55 U15 VCCAUX_NCTF56 T15 VCCAUX_NCTF57 R15

1

NCTF balls are Not Critical To FunctionPP1V05_S0

21 19 17 16 13 12 11 9 8 7 5 66 64 54 34 25 24

U1200945GM NBBGA(7 OF 10)

VSS_NCTF0 AE27 VSS_NCTF1 AE26 VSS_NCTF2 AE25 VSS_NCTF3 AE24 VSS_NCTF4 AE23 VSS_NCTF5 AE22 VSS_NCTF6 AE21 VSS_NCTF7 AE20 VSS_NCTF8 AE19 VSS_NCTF9 AE18 VSS_NCTF10 AC17 VSS_NCTF11 Y17 VSS_NCTF12 U17

NCTF

D

D

PP1V5_S0

25 47 65 5 8 9 13 17 19 24 66

PP1V05_S0 1.05V or 1.5VVCC_0 AA33 VCC_1 W33 VCC_2 P33 VCC_3 N33 VCC_4 L33 VCC_5 J33 VCC_6 AA32 VCC_7 Y32 VCC_8 W32 VCC_9 V32

64 66 5 7 8 17 19

1.05V, Internal Graphics: 3500mA Max 1.05V, External Graphics: 1500mA Max 9 11 12 13 16 21 24 25 34 54 1.5V, Internal Graphics: 5500mA MaxVCC_15 AA31 VCC_16 W31 VCC_17 V31 VCC_21 N31 VCC_22 M31 VCC_23 AA30 VCC_32 M30 VCC_33 L30 VCC_34 AA29 VCC_43 AB28 VCC_44 AA28 VCC_45 Y28 VCC_65 N24 VCC_66 M24 VCC_67 AB23 VCC_68 AA23 VCC_69 Y23 VCC_73 L23 VCC_74 AC22 VCC_75 AB22 VCC_81 L22 VCC_82 AC21 VCC_83 AA21 VCC_87 L21 VCC_88 AC20 VCC_89 AB20 VCC_95 L20 VCC_96 AB19 VCC_97 AA19 VCC_18 T31 VCC_19 R31 VCC_20 P31 VCC_24 Y30 VCC_25 W30 VCC_26 V30 VCC_27 U30 VCC_28 T30 VCC_29 R30 VCC_30 P30 VCC_31 N30 VCC_35 Y29 VCC_36 W29 VCC_37 V29 VCC_38 U29 VCC_39 R29 VCC_40 P29 VCC_41 M29 VCC_42 L29 VCC_46 V28 VCC_47 U28 VCC_48 T28 VCC_49 R28 VCC_50 P28 VCC_51 N28 VCC_52 M28 VCC_53 L28 VCC_54 P27 VCC_55 N27 VCC_56 M27 VCC_57 L27 VCC_58 P26 VCC_59 N26 VCC_60 L26 VCC_61 N25 VCC_62 M25 VCC_63 L25 VCC_64 P24 VCC_70 P23 VCC_71 N23 VCC_72 M23 VCC_76 Y22 VCC_77 W22 VCC_78 P22 VCC_79 N22 VCC_80 M22 VCC_84 W21 VCC_85 N21 VCC_86 M21 VCC_90 Y20 VCC_91 W20 VCC_92 P20 VCC_93 N20 VCC_94 M20 VCC_98 Y19 VCC_99 N19 VCC_100 M19 VCC_101 L19 VCC_102 N18 VCC_103 M18 VCC_104 L18 VCC_105 P17 VCC_106 N17 VCC_107 M17 VCC_108 N16 VCC_109 M16 VCC_110 L16

AB25 AA25 Y25 W25 V25 U25 T25 R25 AD24 AC24 AB24 AA24 Y24 W24 AR6 VCC_SM100 AP6 VCC_SM101 AN6 VCC_SM102 AL6 VCC_SM103 AK6 VCC_SM104 AJ6 VCC_SM105 AW15 VCC_SM74 AV15 VCC_SM75 AU15 VCC_SM76 AT15 VCC_SM77 AR15 VCC_SM78 AJ15 VCC_SM79 AJ14 VCC_SM80 AJ13 VCC_SM81 AH13 VCC_SM82 AK12 VCC_SM83 AJ12 VCC_SM84 AH12 VCC_SM85 AG12 VCC_SM86 AK11 VCC_SM87 BA8 VCC_SM88 AY8 VCC_SM89 AV1 VCC_SM106 AJ1 VCC_SM107 AW8 VCC_SM90 AV8 VCC_SM91 AT8 VCC_SM92 AR8 VCC_SM93 AP8 VCC_SM94 BA6 VCC_SM95 AY6 VCC_SM96 AW6 VCC_SM97 AV6 VCC_SM98 AT6 VCC_SM99 V24 U24 T24 R24 AD23 V23 U23 T23 R23 AD22 V22 U22 T22 R22 AD21 V21 U21 T21 R21 AD20 V20 U20 T20 R20 AD19 V19 U19 T19 AD18 AC18 AB18 AA18 Y18 W18 V18 U18 T18

VCC_10 P32 VCC_11 N32

VCC_12 M32 VCC_13 L32 VCC_14 J32

BGA

OMITAU34 VCC_SM8 AT34 VCC_SM9 AR34 VCC_SM10 BA30 VCC_SM11

AY30 VCC_SM12 AW30 VCC_SM13 AV30 VCC_SM14

AU30 VCC_SM15 AT30 VCC_SM16 AR30 VCC_SM17

AP30 VCC_SM18 AN30 VCC_SM19 AM30 VCC_SM20

AM29 VCC_SM21 AL29 VCC_SM22 AK29 VCC_SM23

AJ29 VCC_SM24 AH29 VCC_SM25 AJ28 VCC_SM26

AH28 VCC_SM27 AJ27 VCC_SM28 AH27 VCC_SM29

BA26 VCC_SM30 AY26 VCC_SM31 AW26 VCC_SM32 AV26 VCC_SM33

AU26 VCC_SM34 AT26 VCC_SM35 AR26 VCC_SM36

AJ26 VCC_SM37 AH26 VCC_SM38 AJ25 VCC_SM39

AH25 VCC_SM40 AJ24 VCC_SM41 AH24 VCC_SM42

BA23 VCC_SM43 AJ23 VCC_SM44 BA22 VCC_SM45

AY22 VCC_SM46 AW22 VCC_SM47 AV22 VCC_SM48

AU22 VCC_SM49 AT22 VCC_SM50 AR22 VCC_SM51

AP22 VCC_SM52 AK22 VCC_SM53 AJ22 VCC_SM54 AK21 VCC_SM55

AK20 VCC_SM56 BA19 VCC_SM57 AY19 VCC_SM58

AW19 VCC_SM59 AV19 VCC_SM60 AU19 VCC_SM61

AT19 VCC_SM62 AR19 VCC_SM63 AP19 VCC_SM64

AK19 VCC_SM65 AJ19 VCC_SM66 AJ18 VCC_SM67

AJ17 VCC_SM68 AH17 VCC_SM69 AJ16 VCC_SM70

NB_VCCSM_LF4 NB_VCCSM_LF5

1

C16150.47uF

66 63 54 37 19 14 5 4 32 31 29 28

PP1V8_S3

AH16 VCC_SM71 BA15 VCC_SM72 AY15 VCC_SM73

AU41 VCC_SM0 AT41 VCC_SM1

AM41 VCC_SM2 AU40 VCC_SM3 BA34 VCC_SM4

AY34 VCC_SM5 AW34 VCC_SM6 AV34 VCC_SM7

C1614 10.47uF20% 6.3V CERM-X5R 2 402

B

A

8

VCC1

C

1.8V Max Current Speed 1 Channel 2 Channel 400MTs 1300mA 2400mA 533MTs 1500mA 2800mA 667MTs 1700mA 3200mA

U1200

(6 OF 10)

945GM NB

C

C16130.47uF

20% 2 6.3V CERM-X5R 402

NB_VCCSM_LF2 NB_VCCSM_LF1

20% 6.3V 2 CERM-X5R 402

Layout Note: Place near pin BA23

C1620 110uF20% 6.3V X5R 2 603

1

C162110uF

1

C16100.47uF Layout Note: Place near pin BA15

C1612 10.47uF20% 6.3V CERM-X5R 2 402

1

C16110.47uF

20% 6.3V 2 X5R 603

20% 6.3V 2 CERM-X5R 402

20% 6.3V 2 CERM-X5R 402

Layout Note: Place in cavity

B

NB Power 1SYNC_MASTER=M1_MLB SYNC_DATE=02/10/2006NOTICE OF PROPRIETARY PROPERTYTHE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER REV.

A

APPLE COMPUTER INC.

DSCALE NONE

051-7023SHT

06 86

16

OF

7

6

5

4

3

2

1

8

7

6

570mA Max VCCA_CRTDAC/VCCSYNC GND GND 60mA Max19

4OMIT PP1V05_S0 800mA Max

3

2

1

H22 VCCSYNC C30 VCC_TXLVDS0 B30 VCC_TXLVDS1 A30 VCC_TXLVDS2 AJ41 VCC3G0 AB41 VCC3G1 Y41 VCC3G2 V41 VCC3G3 R41 VCC3G4 N41 VCC3G5 L41 VCC3G6 AC33 VCCA_3GPLL G41 VCCA_3GBG 2mA H41 VSSA_3GBG F21 VCCA_CRTDAC0 E21 VCCA_CRTDAC1 G21 VSSA_CRTDAC B26 VCCA_DPLLA C39 VCCA_DPLLB AF1 VCCA_HPLL A38 VCCA_LVDS B39 VSSA_LVDS AF2 VCCA_MPLL H20 VCCA_TVBG G20 VSSA_TVBG E20 VCCA_TVDACC0 F20 VCCA_TVDACC1 C20 VCCA_TVDACB0 D20 VCCA_TVDACB1 E19 VCCA_TVDACA0 F19 VCCA_TVDACA1 AH1 VCCD_HMPLL0 AH2 VCCD_HMPLL1 A28 VCCD_LVDS0 B28 VCCD_LVDS1 C28 VCCD_LVDS2

U1200945GM NBBGA(8 OF 10)

VTT0 AC14 VTT1 AB14 VTT2 W14 VTT3 V14 VTT4 T14 VTT5 R14 VTT6 P14 VTT7 N14 VTT8 M14 VTT9 L14 VTT10 AD13 VTT11 AC13 VTT12 AB13 VTT13 AA13 VTT14 Y13 VTT15 W13 VTT16 V13 VTT17 U13 VTT18 T13 VTT19 R13 VTT20 N13 VTT21 M13 VTT22 L13 VTT23 AB12 VTT24 AA12 VTT25 Y12 VTT26 W12 VTT27 V12 VTT28 U12 VTT29 T12 VTT30 R12 VTT31 P12 VTT32 N12 VTT33 M12 VTT34 L12 VTT35 R11 VTT36 P11 VTT37 N11 VTT38 M11 VTT39 R10 VTT40 P10 VTT41 N10 VTT42 M10 VTT43 P9 VTT44 N9 VTT45 M9 VTT46 R8 VTT47 P8 VTT48 N8 VTT49 M8 VTT50 P7 VTT51 N7 VTT52 M7 VTT53 R6 VTT54 P6 VTT55 M6 VTT56 A6 VTT57 R5 VTT58 P5 VTT59 N5 VTT60 M5 VTT61 P4 VTT62 N4 VTT63 M4 VTT64 R3 VTT65 P3 VTT66 N3 VTT67 M3 VTT68 R2 VTT69 P2 VTT70 M2 VTT71 D2 VTT72 AB1 VTT73 R1 VTT74 P1 VTT75 N1 VTT76 M1

5 7 8 9 11 12 13 16 17 19 21 24 25 34 54 64 66

PP1V5_S0_NB_VCC3G

19 77 76 66 65 62 19 5

PP1V5_S0_NB_VCCA_3GPLL PP2V5_S0 GND PP1V05_S0 GND

Max

21 19 17 16 13 12 11 9 8 7 5 66 64 54 34 25 24

See VCCSYNC

19 19 19

TP_NB_VCCA_DPLLA TP_NB_VCCA_DPLLB PP1V5_S0_NB_VCCA_HPLL GND NC_GND_NB_VSSA_LVDS PP1V5_S0_NB_VCCA_MPLL PP1V5_S0 GND PP1V5_S0 PP1V5_S0 PP1V5_S0 PP1V5_S0 GND 20mA Max

50mA Max 50mA Max 45mA Max 10mA Max 45mA Max

19

19

65 47 25 24 19 17 16 13 9 8 5 66

65 47 25 24 19 17 16 13 9 8 5 66

120mA Max

65 47 25 24 19 17 16 13 9 8 5 66

C

65 47 25 24 19 17 16 13 9 8 5 66

POWER

D

1500mA Max VCC3G/3GPLL

D

C

65 47 25 24 19 17 16 13 9 8 5 66

150mA Max

65 47 25 24 19 17 16 13 9 8 5 66 66 65 64 60 59 57 56 53 51 48 24 23 22 21 20 19 14 10 5 4 43 37 36 34 33 29 28 27 26 25 79 78 70

PP1V5_S0 PP3V3_S0 40mA Max PP1V5_S0 PP1V5_S0 1900mA Max

D21 VCCD_TVDAC A23 VCC_HV0 B23 VCC_HV1 B25 VCC_HV2 H19 VCCD_QTVDAC AK31 VCCAUX0 AF31 VCCAUX1 AE31 VCCAUX2 AC31 VCCAUX3 AL30 VCCAUX4 AK30 VCCAUX5 AJ30 VCCAUX6 AH30 VCCAUX7 AG30 VCCAUX8 AF30 VCCAUX9 AE30 VCCAUX10 AD30 VCC