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Fi~. 2.9 Shapes of etched deepings in (llO)-silicon

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Process FeaturesThe c,MOSOl process is a 1.6 ~m Poly Silicon gate CMOS technology.It uses a 12 ~ p-type epi layer on four inch low ohmic p-type subsb"ate wafers. The n-channel device is made directly in the epi and the p-channel device is made in an N-well.For the n.,channel devices precautions are taken ( Ldd implants) to prevent hot electrongate oxide degradation mechanisms.

Some further characteristics:

Single PolyDouble MetalGate Oxide ThicknessMinimum Gate LengthMinimum Pitch for Metal 1 and Metal 2Minimum Pitch for Poly SiliconNominal Supply VoltageMaximum RatingsMOS Transistors W /1..=20/1.6 @ 27 °c

ThresholdVoltages. typical valuesVt_oVt-p

Saturation Cunents @IVdsl=5V, IVgsl=5VIds,sat_nIds,sat_p

2Snm

1.6~m4.8 JJ.m

4.0~5.0 V-0.5 to 6.5 V

.

.

..

.

.

0.75 V-1.10 V

, IVbsl=OV4.75 mA1.90 mA

Process FlowThe eMOSOl process is a conventional CMOS process, based on LOCOS. In thefollowing cross sections the process flow is shown for the construction of a basic CMOSinvener, if the masks NW, OD, NWI, PS, SP, SN, CO, IN, COS and INS are applied.For a detailed definition of these mask names see chapter 4.

Short desription or the subsequent process steps:The staning material is a p-type substrate with a 12 ~m epitaxial layer.A 660 nm thick oxide is grown and NW areas are defined. Phosphor is implanted and themasking oxide layer is removed. Now the pad oxide stack, consisting of 40 nm oxideand 100 nm nitride is defined by the OD mask.Before growing the LOCOS oxide an NWI mask is applied The NW region is maskedby both the pad oxide stack and the photoresist layer and this is thick enough to protectthe NW for the two following boron implantations. The first one with low energy is the(parasitic) channel stopper, which is only present outside the pad oxide stacks. Thesecond implantation with high energy is the n-channel anti punch through implant Dueto its high energy the boron implant can cross the pad oxide stack.Now the LOCOS oxide is grown and the pad oxide is removed. A 25. nm gateoxide isgrown followed by a boron threshold adjust implant. Now poly silicon is deposited,which is made low ohmic by phosphorous doping and the transistor gates, poly siliconresistors and poly tracks are defined by the PS mask. The SN mask is applied and aphosphor implantation fonns the ODN+ areas for the source or drain of n-channelMOSTs and N+ resistors. A gate spacer technology is used consisting of a depositedTEOS oxide layer, which enables the formation of a so called D(ouble)D(iffused)D(rain)or L(igthly)DD. The SN mask is applied again and the second implant is arsenic. Nowthe SP mask is applied and boron is implantated, which forms the ODP+ areas for thesource or drain of p-channel MOSTs and P+ resistors.

The previous steps are defined as front-end processing and all the semiconductor devicesare made. What rests is 'just' the connection between them and to the outside world.The following steps are called back-end processing.

A lOOnm TEOS layer and a 6OOnm B(oron)P(hosphor)S(ilicate)G(lass) layer aredeposited. The latter is reflowed to planarize the topology. The CO mask is applied andcontact windows are etched to reach ODN+, ODP+ and PS regions. The wafer iscovered with aluminium and the IN mask defines the first interconnect layer. Thenplasma oxide is deposited, which serves as insulating layer. The cas mask is appliedand contact windows are etched. The wafer is coverd again with aluminium and the INSmask is applied to define the second interconnect layer. On request the last step in theprocess can be the deposition of a scratch protection layer, which requires the CB maskfor definition of the contact openings to the bondpads.

-

~

.It

DevicesDevice Types

The following devices are available in the

Transistorsn-channel enhancement MaS transistorp-channel enhancement MaS transistorvertical pnp transistor (poor man's bipolar)

Diodesn+/p- junction diode (ODN+/SUB)p+/n- junction diode (ODP+/NW)n-/p- junction diode (NW/SUB;)

Resistors/ConductorsPoly Silicon resistor (PS)Diffused resistors (ODN+ and ODP+)N-Well resistors (NW)First metal resistor (IN)Second metal resistor (INS)

CapacitorsIN-PS plate capacitorINS-IN plate capacitorINS/PS - IN sandwich plate capacitorPS-ODN+ capacitor

Other resistorswhich are - not

variation.

and capacitors should not beexplicitly monitored and have

-

C?l"10S01 process:

used.values

Theythat

just parasitic elements,change due to process

arecan

An

Mask Names

The (ollowing mask names are reserved and can not be used for other purposes thanindicated.

Coding masks for the circuit designer to use:NW - N-Well definitionOD - Oxide Definition for creating active areaPS - Poly Silicon definitionSP - Shallow P, P+ implantation definitionSN - Shallow N, N+ implantation definitionCO - COntact window definition of IN to OD or IN to PSIN - INterconnect definition of first metal layerCOS - COntact window Second, definition of via from INS to ININS - INterconnect Second, definition of second metal layerCB - Contact window Bondpad, definition of scratch protection openings

Additionally the following "software" masks can be specified toexplicitly define the functionality of the layers underneath:This may be useful for layout extraction programs.GRN - Guard Ring N, NW/N+ definitionGRP - Guard Ring P, P+ definitionRNW - Resistor NW definitionRPD - Resistor Poly or 00 definition

Physical masks, used for mask making:NW, OD, NWI (*), PS, SP, SN, CO (**), IN, COS, INS, CB.(*) Inverse NW mask. Necessary because only one type photoresist is used.(**) Note that the CO mask can be a merged mask from the three different

contact types CON, COP and CPS as specified below.CON - Contact hole for connection of IN with ODN+COP - Contact hole for connection of IN with OOP+CPS - Contact hole for connection of IN with polysilicon

-

~

J J

~~i Mask Numbering

In ge.!{".::iil the following convention is used for themasks in a Gds2 output layer file \

Definition of mask numbering in Gds2 for the DIMOSOI process:

There are special mask layers, e.g. plottexts, which are not used formaking physical masks.

-

numbering of the

'"

A.. ?~

-- . 4.,.~~ Layout design rules '

Definitions used in the layout design rules

thin oxide - OD covered with PS.

OD ~ - OD covered with SN.OD P+- - OD covered with SP.

cold 'N-well - N-well connected to the most positive voltage (VDD).hot N-well - N-well not connected to the most positive voltage.

cold diffusions:outside the N -wellinside the N-well

hot diffusions:hot W diffusion

hot P+ diffusion

Terminology and n

O. general rule without specification of geometry in ~m.

1. width or dimension of A

2. space between two regions of A

3. overlap of B over A (in all directions)

4. separation from A to B

5. extension of A edge beyond B edge (in 1 or more directions)

6. extension of A region inside B region (in 1 or more directions)

7. rule for the specified layer. concerning other masks

Note: All specified geometries must be interpreted as Dimensions On Silicon.

~

..

a diffusion which has the samepotential as the substrate..a diffusion which has the same potential as the N-wel.

all N+ diffusion regions outside the N-well which have apotential not equal to the substrate voltageall P+ diffusion regions inside the N-well which have apotential not equal to the N -well potential.

--

umbering used in the layout design rules

~

.,.1'2.

Level: NW. N.Well

NW.l.l The dimensions of NW are detennined by other rules,however the minimum dimensions are

NW.2.1 Minim!with at

NW .2.2 Minimum space between two NW regions,both connected to VDD (cold wells)Merge if spacing is less.

-

A 8.0 ~

between two NW regionsnot connected to VDD (hot well)

urn spaceleast one B 12.8 J.1m

C 8.0 ~m

c. .

Figure 4.3.2. NW Design Rules

-

~4

-

Level: OD - Oxide Definition

CD.O.! CD areas have to be covered with either SN or SP (see SN and SP rules)

CD.I.I Minimum CD width for interconnect J

CD.2.1 Minimum space between two aD regions .1(both regions are inside or outside an N-well)

OD.3.t urn NW overlap over OD P+Minim

OD.3.2 Minimum NW overlap over OD N+ (N-well contact)

Minimum separation from aD N+ to a cold N-well

Minimum separation from OD N+ to a hot N-well

Minimum separation from aD P+ to NW (substrate

OD.4.1

OD.4.2

OD.4.3

.

A 1.6~m

.8 3.2 ~m

c

C

D

D

4.8~

0.0 J1rn

4.8 J1rn

9.6 J1rn

4.8~Econtact)

00 Design RulesFigure 4.3.3..- .

it::;