M PICREF-1 · The battery boost voltage is set slightly lower than the rectiﬁed AC input voltage so that, under normal condi-tions, the rectiﬁed AC input power provides power

M

Uninterruptible Power Supply Reference Design

PICREF-1

INTRODUCTION

At times, power from a wall socket is neither clean noruninterruptible. Many abnormalities such as blackouts,brownouts, spikes, surges, and noise can occur. Underthe best conditions, power interruptions can be aninconvenience. At their worst, they can cause loss ofdata in computer systems or damage to electronicequipment.

It is the function of an Uninterruptible Power Supply(UPS) to act as a buffer and provide clean, reliablepower to vulnerable electronic equipment. The basicconcept of a UPS is to store energy during normaloperation (through battery charging) and releaseenergy (through DC to AC conversion) during a powerfailure.

UPS systems are traditionally designed using analogcomponents. Today these systems can integrate amicrocontroller with AC sine wave generation, offeringthe many benefits listed below.

PIC17C43 Microcontroller Benefits

• High Quality Sine Wave - High throughput allows for high quality output

• Flexibility - core control features and operations can be changed with software modifications only

• Transportability of Design• Variable Loop Response• Digital Filtering• Parts and Complexity Reduction• Peripheral Integration• Ease of Interfacing• Testability• Time to Market

PICREF-1 OVERVIEW

The Microchip Technology PICREF-1 UPS ReferenceDesign offers a ready-made uninterruptible power sup-ply solution with the flexibility of a microcontroller.

The PIC17C43 microcontroller handles all the controlof the UPS system. The PIC17C43 is unique becauseit provides a high performance and low cost solution notfound in other microcontrollers.

The PIC17C43 PWM controls an inverter whose out-put, when filtered, results in a sinusoidal AC outputwaveform. Fault signaling can be initiated internal orexternal to the PIC17C43 depending on the type offault. A fault will disable the entire inverter. The outputvoltage and current will be monitored by the PIC17C43to make adjustments “real-time” to correct for DC offsetand load changes.

The PIC17C43 controls all module synchronization aswell as inverter control and feedback. The PIC17C43uses zero crossing for synchronization of input voltage/phase to output voltage/phase. All internal module syn-chronization is handled by the PIC17C43.

The control algorithms and software are written in C formaintainability and transportability.

PICREF-1 Key Features

• True UPS Topology• True Sinusoidal Output• Point-to-Point Output Correction• 1400 VA Rating• 120/240 V Input

Information contained in this publication is intended through suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Inc. with respect to the accu-racy or use of such information, or infringement of patents arising from such use or otherwise. It is the responsibility of each user to ensure that each UPS is adequately designed, safe, and compatible with all conditions encountered during its use. “Typical” parameters can and do vary in different applications. All operating parameters, including “Typicals”, must be validated for each customer application by the customer's technical experts. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights.

1997 Microchip Technology Inc. DS30450C-page 1

PICREF-1

TABLE OF CONTENTS

System Overview .......................................................................................................................................3Hardware Overview ...................................................................................................................................6Software Overview .....................................................................................................................................9Test Results .............................................................................................................................................13Design Background .................................................................................................................................15Design Modifications ...............................................................................................................................17Appendix A: System Specifications .......................................................................................................19Appendix B: Schematics..........................................................................................................................19Appendix C: Software Listing..................................................................................................................37Appendix D: PCB Layout & Fab Drawing ...............................................................................................41Appendix E: Bill Of Materials (BOM).......................................................................................................45Appendix F: UPS Demo Unit....................................................................................................................53

ACKNOWLEDGMENTS

Project Lead Engineer:Robert Schreiber, Microchip Technology

Reference Design Documentation:Beth McLoughlin, Microchip Technology

System and Code Development:Airborne Power (Consultants)Guy Gazia ([email protected]),David Karipides ([email protected]),Terry Allinder

DS30450C-page 2 1997 Microchip Technology Inc.

PICREF-1

SYSTEM OVERVIEW

The power flow for the PICREF-1 system is shown inFigure 1. The Uninterruptible Power Supply (UPS) iseither supplying power based on the input power, if theunit is plugged in, or based on the batteries.

Power Flow

When available, the input power is filtered for commonmode noise and is protected from surges/spikes byinput power protection circuitry. The power then goesinto the power factor correction (PFC) module whichforces the input current to be sinusoidal so that powerutilization is more efficient. The PFC module also recti-fies the input AC power to produce voltage-regulatedDC power which is used by the rest of the functionalmodules.

This rectified AC power is OR’d through diodes with theDC voltage generated from the battery boost circuit.The battery boost voltage is set slightly lower than therectified AC input voltage so that, under normal condi-tions, the rectified AC input power provides power tothe load. Once the voltage from the rectified AC inputsource drops below the battery boost DC voltage, thepower is drawn from the battery boost module. In thismode the battery charger is turned off so as not tocause an additional load on the battery (i.e., so the bat-tery is not charging itself).

The OR’d DC bus voltage is fed into the free runningchopper which both isolates the DC bus from theH-Bridge inverter and doubles the DC voltage for theinverter to operate at 120 or 240 volts. The output of thechopper is filtered to remove switching noise and thenfed into the H-Bridge.

The PIC17C43 microcontroller controls the inverter bydriving the H-bridge through Hardware Protection cir-cuitry and Insulated Gated Bipolar Transistor (IGBT)drivers. The output of the H-bridge is filtered and drivesthe load with an AC sine wave that is synchronized tothe input AC voltage.

An A/D converter provides feedback to the PIC17C43for output monitoring.

All module synchronization, control, and fault detectionare handled through the PIC17C43.

FIGURE 1: PICREF-1 UNINTERRUPTIBLE POWER SUPPLY (UPS) BLOCK DIAGRAM

PowerFactor

Correction &Rectification

Battery Boost Circuit

Input Power 120/240 V 50/60 Hz

Input Power

Protection

Output Power 120/240 V50/60 Hz

PIC17C43

A/D

ChopperSync

PFCSync

BBCSync

ZeroCrossing

Fault

PWMEnable

Pos_Neg

Voltage Sense

Current Sense

FreeRunning Chopper

H-Bridge (Inverter)

Output Filtering

Hardware Protection

IGBT Drivers

Inverter Control

Battery & Battery Charger

Power Flow

Charge Control

Inverter Fault


PICREF-1

Inverter Operation

The H-bridge circuit works by generating the separatepositive and negative cycles needed for sine wave gen-eration. The PIC17C43 controls all signals to the hard-ware protection circuitry and IGBT drivers and thuscontrols the generation of the sine wave (Figure 2).

Software Fault / No Enable

Driving the FAULT HIGH will disable the inverter’spower stage.

Hardware Fault

The hardware protection logic automatically disablesthe inverter’s power stage in the event any of the IGBT’shave gone out of saturation, i.e., an external short wasplaced on the H-Bridge which was so severe that anappreciable voltage was developed across one of theswitches that was on. This feature prevents a shortfrom immediately destroying the switching devices.

As long as none of the out-of-saturation signals(Q9/Q10/Q11/Q12 OC Alarm) are LOW, the powerstage can be enabled. When the PIC17C43 is first pow-ered up, the ENABLE line (PORTC, bit0) will be in ahigh impedance state. A pull-down resistor keeps theENABLE line held LOW so that any spurious signalswhich may be generated while the system is initializingwill not drive the H-Bridge. If any of the out-of-satura-tion signals go LOW, the FAULT signal goes HIGH,reporting to the PIC17C43 that an external faultoccurred. This will disable the H-Bridge.

The inverter may be re-enabled by cycling the ENABLEline LOW and then HIGH to reset the flip-flop and allowthe PIC17C43 to drive the H-Bridge again.

The PIC17C43 microcontroller and hardware protec-tion circuits are found on the PICREF-1 Inverter ControlCard. IGBT driver circuits are found on the InverterDrive Card. Schematics for these cards can be found inAppendix B.

FIGURE 2: INVERTER OPERATION

Q9 OC Alarm

DCBus

AC Output

AC HI

AC LO

Q9 Q10

Q11 Q12

L1

L2

Q9_G

Q11_G Q12_G

Q10_G

PWM

POS_NEG

FAULT

ENABLE

Q9 Drive

Q11 Drive

Q12 Drive

Q10 Drive

Output Filtering

PIC17C43 Hardware Protection

SimplifiedH-Bridge(Inverter)

IGBT Drivers

Q9_C

Q9_G

Q11_G

Q12_G

Q10_G

Q9_C

Q11_C

Q10_C

Q12_C

Q10 OC Alarm Q10_C

Q11 OC Alarm Q11_C

Q12 OC Alarm Q12_C


PICREF-1

Normal Operation

In normal operation (FAULT is LOW and ENABLE isHIGH), the states of Q9, Q10, Q11 and Q12 are deter-mined by POS_NEG and PWM signals. These signalspass through steering logic which produce transistor(QX) drive signals (see Inverter Control Card schemat-ics in Appendix B).

The steering logic causes the IGBT pairs Q9,Q11 andQ10,Q12 to be held in the OFF state for one microsec-ond before allowing them to switch ON. This preventsshoot-through from occurring during changes of statesfrom the PWM. This is necessary because of the rela-tively slow turn off times for the IGBTs. This preventscomplementary pairs from being ON at the same time.

Table 1 describes the drive values for different input val-ues of POS_NEG and PWM.

TABLE 1 INVERTER CONTROL SIGNALS

The transistor drive signals are fed into the IGBT Drivecircuits (Inverter Drive Card) to determine the state (ONor OFF) of each transistor. A drive signal of ‘1’ corre-sponds to an IGBT being OFF, and a drive signal of ‘0’corresponds to an IGBT being ON.

From Table 1, when the POS_NEG signal is 0, Q10 isheld ON, Q12 is held OFF, and Q9,Q11 are modulatedin a complementary fashion with the PWM signal. Sim-ilarly, when POS_NEG is 1, Q9 is held ON, Q11 is heldOFF, and Q10,Q12 are modulated in a complementaryfashion with the PWM signal. Therefore, the differentialoutput signal from the H-Bridge has an average valueproportional to the duty cycle of the PWM signal and apolarity set by the POS_NEG signal. The output filtersmooths this pulse train and all that remains is the aver-age value of the PWM signal (Figure 3).

To understand how the PIC17C43 determines the mod-ulation for the H-Bridge transistors, please see the sec-tion Software Overview.

FIGURE 3: INVERTER WAVEFORMS

POS_NEG PWMQ9

DriveQ10

DriveQ11

DriveQ12

Drive

0 0 0 0 1 1

0 1 1 0 0 1

1 0 0 0 1 1

1 1 0 1 1 0

QX Drive = 1 -> transistor QX is OFFQX Drive = 0 -> transistor QX is ON

PWM

POS_NEG

AC Output

T

AC HI/LO

T


PICREF-1

HARDWARE OVERVIEW

This section describes the PICREF-1 hardware andhow it functions in the UPS system. Hardware detail(schematics) may be found in Appendix B.

Microcontroller

A typical analog UPS solution is shown in Figure 5. Byusing a microcontroller, this design can be greatly sim-plified. That is, the functions of the DC offset amp, erroramp and PWM drive can be implemented in software.Therefore, modifications to the design are madethrough code changes, not component changes.

In addition, there is no need to generate an externalsine wave reference; this is embedded in the microcon-troller.

The PIC17C43 is the heart of PICREF-1 (Figure 4).The high performance of the Harvard architecture givesthe user the throughput needed for high quality sinewave generation. The single-cycle multiply meansfaster program execution and response to waveformchanges. Only 8 bits of the 10-bit PWM is needed toresolve a high quality output waveform.

In addition, using a PIC17C43 microcontroller enablesthe customer to use the same core control for multipleproducts (transportability) and add further enhance-ments through software changes (flexibility).

Use of the PIC17C43 means the availability of variableloop response, or software that can adjust to differentloads. Digital filtering is another microcontroller benefitas it reduces components that would be necessary foranalog filtering.

Also, the high level of peripheral integration (from thePIC17C43’s USART and PWM modules) furtherreduces the complexity of the design. This reduces thedevelopment time and the components needed.

Converting from analog to digital also enhances therepeatability, manufacturability, and flexibility of thedesign. Product test is made easier as well, andtime-to-market is reduced.

FIGURE 4: PIC17C43 PINOUT

FIGURE 5: TYPICAL ANALOG SOLUTION

PIC

17C4X

RD0/AD8RD1/AD9RD2/AD10RD3/AD11RD4/AD12RD5/AD13RD6/AD14RD7/AD15MCLR/VPP

VSS

RE0/ALERE1/OERE2/WRTESTRA0/INTRA1/T0CKIRA2RA3RA4/RX/DTRA5/TX/CK

VDD

RC0/AD0RC1/AD1RC2/AD2RC3/AD3RC4/AD4RC5/AD5RC6/AD6RC7/AD7

VSS

RB0/CAP1RB1/CAP2

RB2/PWM1RB3/PWM2

RB4/TCLK12RB5/TCLK3

RB6RB7

OSC1/CLKINOSC2/CLKOUT

1234567891011121314151617181920

4039383736353433323130292827262524232221

PDIP, CERDIP, Windowed CERDIP

DC-DCConverter

+200VdcH-BRIDGE

-

+

-

+

-

+

DIFFDC OFFSETCORRECTION

Q1

ERROR AMP+Vcc

-Vcc

PWM

Q3

Q2

Q4

+V

-V

DRIVE A

DRIVE B

SINE WAVE REFERENCE

DRIVE

DRIVE A

DRIVE B

DRIVE B

DRIVE A

DCBus

ACOut

AMP


PICREF-1

Input Power Monitoring

The input power is monitored to determine the value ofthe output waveform. So, if 120V is input, 120V will beoutput, and if 240V is input, 240V will be output.

The 120V/240V relay (power switch) shown in theschematics (Appendix B) has not been implemented asthis would have been part of the software “housekeep-ing” functions.

Input Power Protection

The input filtering circuit provides input protection forthe UPS and isolation from the power source. The maincomponents of the circuit are the MOV, which sup-presses surges/spikes, and the input power line filter.The common mode filter prevents UPS switching noisefrom getting back onto the main power lines.

FIGURE 6: INPUT FILTERING CIRCUIT

EMI/RFI filtering and spike/surge protection are veryimportant in a robust UPS design. Input filtering isheavily dependent upon design specifics (shielding,grounding, layout, etc.), so following sound design prin-ciples and testing is the only way to verify actual perfor-mance.

Power Factor Correction & Rectification

This portion of the PICREF-1 has not been imple-mented. However, the theory of how power factor cor-rection circuitry would function in a UPS is discussedhere, and a general PFC schematic is given inAppendix B.

The output from the input filtering circuit feeds into thepower factor correction (PFC) circuit. The PFC circuitproduces a regulated DC bus by means of a full waverectifier which feeds a boost converter. The PFC con-trol system consists of two feedback loops. A currentloop forces the input current to match the waveshapeand phase of the input voltage, thus producing a highpower factor. The secondary outer loop adjusts themagnitude of the input current so that the output DCvoltage is regulated. This circuit also detects the mag-nitude of the input voltage. This is used to set the outputvoltage magnitude.

Synchronization of the PFC is derived from the micro-controller.

PFC comes into play when designing for high powerrequirement applications. In discussing power require-ments for a system, care must be taken in definingterms. In a DC system, the DC source supplies realcurrent to the real load. The power for this system isdefined in watts (volts x amps).

By their nature, switched mode power supplies have areduced power factor. This is due to the fact that thecurrent is delivered in narrow pulses at the peak of thevoltage sine wave. This increases the RMS value ofcurrent, which limits the current that can be drawn froma typical wall socket. Therefore, with power factor cor-rection, available power increases and distortiondecreases.

The example below shows how PFC can increase theability to drive loads from a typical outlet.

EXAMPLE 1: POWER FACTOR CORRECTION USAGE

The power source is 120 V ±- 10% at 20 Amps witha 20% derating.

The input to the UPS PFC’d to 0.95.

The efficiency of the UPS is 70%.

The load is a workstation which is rated at 900Watts with a PF of 0.65.

Can the load be driven with a 1400 VA rated UPS anda standard outlet (20A)?

Load Power:

PF = (Pout Watts / Pout VA)

0.65 = 900 W / Pout VA

Pout VA = 1384 VA

Input Power:

Pin Watts = Pout Watts / Efficiency

Pin Watts = 900 Watts / 0.70

Pin Watts = 1286 Watts

Pin Watts = Vin (Min) * Iin * PFC

1286 Watts = 108 V * Iin * 0.95

Iin = 12.5 Amps

Available Current:

20 Amps x 80% = 16 Amps

(VA rating is volts * amps. Power drain is watts. PFis Watts/VA and is typically 0.6-0.7 for computers.)

From the output power perspective, the load power forthe workstation is below 1400 VA, so the device can bedriven. From the input power perspective, the powerneed is 1286 watts, which translates into 12.5 Amps ofcurrent at the minimum input voltage. The derating ofthe outlet is 16 Amps, so the outlet is capable of provid-ing the current needed to supply the UPS. However, ifthe PF at the input would have been 0.65 instead of0.95, the current required would have been 18.3 Ampswhich would violate the derating conditions.

Power from

power line

Input Power 120/240 V

Metal Oxide

Varister (MOV)

Common modefilter


PICREF-1

Battery, Battery Charger and Battery Boost Circuit

This portion of the PICREF-1 has not been imple-mented. However, the theory of how a battery back-upcircuit (battery, battery charger and battery boost)would function in a UPS is given here.

The battery is charged from input power once the busvoltage exceeds 40V DC. The input power turns offwhen the bus voltage drops below 40V DC. The batterycharger circuit turns off when the battery power isenabled.

The 48V DC battery bus is stepped up to 360V throughthe battery boost (push-pull) circuit. The battery boostvoltage is slightly less than the battery charger bus volt-age created from the input power source. This is doneso that the power source under normal operation is theinput power. A UC3825 PWM controller is used as partof the battery boost control circuitry due to its inte-grated drive protection and low cost.

The UC3825 is optimized for high frequency switchedmode power supply applications. Particular care wasgiven to minimizing propagation delays through thecomparators and logic circuitry while maximizing band-width and slew rate of the error amplifier. This controlleris designed for use in either current mode or voltagemode systems with the capability for input voltagefeed-forward.

Protection circuitry includes a current limit comparatorwith a 1V threshold, a TTL compatible shutdown port,and a soft start pin which will double as maximum dutycycle clamp. The logic is fully latched to provide jitterfree operation and prohibit multiple pulses at an output.An under-voltage lockout section with 800mV of hyster-esis assures low start up current. During under voltagelockout, the outputs are high impedance.

This device features totem pole outputs designed tosource and sink high peak currents from capacitiveloads, such as the gate of a power MOSFET. The ONstate is designed as a high level.

DC Bus

The 380V DC bus is generated either from the primarypower source, under normal operating conditions, orthe battery boost circuit, under “no power” conditions.The DC bus is filtered for noise and spikes at the inputto the free running chopper.

Free Running Chopper

The free running chopper generates a square wave attwice the magnitude of the DC bus. The frequency ofthe chopper is 100kHz and the duty cycle of the squarewave is approximately 45%. A current transformer isused for sensing the current. A UC3825 PWM control-ler is used due to its high PWM frequency and low cost.

The output of the free running chopper is fed into atransformer which generates the output voltage basedon the magnitude of the source voltage. A relay selectsthe secondaries of a center-tapped transformer which

yields either 120V or 240V AC output levels. The outputis rectified to form a square wave with a duty cycle of90-92%. This is done to minimize the ripple and stresson components. A snubber circuit is in place to bleedcurrent from the parasitic capacitance of the inductorand voltage spikes which occur during the off period ofthe duty cycle.

Synchronization of the chopper circuitry is handledthrough the PIC17C43. In the event of a loss of the syn-chronization signal, the chopper has an internal syn-chronization source.

Inverter and Output Filtering

The input to the inverter is the free running chopperrectified square wave. After appropriate DC Bus filter-ing, this waveform is fed into the H-bridge circuit(Figure 2). The H-Bridge is under the control of aPIC17C43 running at 25MHz.

The output of the H-Bridge (differentially) consists of awaveform of rectangular pulses with a constant fre-quency of 25kHz and a duty cycle that varies to corre-spond with the absolute value of the desired output sinewave. Output filtering produces the smooth sine wave.

There are snubber circuits on Q9 and Q10 of theH-Bridge which discharge spikes back onto the DC busto minimize component stress.

The inductors L1 and L2 suppress ripple and additionalinductors, capacitors and discretes provide further fil-tering of the output voltage.

Hardware Protection and IGBT Drivers

The PIC17C43 controls the inverter through the hard-ware protection circuitry and the drivers for theH-Bridge. Insulated Gate Bipolar Transistors (IGBTs)are used for the H-Bridge rather than MOSFETs due totheir lower ON resistance. Although IGBTs have aslower turn on time than MOSFETs, the relatively lowfrequency of operation (PWM frequency = 25kHz)makes this property irrelevant.

Inverter control signals connect the PIC17C43 and theinverter through the hardware protection circuit and theIGBT drivers. These control signals are: ENABLE,FAULT, POS_NEG and PWM. See System Overview -Inverter Operation for a detailed discussion of howPIC17C43 signals control the H-Bridge inverter.

ENABLE will enable or disable all drive capability to theH-bridge. This is a local enable.

A FAULT will override the ENABLE, but can be reset inthe software so that a hardware retry may beattempted.

A FAULT can also be generated by the H-bridge cir-cuitry directly in order to shut done the IGBTs asquickly as possible (Hardware, or HW, FAULT). In theevent of a catastrophic failure, H-bridge hardware canrespond faster than the PIC17C43 software. This willprevent damage to the IGBTs.


PICREF-1

The POS_NEG signal controls the H-Bridge modula-tion for either positive or negative wave generation.

The modulation scheme (using PWM) is inherent in thehardware protection circuitry. The hardware protectionalso allows for a dead time on the IGBTs during statetransitions.

Output Monitoring Using A/D Converter

Feedback of the output AC sine wave is accomplishedthrough the use of an external 8-bit A/D converter. An8-bit A/D is considered adequate based on the speedof operation of the PIC17C43 and the resolutionneeded for 120V.

Both the output current and output voltage are moni-tored through the A/D converter. The voltage is sensedat the output stage and is fed to the A/D through an opamp circuit. The voltage is attenuated to the A/D inputrange. An op amp is used so that any DC offset compo-nents remain with the signal and can be measured. Thecurrent is monitored through a current transformer.

The current and voltage inputs are used to correct forany errors in the magnitude of the output wave. Theoutput voltage is sampled 32 times per half-wave whichresults in an output wave with 1.5% distortion (resistiveload with feedback) while running the PIC17C43 at 25MHz.

Power factor correction also makes use of the feedbacksignals, as well as zero crossing. Information about theoutput wave is compared with zero crossing informa-tion about the input wave to provide input/output syn-chronization. The zero crossing detect signal comesdirectly from the input wave and is used to indicate if azero crossing point has been detected. The PIC17C43then measures from point-to-point on the zero crossingto calculate the frequency of the input wave. This datais used to generate a sine wave of the same frequencythrough internal look-up tables.

SOFTWARE OVERVIEW

The PIC17C43 embedded software controls the opera-tion of the AC sine wave generation. It is imperative thatthe loop response be fast enough to minimize distortionon the output wave. Therefore, the throughput of themicrocontroller is a critical parameter.

The architecture of the PIC17C43 provides enoughthroughput to execute the control algorithm with a min-imum of distortion. The architecture is efficient enoughto support the device running at 33 MHz (121 nsinstruction cycle), so can easily support 25 MHz (160ns instruction cycle) to meet the distortion requirement.The system described in this paper has a measuredtotal distortion of 3% (resistive load) without feedbackand 1.5% THD with feedback. The load regulation withfeedback was measured to be 0.8%.

The flow diagram for the software is shown in Figure 7.The main software function looks for the zero crossingpoint and calculates the input frequency. Based on thecalculation, the appropriate look-up table is indexed.The SW checks for violation of maximum conditionsand sets the appropriate flags. The loop continuesindefinitely based on the zero crossing detect.

Information on how the look-up table is generated isprovided in the first subsection.

The interrupt is set up to occur periodically based onthe output frequency of the wave. The interrupt periodis initialized so that 32 interrupts occur within thehalf-wave period. During the interrupt, there must besufficient margin to perform two A/D conversions (cur-rent and voltage), calculate offsets and errors, andadjust the output duty cycle. The interrupt flow diagramis shown in Figure 8.

Adjusting the AC output waveform requires adjustingthe PWM that controls the inverter circuitry (H-Bridge).To do this, compensator coefficients need to be deter-mined. That is, in pseudocode:

X = (Output_V) - Vref;Y = c * Yold + d(X + Xold);Yold = Y;Xold = X;

Where Y = output; X = error.

How to calculate the coefficients c and d for a sin-gle-pole compensator is shown in the second subsec-tion.

A listing of all UPS PIC17C43 software is shown inAppendix C.

Note: Power factor correction has not beenimplemented in PICREF1.


PICREF-1

FIGURE 7: MAIN PROGRAM FLOW

Zero Crossing Detected?

Calculate Input Power Frequency

Zero Crossing Detected?

50Hz or 60Hz?

Set pointer to 60Hz Table

Set pointer to 50Hz Table

I > Imax orV > Vmax?

Y

N

Y

N

Set Flags

Y

Inverter Enabled?

N

Y

N

Set Flags Set Flags

Disable Inits

Disable PWM

Shaded objects indicate provisional sections. Power factor correction not implemented.


PICREF-1

FIGURE 8: INTERRUPT HANDLER FLOW Look-Up Table

The sinusoidal reference table for the DSP-basedinverter is generated as follows:

1. Choose Vp such that this number correspondswith the desired output voltage of the inverter.Example: If the desired output voltage is 120Vand the A/D converter used to sample the outputvoltage has a gain of 1.5 counts per output volt,then:

and Vp would be equal to 254.6, or 255 rounded tothe nearest integer.

The external circuitry interfacing the A/D converterto the output of the inverter should scale the inputvoltage to the A/D such that the peak of the desiredoutput voltage should correspond to almost a fullcount on the A/D.

2. The table is generated from the following equa-tion with k = 0.... N/2 - 1 and N = the number ofsamples per cycle.

Example: For the Vp of the previous example andN = 64 samples per cycle, this yields the followingtable entries. Note that only 32 entries are gener-ated as the negative-going halfwave may be gen-erated from the negative of the first 32.

Vref = 0, 25, 50, 74, 98, 120, 142, 162, 180, 197,212, 225, 235, 244, 250, 254, 255, 254, 250, 244,235, 225, 212, 197, 180, 162, 142, 120, 98, 74, 50,25.

Preset Timer for Sampling Rate

Read Voltage

Read Current

Calculate DC Offset

Calculate Duty Cycle based on DCold, Error, Errorold

Return

Calculate DC Error

Vp 1.5 120 2( )=

Vref Vp 2πkN

----------sin=


PICREF-1

Calculating the Compensator Coefficients

A convenient way of determining the coefficients for anIIR (Infinite Impulse Response) compensator from ananalog transfer function in the Laplace (s) domain is theBilinear z-transform. The following example illustratesthe technique for a compensator with a single pole.

EXAMPLE 1: SINGLE-POLE COMPENSATOR

DC Offset Correction

DC Offset is corrected for by taking the DC offset froma single cycle. This offset is integrated over time andused to correct the output wave. The DC offset is addedto the sine wave to determine the point-to-point magni-tude. This is then compared to the reference sine waveto determine DC offset correction.

An inverter is designed that requires a compensatorof the form:

(1)

The first step is to normalize H(s) and make note ofthe cutoff frequency (cutoff frequency = b):

(2)

Choose a sampling frequency at least 32 times thedesired output frequency (i.e., 1.92kHz for a 60 Hzinverter). If the desired gain crossover frequency ofthe loop response is more than 1/4 of the chosensampling rate, a higher rate equal to at least 4 timesthe gain crossover frequency should be used.

Make the following substitution in (1):

(3)

Where α = cot(b * T/2).

Thus,

(4)

The last step is to determine the difference equationthat will yield the transfer function of (4).

(5)

Multiplying both sides by (1/z) and using the fact that;

(6)

yields the desired difference equation.

(7)

H s( ) as b+-------------=

H ' s( ) a b⁄( )bs 1+

-------------------=

s α z 1–z 1+-------------=

H z( )a z 1+( )

αb z α 1+( ) α 1–( )–( )-----------------------------------------------------------=

y z( ) H z( ) x z( )•=

y z( ) αb z α 1+( ) α 1–( )–( )[ ] a z 1+( )x z( )=

Z y k n–[ ][ ] z n–( )Z y k[ ][ ]=

y k[ ] α 1–α 1+-------------y k 1–[ ] a

2 α 1+( ) b( )------------------------------ x k[ ] x k 1–[ ]+( )+=


PICREF-1

TEST RESULTS

No Load Conditions

Figure 9 is an example output waveform under no-load,no feedback conditions.

The example output waveform is a stepped-down ver-sions of the actual output waveform, available for oscil-loscope display by placing a probe on the UPS “LoadMonitor” BNC connector.

FIGURE 9: AC OUTPUT - NO LOAD, NO FEEDBACK

Load Conditions

Figure 10 is an example output waveform under load,no feedback. The load used was resistive, drawing 8.6Amps.

This example output waveform is a stepped-down ver-sion of the actual output waveform, available for oscillo-scope display by placing a probe on the UPS “LoadMonitor” BNC connector.

Figure 11 is an example output waveform under load,with feedback. The load used was resistive and induc-tive, drawing 4 Amps.

This example output waveform is the actual UPS outputwaveform.

FIGURE 10: AC OUTPUT - RESISTIVE LOAD, NO FEEDBACK


PICREF-1

FIGURE 11: AC OUTPUT - RESISTIVE AND INDUCTIVE LOAD WITH FEEDBACK


PICREF-1

DESIGN BACKGROUND

An example of how to implement a UPS system usinga microcontroller has been described in the previoussections. However, if a customer wishes to change partor all of this reference design, then understanding thereasons why the design was developed as it was mustbe understood.

When designing a UPS system, there are three itemsthat must be considered: cost vs. performance, outputwaveform and topology.

Cost vs. Performance

A UPS system has to be reliable. Money saved on fea-tures or performance can be overshadowed by the costassociated with data loss or component failure. So it isimportant to develop a cost effective solution which sat-isfies both end user price sensitivity and design robust-ness.

By incorporating a PIC17C43 microcontroller into theUPS design, the number of necessary components isreduced, thus reducing cost. Also, PIC17C43 peripher-als and speed enhance the performance of the UPSsystem. Software control of the PIC17C43, and thusthe UPS, allows for ease of modification and addition ofspecial features. So in terms of cost vs. performance,the PIC17C43 offers a win-win solution.

Other components of this reference design were cho-sen considering cost and performance. However, thereare other design options which are discussed in thesection Design Modifications.

Output Waveform

Some UPS designs use a square wave output insteadof a sine wave. This makes the system cheaper to pro-duce. But is this type of waveform really acceptable?

Electrical equipment uses power delivered in the formof a sine wave from local utility companies. When con-sidering alternative waveforms, how differing loads relyon different parts of the standard power companywaveform must be examined.

For instance, most appliances are always on, thus thepower used by the appliance is the RMS value of thesine wave, which is approximately 120 volts. However,equipment such as computers use peak voltage val-ues, which are approximately 170 volts.

When a square wave output is used to supply power tocomputer equipment, the RMS and peak values areequivalent, thus stressing some loads and under-sup-plying others. So the best output to provide electricalequipment is the output that they are designed to oper-ate with - a sine wave.

The speed of the PIC17C43 allows this referencedesign to produce a sinusoidal output AC waveform.This causes less stress on all electrical equipment.Actual output waveform graphics are provided in thesection Test Results.

Topology

To an end user, the function of a UPS system is muchmore important than form. Despite the many variationsof UPS systems on the market, they can be boileddown into two major topologies: Off-line and On-lineUPS.

Off-Line UPS

The first topology is known as off-line or standby, mean-ing that the inverter is normally off-line. A block diagramof an off-line UPS is shown in Figure 12. (The solid linerepresents the primary power path and the dashed linerepresents the secondary or back-up power path.)

In normal operation, the output power comes from theinput power source. This implies that there is a transfertime in switching the inverter on-line during a powerinterruption. If this transfer time is too great, there willbe a less than smooth transition for the load on theUPS. This could lead to the same problems that theUPS was designed to avoid.

The advantage of this topology lies in the fact that thestress on the inverter is decreased due to the inverterbeing turned off during normal operation. However,since the inverter only runs during power interruptions,this feature lends itself to latent failures when back-uppower is needed the most.

FIGURE 12: OFF-LINE UPS

Battery Charger

Inverter(DC to AC)

AC Input

Transfer Switch

AC Output

Battery


PICREF-1

On-Line UPS

The other major topology is the on-line or true UPS. Asthe name implies, the inverter is always on-line. A blockdiagram of the on-line UPS is shown in Figure 13.

At start-up the UPS is in bypass mode until the inverteris running and synchronized with the input powersource. Control is then transferred to the inverter. Theinverter remains on-line during normal operation andduring power failure operation until the battery isexhausted. During an inverter failure, the power is

switched back to primary power through the bypassswitch. This allows for the failed condition to be cor-rected while AC input power is still good.

The one drawback to the on-line topology is that theinverter is always on-line. This would imply that the “life”of this topology would be shorter than an off-line UPS.However, the life of a UPS in practice has more to dowith the robustness of the design than the topologyused.

The topology used for this reference design is the true(on-line) UPS.

FIGURE 13: ON-LINE UPS

Battery Charger

AC Input

Rectifier(AC to DC)

AC Output

Bypass Switch

Inverter(DC to AC)

Battery


PICREF-1

DESIGN MODIFICATIONS

This reference design is for guidance only, and it isanticipated that customers will modify parts of it. Withthis in mind, this section suggests modifications thatthe customer may wish to make to the design.

• The PIC16/17 family of microcontrollers offers a wide variety of options for a UPS design from the PIC16C72 to the PIC17C756. The PIC16C72, PIC16C73A, PIC16C74A, PIC17C43, and PIC17C756 all have the processing throughput to generate the sine wave described in this docu-mentation.For this design (PIC17C43), the frame rate for 64 point sampling of a 60Hz sinewave is 260 usec. The feedback code is approximately 200 instruc-tions, which yields a frame usage of 30 usec of the 260 usec. This leaves a margin of 230 usec for additional housekeeping features (serial com-munications, battery management, error detec-tion, fault reporting, etc.) that the user may implement.In converting the design to a PIC17C756, the user would integrate the A/D functionality. This would add additional time to the frame for the A/D con-version. For instance, if the user wanted to moni-tor Line Voltage, Line Current, Battery Voltage, Battery Current, this would add approximately 120 usec to the frame. The overall frame usage would increase from 30 usec to 150 usec out of 260 usec, but the external A/D and associated over-head would be eliminated. Additionally, house-keeping features such as battery management, fault detection, and serial communications could be added easily within the remaining frame time.In converting the design to a PIC16C72, PIC16C73A, or PIC16C74A, the processor fre-quency would be decreased and the math required for the sine wave generation would be performed in firmware. This would increase the frame usage by approximately 60-100 usec depending on the desired resolution. Also, the user would integrate the A/D functionality. As described above, Line Voltage, Line Current, Bat-tery Voltage, and Battery Current monitoring would add approximately 120 usec to the frame. The overall frame usage would increase to approximately 210-250 usec out of 260 usec. This would allow minimal housekeeping functionality to be integrated. If serial communications was desired, the PIC16C73A hardware USART would minimize the software overhead required. The PIC16C74A incorporates this feature as well as additional I/O lines if more I/O is needed.

FIGURE 14: PIC16C72 PINOUT

FIGURE 15: PIC16C73A PINOUT

FIGURE 16: PIC16C74A PINOUT

PDIP, SOIC, SSOP

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0/INT

VDD

VSS

RC7

RC6

RC5/SDO

RC4/SDI/SDA

28

27

26

25

24

23

22

21

2019

18

17

16

15

MCLR/VPP

RA0/AN0

RA1/AN1

RA2/AN2

RA3/AN3/VREF

RA4/T0CKI

RA5/AN4/SS

VSS


RC0/T1OSO/T1CKI

RC1/T1OSI

1

2

3

4

5

6

7

8

910

11

12

13

14

RC2/CCP1RC3/SCK/SCL

PIC

16C72

PDIP, SOIC, SSOP

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RB6

RB5

RB4

RB3

RB2

RB1

RB0/INT

VDD

VSS

RC7/RX/DT

RC6/TX/CK

RC5/SDO

RC4/SDI/SDA

28

27

26

25

24

23

22

21

2019

18

17

16

15

MCLR/VPP

RA0/AN0

RA1/AN1

RA2/AN2

RA3/AN3/VREF

RA4/T0CKI

RA5/AN4/SS

VSS


RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2

1

2

3

4

5

6

7

8

910

11

12

13

14

RC2/CCP1RC3/SCK/SCL

PIC

16C73A

RB7RB6

RB5

RB4RB3

RB2

RB1

RB0/INT

VDD

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RD7/PSP7

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RD4/PSP4

RC7/RX/DT

RC6/TX/CK

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RD2/PSP2

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RA0/AN0

RA1/AN1RA2/AN2

RA3/AN3/VREF

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RE0/RD/AN5

RE1/WR/AN6

RE2/CS/AN7VDD

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OSC1/CLKIN

OSC2/CLKOUT

RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2

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RC3/SCK/SCLRD0/PSP0

RD1/PSP1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

1920

40

39

38

37

36

35

34

33

3231

30

2928

27

26

25

24

23

2221

PIC

16C74A

PDIP


PICREF-1

FIGURE 17: PIC17C756 PINOUT • A different A/D converter for output waveform feedback. An 8-bit A/D is acceptable for 120V, but a 10-bit A/D would yield better resolution for 240V.

• A PAL to replace discrete digital components. Use of external fault detection can also reduce the number of components used.

• MOSFETs are also suitable switching elements for an inverter. They are much faster switches than IGBTs and, in many lower power cases, are less expensive than IGBTs. The faster switching times allow for a higher frequency PWM signal, which would thus require a smaller size/cost out-put filter to remove the switching frequency from the output. Also, driving MOSFETs may be easier than driving IGBTs.The disadvantage of MOSFETs is that their “on” state resistance RDS(on) is large enough to cause dissipation problems for high power inverters and their saturation voltage is less stable over temper-ature. In addition, as the voltage rating of MOS-FETs is increased, their conduction loss increases.IGBTs have the benefit that their saturation volt-age is a relatively constant 3 volts even when many tens to hundreds of amperes are flowing through the device. This makes for an inverter which has high efficiency at high output currents.As for the gate drivers, it is not necessary to use the special IGBT drivers that IGBT manufacturers produce for their product. IGBTs, like MOSFETs, do not draw any continuous gate current, but do have significant amounts for gate capacitance. This requires a circuit that can move the required charge in and out of the gate in short periods of time. Also, the gate drive circuit must have a provi-sion to isolate the high voltage of the IGBT bridge from the logic level voltages on the inverter control PCB. Generally, the hybrid IGBT drivers include some form of out-of-saturation protection circuitry which may or may not be needed based on the application.

Shrink PDIP (750 mil)

1234567891011121314151617181920

6463626160595857565554535251504948474645

PIC

17C756

444342414039

212223242526272829303132

383736353433

VDDRC0/AD0

RD7/AD15RD6/AD14RD5/AD13RD4/AD12RD3/AD11RD2/AD10RD1/AD9RD0/AD8RE0/ALERE1/OERE2/WR

RE3/CAP4MCLR/VPP

TEST

VDDRF7/AN11RF6/AN10

RF5/AN9RF4/AN8RF3/AN7RF2/AN6RF1/AN5RF0/AN4

AVddAVSS

RG3/AN0/VREF+RG2/AN1/VREF-

RG1/AN2

VSS

VSSRC1/AD1RC2/AD2RC3/AD3RC4/AD4RC5/AD5RC6/AD6RC7/AD7RA0/INTRB0/CAP1RB1/CAP2RB3/PWM2RB4/TCLK12RB5/TCLK3RB2/PWM1VSS

OSC2/CLKOUTOSC1/CLKINVDDRB7/SDORB6/SCK

RA2/SS/SCLRA1/T0CKIRA4/RX1/DT1RA5/TX1/CK1RG6/RX2/DT2RG7/TX2/CK2RG5/PWM3RG4/CAP3VDDVSSRG0/AN3

RA3/SDI/SDA


PICREF-1

APPENDIX A: SYSTEM SPECIFICATIONS

The following is a list of specifications for the UPS unit:

APPENDIX B: SCHEMATICSThe UPS schematics shown in this section may beobtained electronically on the Microchip BBS andWWW site (HPGL format; recommend 0.3 pen).

The UPS may be split into 4 main circuits: Input PowerFactor Correction, Battery Boost, Free-Running Chop-per, and Inverter. The UPS is an on-line device whichnormally will have the Power Factor Correction circuitfeeding the Chopper, which then feeds the Inverter. Ifthe input power should be lost, the Power Factor Cor-rection circuit falls out of the power flow and the BatteryBoost circuit automatically provides power to theChopper.

The Inverter is driven by the Inverter Drive circuitry,which in turn is controlled by the Inverter Control cir-cuitry containing the microcontroller.

UPS circuit board (PCB) power flow is shown inFigure B-1.

B.1 UPS System Overview

In the Battery Boost circuit, the transistor pairs are con-nected in parallel for the purpose of handling high cur-rents. The current transformer T2 is connected asshown to sense each pair’s current with just one trans-former, i.e., to prevent it from saturating.

The control for the 120V/240V relay (power switch) wasnot implemented. Wherever input power monitoringwould take place, monitoring for 120 or 240V wouldalso occur and switch the relay. These functions wouldbe placed before the PFC circuit.

B.2 Power Factor Correction

The Power Factor Correction circuit is provisional, sothe parts listed are generic parts.

FIGURE B-1: PCB POWER FLOW

AC Input: 120/240 VAC ± 10%, 50/60 Hz ± 3Hz

UPS Output: 120/240 VAC ± 10%, 50/60 Hz ± 3Hz (User-Selectable), Sinusoidal

Rating: 1400 VA

Input Filtering: EMI/RFI Filtering

Metal Oxide Varistor (MOV) for Spike/Surge Protection

Battery Boost PCB

Power FactorCorrection PCB

Free-Running Chopper PCB

Inverter Drive Card

Inverter Control CardFromBattery

FromInput Filter

PIC17C43, Hardware Protection

H-Bridge (Inverter)

IGBT Drivers

ToOutput Filter

Power Flow

ControlOther Circuitry

PCB


PICREF-1

FIGURE B-2: UPS SYSTEM OVERVIEW - PAGE 1 OF 3

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PICREF-1


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PICREF-1


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PICREF-1

FIGURE B-3: POWER FACTOR CORRECTION (PFC) – PAGE 1 OF 2

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PICREF-1

FIGURE B-3: PFC – PAGE 2 OF 2

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PICREF-1

FIGURE B-4: BATTERY BOOST (BB) CONTROL CARD – PAGE 1 OF 3

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PICREF-1

FIGURE B-4: BB – PAGE 2 OF 3

VD

DV

DD

GN

DG

ND

1 INO

UT

OU

T

U2

TS

C42

9CP

A

C3

1µF

C4

0.47

µF

Vcc

B_G

ND

2

45

67

8

R5

1k

B_G

ND

R4

2kO

UT

A

VD

DV

DD

GN

DG

ND

1 INO

UT

OU

T

U3

TS

C42

9CP

A

C13

1µF

C14

0.47

µF

Vcc

B_G

ND

2

45

67

8

R16

1k

B_G

ND

R15

2k

R6

5.6

R7

5.6

R17

5.6

R18

5.6

Tra

nsis

tor

Pai

r A

Pus

h-P

ull B

atte

ryB

oost

Circ

uit

Tra

nsis

tor

Pai

r B

Pus

h-P

ull B

atte

ryB

oost

Circ

uit

B_G

ND

(Fro

m p

age

1)

OU

T B

(Fro

m p

age

1)

B_G

ND

B_G

ND

LEG

EN

D

Ext

erna

l to

Boa

rd

Inte

rnal

to B

oard

Q2_

DR

IVE

Q4_

DR

IVE

Q3_

DR

IVE

Q1_

DR

IVE

Q2_

DR

IVE

Q1_

DR

IVE

Q4_

DR

IVE

Q3_

DR

IVE

Por

tion

of B

atte

ry B

oost

Circ

uit


PICREF-1

FIGURE B-4: BB – PAGE 3 OF 3

D1

D3

D2

D4

1N56

15

1N56

15

1N56

15

1N56

15

T1

C1

33µF

35V

7815

IO

R

1

2

3U

1

C2

100µ

F25

V

Vcc

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

1 2 3 4

CN

2

CN

1

R19

47

B_G

ND

ZZ

3448

1/2w

1 2 3 4

CN

3

B_G

ND

BB

_I_F

DB

K1

BB

_I_F

DB

K2

FE

ED

BA

CK

B_G

ND

B_G

ND

B_G

ND

B_G

ND

X1

X2

BA

TT

ER

Y(+

)BU

S

LOW

_BA

T

X1

X2

LEG

EN

D

Ext

erna

l to

Boa

rd

Inte

rnal

to B

oard

Q2_

DR

IVE

Q1_

DR

IVE

Q4_

DR

IVE

Q3_

DR

IVE

BB

_SY

N1


PICREF-1

FIGURE B-5: FREE-RUNNING CHOPPER (FRC) CONTROL CARD – PAGE 1 OF 3

INV

E/A

OU

T

Rt

CLK

/LE

B

Ct

RA

MP

SS

OU

T A

OU

T B

Vcc

1 311

6 75

1214

15

4

C4

0.47

µF

Vcc

CH

_GN

DR

410

0

Q2

2N22

22A

U2

UC

3825

AN

I Lim

GN

D

PG

ND

Vc

VR

EF

NL

1µF

1316

2

89

10

C10

470p

FC

1168

0pF

C3

CH

_GN

D

3 5

2 4

U5a

4049

U5b

4049

100k

Hz

Out

A

100k

Hz

Out

B

R5

10k

R18

4.7k

Q2

2N22

22A

Vcc

CH

_GN

D

R19

100k

R3

1.5k

CH

_GN

D

D8

1N41

50-1

4700

pFC

7

FR

C_S

YN

1

C10

100p

F

D7

1N98

5B

D6

1N98

5B

D5

1N98

5B

R1

24

CH

_GN

D

R6

1kR

751

0

R7

20.0

D9

1N41

50-1

CH

_GN

D

CH

_I_F

DB

K1

CH

_I_F

DB

K2

CH

_GN

D

CH

_GN

D

LEG

EN

D

Ext

erna

l to

Boa

rd

Inte

rnal

to B

oardC

H_G

ND

CH

_GN

D

+D

C_B

US

S

(To

page

2)

(To

page

2)


PICREF-1

FIGURE B-5: FRC – PAGE 2 OF 3

VD

DV

DD

GN

DG

ND

1 INO

UT

OU

T

U3

TS

C42

9CP

A

C5

1µF

C6

0.47

µF

Vcc

CH

_GN

D

2

45

67

8

R9

1k

CH

_GN

D

R8

2.2k

VD

DV

DD

GN

DG

ND

1 INO

UT

OU

T

U4

TS

C42

9CP

A

C12

1µF

C13

0.47

µF

Vcc

CH

_GN

D

2

45

67

8

R11

1k

CH

_GN

D

R10

2.2k

Q5_

DR

IVE

_RE

T

Q5_

DR

IVE

Q8_

DR

IVE

_RE

T

Q8_

DR

IVE

Q7_

DR

IVE

_RE

T

Q7_

DR

IVE

T2

Q6_

DR

IVE

_RE

T

Q6_

DR

IVE

R12 12 R13 12 R14 12 R15 12

Out

A(F

rom

pag

e 1)

Out

B(F

rom

pag

e 1)

CH

_I_F

DB

K1

CH

_I_F

DB

K2

+D

C_B

US

S

LEG

EN

D

Ext

erna

l to

Boa

rd

Inte

rnal

to B

oard

Q5_

DR

IVE

_RE

T

Q5_

DR

IVE

Q7_

DR

IVE

_RE

T

Q7_

DR

IVE

Q6_

DR

IVE

_RE

T

Q6_

DR

IVE

Q8_

DR

IVE

_RE

T

Q8_

DR

IVE

Por

tion

of F

ree-

Run

ning

Cho

pper

Circ

uit C

H_G

ND

CH

_GN

D

100k

Hz

100k

Hz


PICREF-1

FIGURE B-5: FRC – PAGE 3 OF 3

D1

D3

D2

D4

1N56

15

1N56

15

1N56

15

1N56

15

T1

C1

33µF

35V

7815

IO

R

1

2

3U

1

C2

100µ

F25

V

Vcc

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

1 2 3 4

J2

J1

R17 47

CH

_GN

D

ZZ

3448

1/2

W

LEG

EN

D

Ext

erna

l to

Boa

rd

Inte

rnal

to B

oard

+D

C_B

US

S

CH

_I_F

DB

K1

CH

_I_F

DB

K2

Q5_

DR

IVE

_RE

T

Q5_

DR

IVE

Q6_

DR

IVE

_RE

T

Q6_

DR

IVE

Q7_

DR

IVE

_RE

T

Q7_

DR

IVE

Q8_

DR

IVE

_RE

T

Q8_

DR

IVE

CH

_GN

D

CH

_GN

DC

H_G

ND

X1

X2

X1

X2

FR

C_S

YN

1


PICREF-1

FIGURE B-6: INVERTER CONTROL (INV CRTL) CARD – PAGE 1 OF 4

RA

5/T

X/C

K

RA

4/R

X/D

T

RA

3

RA

2

RA

1/T

0CK

I

RA

0/IN

T

RB

7

RB

6

RB

5/T

CLK

3

RB

4/T

CLK

12

RB

3/P

WM

2

RB

2/P

WM

1

RB

1/C

AP

2

RB

0/C

AP

1

TE

ST

OS

C1/

CLK

IN

OS

C2/

CLK

OU

T

VD

D

VS

S

VS

S

RD

7/A

D16

RD

6/A

D14

RD

5/A

D13

RD

4/A

D12

RD

3/A

D11

RD

2/A

D10

RD

1/A

D9

RD

0/A

D8

RC

7/A

D7

RC

6/A

D6

RC

5/A

D5

RC

4/A

D4

RC

3/A

D3

RC

2/A

D2

RC

1/A

D1

RC

0/A

D0

RE

2/W

R

RE

1/O

E

RE

0/A

LE

MC

LR/V

PP

U1

PIC

17C

43

33 34 35 36 37 38 39 40 9 8 7 6 5 4 3 2 28 29 30 32

21 22 23 24 25 26 18 17 16 15 14 13 12 11 27 19 20 1 31 10

C26

4.7µ

F

PW

M

10V

47k

R30

+5V

D10

1N41

50-1

C4

0.1µ

F

+5V

D7

D6

D5

D4

D3

D2

D1

D0

RD

’

WR

’

CS

’

INT

’

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Q8

Q9

Q10

Q11

Q12

Clr

Clk

Out

Gnd

VD

D

8714

C5

0.1µ

F

+5V

U4

25M

Hz

CT

X17

1

U9

74H

C40

40

C7

0.1µ

F

+5V

9 7 6 5 3 2 4 13 12 14 15 1

3.12

5MH

z

195k

Hz

11 10

DB

7

DB

6

DB

5

DB

4

DB

3

DB

2

DB

1

DB

0

RD

WR

INT

CS

CLK

DV

+

DG

ND

D7

D6

D5

D4

D3

D2

D1

D0

RD

’

WR

’

INT

’

CS

’

13 14 15 16 17 18 19 20 3 23 21 2 22 24 12C

60.

1µF

+5V

U5

AD

C10

154C

IN

CH

0

CH

1

CH

2

CH

3

AV

+

Vr+

Vr-

V-

Vro

ut

4 5 6 7 1 9 10 11 8

C23

330µ

F

-5V

10v

C13

0.1µ

F

-5V

C14

0.1µ

F

+5V

4.75

kR

25

4.75

kR

26

4.75

kR

31

6 57

4.75

kR

32

LM15

8U

16b

CH

0 (F

rom

pag

e 2)

CH

1 (F

rom

pag

e 2)

4.75

kR

23

4.75

kR

24

2 31

LM15

8U

16a

+12

V

- +

- +

-12V8 4

3.12

5MH

z

195k

Hz

l

l

1kR29

+5V

FLT

+

1kR27

l

1kR28

EN

AB

LE+

+5V

U19

4N35

U21

4N35

U20

4N35

(T

o pa

ge 2

)

(To

page

2)

-5V

C32

0.1µ

FC

310.

1µF

100

R37

100

R36

FLT

-

ZC

+ ZC

-

EN

AB

LE-

ALA

RM

PO

S_N

EG

FA

ULT

EN

AB

LE

LEG

EN

D

Ext

erna

l to

Boa

rd

Inte

rnal

to B

oard

(T

o/fr

om

(T

o pa

ge 3

)

page

3)


PICREF-1

FIGURE B-6: INV CRTL - PAGE 2 OF 4

100k

R5

931

R2

100k

R4

2 31

931

R3

LT10

13C

N8

U6a

2.2k

R11

- +C

H0

+12

V

-12V

8 4

+5V -5V

C10

47pF

C11

47pF

100k

R7

100k

R6

1kR9

82k

R8

49.9

R10

6 57

LT10

13C

N8

U6b

2.2k

R12

- +C

H1

+5V -5V

D6 D

5D

7

D8

3.12

5MH

z

195k

Hz

C22

22pF

1kR22

10 98

13 1211

1 23

4 56

C24

0.1µ

F

+5V

74A

C00

U15

c

74A

C00

U15

d

74A

C00

U15

a

74A

C00

U15

b

7400

U18

c10 9

8

1kR20

C21

0.1µ

F

220

R21

+5V

Q1

2N22

22A

T2

(To

page

1)

(To

page

1)

(Fro

m p

age

1)

(Fro

m p

age

1)

LEG

EN

D

Ext

erna

l to

Boa

rd

Inte

rnal

to B

oard

CS

EN

SE

_1O

SE

NS

E_1

OS

EN

SE

_2

BB

_SY

NC

1

BB

_SY

NC

2

FR

C_S

YN

C1

FR

C_S

YN

C2

PF

C_S

YN

C1

PF

C_S

YN

C2


PICREF-1

FIGURE B-6: INV CRTL – PAGE 3 OF 4

D3

D1

D4

D2

1N56

15

1N56

15

1N56

15

1N56

15

T1

HF

_BIA

S1

L1

C1

47µF

C8

47µF

25V

25V

7812

IO

R

1

2

3U

2

C3

2.2µ

F25

V

7805

IO

R

1

2

3U

3

C2

2.2µ

F25

V

7905

IO

R 1

23

U7

C9

2.2µ

F25

V

7912

IO

R 1

23

U8

C12

2.2µ

F25

V

+12

V

+5V

-5V

-12V

1 23

4 56

C25

0.1µ

F

+5V

74A

C00

U13

a

74A

C00

U13

b

74A

C00

U13

c10 9

8

4.75

kR

19

74A

C00

U13

d13 12

11

4.75

kR

1

Out

of

D9

1N41

50-1

+5V

74A

C00

U11

a1 2

374

00U

18d

13 1211

74A

C00

U11

b4 5

6

74A

C00

U11

c10 9

8

74A

C00

U11

d13 12

11

C29

0.1µ

F

+5V

1kR33

C27

1nF

1 23

4 56

1kR35

+5V

7486

U17

a

7486

U17

b

7400

U18

a1 2

3

74A

C00

U14

b4 5

6

74A

C00

U14

a1 2

3

1kR34

C28

1nF

10 98

13 1211

7486

U17

c

7486

U17

d

7400

U18

b4 5

6

74A

C00

U14

d13 12

11

74A

C00

U14

c10 9

8

C30

0.1µ

F

+5V

Sat

urat

ion

(Fro

m p

age

4)

LEG

EN

D

Ext

erna

l to

Boa

rd

Inte

rnal

to B

oard

HF

_BIA

S2

EN

AB

LE

FA

ULT

PO

S_N

EG

PW

M

L_H

I

L_H

I

Q10

_DR

IVE

Q11

_DR

IVE

Q12

_DR

IVE

Q9_

DR

IVE


PICREF-1

FIGURE B-6: INV CRTL – PAGE 4 OF 4

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

1kR13

C19

0.1µ

F

+12

V

C20

0.1µ

F

+5V

C15

1nF

1kR14

C16

1nF

1kR15

C17

1nF

1kR16

C18

1nF

54 3

2

1U

10a

4082

1211 10

9

13U

10b

4082

1 2 3 4

CN

1

CN

2

1 2 3 4

CN

3

1 2 3 4

CN

4

1 2 3 4

CN

5

1 2 3 4

CN

6

1 2 3 4

CN

7

Out

of

Sat

urat

ion

(To

page

3)

LEG

EN

D

Ext

erna

l to

Boa

rd

Inte

rnal

to B

oard

HF

_BIA

S1

HF

_BIA

S2

OS

EN

SE

_1

OS

EN

SE

_2

CS

EN

SE

_1

FLT

+ FLT

-

ZC

+ ZC

-

EN

AB

LE+

EN

AB

LE-

BB

_SY

NC

1

BB

_SY

NC

2

CH

P_S

YN

C1

CH

P_S

YN

C2

PF

C_S

YN

C1

PF

C_S

YN

C2

Q10

_DR

IVE

Q11

_DR

IVE

Q12

_DR

IVE

Q9_

DR

IVE

Q9_

OC

_ALA

RM

Q10

_OC

_ALA

RM

Q11

_OC

_ALA

RM

Q12

_OC

_ALA

RM


PIC

RE

F-1

1997 M

icrochip Technology Inc.

DS

30450C-page 35

FIG

UR

E B

-7:IN

VE

RT

ER

DR

IVE

(INV

DR

V) C

AR

D – P

AG

E 1 O

F 2

, D7, D11,

0, D8, D12,

17

18

D15, D19

D16, D20

5

5

1N5615

1N5615

T1, T2, T3, T4ZZ3448

Q# ofInverterH-Bridge

X1

X2

AMP

OVP

U1, U2, U3, U4EXB840

R2, R6,

1.5kR10, R14

+5Vdc

Q#_GND

O_GND

+12Vdc

R1, R5,

1.5kR9, R13

U5, U6, U7, U8H11L1

R3, R7,

1.5kR11, R15

D1, D2,

ERA34-10D3, D4

To InverterControl Board

From InverterControl Board

Q#_GND

C1, C5,

33µFC9, C13

35V

C2, C6,

33µFC10, C14

35V

D5, D9

D6, D1

C4, C8,

33µFC12, C16

35V

C3, C7,

100µFC11, C15

25V

O IR

1

2

3

U9, U10

7818U11, U12

D13, D

D14, D

1N561

1N561

R4, R8,

33R12, R16

Note: The Inverter Drive Card has four (4) circuits as shownto drive each of the four Inverter H-Bridge transistors(# = 9, 10, 11, 12).

1

2

3

45 6

9

14

15

Q#_GND

C17, C18,

330pFC19, C20

Q#_DRIVE

Q#_OC_ALARM

LEGEND

External to Board

Internal to Board

Q#_C

Q#_G

Q#_E

PICREF-1

FIGURE B-7: INV DRV – PAGE 2 OF 2

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

+12

Vdc

+5V

dc

1 2 3 4

CN

1

CN

2

1 2 3 4

CN

3

O_G

ND

1 2 3 4

CN

4

1 2 3 4

CN

5

1 2 3 4

CN

6

LEG

EN

D

Ext

erna

l to

Boa

rd

Inte

rnal

to B

oard

X1

X2

Q9_

C

Q9_

G

Q9_

E

Q10

_C

Q10

_G

Q10

_E

Q11

_C

Q11

_G

Q11

_E

Q12

_C

Q12

_G

Q12

_E

Q10

_DR

IVE

Q10

_OC

_ALA

RM

Q11

_DR

IVE

Q11

_OC

_ALA

RM

Q12

_DR

IVE

Q12

_OC

_ALA

RM

Q9_

DR

IVE

Q9_

OC

_ALA

RM


PICREF-1

APPENDIX C: SOFTWARE LISTINGThe main purpose of the microcontroller software is toprovide an inverter fast feedback loop response, suchthat the transient response and output distortion arethat of a high performance design.

In addition, the inverter software may be used to pro-vide the necessary communication to any “housekeep-ing” code as well as synchronization of the outputvoltage to the input voltage waveform. The housekeep-ing software was not developed for this referencedesign; however, the inverter software has “hooks” inplace for such interfacing.

Housekeeping software should provide an overviewcontrol of the UPS power stream as well as the neces-sary communication and test functions to the outsideworld (i.e., on-board LCD display and host computersoftware interface).

The PICREF-1 software source code, as it existed atthe time this document was published, is listed below.The most current version of PICREF-1 software may beobtained electronically on the Microchip BBS andWWW site.

/****************************************************************************** Filename: MAIN.C******************************************************************************** Author: Dave Karipides* Company: APS, Inc.* Date: 3-3-97* Compiled Using MPLAB-C Rev 1.21********************************************************************************* Include Files:* ******************************************************************************** Description: The main routine calls all the functions for generating* an OPEN_LOOP or FEEDBACK sine wave of either 50 or 60 Hz.********************************************************************************* Revisions:* 3/3/97 Added FEEDBACK LOOP********************************************************************************/

/****************************************************************************** main()** Description: The main routine initializes the registers and loops* forever. All control is handled in the TMR0 INT* routine.*** Input Variables: NONE** Output Variables: NONE********************************************************************************/

//#define OPEN_LOOP#define FEEDBACK//#define 50Hz#define 60Hz

#pragma option v#include <17c43.h>#include <math.h>#include <delay16.h>

#ifdef OPEN_LOOP


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// This table yields Full VRMS inputunsigned char const pwmtab[32]=0,25,50,74,98,120,142,162,180,197,212, 225,235,244,250,254,255,254,250,244,235, 225,212,197,180,162,142,120,98,74,50,25;#endif#ifdef FEEDBACK// This table yields slightly less than Full VRMS inputunsigned char const pwmtab[32]=0,20,40,60,79,97,114,131,145,159,171, 181,189,197,202,205,206,205,202,197,189, 181,171,159,145,131,114,97,79,60,40,20;#endif

long read_ad(unsigned char); // Prototype for A/D converter function

unsigned char index; // Index into the sinewave reference tableunsigned char sign; // Flag used to unfold sinewave reference tablelong reference; // Value of the sinewave refrence after unfoldingunsigned char reference_lo @ reference; // V1.21 of Compiler does not type cast unsigned // char to long so we will write to low byte separatelylong out_volt; // Magnitude of the output voltage;long y; // Variables used in compensation routinelong yold;long x;long xold;long ad_value; // A/D Converter Value

void main(void) CLRWDT(); PORTC = 0; // Zero out portc latches DDRC = 0x22; // Set up Data direction register for C DDRB = 0; // Set up Data direction register for B PR1 = 0xFF; // Setup PR1 register (24.4Khz @ 25Mhz clk) PW1DCL = 0; // Set low bits of PWM to 0 PW1DCH = 0; // Init PWM duty cycle to 0

T0STA = 0x20; // Configure Timer0 prescaler INTSTA.T0IE = 1; // Enable Timer 0 interrupt TCON1.TMR1CS = 0; TCON1.T16 = 0; TCON2.TMR1ON = 1; // Start timer 1 (PWM timer) TCON2.PWM1ON = 1; // Turn on the PWM CPUSTA.GLINTD = 0; // Unmask the interrupts

index = 0; // Initialize variables sign = 0; y = 0; yold = 0; x = 0; xold = 0; PORTC.0 = 1; // Enable the Inverter while(1); // Loop forever, execute in INT Routine

#ifdef FEEDBACK__TMR0() // Timer interrupt T0STA.T0CS = 0; // Stop timerPORTB.7=1;#ifdef 60Hz TMR0L=0xA5; TMR0H=0xF9; // Make Timer0 interrupt at 3.84KHz for 60Hz output#endif#ifdef 50Hz TMR0L=0x5F; // Make Timer0 interrupt at 3.20KHz for 50Hz output TMR0H=0xF8;


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#endif T0STA.T0CS = 1; // Start timer CLRWDT();

reference = 0; // Clear Reference Value reference_lo = pwmtab[index]; // Lookup the value of the sinewave reference

if (!index) // Toggle Sign Every Cycle Through table sign = ~sign; ++index; // Increment index if (index == 32) // If end of table, reset counter index = 0; if (sign) // If negative going wave reference = ~reference; // V1.21 of Compiler negate (-ref) doesn’t work for reference = reference + 1; // ref<=0 ad_value = read_ad(0); out_volt = ad_value - 512; // Read output voltage (512 counts=0 volts out)

// Form the expression y = yold + (0.09261 * (x + xold))// Where yold, xold is the value of y, x from the previous sample// x is the <error signal>, formed by the difference between the output // of the inverter and the reference signal. x = out_volt - reference; y = ((x + xold) * 24); y = y / 256; y = y + yold; if (y >= 0) PORTC.2 = 0; // Set positive going cycle else PORTC.2 = 1; // Set negative going cycle y = ~y; y = y + 1; if (y > 255) y = 255; // Limit y PW1DCH = y; // Update duty cycle xold = x; // Store previous sample’s state yold = y;PORTB.7=0; #endif

#ifdef OPEN_LOOP// The inverter runs in an open loop mode with OPEN_LOOP defined.__TMR0() // Timer interrupt T0STA.T0CS = 0; // Stop timer#ifdef 60Hz TMR0L=0xA5; TMR0H=0xF9; //Make Timer0 interrupt at 3.84KHz for 60Hz output#endif#ifdef 50Hz TMR0L=0x5F; //Make Timer0 interrupt at 3.20KHz for 50Hz output TMR0H=0xF8;#endif T0STA.T0CS=1; //Start timer CLRWDT(); PW1DCH = pwmtab[index]; if (!index) PORTC.0 = 0; // Gate Drive off


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PORTC.2 = ~PORTC.2; // Flip Pos/Neg bit PORTC.0 = 1; // Gate Drive on ++index; if (index == 32) index = 0; PORTC.3 = ~PORTC.3; // Toggle bit to test freq.#endif

long read_ad(unsigned char channel)long result;

PORTC.6 = 1; // Write bit high PORTC.7 = 1; // Read bit high PORTC.4 = 1; // Chip select high DDRD = 0; // Make PORTD an output PORTD = 0x04; // Single ended mode signed 10 bit chan 0 Right justified PORTC.4 = 0; // Select chip PORTC.6 = 0; // latch command word int A/D PORTC.6 = 1; // Start conversion PORTC.4 = 1; // Deselect chip while (PORTC.5); // Wait for conversion to complete DDRD = 0xFF; // Make PORTD an input PORTC.4 = 0; // Select chip PORTC.7 = 0; // Read high byte *( ((unsigned char*)&result) + 1) = PORTD; PORTC.7 = 1; PORTC.4 = 1; PORTC.4 = 0; PORTC.7 = 0; // Read low byte *( ((unsigned char*)&result) ) = PORTD; PORTC.7 = 1; PORTC.4 = 1; // Reset chip select lines return (result); // Return data


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APPENDIX D: PCB LAYOUT & FAB DRAWINGTop silk screen drawings for the UPS control cards areshown in the following sections. The board dimensionslisted are, with respect to the orientation of this page;(horizontal dimension x vertical dimension).

The boards shown are:

• Battery Boost PCB• Free Running Chopper PCB• Inverter Drive Card• Inverter Control Card.

The Power Factor Correction circuit was not built uponto a board.

These drawings, and additional layout and fab drawings(top and bottom copper, top and bottom solder masks,drill drawings, report drawings and board drawings),may be obtained electronically on the Microchip BBS orWWW site.

FIGURE D-1: BATTERY BOOST PCB

( 5” x 3.8” )CN21R6

R7

C4C3

R4

R5

R15

R16

U2

U3 R17

R18

C13 C14

D16

D18D17

D15R1

R2

R3D2

D4D3

D1R19

T1-1 T1-4T1-3

T1-2

C1

CN1

1

C2R14

R13

R12C12 R24

C19C11R21

R10

C9

C16

C15

Q1

R20R11R9

CN3

1 C18C10

R8

C5

U4

UC

3825

AN

U5

C6

C8

U6

R25

R26

C7

R23

R22

C17

T1

U1

© 1997 Microchip Technology Inc. Preliminary DS30450B-page 41

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FIGURE D-2: FREE RUNNING CHOPPER PCB

( 4” x 5” )

C6C5

R9R8

U3

U4

T2-1

T2-2

T2

C12

C13

T2-3

T2-5

R12

T2-4

R15

T2-6

T2-7

R14

T2-8

R13T2-9

T2-10C10

U5

U2

J21

D8

D9

D5

R16

R5

R19

D6

D7Q2

R18

R7

Q1

T1-2T1-1

J1

T1-3T1-4

R6

C11C7

C8

R4

R1

D2

D3

D4

R2

R3

C9

U1

C1

D1

R17

T1

1

R11

R10

C3

C4

C2

DS30450B-page 42 Preliminary © 1997 Microchip Technology Inc.

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FIGURE D-3: INVERTER DRIVE CARD

( 5” x 8” )

1

CN3

C3C4

C1

1

D7

C2

D1

R4

U9

D8

D5D6

T1-3

T1-4

U1

C17

R3

U5R1

15

R2T1

T1-1T1-2

1

CN4

C7C8

C5

1

D11

C6

D2

R8

U10

D12

D9D10T2-4

U2

C18

R7

U6

R5

15

R6

T2-1

T2

T2-2

T2-3

CN

1

CN

2C

N2

1

1

CN5

C11C12

C9

1

D15

C10

D3

R12

U11

D16

D13D14T3-4

U3

C19

R11

U7

R9

15

R10

T3

T3-3

1

1

CN6

C15C16

C13

1

D19

C14

D4

R16

U12

D20

D17D18T4-4

U4

C20

R15

U8

R13

15

R14

T4-1

T4

T4-2

T4-3

1

T3-1T3-2

© 1997 Microchip Technology Inc. Preliminary DS30450B-page 43

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FIGURE D-4: INVERTER CONTROL CARD

1

CN2

D1

D3

D4

D2

T1-2

T1-1

T1-6

L1-3

T1-4

T1-5

T1-3

T1

L1

C1

C8

L1-4

L1-2

C2

U3U2U7U8

C12 C9 C3

R10

R9

R8

R12

U6LT1013CN8

R2

R11

R4R5

C11R7C10

CN5

R6

R3R25R26R23R24R32

U16

LM158

R19

C4

C25

C19

C20

D9

R1

R16

C18

R15

C17

R14

C16

R13

C15

C29

C14

C27

R33

C30

CN1

R34

C28

R35

R22

C22

R20

Q1

C7

R21

C21

U1374AC00

U1174AC00

U974HC4040

U104082

U187400

U1574AC00

U177486

U1474AC00

U1

PIC17C43

T2-1 T

2-3

T2-2

T2-4

CN6

CN7

CN4

CN3

1

T2

T2-5

D10

R30

C26 T2-7

C5

U4CTX171

R31

R37

R36

C31

C32

C23

U21

4N35

U19

4N35

U20

4N35R

29R

27R

28

D7 D

8

D5 D6

U5

AD

C10154

C24

C13 C6

L1-1

1

1

1

1

DS30450B-page 44 Preliminary © 1997 Microchip Technology Inc.

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APPENDIX E: BILL OF MATERIALS (BOM)This appendix lists the Bill of Materials (BOM) for theUPS system assembly and for each of the UPS boardsdescribed in Appendix D.

E.1 UPS System Assembly

DESCRIPTION QTY DESIGNATORSPART #, MANUFACTURER,

CONTACT #

Transistor 4 Q1 - Q4 IRFP264, International Rectifier,(310) 322-3331

Transistor 4 Q5 - Q8 IRF450, International Rectifier,(310) 322-3331; or Generic 2N6770

Transistors, 2 to a block, 75A 2 Q9 - Q12 2MBI75L-060, Fuji,(408) 922-9000; orCM75DY-12H, Powerex,(412) 925-7272(800) 451-1415 (USA only)

Transformer 1 T1 ZZ3449, Airborne PowerSee Acknowledgments for email address

Transformer, current 1 T2 ZZ3450, Airborne PowerSee Acknowledgments for email address

Transformer 2 T4, T5 ZZ9454, Airborne PowerSee Acknowledgments for email address



Inductor, 500uH 1 L1 ZZ3451, Airborne PowerSee Acknowledgments for email address


Inductor, 300uH 2 L5, L6 ZZ3457, Airborne PowerSee Acknowledgments for email address


Switch 2 RLY1, RYL2

Diode 3 D1, D2, D3 DESI 30-12A

Diode 2 D9, D10 DESI 60-12A

Capacitor, 1uF, 600V 3 C1, C4, C9 Generic

Capacitor, Electrolytic, 6100uF, 350V 2 C5, C6 Generic

Capacitor, Electrolytic, 250uF, 350V 2 C10, C11 Generic

Capacitor, 0.58uF 2 C12, C13 Generic

Capacitor, 10uF, 600V 4 C14 - C17 Generic

Resistor, 100kΩ, 2W 4 R4 - R7 Generic

Resistor, 5.6Ω 1 R8 Generic


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E.2 Battery Boost PCB


CONTACT #

Cap, Ceramic0.01µF, Radial Lead

3 C9,16,17 ECU-S1J103KBA, Panasonic(714) 373-7366

Cap, Ceramic0.1µF, Radial Lead

1 C15 ECU-S2A104KBA, Panasonic(714) 373-7366

Cap, Ceramic.47µF, Radial Lead

3 C4, 6, 14 ECU-S1J474KBB, Panasonic(714) 373-7366

Cap, Tantalum1.5µF, 25V, Radial Lead

4 C3, 5, 13, 18 ECS-F1EE155K, Panasonic(Digikey: P2044-ND)(714) 373-7366

Cap, Electrolytic33µF, 35V, Axial Lead

1 C1 ECE-A1VU330, Panasonic(714) 373-7366


1 C2 ECE-B1EU101Y, Panasonic(714) 373-7366

Cap, Ceramic100pF, Radial Lead

1 C10, 19 ECU-S2A101JCA, Panasonic(714) 373-7366


2 C7, 11 ECU-S2A471JCB, Panasonic(714) 373-7366


1 C12 ECU-S2A681JCB, Panasonic(714) 373-7366



Terminal Block, Wire-to-PCB Stackable, 200mil

12 CN1, 2, 3 ED120/2DS, On-Shore Technology(602) 921-3000

Diode, Small-signal, Axial Lead 4 D15,16,17,18 1N4150-1, Microsemi(602) 244-6900

Diode, Fast-Recovery, 200V, 1A,Axial Lead

4 D1-4 1N5615, Microsemi(602) 244-6900

Transistor, Small-signal, NPN, TO-18 1 Q1 2N2222A, National Semiconductor(408) 712-5800(800) 272-9959 (USA Only)

Resistor, 5.6Ω, 1/4 Watt, Axial Lead 4 R6, 7, 17,18 Generic

Resistor, 6.2Ω 1/4 Watt, Axial Lead 1 R14 Generic

Resistor, 24Ω, 1/4 Watt, Axial Lead 1 R10 Generic





Resistor, 1kΩ, 1/4 Watt, Axial Lead 3 R 5, 13, 16 Generic

Resistor, 2kΩ, 1/4 Watt, Axial Lead 2 R4, 15 Generic

Resistor, 2.67kΩ, 1/4 Watt, Axial Lead 1 R9 Generic


Resistor, 10.4kΩ, 1/4 Watt, Axial Lead 3 R8, 21, 22 Generic






PICREF-1

IC, Hex Inverter14-PIN DIP

1 U4 MC14049UBCL, Motorola(602) 244-6900

IC,+15V Voltage RegulatorTO-220

1 U1 MC7815CT, Motorola(602) 244-6900

IC, Quad Comparator14-PIN DIP

1 U6 LM339N, National Semiconductor(408) 712-5800(800) 272-9959 (USA Only)

IC, Driver, Line,8-PIN DIP

2 U2, 3 TSC429CPA, TelCom(415) 968-9241(800) 888-9966 (USA Only)

IC, PWM,18-PIN DIP

1 U5 UC3825AN, Unitrode(603) 429-8610

E.2 Battery Boost PCB (Continued)


CONTACT #


PICREF-1

E.3 Free Running Chopper PCB


CONTACT #

Cap, Ceramic.47µF, Radial Lead

3 C4, 6, 13 ECU-S1J474KBB, Panasonic(714) 373-7366

Cap, Tantalum 1.5µF, 25V, Radial Lead

3 C3, 5, 12 ECS-F1EE155K, Panasonic(714) 373-7366

Cap, Electrolytic33µF, 35V, Radial Lead

1 C1 ECE-A1VU330, Panasonic(714) 373-7366


1 C2 ECE-B1EU101Y, Panasonic(714) 373-7366


1 C9 ECU-S2A101JCA, Panasonic(714) 373-7366








1 C7 ECU-S1J472KBA, Panasonic(714) 373-7366

Terminal Block, Wire-to-PCBDual-Stackable, 200mm spacing

12 CN1, 2 ED120/2DS, On-Shore Technology(602) 921-3000

Diode, Small-signalAxial Lead

2 D8, 9 1N4150-1, Microsemi(602) 244-6900

Diode, Fast Rectifier200V, 1A, Axial Lead

4 D1-4 1N5615, Microsemi(602) 244-6900

Diode, ZenerAxial Lead

3 D5-7 1N985B, Motorola(602) 244-6900

Transistor, Small-signalNPN, TO-18

2 Q1,2 2N2222A, National Semiconductor(408) 712-5800(800) 272-9959 (USA Only)

Resistor, 12Ω, 1/4 Watt, Axial Lead 4 R12-15 Generic





Resistor, 1kΩ, 1/4 Watt, Axial Lead 3 R6, 9, 11 Generic



Resistor, 2.2kΩ, 1/4 Watt, Axial Lead 2 R8, 10 Generic



Resistor, 10kΩ, 1/4 Watt, Axial Lead 1 R5 Generic

Resistor, 100kΩ, 1/4 Watt, Axial Lead 2 R19 Generic

TransformerBias Supply

1 T1 TF5S03ZZ3448, Airborne PowerSee Acknowledgments for email address

TransformerDrive


IC, Hex Inverter14-Pin DIP

1 U5 MC14049UBCL, Motorola(602) 244-6900


PICREF-1

IC, +15V Voltage RegulatorTO-220

4 U1 MC7815CT, Motorola(602) 244-6900

IC, Driver, Line8-Pin DIP

2 U3, 4 TSC429CPA, TelCom(415) 968-9241(800) 888-9966 (USA Only)

IC, PWM18-Pin DIP

1 U2 UC3825AN, Unitrode(603) 429-8610

E.3 Free Running Chopper PCB (Continued)


CONTACT #


PICREF-1

E.4 Inverter Drive Card


CONTACT #

Cap, Electrolytic,33µF, 35V, Axial Lead

12 C1, 2, 4-6, 8-10, 12-14, 16

ECE-A1VU330, Panasonic(714) 373-7366

Cap, Film, 100µF, 25V, Axial Lead 4 C3, 7, 11, 15 ECE-B1EU101Y, Panasonic(714) 373-7366

Connector, Ribbon Cable,20-position

1 CN1 3428-6002, 3M Scotchflex(512) 984-1800(800) 225-5373 (USA Only)

Terminal Block, Wire-to-PCB,2 Position Dual, 200mil spacing

10 CN2-6 ED120/2DS, On-Shore Technology(602) 921-3000

Diode, Fast Recovery,600V, 1A, Axial Lead

4 D1-4 ERA34-10, Fuji (Collmer)(214) 233-1589

Diode, Fast-Recovery,200V, 1A, Axial Lead

16 D5-20 1N5615, Microsemi(602) 244-6900

Resistor, 1/2 Watt, 33Ω, 1%, Axial Lead 4 R4, 8, 12, 16 Generic

Resistor, 1/4 Watt, 1.5kΩ, 1%, Axial Lead 12 R1-3, 5-7, 9-11, 13-15

Generic

Transformer, Toroid100kHz, 24:27

4 T1-4 TF5S03ZZ3448, Airborne Power(Core is XJ-41605-TC)See Acknowledgments for email address

IC, Optocoupler, 6-Pin DIPSchmitt Trigger Logic-Output

4 U5-8 H11L1QT, QT Optoelectronics(214) 447-1304

Voltage Regulator, TO-22018Vdc

4 U9-12 MC7818CT, Motorola(602) 244-6900

Driver, IGBT. Hybrid Package 4 U1-4 EXB840, Fuji(201) 712-0555

Retainer, Toroid 4 100-2, Delbert-Blinn(909) 629-3900

Screw, 4-40x1/2 ”, Stainless Steel 4 Generic

Washer, 4-40”, Stainless Steel 4 Generic


PICREF-1

E.5 Inverter Control Card


CONTACT #

Cap, Ceramic, C0G22pF, 100V, Radial Lead

1 C22 ECU-S2A220JCA, Panasonic(714) 373-7366

Cap, Ceramic, X7R0.001µF, 100V, Radial Lead

8 C10, 11, 15-18, 27, 28

ECU-S2A102KBA, Panasonic(714) 373-7366

Cap, Ceramic, X7R0.1µF, 100V, Radial Lead

15 C4-7, 13, 14, 19-21, 24, 25, 29, 30, 31, 32

ECU-S2A104KBA, Panasonic(714) 373-7366

Cap, Tantalum,2.2µF, 25V, Axial Lead

4 C2, 3, 9, 12 ECS-F1EE225K, Panasonic(714) 373-7366

Cap, Electrolytic,330µF, 16V, Radial Lead

1 C23 ECE-A1CU331, Panasonic(714) 373-7366

Cap, Electrolytic,47µF, 25V, Axial Lead

2 C1, 8 ECE-B1EFS470, Panasonic(714) 373-7366

Cap, Tantalum,4.7µF, 10V, Axial Lead

1 C26 ECS-F1AE475K, Panasonic(714) 373-7366

Connector, Ribbon Cable,20-position

1 CN1 3428-6002, 3M Scotchflex(512) 984-1800(800) 225-5373 (USA Only)

Terminal Block, Wire-to-PCB,2 Position Dual-Stackable, 200mm spacing

12 CN2-7 ED120/2DS, On-Shore Technology(602) 921-3000

Diode, Small-signal,Axial Lead

6 D5-10 1N4150-1, Motorola(602) 244-6900

Diode, Fast Recovery,200V, 1A, Axial Lead

4 D1-4 1N5615, Microsemi(602) 244-6900

Transistor, Small-signal,NPN, TO-18

1 Q1 2N2222A, National Semiconductor(408) 712-5800(800) 272-9959 (USA Only)

Resistor, 1/4 Watt, 49.9Ω, 1%, Axial Lead 1 R10 Generic

Resistor, 1/4 Watt, 220Ω, 1%, Axial Lead 1 R21 Generic

Resistor, 1/4 Watt, 1kΩ, 1%, Axial Lead 13 R9, 13-16, 20, 22, 27-29, 33-35

Generic

Resistor, 1/4 Watt, 2.2kΩ, 1%, Axial Lead 2 R11, 12 Generic

Resistor, 1/4 Watt, 4.75kΩ, 1%, Axial Lead 8 R1, 19, 23-26, 31, 32

Generic

Resistor, 1/4 Watt, 932kΩ, 1%, Axial Lead 2 R2, 3 Generic

Resistor, 1/4 Watt, 82kΩ, 1%, Axial Lead 1 R8 Generic

Resistor, 1/4 Watt, 100kΩ, 1%, Axial Lead 4 R4-7 Generic

Inductor, Toroid 1 L1 TF5S04ZZ3461, Airborne PowerSee Acknowledgments for email address

Transformer, Toroid1P/2S CT’ed


Transformer, Toroid1P/1S


IC, 18-bit Shift Register,16-Pin DIP

1 U9 MC14040BAP, Motorola(602) 244-6900


1 U3 MC7805CT, Motorola(602) 244-6900

IC, -5V Voltage RegulatorTO-220

1 U7 MC7905CT, Motorola(602) 244-6900


PICREF-1


1 U2 MC7812CT, Motorola(602) 244-6900

IC, -12V Voltage RegulatorTO-220

1 U8 MC7912CT, Motorola(602) 244-6900

IC, Optocoupler6-Pin DIP

3 U19-21 4N35QT, QT Optoelectronics(214) 447-1304

IC, Quad NAND Gates14-Pin DIP

4 U11, 13-15, 18 74AC00PC, National Semiconductor(408) 712-5800(800) 272-9959 (USA Only)

IC, A-D Converter,24-Pin DIP

1 U5 ADC10154CIN, National Semiconductor(408) 712-5800(800) 272-9959 (USA Only)

Oscillator, Clock25MHz, (14-Pin DIP compatible)

1 U4 CTX171, CTS(815) 786-8411

IC, Op AmpsLow-Power, Dual, 8-Pin DIP

1 U16 LM358AN, National Semiconductor(408) 712-5800(800) 272-9959 (USA Only)

IC, Op AmpPrecision, Dual, 8-Pin DIP

1 U6 LT1013CN8, Linear Technology(408) 432-1900

IC, Microcontroller40-Pin DIP

1 U1 PIC17C43, Microchip Technology(602) 786-7200

IC, Dual 4-input AND Gate14-Pin DIP

1 U10 CD4082BE, Harris(407)724-7000(800) 4 HARRIS (USA Only)

IC, Quad 2-input Exclusive-ORGate, 14-pin DIP

1 U17 74AC86PC, National Semiconductor(408) 712-5800(800) 272-9959 (USA Only)

E.5 Inverter Control Card (Continued)


CONTACT #


PICREF-1

APPENDIX F: UPS DEMO UNITThe Demo Unit is a subset of the UPS. This unit wasdesigned to showcase the inverter, featuring thePIC17C43 microcontroller. Therefore, there is no bat-tery back-up circuitry.

AC power is filtered as it enters the UPS demo unit.There is also an input fuse to protect against surges.There is no power factor correction circuitry, and a rec-tifier-bridge is used to feed the inverter, or H-Bridge(i.e., no free-running chopper). There is output filteringand feedback circuitry.

The circuit boards used on the demo unit are theinverter drive PCB, the inverter control PCB and a biassupply board used to supply 15Vdc to the unit’s dis-crete components.

F.1 Demo Specifications

The UPS demo specifications are the same as for theUPS system.

F.2 Demo Additional Schematics, PCB’s, BOMs

FIGURE F-1: BIAS SUPPLY CIRCUIT

RtCtR(T)DtSynOsc

SS

E-

VrCmp

AB

Vcc

GND

U1UC3525BN

Vc

E+ Inh Gnd

R16.04k

C11pF

C20.1µF

C347µF

+15Vdc

25v

GND

1

2

CN1

1

2

CN2

T1ZZ3464

R247

R347

Q2NDP4050

Q1NDP4050


PICREF-1

FIGURE F-2: BIAS SUPPLY BOARD FIGURE F-3: RECTIFIER-BRIDGE CIRCUIT

(2.4” X 2.4”)

R3

C3C2

Q2

CN1+15V 1

GNDC1

U1

R2

R1

+

Q1

CN2T1

AC LO

AC HI 1

ACAC

+

-

TABLE F-1: BIAS SUPPLY BOM


CONTACT #

Cap, Electrolytic,47µF, 25V, Radial Lead

1 C3 ECE-A1EU470, Panasonic(714) 373-7366

Cap, Ceramic,.1µF, 63V, Radial Lead

1 C2 ECU-S1J104KBB, Panasonic(714) 373-7366

Cap, Ceramic,.001µF, 63V, Radial Lead

1 C1 ECU-S1J102JCB, Panasonic(714) 373-7366

Terminal Block, Wire-to-PCB,2 Position Dual-Stackable,200mil spacing

2 CN1,2 ED120/2DS, On-Shore Technology(602) 921-3000

Resistor, 1/4 Watt, 47Ω, 1%, Axial Lead 2 R2,3 Generic

Resistor, 1/4 Watt, 6.04KΩ, 1%, Axial Lead 1 R1 Generic

Transformer, Toroid100KHz

1 T1 TF5S03ZZ3464, Airborne Power(Core XJ-41605-TC)See Acknowledgments for email address

IC, PWM, 16-Pin DIP 1 U1 UC3525BN, Unitrode(603) 429-8610

Transistor, TO-220N-Chan, MOSFET, 50V

2 Q1,2 NDP4050, National Semiconductor(408) 712-5800(800) 272-9959 (USA Only)

PCB, 2.4” x 2.4”Bias Supply, 100KHz

1 Generic PCB

Retainer, Toroid 1 100-2, Delbert-Blinn(909) 629-3900

Screw, 4-40x1/2 ”, Stainless Steel 1 Generic

Washer, 4-40”, Stainless Steel 1 Generic


PICREF-1

TABLE F-2: OTHER BOM


CONTACT #

Rectifier-Bridge Circuit 1 M5060SB1200, CRYDOM(818) 956-3900

Power Supply PCB 1 SW10-15PC, Toko America(847) 297-0070

Audio Transformer(On-Board Isolation Transformer)

1 705-0862, Allied(817) 595-3500(800) 433-5700 (USA Only)


PICREF-1

F.2.1 DEMO UNIT ASSEMBLY A UPS Demo Unit is shown in different stages ofassembly, for top and side aspects, in the figures below.

FIGURE F-4: DEMO PARTIAL ASSEMBLY - TOP VIEW

FIGURE F-5: DEMO FULL ASSEMBLY - TOP VIEW

DANGERElectrocution Hazard

Do Not Disassemble Unit

rectifier

input filterinductor

inputfiltering

output filterinductors

outputpower

inputpower

inputfuse

IGBT’s

IGBT’s

biasboard

heatsink

DC Buscapacitor

outputfiltering

H-Bridge(IGBT’s)

inverter controlcard

inverter drivecard

“Electrical Hazard”

“Danger:High Voltage”

outputpower

biasboard


powersupply

on-boardisolationtransformer

DC Bus


PICREF-1

FIGURE F-6: DEMO PARTIAL ASSEMBLY - FRONT VIEW

FIGURE F-7: DEMO FULL ASSEMBLY - FRONT VIEW

input filterinductor

biasboard IGBT’s IGBT’s

rectifierinputfiltering

output filterinductors

outputpower

inputpower

heatsink

fuse


inverter drive card(underneath inverter control card)

DC Buscapacitor

outputfiltering

H-Bridge(IGBT’s)

“Electrical Hazard”



biasboard

powersupply

outputpower

DC Bus


PICREF-1

FIGURE F-8: DEMO PARTIAL ASSEMBLY - INVERTER CARDS DETAIL

FIGURE F-9: DEMO FULL ASSEMBLY - DC BUS DETAIL


inverter drivecard

DC Buscapacitor

outputfiltering

H-Bridge(IGBT’s)

biasboard

DC Buscapacitor

DC Bus

DC Bus

IGBT’s IGBT’s


Do Not Touch DC Bus


PICREF-1

F.3 How to Demo the PICREF-1

The UPS Demo Unit was not designed for sustaineduse, but only for short-term demonstration. Disconnectthe unit when not in use.

Follow these steps to demo the UPS Demo Unit:

1. Plug the receptacle end of a power cord into theUPS Demo Unit “AC Input”. Plug the prongedend of the power cord into an AC wall socket.

2. Plug the load into the UPS Demo Unit “Load”socket (Optional). Make sure load can be drivenby the UPS Demo.

3. Connect an oscilloscope probe to the UPSDemo Unit “Load Monitor” BNC connector.

4. Display (Stepped Down) AC Output waveformon oscilloscope.

FIGURE F-10: HOW TO SET UP DEMO UNIT - REAR VIEW

Note: An isolation transformer should be usedwith the UPS Demo Unit to avoid impropergrounding.


Do Not Disassemble Unit

Load MonitorRatio 1:23

LoadAC Input


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Documents

M PICREF-1 · The battery boost voltage is set slightly lower than the rectiﬁed AC input voltage so that, under normal condi-tions, the rectiﬁed AC input power provides power