M. Labiche - INTAG workshop GSI 24-25 May 2007 1

Se-D prototype for the focal plane of the PRISMA spectrometer

(Task4)

Digitisers for SAGE & LISA(task1)

M. Labiche - INTAG workshop GSI 24-25 May 2007 2

Se-D prototype for the focal plane of the PRISMA spectrometer

(Manchester, Daresbury, Paisley EPSRC grant)

• Detector:– Principle (see Ivan Mikka’s talk)

– Prototype at Manchester

• Electronics– ASIC’s + FADCs

3

Motivation

Z, A identification for medium mass and heavy nuclei

4

In-beam MWPC

Out-of-beam MWPC

Emissive foilSED

Californium source (for tests in Manchester only)

FIGURE 2: Prototype SED with in-beam MWPC and source

In-beam MWPC

Out-of-beam MWPC

Emissive foilSED

Californium source (for tests in Manchester only)

FIGURE 2: Prototype SED with in-beam MWPC and source

Prototype at Manchester University

- Aluminized mylar emissive foil (~.9µm thick)

- MWPC with 64 wires

- with individual wire readout

5

Prototype SED PPAC readout

•Gassiplex 16 channel ASIC

•Preamp – Shaping amp – Track and hold

•Analog multiplexed output

•Two GAS32 boards – 64 PPAC wires – four connections.

• 5Mhz readout clock – 14us

• 10 ADC samples per channel – average of four recorded.

•PowerPC in the FPGA formats data

•Currently slow serial link to MIDAS in PC – 100hz event rate.

•Ethernet is in development

GAS32 boardTwo 16 channelGassiplex ASICs

GAS32 boardTwo 16 channelGassiplex ASICs

V4FADC board

8 x 12 bit FADC50Mhz

Xilinx FPGA XC4VFX12Operates the Gassiplex

control and readout. FADCconversion and data storage

Clock +

readout control s

Ana

logu

e mul

tiplex

ed

RS-232 Serial

Trigger

64 chan

nels - t im

e mu

ltiplexed

onto on

e analo gu

e signal

Data read

out fr om

FP

GA

Regis ter an

d m

emory acc ess.

10 x LVDS links

JTAG FPGAre-programming

32 PPAC wires 32 PPAC wires

The EDAQ readout system

From P. Coleman-Smith

6

Existing ASICS chips : Gassiplex (Gas32)

Two Gas32 cards(with 2x16 Gassiplex

ASICs per card)reading 64 PPAC

wires in place behind the MWPC.

ASICs

7

Eight channel FADC - ASIC readout module in the laboratory during development

Flash ADCs module

8

Test of the FEE prototype at Daresbury Lab.

1 Gas32 cardconnected to a 16x2 strips DSSD

3- source used

The FEE prototypeperformed well

9

10

Gaseousdetector

64 outputchannels

11

- Two GAS32 boards are installed in the chamber to read 64 wires from the gaseous detector.

- The V4FADC and data acquisition equipment is installed in Manchester for use with the SED prototype.

- VME readout of a second MWPC installed into the same data acquisition system.

- Ten further V4FADC modules have been manufactured by Norcott Engineering.Commissioning will be carried out by P.J. Coleman-Smith.

In summary :

M. Labiche INTAG workshop GSI 24-25 May 2007 12

Digitisers for SAGE & LISA

• Detector SAGE & LISA:

• Digitisers + TDR interface

13

Silicon And Germanium array (SAGE)(Liverpool, Daresbury EPSRC grant)

• For spectroscopy of heavy nuclei

• SAGE will be used to detect in coincidence the electrons and photons at target position of RITU. SAGE sensitive to both E2 and M1 transitions

• SAGE : Jurogam + SACRED

14

Light Ion Spectroscopy Array (LISA)(Liverpool, Surrey, Daresbury EPSRC grant)

• For proton drip line spectroscopy (in the region N=Z)

• LISA = Si detector at target position of RITU to detect prompt charged particles (protons or alphas).

• LISA design:

Resis. strip octagonal detector +

annular DSSD at forward angles

15

Digital Electronics Requirements:

• 14bits, 100MHz for pulse shape analysis & energy is normal

• But, don’t need PSA because detectors aren’t segmented and preamps are too slow.

• So 14 bits 50MHz would be fast enough.

• Real time processing up to 30kHz count rate (energy only)

• Data rate: 30k x (energy (2) + timestamp (6) + ID (2))= 300kBytes/second per channel: 5Mbytes/sec/16 chan card.

• 100 channels = 30Mbytes/sec.

From Ian Lazarus

16

Commercial electronics: why?

• Nicely packaged for our application

• Volume users (Radar, software radio)= sensible price

• Powerful FPGA built in

• Can process 50kHz singles rate on 48 channels

• 20-30Mbytes/sec output- OK over CPCI backplane

• Needs interface cards for TDR port and analogue matching

From Ian Lazarus

17

TDR

Interface

Clk Sync Rst outErr in

Clk

Exttrig gpio

AD

Cs

FPGA

FPDP CPCI

16

Clk

Exttrig gpio

AD

Cs

FPGA

FPDP CPCI

16

Clk

Exttrig gpio

AD

Cs

FPGA

FPDP CPCI

16

Clk

Exttrig gpio

AD

Cs

FPGA

FPDP CPCI

16

CPCIhost

CPCI for setup, readout and control

Diagram of example 64 channel DAQ system

From Ian Lazarus

18

GREATMetronome

VHS-ADC

VHS-ADC

VHS-ADC

VHS-ADC

TDR Port Clk 100

Sync

Reset outError in

STFC- madeTDR interface

Andclock fan-out

Also AnalogueGain/offset

Clock/TDR Interface card

From Ian Lazarus

19

Block Diagram ofSmartpet GPIOand TDRInterface Cardv0.1 28-11-05

TDRPort

Precision 1:8clock driver.Clock Sync

Precision 1:8clock driver100MHz clk.

FPGA for control,decoding andlogic signalconnections

Ethernetor Xport

Diff ECL logic i/o4x16 = 64 signals

ADC card GPIO(4x32= 128 pins)

DAC

Front PanelClock input

Front PanelSync input

TDR clock input

TDR sync input

Front PanelClock outputs

Front PanelSync outputs

100MHz ClockClock sync pulse

Clock in select

Algorithmvisualisationoutputs

EEPROM JTAG

Block Diagram ofSmartpet GPIOand TDRInterface Cardv0.1 28-11-05

TDRPort

Precision 1:8clock driver.Clock Sync

Precision 1:8clock driver100MHz clk.

FPGA for control,decoding andlogic signalconnections

Ethernetor Xport

Diff ECL logic i/o4x16 = 64 signals

ADC card GPIO(4x32= 128 pins)

DAC

Front PanelClock input

Front PanelSync input

TDR clock input

TDR sync input

Front PanelClock outputs

Front PanelSync outputs

100MHz ClockClock sync pulse

Clock in select

Algorithmvisualisationoutputs

EEPROM JTAG

Clock/TDR Interface card

From Ian Lazarus

20

Gainadjust

Offset adjust

Ethernetor Xport

Gainadjust

Gainadjust

Gainadjust

Gainadjust

Gainadjust

Gainadjust

Gainadjust

Offset adjustOffset adjustOffset adjustOffset adjustOffset adjustOffset adjustOffset adjust

FPGA toDecode

commands

NovRAMholds

latest values

0 to +/-12V inputrange defined by preampSensitivity is 300mV/MeV

Gain range x1 to x64(Needs 12V rails for input side; output only +/-1.1V)

Can operate standalone using previously loaded gains and offsets

0 to +/-1.1V output(defined by ADC)

64 64

Block Diagram of Smartpet Analogue Interface Card v0.1 28-11-05

Maximum output offset is only +/-1.1V but input could be much large- use +/-12V rails.

Gainadjust

Offset adjust

Ethernetor Xport

Gainadjust

Gainadjust

Gainadjust

Gainadjust

Gainadjust

Gainadjust

Gainadjust

Offset adjustOffset adjustOffset adjustOffset adjustOffset adjustOffset adjustOffset adjust

FPGA toDecode

commands

NovRAMholds

latest values

0 to +/-12V inputrange defined by preampSensitivity is 300mV/MeV

Gain range x1 to x64(Needs 12V rails for input side; output only +/-1.1V)

Can operate standalone using previously loaded gains and offsets

0 to +/-1.1V output(defined by ADC)

64 64

Block Diagram of Smartpet Analogue Interface Card v0.1 28-11-05

Maximum output offset is only +/-1.1V but input could be much large- use +/-12V rails.

Analogue Interface card

From Ian Lazarus

21

• Lyrtech digitiser cards purchased for another project have been evaluated.

•Electronics and DAQ work has confirm the suitability of new (commercial) digitisers, built by Lyrtech, as the basis for EDAQ in experiments such as SAGE and LISA.. • Software for backplane data readout has already been implemented by V. Pucknell

Summary

22

• a NIM card has been designed and built to interface the new digitisers with the GREAT TDR and clock system.

• This card is being commissioned now (Spring 2007), and the VHDL code for its programmable logic has recently been completed.

•Another NIM card has been built and is being debugged which allows gain and offset control for the digitiser inputs (controlled over Ethernet link).

Summary