Lund University Lund

Skåne

Sweden

Ulf Mjörnmark

Status and plans

JRA2TPC DAQ

TPC local trigger

TPC

RCU

back

plane

25cm FECData in/out200MB/s2 fibres

Distrbox40MHz

clk

lvl1

busy

2048ch,16 FEC

close

BUSy

Trigger +event #

TLUMainDAQ

CLk

metersaway

clk

busy

Trigger +event #

Other subsys daq

ethernet

Based on the ALICE TPC readout:Front End Card (FEC), to be modified for new amplifierReadout Control Unit (RCU), modified for clock/trigger/25Mhz sample clockSource Interface Unit (SIU)Read Out Receiver Card (DRORC), Destination Interface Unit (DIU)ALICE API/driversBuild our own DAQ on topDistributor Box (DBOX) to distribute clock/trigger/busyInterface to common DAQ

EUDET: 1 RCU10000 ch: 4 RCUpossible to distribute 1 RCU system

Hardware overviewFrontEndCardReadoutControlUnitReadOutReceivrCardDistributorBOX

19 cm

17 c

m

ALICE TPC Front End Card

ALTRO 16 ch ADC

PASA to be raplced with

Programmable Charge Amplifier (PCA16)

Trigger/Busy system

Ethernet

ALTRO bus

synchronization:compare event numbercompare time stampsfrom RCU/TLU/DAQPC

busy logic:trigger sets system busybusy reset either:1) DAQPC via ethernet2) Fixed time in distributor box

Cables

TEST SETUP

DRORC

Optical fiberALICE FECBackplane

RCU

Trigger

Power

Pulser

Busy/Control( Parallel port )

Raw data (double pulse)

TIME = 100ns per bin (10 MHz sample clock)410 samples

AD

C v

alu

e

AD

C v

alu

e

Pedestal subtractedZero suppressed(Multiple pulses)

DATA

from

TEST

SETUP

Use ALICE drivers and APIs as isBuild DAQ (readout/control) on topInterface to common DAQ

SUMMARY

Based on ALICE TPC readoutNew preamplifier on front end card Using ALICE driversBuild simple DAQ on topDistributor box to distribute trigger/clock/busy

Simple test setup working

Work in progress on:front end cardsdistributor boxreadout of hardwarereadout configuration

Missing:run controlmonitoringdetector controldata transfer and format