LSST Electronics Review – BNL, January 25-26 20121 LSST Electronics Review BNL January 25-26 2012 Raft Electronics Overview R. Van Berg Electronics Mini-Review

LSST Electronics Review – BNL, January 25-26 2012 1LSST Electronics Review • BNL • January 25-26 2012

Raft Electronics Overview

R. Van Berg

Electronics Mini-ReviewJanuary 25th, 2012

LSST Electronics Review – BNL, January 25-26 2012 2

Outline – LSST Raft Electronics

• Driving Requirements• Raft Functionality• FEB Overview• ASIC Functions• Raft Logical Organization• Back End Functions• Back End Logical Organization• Institutional Responsibilities


Driving Requirements

• Noise (10 e-)– ASPIC design– Diff amp and ADC choice– Integration time (vs. readout time)

• Crosstalk (0.05%)– ASPIC design– FEB design– Cable design– Power distribution

• Readout time (2 sec)– Integration time (vs. noise)– ADC speed– DAQ speed

• Dynamic range (> 90,000 e-)– ADC range– Noise

• Space– Fit in shadow of focal plane– Front and BE electronics in cryostat– Small cable plant to feed through flange

• Thermal– Low temperature differences across

boards• Power (as low as possible)

– Cryo cooling for FEB– Cold cooling for RCC

• Environmental contamination– Low outgassing (to protect CCD surface)

• Repairability– Modularity (rafts vs. unitary FP)– Raft level power, control, data flow

• Reliability– Conservative design– Extensive testing– High quality materials, parts


Cryostat Main Chamber Housing is the Primary Integrating Structure of the Camera• FUNCTIONALITY:– Low mass aluminum vacuum vessel & rigid support ring– Stiff Si Carbide Grid to support &

stabilize focal plane array– Cryo-plate, cold-plate & shrouds

to stabilize thermal environment of Grid, the sensors and electronics

– Getter pumping to reduce condensates on focal plane

Cryo Feedthru (3.07.07)

Cold Plate (3.07.03)

Grid(3.07.05)

Focal planeRaft Sensor

Array

Cryo shrouds (3.07.03)

Back end crate

Front end crate Housing (3.07.02)

Backend Vacuum plate (3.07.07)

Getter Pump (3.07.06)

Support Ring (3.07.02)

L3 & L3 Flange

Cryo Plate (3.07.03)


Raft Functionality – Front End Cage + Raft Control Crate

• ASPIC– Preamp– DSI

• CABAC– Clock Drive– Bias drive (OD, RD, etc.)

• Current Source– OS sink

• Power Regulators for ASICs

3.2 Gb/s I/O

18 Bit 1MS/s

ASPIC ADC

FPGA

CABAC

Diff Amp

FEB – 24 ChannelsFull Custom ASICs

BEB – 24 ChannelsCommercial parts

RCM – 144 ChannelsCommercial parts

i

CCD

CCD

CCD

• Diff Amps– ADC Drive– Offset

• ADCs– 18 bit for video– 12+ bit for monitor*

• Low Level Clock Drive• DACs and V Regulators

– Clock levels– Biases

• FPGA– Generate timing phases– Absorb ADC data– Serialize and Xmit ADC data– Configure and control SPI

bus devices

DACs

6X 6X 1X

* Not yet implemented


3.2 Gb/s I/O

18 Bit 1MS/s

Raft Functionality

ASPIC ADC

FPGA

CABAC

Diff Amp

FEB – 24 ChannelsFull Custom ASICs

BEB – 24 ChannelsCommercial parts

RCM – 144 ChannelsCommercial parts

Front End Cage -100C Raft Control Crate -40C

i

CCD

CCD

CCD

DACs


Front End Board – Six per Front End Cage

• All Analog processing– Preamplification– Dual Slope Integration

• Clock Drive• Bias generation for CCDs• 10 Layers

– Shielded transmission lines to back end– Multiple GND planes– Lo capacity inputs to ASPIC– All command lines LVDS– Separate LDO analog regulators for

ASPIC and SCC chips• High thermal conductivity to edge

bars– Thermal simulations show only a few

deg rise across board – need to verify• High rel. connectors – nano to CCD

and micro to BEB

24 Current sources (IS)3 ASPICs (8 channels each)

6 SCCs (3 serial clocks, 3 parallel) Goes to

3 CABACs next version

CCD connectors (3)Bias and control

Video output


Analog signal processing of CCD :ASPIC – 3 Per FEB

Techno : CMOS 0.35µ/5V Vendor : AMS Packages :

CQFP100 CQFN100

8 DSI channels

3 programmable input amplifier gains : 2.5 – 5 – 7.5 to deal with CCD gain spread.

3 integration time constants : 500ns – 1µs – 1.5µs to deal with CCD readout frequency.

Idle mode : DC current reduction by a factor of 1000

baseline : { gain 5 & 500ns integration time}

IntegratorsInput amp

Single ended to diff

Thermal PAD

CQFN pack.


Read Out Method : Dual Slope Integration

CCD Reset

ASPIC Reset

CCD Output

Integration TimeTint

Isolation Time

ADC S/H

Dual Slope Integration sequence

One of the 2 differential channel output

Ramp Down(integrate noise)

Ramp Up(integrate signal + noise)


CABAC : clock and biases asic for CCD

10

IΦ0

IΦ1

IΦ2

IΦ3

IΦ3

CABAC

Serial link

RO

EXT<5:0>

Clocks

OD

Biases

Muxout<1:0>Clock timing


Logical Organization – a short RTM primer….

• Each Raft has 9 sensors– Each sensor has 16 outputs –

8+8• Each Raft has 6 FEBs• Each FEB has 24 channels

– Two FEBs handle 3 CCDs• 3 x 8 outputs = 24 channels• 3 ASPICs per FEB• Serial clocks from both FEBs• Parallel clocks from one FEB• Two types of FEB (CABAC will

simplify)– One BEB per FEB – all BEBs

identical• Geographical coding selects clock

type– One RCM per raft – 144

Mpixels, 3.2Gbps output

6 BEBs 6 FEBs 9 CCDs1 RCM

Front End CageFEC

Raft Tower ModuleRTM

Raft Control CrateRCC


RCC Functionality - BEB

• Video Digitization – 18 Bit, 1Msps precision ADCs– Run at ~ 550 kpixels/sec to meet 2 second readout requirement– Differential output from ASPIC into discrete diff amp to drive ADC (high C load)

• ADC diff input range from +5V to -5V 18 bits• ASPIC output actually goes from 0 diff to +5V diff so really only 17 bits at ADC

• Data Parallelization (serial to ||)– 24 streams of serial 18 bit data are rearranged into 24 parallel 18 bit words via

CPLD on BEB• Voltage and Bias supply

– Provide adjustable upper and lower rail voltages for clocks (three “types” – parallel, serial, reset)

– Provide adjustable “high” rails for bias drives (OD, guard, RD)– Pass through negative substrate supply from external power supply

• Control and Monitoring– Provide raft heater power drive (resistors on raft baseplate)– Provide temp and voltage digitization*– Provide fast spy digitization (TBD)** Not on present version.


RCC Functionality - Backplane

• Connects 6 BEBs to one RCM• Bus power to all BEBs• Bus timing signals to appropriate BEBs

– ASPIC timing to all BEBs– Parallel Clocks to half of BEBs– Serial (+Reset) Clocks to other BEB of each pair

• Handle slow control signals to BEBs– Provide Geographic address for each BEB– Bus SPI bus and SPI address to all BEBs


RCC Functionality – Raft Control Module (RCM)

• Provide timing signals to backplane– Timing engine in FPGA based upon 50 MHz clock programmed by simple,

concatenated commands – a dozen or so lines of code define an entire readout sequence

– Convert single ended timing signals from FPGA to LVDS• Receive digitized words from backplane and transmit packets to DAQ (|| to serial)

– Twenty four 18 bit words per BEB per pixel position– Build data packets to pass to DAQ engine in FPGA that then ships data to SDS over

a 3.2 Gbps link (significant spare bandwidth given 144 Mpixels x 2.25 Bytes in 2 sec)• Control ADCs and DACs on BEBs through SPI

– Measure temperatures– Measure voltages and currents– Set voltages and currents

• Configure FEB (ASPIC and CABAC) through SPI– Set gains, integrations times, voltages, test modes, monitoring paths– Single SPI bus, 7 address bits available, SS done in BEB CPLD


RCC Functionality – Raft Control Module (RCM) - II

• USB Interface (present version only)– Debugging interface– Data interface for a small subset of data (limited by FPGA buffer memory)

• TCM Interface– Originally ideated as similar to NOvA scheme

• Reference clock input• Control stream input / output• Reconfigure FPGA via CPLD on RCM

– Next version will use only reference clock and fast command signals from TCM• Single serial input 8b/10b• Command carried on clock line, single byte, 255 possible commands (e.g. synch, reset,

begin readout, ….• Reconfigure FPGA via standard JTAG• No USB


RCC – Back End Board (BEB); Backplane; Raft Control Module (RCM)• BEB – 24 eighteen bit 1 MHz ADCs with high speed differential drivers• DAC-Op amp driver combos to supply programmable voltages to FEB• CPLD to decode and drive LVDS timing signals to FEB• CPLD to deserialize, store, and transmit ADC serial streams to RCM• RCM collates data from 6 BEBs and spits out a 3.125 Gbps stream to DAQ


BEB Block (crudely)

24 X (Diff Amp + ADC)

LVDS Drive X 14

Video In

Timing Out

SPI Bus to FEB

V from DACs

V from Regulators

V from PDS

FP Temp measureBEB SPI bus

CPLD

BackplaneTo RCM

ClocksADC cvtPowerSPI +Addr Bus


RCM (crudely)

BackplaneFrom RCM

ClocksADC ConvPowerSPIAddr Bus

FPGA

DAQ

Clock

TCM

Data


Institutional Responsibilities – RTM Electronics(2011)• IN2P3

– ASPIC• Design• Fabrication• Testing

– CABAC• Design• Fabrication• Testing

– CCD Readout• Harvard

– RCC – all boards• Design• Fabrication• Testing• Firmware

– TCM– Vertical Slice Test

• Digital testing• Preparation for CCD readout

• Penn– FEB

• Design• Fabrication• Testing

– Vertical Slice Test• Analog testing• Preparation for CCD readout

• SLAC– DAQ

• Firmware in RCM FPGA• Testing

– Vertical Slice Test• Preparation for CCD readout

• Ohio State– Optical Transition Module

• Design• Fabrication• Testing

End of Presentation

Documents

LSST Electronics Review – BNL, January 25-26 20121 LSST Electronics Review BNL January 25-26 2012 Raft Electronics Overview R. Van Berg Electronics Mini-Review