LSISAS2008 6Gb/s SAS/SATA Controller Reference Manualread.pudn.com/downloads701/doc/project/2821052/LSISAS2008... · 2015. 8. 21. · LSISAS2008 6Gb/s SAS/SATA Controller Reference

LSISAS2008 6Gb/sSAS/SATA Controller

Reference Manual

Version 2.1September 2010

Revision History

Version and Date Description of Changes

Version 2.1, September 2010 Corrected the maximum 1.0-V supply voltage in Table 19.Added default setting information to the Flash ROM timing tables in Chapter 5.Updated the PBSRAM and Flash RAM Write timing diagrams in Chapter 5.

Version 2.0, February 2010 Added the supported JTAG version in Section 1.6.10.Updated the default device ID information in Section 3.2.2.Updated the package drawing in Section 4.2.1.Updated the timing parameter information in Section 5.3.Applied minor editing changes.

Version 1.4, August 2009 Added a new SAS feature to Section 1.6: support for greater than 2-TB addressing.

Version 1.3, June 2009 Corrected the package number in Section 4.2.1.Removed Vdd-ppc from Table 19 because the controller does not separate PPC from Vdd.Removed Vdd-ppc1.2 from Table 20 and changed the Vdd-1.0 values to match the 2% tolerance.Updated the SAS/SATA transmitter characteristic tables in Section 5.1.2.

Version 1.2, September 2008 Corrected the dimensions of the die in Section 4.2.1.

Version 1.1, July 2008 Added SRAM timings to Table 5-21. Removed references to DDR2 Modes 1–3 from Table 5-20.

Version 1.0, June 2008 Initial release of this document.

LSI, the LSI logo, Fusion-MPT, and GigaBlaze are trademarks or registered trademarks of LSI Corporation or its subsidiaries. All other brand and product names may be trademarks of theirrespective companies.

LSI Corporation reserves the right to make changes to the product(s) or information disclosed herein at any time without notice. LSI Corporation does not assume any responsibility or liability arisingout of the application or use of any product or service described herein, except as expressly agreed to in writing by LSI Corporation; nor does the purchase, lease, or use of a product or service fromLSI Corporation convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of LSI Corporation or of third parties.

This document contains proprietary information of LSI Corporation. The information contained herein is not to be used by or disclosed to third parties without the express written permission ofLSI Corporation.

Corporate Headquarters Email WebsiteMilpitas, CA [email protected] www.lsi.com800-372-2447

Document Number: DB13-000117-07Copyright © 2010 LSI CorporationAll Rights Reserved

LSISAS2008 6Gb/s SAS/SATA Controller Reference Manual Table of Contents

Table of Contents
Chapter 1: Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
1.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

1.2 Benefits of PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

1.3 Benefits of SAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

1.4 Benefits of Fusion-MPT Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

1.5 Benefits of GigaBlaze Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

1.6 Summary of LSISAS2008 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111.6.1 PowerPC Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111.6.2 RAID Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111.6.3 PCI Express Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111.6.4 SAS Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121.6.5 SATA/STP Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131.6.6 Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131.6.7 Usability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131.6.8 Flexibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131.6.9 Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131.6.10 Testability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Chapter 2: Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

2.1 Block Diagram Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152.1.1 PCI Express Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162.1.2 PowerPC 440 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172.1.3 SAS Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172.1.4 Peripheral Bus Access Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172.1.5 Clock, Configuration, and Reset Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182.1.6 Context RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

2.2 Overview of Fusion-MPT Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182.2.1 System Interface Doorbell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182.2.2 Messaging Queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

2.3 SAS Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Chapter 3: Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

3.1 PCI Express Configuration Space Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213.1.1 IOV Virtual Function PCI Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213.1.2 Single-Root I/O Virtualization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213.1.3 PCI Express Configuration Register Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

3.2 PCI Express Configuration Space Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283.2.1 Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283.2.2 Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283.2.3 Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293.2.4 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .303.2.5 Revision ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .313.2.6 Class Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .313.2.7 Cache Line Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .313.2.8 Latency Timer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .323.2.9 Header Type Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .323.2.10 BIST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .323.2.11 I/O Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333.2.12 Mem 0 BAR Lower Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

LSI Corporation Confidential | September 2010 Page 3

Table of Contents LSISAS2008 6Gb/s SAS/SATA Controller Reference Manual

3.2.13 Mem 0 BAR Upper Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .343.2.14 Mem 1 BAR Lower Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .343.2.15 Mem 1 BAR Upper Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .353.2.16 Subsystem Vendor ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .353.2.17 Subsystem ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .363.2.18 Expansion ROM Base Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .363.2.19 Capabilities Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .373.2.20 Interrupt Line Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .373.2.21 Interrupt Pin Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .383.2.22 Power Management Capability ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .383.2.23 Power Management Next Capability Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .393.2.24 Power Management Capabilities Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .393.2.25 Power Management Control/Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .403.2.26 PCI Express Capability ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .413.2.27 PCI Express Next Capability Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .413.2.28 PCI Express Capabilities Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .423.2.29 PCI Express Device Capabilities Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .433.2.30 PCI Express Device Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .443.2.31 PCI Express Device Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .453.2.32 PCI Express Link Capabilities Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .463.2.33 PCI Express Link Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .473.2.34 PCI Express Link Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .493.2.35 PCI Express Device Capabilities 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .503.2.36 PCI Express Device Control 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .513.2.37 PCI Express Device Status 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .533.2.38 PCI Express Link Capabilities 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .533.2.39 PCI Express Link Control 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .533.2.40 PCI Express Link Status 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .563.2.41 MSI Capability ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .573.2.42 MSI Next Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .573.2.43 MSI Message Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .583.2.44 MSI Lower Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .593.2.45 MSI Upper Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .593.2.46 MSI Message Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .593.2.47 MSI Mask Bits Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .603.2.48 MSI Pending Bits Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .603.2.49 MSI-X Capability ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .603.2.50 MSI-X Next Capability Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .613.2.51 MSI-X Message Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .613.2.52 MSI-X Table Offset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .623.2.53 MSI-X PBA Offset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .633.2.54 Vital Product Data Capability ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .633.2.55 Vita Product Data Next Capability Pointer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .633.2.56 Vital Product Data Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .643.2.57 Vital Product Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .643.2.58 PCI Express Advanced Error Reporting Enhanced Capability Header Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .653.2.59 PCI Express Uncorrectable Error Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .663.2.60 PCI Express Uncorrectable Error Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .673.2.61 PCI Express Uncorrectable Error Severity Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .683.2.62 PCI Express Correctable Error Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .693.2.63 PCI Express Correctable Error Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .703.2.64 PCI Express Advanced Error Capabilities and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .703.2.65 PCI Express Header Log Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .713.2.66 PCI Express Power Budgeting Enhanced Capability Header Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .713.2.67 PCI Express Power Budgeting Data Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

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LSISAS2008 6Gb/s SAS/SATA Controller Reference Manual Table of Contents

3.2.68 PCI Express Power Budgeting Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .723.2.69 PCI Express Power Budgeting Capability Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .743.2.70 SR-IOV Extended Capability Header Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .743.2.71 SR-IOV Capabilities Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .753.2.72 SR-IOV Status/Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .753.2.73 SR-IOV Total/Initial VFs Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .763.2.74 SR-IOV Func Dependency Links/ Num VFs Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .773.2.75 SR-IOVx VF Stride/First VF Offset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .783.2.76 SR-IOV VF Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .783.2.77 SR-IOV Supported Page Sizes Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .793.2.78 SR-IOV System Page Size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .793.2.79 SR-IOV VF Mem0 Lower BAR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .803.2.80 SR-IOV VF Mem0 Upper BAR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .803.2.81 SR-IOV VF Mem1 Lower BAR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .803.2.82 SR-IOV VF Mem1 Upper BAR Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .813.2.83 SR-IOV VF Migration State Array Offset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .813.2.84 ARI Extended Capability Header Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .823.2.85 ARI Control/Capability Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

3.3 System Interface Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .833.3.1 Doorbell Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .853.3.2 WriteSequence Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .853.3.3 HostDiagnostic Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .863.3.4 DiagRWData Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .873.3.5 DiagRWAddressLow Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .883.3.6 DiagRWAddressHigh Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .883.3.7 HostInterruptStatus Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .893.3.8 HostInterruptMask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .903.3.9 DCRData Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .903.3.10 DCRAddress Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .913.3.11 ReplyFreeHostIndex Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .913.3.12 ReplyPostHostIndex Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .913.3.13 HCBSize Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .923.3.14 HCBAddressLow Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .923.3.15 HCBAddressHigh Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .933.3.16 RequestDescriptorPostLow Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .933.3.17 RequestDescriptorPostHigh Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

Chapter 4: Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

4.1 Signal Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .954.1.1 PCI Express Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .954.1.2 6Gb/s SAS Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .964.1.3 External Memory Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .964.1.4 UART Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .974.1.5 I2C Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .974.1.6 GPIO Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .974.1.7 Serial GPIO Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .984.1.8 ICE Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .984.1.9 Internal Test Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .994.1.10 System Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .994.1.11 Power and Ground Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

4.2 Pinout and Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1014.2.1 Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1014.2.2 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102


Table of Contents LSISAS2008 6Gb/s SAS/SATA Controller Reference Manual

Chapter 5: AC, DC, and Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

5.1 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1115.1.1 PCI Express Transceiver Signal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1125.1.2 6Gb/s SAS Transceiver Signal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1135.1.3 External Memory Signal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1145.1.4 UART, System, and Other Signal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1155.1.5 I2C Signal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1165.1.6 GPIO and Serial GPIO Signal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

5.2 AC Characteristics: Reset Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

5.3 External Memory Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1175.3.1 PBSRAM Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1185.3.2 Flash ROM Read Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1195.3.3 Flash ROM Write Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1205.3.4 NVSRAM Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120


LSISAS2008 6Gb/s SAS/SATA Controller Reference Manual Chapter 1: Introduction | General Description

Chapter 1

1.1 General Description The LSISAS2008 controller is a 6Gb/s SAS/SATA I/O controller device that is designed around the Fusion-MPT™ architecture. The LSISAS2008 controller, which provides an eight-lane PCI Express interface and supports the Integrated RAID solution, is available in a 490-pin FPBGA package. The versatile LSISAS2008 controller supports both SAS and SATA devices and provides the backbone of both servers and high-end workstation environments. The controller is ideal for the host-side or drive-side connect for external storage controllers requiring a SAS/SATA interface. The Integrated RAID feature is a low-cost, high-performance RAID solution designed for blade, entry, and mid-range servers that require redundancy and high availability but for which a full-featured RAID implementation is cost prohibitive or is not desired. The advanced Integrated RAID options include support for the Integrated Mirroring (RAID 1), Integrated Mirroring Enhanced (RAID 1E), Integrated Striping (RAID 0), and Integrated Striping/Integrated Mirroring (RAID 10) solutions.

The following figure shows the LSISAS2008 controller used in a direct-attach storage configuration.

Figure 1: LSISAS2008 Controller Direct-Attach Storage Example

IntroductionThis chapter introduces the main features and functionality of the LSISAS2008 PCI Express to 8-Port Serial Attached SCSI/SATA Controller.

Flash ROM/LSISAS2008

PCI Express to SAS ControllerNVSRAM/

PCI Express Interface

PeripheralBus

8

PBSRAM/

SAS/SATADrives

SAS/SATADrives

I2C/UART


Chapter 1: Introduction | General Description LSISAS2008 6Gb/s SAS/SATA Controller Reference Manual

The following figure shows an example of an LSISAS2008 controller used in a configuration with SAS expanders.

Figure 2: LSISAS2008 Controller and LSISAS2x36 Expander Example

The LSISAS2008 controller supports the PCI Express Specification, Revision 2.0; the Working Draft of the Serial Attached SCSI-2 Standard; and the Serial ATA Specification, Revision 2.6 (15-February-2007). The PCI Express software is backward compatible with previous revisions of the PCI bus and PCI-X bus.

The point-to-point connections of the PCI Express interface limit the electrical load on links and enable increased transmission and reception frequencies. The PCI Express transmission and reception data rate is up to 5.0 Gb/s in each direction, yielding a total bandwidth of up to 10.0 Gb/s for each full-duplex interconnect. The LSISAS2008 controller has eight PCI Express phys, which provide possible host-side maximum transmission and reception rates of up to 40 Gb/s. The LSISAS2008 controller supports x8, x4, x2, and x1 PCI Express link widths, and automatically downshifts if plugged into a x4, x2, or x1 connector. The serial PCI Express interconnect also lowers the number of pins per device, which reduces both the PCI Express board design costs and the overall board design complexity.

PCI Express implements a switch-based technology to connect a large number of devices. Communication over the serial interconnect is accomplished using packet-based communication protocol. Quality of Service (QoS) features provide differentiated transmission performance for different applications. Hot-plug and hot-swap support enables "always-on" systems. Error-handling features make PCI Express suitable for robust high-end server applications.

Each of the eight SAS phys on the LSISAS2008 controller is capable of SAS/SATA link rates of 6Gb/s, 3Gb/s, and 1.5Gb/s. Ports can be configured as wide or narrow. Each port supports the SSP, SMP, STP, and SATA protocols.

SAS/SATADrives

SAS/SATADrives

PCI Express Interface

SAS/SATADrives

8

LSISAS2x36

LSISAS2008PCI Express to SAS Controller

PeripheralBus

SAS/SATADrives

SAS/SATADrives

LSISAS2x36

Flash ROM/NVSRAM/PBSRAM/I2C/UART


LSISAS2008 6Gb/s SAS/SATA Controller Reference Manual Chapter 1: Introduction | Benefits of PCI Express

The SAS interface uses the proven SCSI command set to ensure reliable data transfers, while providing the connectivity and flexibility of point-to-point serial data transfers. The SAS interface provides improved performance, simplified cabling, smaller connectors, lower pin count, and lower power requirements when compared to parallel SCSI. SAS devices leverage a common electrical and physical connection interface that is compatible with Serial ATA technology.

Fusion-MPT architecture is a multithreaded I/O algorithm that supports data transfers between the host system and SAS/SATA devices. The Fusion-MPT architecture is a performance-based, message passing protocol that offloads the host CPU by completely managing all I/Os and minimizes system bus overhead. The Fusion-MPT architecture requires only a thin, easy-to-develop device driver (provided by LSI) that is independent of the I/O bus.

1.2 Benefits of PCI Express The LSISAS2008 controller supports the PCI Express Specification, Revision 2.0. PCI Express software is backward compatible with previous revisions of the PCI bus and PCI-X bus. PCI Express is ideally suited for applications in mobile, desktop, workstation, server, embedded computing, and communication platforms.

Active State Power Management (ASPM) improves upon conventional PCI-based power management. ASPM enables PCI Express devices to reduce power consumption by powering down links that are not in use. Link power management functions permit powering down a single direction of a link, as could be the case during large file transfers. The LSISAS2008 controller supports the L0, L0s, and L1 link power management states, as well as the D0, D3hot, and D3cold power management states.

Error handling features make PCI Express suitable for robust high-end server applications. The LSISAS2008 controller supports end-to-end CRC (ECRC) to ensure data integrity, and contains a replay buffer that preserves a copy of the data for retransmission if a CRC error occurs. The LSISAS2008 controller also implements the PCI Express Advanced Error Reporting capability structure, which enables users to track error types and to assign severity levels (fatal or nonfatal) to errors.

As a native feature, PCI Express includes hot-plug capabilities that enable "always-on" systems. The PCI Express usage model enables hot-plug and hot removal of devices.

PCI Express implements a switch-based technology to connect a large number of devices. Communication over the serial interconnect is accomplished with packet-based communication protocol. Hot plug, power management, error handling, and interrupt signaling are accomplished using packet-based messaging rather than sideband signals.

PCI Express provides a scalable interface. The data transfer rate increases in proportion to the number of PCI Express phys. The LSISAS2008 controller provides eight PCI Express phys that operate at 5.0 GT/s in each direction to provide a maximum aggregate bandwidth of up to 8.0 GB/s (8000 MB/s).

PCI Express eliminates the need for sideband interrupt signals by using message signaled interrupts (MSI) and MSI-X. MSI and MSI-X messages are delivered to the host using a memory write transaction. The implementation of MSI and MSI-X is described in the PCI Express specification and the PCI specification.


Chapter 1: Introduction | Benefits of SAS LSISAS2008 6Gb/s SAS/SATA Controller Reference Manual

The LSISAS2008 controller supports lane reversal, which enables reversal of the lane numbers on the controller. The controller also supports polarity inversion, which permits swapping of the positive and negative signals of the transceiver. These features simplify board routing and layout.

Quality of Service (QoS) provides predictable latency and bandwidth. The LSISAS2008 controller supports a traffic class of 0 (TC0) and one virtual channel (VC0).

1.3 Benefits of SAS SAS is a serial, point-to-point, enterprise-level device interface that leverages the proven SCSI protocol set. SAS is a convergence of the advantages of SATA, SCSI, and Fibre Channel, and is the future mainstay of the enterprise and high-end workstation storage markets. SAS offers a higher bandwidth per pin than parallel SCSI and improves signal and data integrity.

The SAS interface uses the proven SCSI command set to ensure reliable data transfers, while providing the connectivity and flexibility of point-to-point serial data transfers. The serial transmission of SCSI commands eliminates clock-skew challenges. The SAS interface provides improved performance, simplified cabling, smaller connectors, lower pin count, and lower power requirements when compared to parallel SCSI.

SAS/SATA connectors and cables are easy to manipulate, allow connections to smaller devices and do not inhibit airflow. The point-to-point SATA architecture eliminates inherent difficulties created by the legacy ATA master-slave architecture, while maintaining compatibility with existing ATA firmware.

The LSISAS2008 controller can function as an SSP initiator, an SSP target, an SMP initiator, an STP initiator, or a SATA initiator. The controller uses SSP to communicate with other SAS devices and uses SMP to communicate topology management information with other SAS devices. STP communicates with SATA devices by tunneling through SAS expanders to the SATA device or by using the SATA protocol to communicate directly with the SATA device.

Additionally, the LSISAS2008 controller supports pattern generation for SAS and SATA connections, which facilitates board debugging and bring-up.

1.4 Benefits of Fusion-MPT Architecture

The Fusion-MPT architecture provides an open architecture that is ideal for the SAS and SATA interfaces. The I/O interface is interchangeable at the system and application level; embedded software uses the same device interface for different bus implementations, just as application software uses the same storage management interfaces for different bus implementations.

The Fusion-MPT architecture improves overall system performance by requiring only a thin device driver. The use of thin, easy to develop, common OS device drivers accelerates time-to-market by reducing device driver development and certification times.

The Fusion-MPT architecture supports interrupt coalescing, which allows an I/O controller to send multiple reply messages in a single interrupt to the host processor. Sending multiple reply messages per interrupt reduces context switching of the host processor and maximizes the host processor efficiency, which results in a significant improvement of system performance.


LSISAS2008 6Gb/s SAS/SATA Controller Reference Manual Chapter 1: Introduction | Benefits of GigaBlaze Transceivers

The Fusion-MPT architecture also provides built-in device driver stability because the device driver need not change for each revision of the LSISAS2008 silicon or firmware. This architecture is a reliable, constant interface between the host device driver and the LSISAS2008 controller. Changes within the controller are transparent to the host device driver, operating system, and user.

1.5 Benefits of GigaBlaze Transceivers

The GigaBlaze® transceivers that provide the physical layer for the LSISAS2008 controller are a proven component of LSI semiconductor expertise. The GigaBlaze transceivers are the fifth generation of the LSI GigaBlaze core. The GigaBlaze transceivers provide full-duplex, point-to-point communications channels that can operate at6Gb/s, 3Gb/s, and 1.5Gb/s SAS/SATA transfer rates.

The integrated GigaBlaze transceivers perform the 8b/10b conversion required for SAS and SATA transfers. The transmitter accepts parallel data, serializes it, and transmits it on the differential TX± signals. The receiver recovers the clock and deserializes the data from the bitstream that it receives on the RX+/RX– signals. Because the transceiver and receiver operate independently, the GigaBlaze transceivers can send and receive data simultaneously, which maximizes system performance. The GigaBlaze transceivers provide integrated internal termination. To facilitate board layout and routing, the polarity of the positive and negative signals can easily be reversed on both the TX± signals and the RX± signals.

1.6 Summary of LSISAS2008 Features

This section lists the features and benefits of the LSISAS2008 controller.

1.6.1 PowerPC Features The LSISAS2008 controller has a PowerPC 440 core, which supports the following features:

32-bit RISC CPU with up to 533-MHz performance

64-way, 32-KB I-Cache, 32-KB D-Cache units with parity

Superscalar seven-stage pipeline

Dynamic branch prediction

64-entry fully associative unified TLB

128-bit PLB interfaces

1.6.2 RAID Features The LSISAS2008 controller offers the following Integrated RAID features:

Integrated Mirroring (RAID 1)

Integrated Mirroring Enhanced (RAID 1E)

Integrated Striping (RAID 0)

Integrated Striping/Integrated Mirroring (RAID 10)

1.6.3 PCI Express Features The LSISAS2008 controller supports these PCI Express 2.0 features:

Eight PCI Express phys, with support for x8, x4, x2, and x1 link widths

Single-phy (1-lane) link transfer rate of up to 5.0 GT/s in each direction

Automatic downshift to a x4, x2, or x1 link width if plugged into a x4, x2, or x1 connector


Chapter 1: Introduction | Summary of LSISAS2008 Features LSISAS2008 6Gb/s SAS/SATA Controller Reference Manual

Scalable interface with the following options:

— Single-lane aggregate bandwidth of up to 1.0 GB/s (1000 MB/s)— Quad-lane aggregate bandwidth of up to 4.0 GB/s (4000 MB/s)— Eight-lane aggregate bandwidth of up to 8.0 GB/s (8000 MB/s)

Serial, point-to-point interconnections between devices, which enables higher transmission and reception frequencies and reduces the electrical load of the connection

Lane reversal and polarity inversion

PCI Express hot plug

PCI Power Management 1.2

Active State Power Management, including the L1 and L0s states, is supported by placing links in a power-saving mode when there is no link activity

32-deep command queue

Software compatibility with PCI and PCI-X software, which leverages existing PCI device drivers and provides support for the following:

— Memory, I/O, and configuration address spaces— Memory read/write transactions, I/O read/write transactions, and configuration

read/write transactions

4 KB of PCI configuration address space per device

Posted and nonposted transactions

QoS link configuration and arbitration policies

PCI Express Traffic Class 0 and one virtual channel, with native support for 16 virtual functions (single-root)

Message Signaled Interrupts (both MSI and MSI-X), as well as INTx interrupt signaling for legacy PCI support

1.6.4 SAS Features The LSISAS2008 controller supports these SAS 2.0 features:

6Gb/s, 3Gb/s, and 1.5Gb/s SAS data transfers

Serial, point-to-point, enterprise-level storage interface

Wide data transfers using from two to eight phys

Narrow ports consisting of a single phy

Data transfers using SCSI information units

Compatibility with SATA target devices

T10 Data Protection information model

2 MB of on-chip EDRAM for context RAM

Greater than 2-TB addressing by means of 16-byte SCSI Read/Write/Verify CDB for SAS and SATA


LSISAS2008 6Gb/s SAS/SATA Controller Reference Manual Chapter 1: Introduction | Summary of LSISAS2008 Features

1.6.5 SATA/STP Features The LSISAS2008 controller supports these SATA/STP features:

6Gb/s, 3Gb/s, and 1.5Gb/s SATA data transfers

6Gb/s, 3Gb/s, and 1.5Gb/s STP data transfers

Addressing of multiple SATA targets through an expander

Ability for multiple initiators to address a single target (in a failover configuration) through an expander

1.6.6 Integration These features make the LSISAS2008 controller easy to integrate:

Ability for PCI Express devices to use PCI-based device drivers, which reduces integration challenges and risks

Unequalled performance through the Fusion-MPT architecture

Reduced time to market with the Fusion-MPT architecture, which enables thin, easy-to-develop drivers and reduces integration and certification effort

High level of system integration, with support for a combination of 3000 devices, outstanding I/Os, or both without external RAM

1.6.7 Usability These usability features are incorporated into the design of the LSISAS2008 controller:

Simplified cabling with point-to-point, serial architecture

Drive spin-up sequencing control

Two SGPIO interfaces

1.6.8 Flexibility These features increase the flexibility of the LSISAS2008 controller:

Flash controller with up to 64 MB of flash memory

NVSRAM and PBSRAM controllers

One 16550-compatible UART

Two general-purpose timers

Flexible programming interface to tune I/O performance

Mixed connections to SAS or SATA targets

Grouping of up to eight SAS phys into a wide port

Compatible connectors for SAS and Serial ATA connections

36 conventional GPIO signals and two serial GPIO modules; 24 of the GPIO pins are configurable as LED indicators for Activity, Error, and Status

32-KB I/D L1 cache

1.6.9 Reliability These features enhance the reliability of the LSISAS2008 controller:

Isolation of the power and ground of I/O pads and internal chip logic

2-kV ESD protection

Latch-up protection

High proportion of power and ground pins

1.6.10 Testability These features enhance the testability of the LSISAS2008 controller:

JTAG 1149.6 boundary scan

UART connections to output debug information


Chapter 1: Introduction | Summary of LSISAS2008 Features LSISAS2008 6Gb/s SAS/SATA Controller Reference Manual


LSISAS2008 6Gb/s SAS/SATA Controller Reference Manual Chapter 2: Functional Description | Block Diagram Description

Chapter 2

2.1 Block Diagram Description

The following figure shows the block diagram for the LSISAS2008 controller. The following sections explain each major part of the block diagram.

Functional DescriptionThis chapter provides a subsystem-level overview of the LSISAS2008 PCI Express to 8-Port Serial Attached SCSI/SATA Controller, an overview of Fusion-MPT architecture, and an overview of SAS functionality.


Chapter 2: Functional Description | Block Diagram Description LSISAS2008 6Gb/s SAS/SATA Controller Reference Manual

Figure 3: LSISAS2008 Block Diagram

2.1.1 PCI Express Interface The PCI Express interface block supports an 8-lane PCI Express interface. This high-bandwidth serial interface features point-to-point interconnects between device, and an advanced packetized and layered protocol architecture. The LSISAS2008 controller supports PCI Express connections with x1, x2, x4, and x8 link widths. The LSISAS2008 controller supports revision 2.0 of the PCI Express specification, and the LSISAS2008 PCI Express software is backward compatible with previous implementations of the PCI specification.


LSISAS2008 6Gb/s SAS/SATA Controller Reference Manual Chapter 2: Functional Description | Block Diagram Description

2.1.2 PowerPC 440 Core The LSISAS2008 CPU core is the PowerPC 440, which provides an estimated 1066 DMIPS when running at 533 MHz. The PowerPC 440 core provides a 64-entry, fully associative unified translation lookup table, a 64-way, 32-KB data cache, and a 64-way, 32-KB instruction cache.

2.1.3 SAS Module The LSISAS2008 controller supports 6Gb/s, 3Gb/s, and 1.5Gb/s SAS, as well as 6Gb/s, 3Gb/s, and 1.5Gb/s SATA. The SAS module provides SSP Initiator and Target support, SMP Initiator support, SMP Target support for initialization, SATA/STP Initiator support, and SATA II Native Command Queuing support.

The SAS module manages SAS connections between initiator and target ports, data clocking, and CRC checking on transmitted data. They are also responsible for starting a link reset sequence. The SAS phys interface to the physical layer, perform serial-to-parallel conversion of received data and parallel-to-serial conversion of transmit data, manage phy reset sequences, and perform 8b/10b encoding.

The two serial GPIO blocks provide serial GPIO interfaces, conforming to SFF-8485, “Specification for Serial GPIO (SGPIO) Bus,” Revision 0.7 (1 February 2006).

The T10 Technical Committee of the International Committee of Information Technology Standards (INCITS) has standardized the basic requirements to implement a data protection model for end-to-end data protection. The main purpose of this model is to protect user data within a storage system from various sources of corruption that have historically gone undetected. Some examples of sources of this corruption are hardware data path errors (such as FIFO overruns/underruns), firmware errors (such as arithmetic overflow or incorrect pointer usage), and external agents overwriting the data in memory.

A fundamental component of the T10 data protection model is the addition of 8 bytes of extra protection information transferred with each block of user data in the storage system, as shown in the following figure. Although not specifically named in the T10 standards, this collection of 8 bytes is commonly referred to as the Data Integrity Field (DIF). The DIF contains three distinct values: a 2-byte Logical Block Guard, a 2-byte Logical Block Application Tag, and a 4-byte Logical Block Reference Tag. The T10 specification defines four types of usage models of data protection: Type 0, Type 1, Type 2, and Type 3 (refer to the most current revision of INCITS T10/1799-D for further information).

Figure 4: T10 Data Integrity Field

In addition to conforming to the T10 standards for the DIF, the LSISAS2008 controller supports passthrough, add, and remove operations.

2.1.4 Peripheral Bus Access Module The Peripheral Bus Access Module (PBAM) block manages the interface between an internal Processor Local Bus (PLB) and external memory devices for the LSISAS2008 controller. The PBAM interfaces to two I2C blocks, one 16550-compatible UART port, and General-Purpose I/O. The PBAM also provides control for external PBSRAM, FLASH, and NVSRAM.

User Data Logical BlockGuard

Logical BlockApplication Tag

Logical BlockReference Tag

“Block Size”Number of Bytes 8 Bytes of DIF

~ ~~ ~


Chapter 2: Functional Description | Overview of Fusion-MPT Architecture LSISAS2008 6Gb/s SAS/SATA Controller Reference Manual

2.1.5 Clock, Configuration, and Reset Logic

The Clock, Configuration, and Reset Logic block provides clock and reset distribution, miscellaneous control registers, and an I2C bootstrap controller (BSC) for loading optional configuration I2C serial EEPROM.

2.1.6 Context RAM The LSISAS2008 controller contains 2 MB of EDRAM for context RAM, which is used for the message frames, the FIFOs, and a portion of the firmware.

2.2 Overview of Fusion-MPT Architecture

The Fusion-MPT architecture provides two I/O methods for the host system to communicate with the IOP: the system interface doorbell and the message queues.

2.2.1 System Interface Doorbell The system interface doorbell is a simple message-passing mechanism that allows the PCI host system and the IOP to exchange information. The doorbell must be accessed as a 32-bit value. When the host system writes to the doorbell, the LSISAS2008 hardware interrupts the IOC so the IOC may read the value. The system cannot read the same value it wrote. When the IOC writes a value to the doorbell, the LSISAS2008 hardware generates a maskable interrupt to the host system, and then the system can read the value written by the IOC. The System Interface Doorbell register is also used to send commands and data to the IOC, primarily during initialization.

The system interface doorbell has a function called IOC Message Unit Reset, which instructs the IOC to perform the actions required to cease all DMA activity and transition the IOC to the Ready state. The system primarily uses this function to transition from one driver to another, but it may also be used when there is no other means to recover from an error, such as the IOC entering the Fault state.

The Handshake function passes an MPI request message to the IOC a word at a time, using successive accesses of the doorbell. The Handshake function is typically used as the host driver initializes the IOC because the message queues are not yet operational and the driver needs information to handle dynamic initialization parameters.

All request messages should be sent through the message queues whenever possible. Unless specified otherwise, all messages that are not part of the initialization sequence must be sent through the message queues.

2.2.2 Messaging Queues Message queues are the primary communications mechanism between the host system and the IOC. In general, the host system sends a request message to the IOC using a request queue. The IOC processes the request and sends a reply message using a reply queue.

The IOC provides a request queue that the host accesses by writing a request descriptor to the Request Descriptor Post register. The IOC also provides a Reply Post Host Index register to manage a reply descriptor post queue and a Reply Free Host Index register to manage a reply free queue. Both the reply post descriptor queue and the reply free queue are in host memory.

To send a request message to the LSISAS2008 controller, the host builds the message in system memory and writes a request descriptor describing the message to the Request Descriptor Post register. The controller processes the request, transfers the reply message to the host, and places a reply descriptor on the reply descriptor post queue.


LSISAS2008 6Gb/s SAS/SATA Controller Reference Manual Chapter 2: Functional Description | SAS Functional Description

There are two types of request message frames:

System request message frames reside in host system memory.

Local request message frames reside in the IOC and are private to the IOC.

During initialization, the host can determine from the IOC the required size of each request message frame and the number supported. The host must allocate a pool of system request message frames in physically contiguous system memory. The host uses these system request message frames to construct request messages.

For some specific message function codes, the IOC may send more than one reply per request message. For these cases, MPI provides a mechanism to allow the IOC to explicitly indicate whether a reply descriptor is returning control of a system request message frame to the host driver.

Credit is a method of flow control between the host and the IOC to prevent the overflow of the request queues. The IOC allocates credits to a host driver and reports the allocated credit in the IOCFacts reply message. The amount of credit allocated to the host driver does not change during run-time, but may change across power cycles or system-level resets. The reported credit value is the maximum number of outstanding request messages the host may have with the IOC. A request message is considered outstanding from the time the host writes the request descriptor to the Request Descriptor Post register until the host processes the corresponding reply descriptor that indicates the request is complete.

2.3 SAS Functional Description

The LSISAS2008 controller provides eight SAS/SATA phys. Each phy can form one side of the physical link in a connection with a phy on a different SAS/SATA device. The physical link contains four wires that form two differential signal pairs. One differential pair transmits signals, while the other differential pair receives signals. Both differential pairs operate simultaneously and allow concurrent data transmission in both the receive and the transmit directions.

The following figure shows two phys that are attached with a physical link.

Figure 5: Transceivers within a Phy

Phys are contained within ports. A port can contain a single phy or multiple phys. A narrow port contains a single phy, and a wide port contains two or more phys. The LSISAS2008 controller supports wide ports that contain up to eight phys. Because each phy within a wide port can transmit data at 6Gb/s SAS, increasing the number of phys in a port increases the data transfer rate. When eight phys are combined into a wide port a bandwidth of up to 48.0 Gb/s is possible.

Transmitter

Transmitter

Receiver

Receiver

RX–

RX+

TX–

TX+

TransceiverTransceiver

PhyPhy


Chapter 2: Functional Description | SAS Functional Description LSISAS2008 6Gb/s SAS/SATA Controller Reference Manual

A link between two narrow ports is a narrow link. A link between two wide ports is a wide link. The following figure shows a narrow link and a wide link. The wide link in the example contains four phys in each port. Wide links can contain up to eight phys in each port.

Figure 6: Narrow and Wide Links

Each phy on the LSISAS2008 controller can function as an SSP initiator, an SSP target, an SMP initiator, an STP initiator, or a SATA initiator. A phy can function in only one role during a connection but function in different roles during different connections. The controller uses SSP to communicate with other SAS devices and uses SMP to communicate management information with other SAS devices. STP communicates with SATA devices in a SAS domain by tunneling through SAS expanders to the SATA device. The LSISAS2008 controller can also use SATA to communicate with other SATA devices.

Phy

Phy

Phy

Phy

RX

TXPhy

Narrow Port

Phy

Narrow Port

a. Narrow Link: One Phy in Each Port

RX

TXPhy

Wide Port

b. Wide Link: Four Phys in Each Port

RX

TXPhy

RX

TXPhy

RX

TXPhy

Wide Port


LSISAS2008 6Gb/s SAS/SATA Controller Reference Manual Chapter 3: Register Map | PCI Express Configuration Space Map

Chapter 3

3.1 PCI Express Configuration Space Map

The LSISAS2008 PCI configuration registers follow the configuration space definition of the PCI Express Specification, Revision 2.0. Table 1 summarizes the PCI Express Configuration Registers for Physical Functions, and Table 2 summarizes the PCI Express Configuration Registers for Virtual Functions. See the PCI Express specification for register details.

3.1.1 IOV Virtual Function PCI Address Map

The virtual function (VF) address map has a variable base address where registers for VF1 start. Each virtual function address range is a fixed stride (range of addresses). The stride is the same size for all virtual functions associated with the same physical function (PF). The following figure shows VF address mapping.

Figure 7: Virtual Function Address Mapping

3.1.2 Single-Root I/O Virtualization Physical functions are discoverable in configuration space, as with all functions. Physical functions contain the Single-Root I/O Virtualization (SR-IOV) extended capability. Physical functions discover, configure, and manage the virtual functions associated with the physical function.

The descriptions of the SR-IOV registers start at Section 3.2.70 on page 74. For more information, refer to the Single-Root I/O Virtualization and Sharing Specification, Revision 1.0.

Register MapThis chapter describes the PCI Express host register space.

Base Address

VF1

VF2

VF3

VF16

Stride


Chapter 3: Register Map | PCI Express Configuration Space Map LSISAS2008 6Gb/s SAS/SATA Controller Reference Manual

3.1.3 PCI Express Configuration Register Maps

The following tables list the PCI Express configuration registers for physical functions and virtual functions.

Table 1: PCI Express Configuration Registers for Physical Functions

Offset 31 16 15 0

0x00 Device ID Vendor ID

0x04 Status Command

0x08 Class Code Revision ID

0x0C BIST Header Type Latency Timer Cache Line Size

0x10 I/O Base Address Register

0x14 Mem 0 BAR Lower

0x18 Mem 0 BAR Upper

0x1C Mem 1 BAR Lower

0x20 Mem 1 BAR Upper

0x24 Reserved

0x28

0x2C Subsystem ID Subsystem Vendor ID

0x30 Expansion ROM Base Address Register

0x34 Reserved Capabilities Pointer

0x38 Reserved

0x3C Reserved Interrupt Pin Interrupt Line

0x40 Reserved

0x44

0x48

0x4C

0x50 Power Management Capabilities Next Capability Pointer

Capability ID

0x54 Power Management Control/Status

0x58 Reserved

0x5C

0x60

0x64

0x68 PCIe Capability PCIe Next Capability Pointer

PCIe Capabilities ID

0x6C Device Capabilities

0x70 Device Status Device Control

0x74 Link Capabilities

0x78 Link Status Link Control



0x7C Reserved

0x80

0x84

0x88

0x8C Device Capabilities 2

0x90 Device Status 2 Device Control 2

0x94 Link Capabilities 2

0x98 Link Status 2 Link Control 2

0x9C Reserved

0xA0

0xA4

0xA8 Message Signaled Interrupt Capabilities Next Capability Pointer

Capability ID

0AC MSI Lower Address

0xB0 MSI Upper Address

0xB4 MSI Data

0xB8 MSI Mask Bits

0xBC MSI Pending Bits

0xC0 MSI-X Capabilities Next Capability Pointer

Capability ID

0xC4 MSI-X Table Off

0xC8 MSI-X PBAOff

0xCC Reserved

0xD0 Vital Product Data Capability ID Next Capability Pointer

Capability ID

0xD4 Vital Product Data

0xD8 Reserved

0xDC

0xE0

0xE4

0xE8

0xEC

0xF0

0xF4

0xF8

0xFC

0x100 Advanced Error Reporting Enhanced Capability Header

0x104 Uncorrectable Error Status

0x108 Uncorrectable Error Mask

Table 1: PCI Express Configuration Registers for Physical Functions (Continued)

Offset 31 16 15 0



0x10C Uncorrectable Error Severity

0x110 Correctable Error Status

0x114 Correctable Error Mask

0x118 Advanced Error Capability and Control

0x11C Advanced Error Header Log 0

0x120 Advanced Error Header Log 1



0x12C Reserved

0x130

0x134

0x138 Power Budgeting Enhanced Capability

0x13C Reserved PB Data Select Register

0x140 Power Budgeting Data Register

0x144 Reserved PB Capability Register

0x148 Reserved

0x14C

0x150 SR-IOV Extended Capability Header

0x154 SR-IOV Capabilities

0x158 SR-IOV Status SR-IOV Control

0x15C Total VFs Initial VF

0x160 Reserved Func Dependency Link

Num VFs

0x164 VF Stride First VF Offset

0x168 VF Device ID Reserved

0x16C Supported Page Size

0x170 System Page Size

0x174 VF BAR 0

0x178 VF BAR 1

0x17C VF BAR 2

0x180 VF BAR 3

0x184 Reserved

0x188

0x18C VF Migration State Array Offset

0x190 ARI Extended Capability Header


Offset 31 16 15 0



0x194 ARI Control ARI Capability

0x198 Reserved

0x19C

Table 2: PCI Express Configuration Registers for Virtual Functions

Offset 31 16 15 0

0x00 Device ID Vendor ID

0x04 Status Command

0x08 Reserved

0x0C Reserved

0x10 Reserved

0x14 Reserved

0x18 Reserved

0x1C Reserved

0x20 Reserved

0x24 Reserved

0x28

0x2C Subsystem ID Subsystem Vendor ID

0x30 Reserved

0x34 Reserved Capabilities Pointer

0x38 Reserved

0x3C Reserved Interrupt Pin Interrupt Line

0x40 Reserved

0x44

0x48 Reserved

0x4C Reserved

0x50 Reserved

0x54 Reserved

0x58 Reserved

0x5C

0x60

0x64

0x68 PCIe Capability PCIe Next Capability Pointer

PCIe Capabilities ID

0x6C Device Capabilities

0x70 Device Status Device Control

0x74 Link Capabilities


Offset 31 16 15 0



0x78 Link Status Link Control

0x7C Reserved

0x80

0x84

0x88

0x8C Device Capabilities 2

0x90 Device Status 2 Device Control 2

0x94 Link Capabilities 2

0x98 Link Status 2 Link Control 2

0x9C Reserved

0xA0

0xA4

0xA8 Message Signaled Interrupt Capabilities Next Capability Pointer

Capability ID

0AC MSI Lower Address

0xB0 MSI Upper Address

0xB4 MSI Data

0xB8 MSI Mask Bits

0xBC MSI Pending Bits

0xC0 MSI-X Capabilities Next Capability Pointer

Capability ID

0xC4 MSI-X Table Off

0xC8 MSI-X PBAOff

0xCC Reserved

0xD0 Reserved

0xD4

0xD8 Reserved

0xDC

0xE0

0xE4

0xE8

0xEC

0xF0

0xF4

0xF8

0xFC

0x100 Advanced Error Reporting Enhanced Capability Header

0x104 Uncorrectable Error Status

0x108 Uncorrectable Error Mask

Table 2: PCI Express Configuration Registers for Virtual Functions (Continued)

Offset 31 16 15 0



0x10C Uncorrectable Error Severity

0x110 Correctable Error Status

0x114 Correctable Error Mask

0x118 Advanced Error Capability and Control

0x11C Advanced Error Header Log 0




0x12C Reserved

0x130

0x134

0x138 Reserved

0x13C Reserved

0x140 Reserved

0x144 Reserved

0x148 Reserved

0x14C

0x150 Reserved

0x154 Reserved

0x158 Reserved

0x15C Reserved

0x160 Reserved

0x164 Reserved

0x168 Reserved

0x16C Reserved

0x170 Reserved

0x174 Reserved

0x178 Reserved

0x17C Reserved

0x180 Reserved

0x184 Reserved

0x188 Reserved

0x18C Reserved

0x190 ARI Extended Capability Header

0x194 AI Control ARI Capability

0x198 Reserved

0x19C

Table 2: PCI Express Configuration Registers for Virtual Functions (Continued)

Offset 31 16 15 0


Chapter 3: Register Map | PCI Express Configuration Space Registers LSISAS2008 6Gb/s SAS/SATA Controller Reference Manual

3.2 PCI Express Configuration Space Registers

This section defines the registers in the PCI Express Configuration Space. This space is available to legacy PCI devices and PCI Express devices through PCI and PCI Express mechanisms.

3.2.1 Vendor ID Register Offset: 0x00–0x01 (Read Only)

3.2.2 Device ID Register Offset: 0x02–0x03 (Read Only)

15 8 7 0

Vendor ID

0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0

Name Bits Description

Vendor ID 15:0 This 16-bit register identifies the manufacturer of the device. The Vendor ID is 0x1000.

15 8 7 0

Device ID

0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 0


Device ID 15:0 This register identifies the particular device. The default device ID for the LSISAS2008 controller is 0x0072.


LSISAS2008 6Gb/s SAS/SATA Controller Reference Manual Chapter 3: Register Map | PCI Express Configuration Space Registers

3.2.3 Command Register Offset: 0x04–0x05 (Read/Write)

This register provides coarse control over the ability of the PCI function to generate and respond to PCI cycles. Writing a 0 to this register logically disconnects the LSISAS2008 PCI function from the PCI bus for all accesses except configuration accesses.

15 8 7 0

Command

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Reserved 15:11 This field is reserved.

Interrupt Disable 10 Clearing this bit enables the PCI function to generate interrupt messages (INTA/). Setting this bit disables the PCI function from generating interrupt messages (INTA/).

Reserved 9 This bit is hardwired to 0.

SERR/ Enable 8 Setting this bit enables the LSISAS2008 controller to report errors. Clearing this bit disables error reporting. Note that to disable error reporting, this bit and the error control bits in the PCI Express Device Control register must be set.

Reserved 7 This bit is reserved.

Enable Parity Error Response

6 This bit controls the logging of poisoned Transaction Layer Packets (TLPs) in the Master Data Parity Error bit in the PCI Status register. The default value of this bit is 0.


Enable Bus Mastering

2 Setting this bit enables the LSISAS2008 controller to issue memory and I/O read/write requests. Clearing this bit disables the LSISAS2008 controller from issuing these requests. Note that as MSI interrupt messages are in-band memory writes, disabling the Bus Master Enable bit disables MSI interrupt messages.

Enable Memory Space

1 This bit controls the ability of the PCI Express function to respond to Memory Space accesses. Setting this bit allows the LSISAS2008 controller to respond to Memory Space accesses. Clearing this bit disables the PCI Express function from responding to PCI Express Memory Space accesses.

Enable I/O Space 0 This bit controls the ability of the LSISAS2008 PCI Express function to respond to I/O Space accesses. Setting this bit enables the PCI Express function to respond to I/O Space accesses. Clearing this bit disables the PCI Express function from responding to I/O Space accesses.



3.2.4 Status Register Offset: 0x06–0x07 (Read/Write)

Reads to this register behave normally. To clear a bit location that is currently set, write the bit to 1. For example, to clear bit 15 when it is set without affecting any other bits, write 0x8000 to the register.

15 8 7 0

Status

0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0


Detected Parity Error 15 The LSISAS2008 controller sets this bit when it receives a poisoned TLP, regardless of the state of the Parity Error Enable bit.

Signaled System Error 14 The LSISAS2008 controller sets this bit when it sends an ERR_FATAL or ERR_NONFATAL message, and the SERR Enable bit of the Command register is set.

Received Master Abort 13 This bit is set when a requester receives a Completion with Unsupported Request Completion Status.

Received Target Abort 12 This bit is set when a requester receives a Completion with Completer Abort Completion Status.

Signaled Target Abort 11 This bit is set when a device completes a Request using Completer Abort Completion Status.


Master Data Parity Error

8 This bit is set by a requester if its Parity Error Enable bit is set and either of the following two conditions occurs:• Requester receives a Completion marked poisoned• Requester poisons a write RequestIf the Parity Error Enable bit is cleared, this bit is never set.


Capabilities List 4 This bit indicates the presence of an extended capability list item. Because all PCI Express devices are required to implement the PCI Express capability structure, this bit must be set to 1.

Interrupt Status 3 This bit indicates that an INTx interrupt message is pending internally to the device.




3.2.5 Revision ID Register Offset: 0x08 (Read/Write)

3.2.6 Class Code Register Offset: 0x09–0x0B (Read Only)

3.2.7 Cache Line Size Register Offset: 0x0C (Read/Write)

The LSISAS2008 controller implements this register for legacy compatibility, according to the PCI Express Specification, Revision 2.0. The register has no impact on PCI Express functionality.

7 0

Revision ID

x x x x x x x x


Revision ID 7:0 This register indicates the current revision level of the device.

23 16 15 8 7 0

Class Code

0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0


Class Code 23:0 This 24-bit register identifies the generic function of the device. The upper byte of this register is a base class code, the middle byte is a subclass code, and the lower byte identifies a specific register-level programming interface. The value of this register is 0x010700, which identifies a SAS controller.

7 0

Cache Line Size

0 0 0 0 0 0 0 0


Cache Line Size 7:3 —




3.2.8 Latency Timer Register Offset: 0x0D (Read/Write)

The LSISAS2008 controller implements this register for legacy compatibility, according to the PCI Express Specification, Revision 2.0. The register has no impact on PCI Express functionality.

3.2.9 Header Type Register Offset: 0x0E (Read Only)

3.2.10 BIST Register Offset: 0x0F (Reserved)

7 0

Latency Timer

0 0 0 0 0 0 0 0


Latency Timer 7:4 —


7 0

Header Type

0 0 0 0 0 0 0 0


Header Type 7:0 This 8-bit register identifies the layout of bytes 0x10 through 0x3F in the configuration space and also indicates if the device is a single function or multifunction PCI device. Because the LSISAS2008 controller is a single function PCI device, bit 7 is cleared.

7 0

Reserved

0 0 0 0 0 0 0 0


Reserved 7:0 This register is reserved.



3.2.11 I/O Base Address Register Offset: 0x10–0x13 (Read/Write)

This base address register (BAR) maps the operating register set into I/O Space. The LSISAS2008 controller requires 256 bytes of I/O Space for this base address register. Hardware sets bit 0 to 1. Bit 1 is reserved and returns 0 on all reads.

3.2.12 Mem 0 BAR Lower Register Offset: 0x14–0x17 (Read/Write)

The Mem 0 BAR Lower and the Mem 0 BAR Upper map operating registers into Memory Space [0]. This register contains the lower 32 bits of the Memory Space [0] base address. The size is modified from the serial boot record, and defaults to 64 KB.

31 24 23 16 15 8 7 0

I/O Base Address

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1


I/O Base Address 31:2 This field contains the I/O Base Address.


31 24 23 16 15 8 7 0

Memory [0] Low

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0


Mem 0 BAR Lower 31:0 This field contains the Memory [0] Low address.



3.2.13 Mem 0 BAR Upper Register Offset: 0x18–0x1B (Read/Write)

The Mem 0 BAR Upper and the Mem 0 BAR Lower map operating registers into Memory Space [0]. This register contains the upper 32 bits of the Memory Space [0] base address. The size is modified from the serial boot record, and defaults to 64 KB.

3.2.14 Mem 1 BAR Lower Register Offset: 0x1C–0x1F (Read/Write)

The Mem 1 BAR Lower and the Mem 1 BAR Upper map the RAM into Memory Space [1]. This register contains the lower 32 bits of the Memory Space [1] base address. By default, this base address register is disabled. The size can be changed with the serial boot record.

31 24 23 16 15 8 7 0

Memory [0] High

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Mem 0 BAR Upper 31:0 This field contains the Memory [0] High address.

31 24 23 16 15 8 7 0

Memory [1] Low

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0


Memory [1] Low 31:0 This field contains the Memory [1] Low address.



3.2.15 Mem 1 BAR Upper Register Offset: 0x20–0x23 (Read/Write)

The Mem 1 BAR Upper and the Mem 1 BAR Lower map the RAM into Memory Space [1]. This register contains the upper 32 bits of the Memory Space [1] base address. By default, this base address register is disabled. The size can be changed with the serial boot record.

Offset: 0x24–0x2B (Reserved)

These registers are reserved.

3.2.16 Subsystem Vendor ID Register Offset: 0x2C–0x2D (Read Only)

31 24 23 16 15 8 7 0

Memory [1] High

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Memory [1] High 31:0 This field contains the Memory [1] High address.

15 8 7 0

Subsystem Vendor ID

0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0


Subsystem Vendor ID 15:0 This 16-bit register uniquely identifies the vendor that manufactures the add-in board or subsystem where the LSISAS2008 controller resides. This register provides a mechanism for an add-in card vendor to distinguish its cards from another vendor’s cards, even if the cards use the same PCI controller (and have the same Vendor ID and Device ID). The default value is 0x1000; this value can be changed with the serial boot record.



3.2.17 Subsystem ID Register Offset: 0x2E–0x2F (Read Only)

3.2.18 Expansion ROM Base Address Register

Offset: 0x30–0x33 (Read/Write)

This 4-byte register contains the base address and size information for the expansion ROM.

15 8 7 0

Subsystem ID

0 0 0 0 0 0 0 0 0 1 1 1 0 1 1 x


Subsystem ID 15:0 This 16-bit register uniquely identifies the add-in board or subsystem where this PCI device resides. This register provides a mechanism for an add-in card vendor to distinguish its cards from one another, even if the cards use the same PCI controller (and have the same Vendor ID and Device ID). The default value is 0x007z; this value can be changed with the serial boot record.

31 24 23 16 15 8 7 0

Expansion ROM Base Address

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Expansion ROM Base Address

31:11 These bits correspond to the upper 21 bits of the expansion ROM base address. The host system detects the size of the external memory by first writing 0xFFFFFFFF to this register and then reading the register back. The LSISAS2008 controller responds with 0s in all don’t care locations. The least significant 1 that remains represents the binary version of the external memory size. For example, to indicate an external memory size of 32 KB, this register returns ones in the upper 17 bits when written with 0xFFFFFFFF and read back.


Expansion ROM Enable 0 This bit controls if the device accepts accesses to its expansion ROM. Setting this bit enables address decoding. Depending on the system configuration, the device can optionally use an expansion ROM. Note that to access the expansion ROM, the user must also set bit 1 in the PCI Command register.



3.2.19 Capabilities Pointer Register Offset: 0x34 (Read Only)

Offset: 0x35–0x3B (Reserved)


3.2.20 Interrupt Line Register Offset: 0x3C (Read/Write)

7 0

Capabilities Pointer

x x x x x x x x


Capabilities Pointer 7:0 This register indicates the location of the first extended capabilities register in PCI Configuration Space. The value of this register varies according to system configuration.

7 0

Interrupt Line

0 0 0 0 0 0 0 0


Interrupt Line 7:0 This register communicates interrupt line routing information. Power-On Self-Test (POST) software writes the routing information into this register as it configures the system. This register indicates the system interrupt controller input to which the interrupt pin of this PCI function is connected. System architecture determines the values in this register.



3.2.21 Interrupt Pin Register Offset: 0x3D (Read Only)

Offset: 0x3E–0x4F (Reserved)


3.2.22 Power Management Capability ID Register

Offset: 0x50 (Read Only)

7 0

Interrupt Pin

0 0 0 0 0 0 0 1


Interrupt Pin 7:0 This read-only register indicates which legacy interrupt message the PCI function uses. This register is set to 0x01, which indicates that the PCI function uses INTA/ messages.

7 0

Power Management Capability ID

0 0 0 0 0 0 0 1


Power Management Capability ID

7:0 This register indicates the type of the current data structure. It is set to 0x01 to indicate the Power Management Capability structure.



3.2.23 Power Management Next Capability Pointer Register


3.2.24 Power Management Capabilities Register

Offset: 0x52–0x53 (Read Only)

7 0

Power Management Next Pointer

x x x x x x x x


Power Management Next Pointer

7:0 This register contains the pointer to the next item in the extended capabilities list of the PCI function. The value of this register varies according to system configuration. This register indicates 0x00 if no other items are in the linked list of capabilities.

15 8 7 0

Power Management Capabilities

0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1


PME_Support 15:11 These bits define the power management states in which the device asserts the Power Management Event (PME) pin. The LSISAS2008 controller clears these bits because the controller does not provide a PME signal.

D2_Support 10 The PCI function clears this bit because the LSISAS2008 controller does not support power management state D2.

D1_Support 9 The PCI function sets this bit because the LSISAS2008 controller supports power management state D1.

Aux_Current 8:6 The PCI function clears this field because the LSISAS2008 controller does not support Aux_Current.

Device Specific Initialization

5 The PCI function clears this bit because no special initialization is required before a generic class device driver can use it.


Version 2:0 The PCI function programs these bits to 0b011 to indicate that the LSISAS2008 controller complies with the PCI Power Management Interface Specification, Revision 1.1.



3.2.25 Power Management Control/Status Register


Offset: 0x58–0x67 (Reserved)


15 8 7 0

Power Management Control/Status

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


PME_Status 15 The PCI function clears this bit because the LSISAS2008 controller does not support PME signal generation from D3cold.

Data_Scale 14:13 This 2-bit read-only field indicates the scaling factor to be used when interpreting the value of the Data register. The value and meaning of this field varies depending on which data value has been selected by the Data_Select field.

Data_Select 12:9 This 4-bit field selects which data is to be reported through the Data register and Data_Scale field.

PME_Enable 8 The PCI function clears this bit because the LSISAS2008 controller does not provide a PME signal and disables PME assertion.


Power State 1:0 These bits determine the current power state of the LSISAS2008 controller. The bit encodings are as follows:

Encoding Power State

0b00 D0

0b01 D1

0b10 D2

0b11 D3hot



3.2.26 PCI Express Capability ID Register


3.2.27 PCI Express Next Capability Pointer Register


7 0

PCI Express Capability ID

0 0 0 1 0 0 0 0


PCI Express Capability ID

7:0 This register indicates the type of the current data structure. This register always returns 0x10, indicating the PCI Express capability structure.

7 0

PCI Express Next Capability Pointer

x x x x x x x x


PCI Express Next Capability Pointer

7:0 This register points to the next item in the extended capabilities list of the PCI Express function. The value of this register varies according to system configuration. This register indicates 0x00 if no other items are in the linked list of capabilities.



3.2.28 PCI Express Capabilities Register

Offset: 0x6A–0x6B (Read Only)

15 8 7 0

PCI Express Capabilities

0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0



Undefined 14 The value read from this bit is undefined. The system software should ignore the value read from this bit. The system software can write any value to this bit.

Interrupt Message Number

13:9 This field indicates which MSI/MSI-X vector is used for the interrupt message generated in association with any of the status bits of this capability structure. See also the PCI Express Base Specification, Rev. 2.0.


Device/Port Type 7:4 This read-only field indicates the PCI Express logical device type. This field is set to 0b000 to indicate a PCI Express endpoint device. The LSISAS2008 controller does not require I/O resources for run-time operations.

Capability Version 3:0 This read-only field indicates the PCI Express capability structure version number, as defined by PCI-SIG. This field is set to 0x2.



3.2.29 PCI Express Device Capabilities Register

Offset: 0x6C–0x6F (Read Only)

31 24 23 16 15 8 7 0

PCI Express Device Capabilities

0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 x x x 0 0 0 0 0 0 1 0 0 1 0 1


Reserved 31:29 This field is reserved.Function Level Reset Capability

28 This bit must be set to 1, indicating that the function supports the optional Function Level Reset mechanism. This LSISAS2008 device functions as an endpoint only.

Captured Slot Power Limit Scale

27:26 (Upstream Ports only) – This field specifies the scale used for the Slot Power Limit Value. The range of values is as follows:• 0b00 = 1.0x• 0b01 = 0.1x• 0b10 = 0.01x• 0b11 = 0.001xThis value is set by the Set_Slot_Power_Limit Message or hardwired to 0b00. The default value is 0b00.

Captured Slot Power Limit Value

25:18 (Upstream Ports only) – In combination with the Slot Power Limit Scale value, specifies the upper limit on power supplied by slot. Power limit (in watts) is calculated by multiplying the value in this field by the value in the Slot Power Limit Scale field. This value is set by the Set_Slot_Power_Limit Message or hardwired to 0x00. The default value is 0x00.

Reserved 17:16 This field is reserved.Role-Based Error Reporting

15 When set, this bit indicates that the function implements the functionality originally defined in the Error Reporting ECN for PCI Express Base Specification, Revision 1.0a, and later incorporated into PCI Express Base Specification, Revision 1.1. This bit must be set by all functions conforming to the PCI Express Base Specification, Revision 1.1, or to the subsequent revisions of this specification.The default value is 1.

Undefined 14:12 The value read from this field is undefined. The system software should ignore the value read from this bit. The system software can write any value to this field.

Endpoint L1 Acceptable Latency

11:9 This field indicates the acceptable latency that the device can withstand when transitioning from the L1 state to the L0 state. This field is set to 0b000 to indicate a latency of less than 1 s.

Endpoint L0s Acceptable Latency

8:6 This field indicates the acceptable total latency that the device can withstand when transitioning from the L0s state to the L0 state. This field is set to 0b000 to indicate a latency of less than 64 ns.

Extended Tag Field Supported

5 This bit is hard-coded to 1 to indicate 8-bit Tag field support.

Phantom Functions Supported

4:3 This field is hard-coded to 0b00 to indicate that no function number bits are used for Phantom functions.

Maximum Payload Size Supported

2:0 This field indicates the maximum TLP payload size that the device can support. This field is hard-coded to 0b101 to indicate support for TLPs with up to 4 KB.



3.2.30 PCI Express Device Control Register


15 8 7 0

PCI Express Device Control

0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0


Bridge Configuration Retry Enable/Initiate Function Level Reset

15 A write of 1 initiates Function Level Reset to the function. The value read by software from this bit is always 0.

Maximum Read Request Size

14:12 This field sets the maximum read request size that the device can generate. The encodings are as follows:

Enable Snoop Not Required

11 Setting this bit to 1 enables the device to set the No Snoop bit in the requester attributes of the transactions it initiates.

Auxiliary Power PM Enable

10 Setting this bit enables the device to draw auxiliary power independent of the PME AUX power. The LSISAS2008 controller hardwires this bit to 0 to indicate that it does not support PME AUX power.

Phantom Functions Enable

9 When set, this bit enables a function to use unclaimed functions as Phantom functions to extend the number of outstanding transaction identifiers. If the bit is clear, the function is not allowed to use Phantom functions. Functions that do not implement this capability hardwire this bit to 0. The default value of this bit is 0.

Extended Tag Field Enable

8 When this bit is set, the device can use an extended 8-bit Tag field as a requester. When this bit is cleared, the device can only use a 5-bit Tag field.

Maximum Payload Size

7:5 This field indicates the maximum TLP payload size. This field is set to 0b000 to indicate support for TLPs of up to 128 bytes. This value is set by system software.

Enable Relaxed Ordering

4 Setting this bit permits the device to set the Relaxed Ordering bit in the Attributes field of the transactions it initiates. This bit defaults to 1.

Unsupported Request Reporting Enable

3 Setting this bit enables the reporting of unsupported requests.

Encoding Max Read Request Size

0b000 128 bytes

0b001 256 bytes

0b010 512 bytes

0b011 1024 bytes

0b100 2048 bytes

0b101 4096 bytes

0b110 Reserved

0b111 Reserved



3.2.31 PCI Express Device Status Register


Errors are logged into this register regardless of whether error reporting is enabled in the PCI Express Device Control register and regardless of the settings in the Correctable Error Mask register.

Fatal Error Reporting Enable

2 Setting this bit enables the reporting of fatal errors. Clearing this bit disables the reporting of fatal errors.

Nonfatal Error Reporting Enable

1 Setting this bit enables the reporting of nonfatal errors. Clearing this bit disables the reporting of nonfatal errors.

Correctable Error Reporting Enable

0 Setting this bit enables the reporting of correctable errors. Clearing this bit disables the reporting of correctable errors.

Name Bits Description (Continued)

15 8 7 0

PCI Express Device Status

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0



Transactions Pending 5 This read-only bit indicates that the device has issued nonposted requests that have not been completed. The device clears this bit only when all outstanding nonposted requests have completed or timed out.

Aux Power Detected 4 This bit is set if the device detects auxiliary power.

Unsupported Request Detected

3 This bit is set when the device receives an unsupported request.

Fatal Error Detected 2 This bit is set when the device detects a fatal error.

Nonfatal Error Detected

1 This bit is set when the device detects a nonfatal error.

Correctable Error Detected

0 This bit is set when the device detects a correctable error.



3.2.32 PCI Express Link Capabilities Register


31 24 23 16 15 8 7 0

PCI Express Link Capabilities

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 1 0


Port Number 31:24 This field indicates the port number of the given PCI Express link.


Data Link Layer Link Active Reporting Capable

20 For a Downstream Port, this bit must be hardwired to 1 if the component supports the optional capability of reporting the DL_Active state of the Data Link Control and Management State Machine. For a hot-plug capable Downstream Port (as indicated by the Hot-Plug Capable bit of the Slot Capabilities register), this bit must be hardwired to 1.For Upstream Ports and components that do not support this optional capability, this bit must be hardwired to 0.

Surprise Down Error Reporting Capable

19 For a Downstream Port, this bit must be set if the component supports the optional capability of detecting and reporting a Surprise Down error condition.For Upstream Ports and components that do not support this optional capability, this bit must be hardwired to 0.

Clock Power Management

18 For Upstream Ports, a value of 1 in this bit indicates that the component tolerates the removal of any reference clocks via the clock request (CLKREQ#) mechanism when the link is in the L1 and L2/L3 Ready Link states. A value of 0 indicates the component does not have this capability and that reference clocks must not be removed in these link states.This capability is applicable only in form factors that support the clock request (CLKREQ#) capability.For a multifunction device, each function indicates its capability independently. Power Management configuration software must only permit reference clock removal if all functions of the multifunction device indicate a 1 in this bit.For downstream ports, this bit must be hardwired to 0.

L1 Exit Latency 17:15 This field indicates the L1 latency for a link. This indicates the amount of time required for the port to transition from the L1 state to the L0 state. This field is set to 0b000 to indicate an L1 exit latency of less than 1 s.

L0s Exit Latency 14:12 This field indicates the L0s latency for a link. This indicates the amount of time required for the port to transition from the L0s state to the L0 state. This field is set to 0b000 to indicate an L0s exit latency of less than 64 ns.

ASPM Support 11:10 This field is set to 0b11 to indicate support for the L0s and L1 Advanced State Power Management levels.

Maximum Link Width 9:4 This field is set to 0b001000 to indicate a maximum link width of eight lanes.



3.2.33 PCI Express Link Control Register


Maximum Supported Link Speeds

3:0 This field indicates the supported Link speeds of the associated Port. Defined encodings are as follows:• 0b0001 = 2.5-GT/s Link speed supported• 0b0010 = 5.0-GT/s and 2.5-GT/s Link speeds supportedAll other encodings are reserved.Multifunction devices must report the same value in this field for all functions.


15 8 7 0

PCI Express Link Control

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0



Hardware Autonomous Width Disable

9 When set, this bit disables hardware from changing the Link width for reasons other than attempting to correct an unreliable Link operation by reducing Link width.For a multifunction device associated with an upstream port, the bit in Function 0 is of type R/W (read/write), and only Function 0 controls the component’s Link behavior. In all other functions of that device, this bit is of type RsvdP.Components that do not implement the ability autonomously to change a Link width are permitted to hardwire this bit to 0.The default value of this bit is 0.

Enable Clock Power Management

8 Applicable only for Upstream Ports and with form factors that support a “Clock Request” (CLKREQ#) mechanism, this bit operates as follows:• 0 = Clock power management is disabled and the device

must hold the CLKREQ# signal low.• 1 = The device is permitted to use CLKREQ# signal to

power manage the Link clock according to protocol defined in the appropriate form factor specification.

For a multifunction device, power management configuration software must set this bit only if all functions of the multi-function device indicate a 1 in the Clock Power Management bit of the Link Capabilities register. The component is permitted to use the CLKREQ# signal to power manage the Link clock only if this bit is set for all functions.Downstream Ports and components that do not support Clock Power Management (as indicated by a 0 value in the Clock Power Management bit of the Link Capabilities register) must hardwire this bit to 0.The default value of this bit is 0.



Extended Sync 7 Setting this bit forces the device to transmit 4096 fast training sequence ordered sets in the L0s state. This is followed by a single skip ordered set prior to entering the L0 state and the transmission of 1024 training sequence one-ordered sets in the L1 state prior to entering the Recover state. Refer to the PCI Express Specification, Revision 2.0 for more information.

Common Clock Configuration

6 Setting this bit indicates that the link operates with a distributed common reference clock. Clearing this bit indicates that the link operates with an asynchronous reference clock.

Retrain Link 5 This bit is not applicable and is reserved for endpoints, PCI Express to PCI/PCI-X bridges, and upstream ports of switches.This bit always returns 0 when read.

Link Disable 4 This bit disables the Link by directing the Link Training and State Status Machine (LTSSM) to the Disabled state when set; this bit is reserved on endpoints, PCI Express to PCI/PCI-X bridges, and upstream ports of switches.Writes to this bit are immediately reflected in the value read from the bit, regardless of actual Link state.The default value of this bit is 0.

Read Completion Boundary

3 The LSISAS2008 controller hardwires this bit to 0 to indicate that it does not support Read Completion Boundary.

Reserved 2 This field is reserved.

ASPM Control 1:0 This field controls the ASPM level that the device supports.




3.2.34 PCI Express Link Status Register


15 8 7 0

PCI Express Link Status

0 0 0 0 0 0 x x x x x x 0 0 x x



Data Link Layer Link Active

13 This bit indicates the status of the Data Link Control and Management State Machine. It returns a 1 to indicate the DL_Active state, 0 otherwise. This bit must be implemented if the corresponding Data Link Layer Link Active Reporting capability bit is implemented. Otherwise, this bit must be hardwired to 0.

Slot Clock Configuration

12 This bit indicates that the device uses the same physical reference clock that the platform provides on the connector.

Link Training 11 This read-only bit indicates that the Physical Layer LTSSM is in the Configuration or Recovery state, or that 1 was written to the Retrain Link bit but Link training has not yet begun. Hardware clears this bit when the LTSSM exits the Configuration/Recovery state.This bit is not applicable and reserved for Endpoints, PCI Express to PCI/PCI-X bridges, and Upstream Ports of Switches, and must be hardwired to 0.


Negotiated Link Width 9:4 This field indicates the negotiated width of the given PCI Express link. The defined encodings are:

All other encodings are reserved.

Current Link Speed 3:0 This field indicates the negotiated link speed of the given PCI Express link. The defined encodings are:

All other encodings are reserved. The value in this field is undefined when the link is not up.

Encoding Link Width

0b000001 x1

0b000010 x2

0b000100 x4

0b001000 x8

Encoding Link Speed

0b0001 2.5 GT/s

0b0010 5 GT/s



Offset: 0x7C–0x8B (Reserved)


3.2.35 PCI Express Device Capabilities 2 Register

Offset: 0x8C–0x8F (Read Only)

31 24 23 16 15 8 7 0

PCI Express Device Capabilities 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0



Completion Timeout Disable Supported

4 A value of 1 means that the Completion Timeout Disable mechanism is supported.The Completion Timeout Disable mechanism is required for Endpoints that issue Requests on their own behalf and PCI Express to PCI/PCI-X Bridges that take ownership of Requests issued on PCI Express.This mechanism is optional for Root Ports. For all other functions, this field is reserved and must be hardwired to 0.

Completion Timeout Ranges Supported

3:0 This field indicates device function support for the optional Completion Timeout programmability mechanism, which allows the system software to modify the Completion Timeout value.This field is applicable only to Root Ports, Endpoints that issue Requests on their own behalf, and PCI Express to PCI/PCI-X Bridges that take ownership of Requests issued on PCI Express. For all other functions, this field is reserved and must be hardwired to 0000b.Four time value ranges are defined:• Range A: 50 μs to 10 ms• Range B: 10 ms to 250 ms• Range C: 250 ms to 4 s• Range D: 4 s to 64 sBits are set as follows to show the supported timeout value ranges.• 0b0000 = Completion Timeout programming not supported; the

function must implement a timeout value in the range 50 μs to 50 ms.

• 0b0001 = Range A• 0b0010 = Range B• 0b0011 = Ranges A and B• 0b0110 = Ranges B and C• 0b0111 = Ranges A, B, and C• 0b1110 = Ranges B, C, and D• 0b1111 = Ranges A, B, C, and DAll other values are reserved.LSI strongly recommends that the Completion Timeout mechanism not be allowed to expire in less than 10 ms. The default value for the LSISAS2008 controller is 0x6.



3.2.36 PCI Express Device Control 2 Register


15 8 7 0

PCI Express Device Control 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0



Completion Timeout Disable

4 When set, this bit disables the Completion Timeout mechanism. This bit is required for all functions that support the Completion Timeout Disable capability. Functions that do not support this optional capability are permitted to hardwire this bit to 0.The software can set or clear this bit at any time. When set, the Completion Timeout detection mechanism is disabled. If there are outstanding requests when the bit is cleared hardware is permitted, but not required, to apply the completion timeout mechanism to the outstanding requests. If this is done, the start time for each request can be based on either the time this bit was cleared or the time each request was issued. The default value for this bit is 0.



Completion Timeout Value

3:0 In device functions that support Completion Timeout programmability, this field allows system software to modify the Completion Timeout value. This field is applicable to Root Ports, Endpoints that issue Requests on their own behalf, and PCI Express to PCI/PCI-X Bridges that take ownership of Requests issued on PCI Express. For all other functions, this field is reserved and must be hardwired to 0b0000.A function that does not support this optional capability must hardwire this field to 0b0000 and is required to implement a timeout value in the range 50 μs to 50 ms. Functions that support Completion Timeout programmability must support the values listed below, corresponding to the programmability ranges listed in the Completion Timeout Ranges Supported field.The defined encodings are as follows:• 0b0000 = Default range: 50 μs to 50 msLSI strongly recommends that the Completion Timeout mechanism not be allowed to expire in less than 10 ms.The following values are available if the Range A (50 μs to 10 ms) programmability range is supported:• 0b0001 = 50 μs to 100 μs• 0b0010 = 1 ms to 10 msThe following values are available if the Range B (10 ms to 250 ms) programmability range is supported:• 0b0101 = 16 ms to 55 ms• 0b0110 = 65 ms to 210 msThe following values are available if Range C (250 ms to 4 s) programmability range is supported:• 0b1001 = 260 ms to 900 ms• 0b1010 = 1 s to 3.5 sThe following values are available if the Range D (4 s to 64 s) programmability range is supported:• 0b1101 = 4 s to 13 s• 0b1110 = 17 s to 64 sValues not previously defined are reserved.The software can change the value in this field at any time. For Requests already pending when the Completion Timeout Value is changed, the hardware can use either the new or the old value for the outstanding requests, and is permitted to base the start time for each request either on when this value was changed or on when each request was issued.The default value for this field is 0b0000.




3.2.37 PCI Express Device Status 2 Register


There are no capabilities that require this register. This register must be treated by software as Reserved.

3.2.38 PCI Express Link Capabilities 2 Register


There are no capabilities that require this register. This register must be treated by software as Reserved.

3.2.39 PCI Express Link Control 2 Register


15 8 7 0

PCI Express Device Status 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

31 24 23 16 15 8 7 0

PCI Express Link Capabilities 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15 8 7 0

PCI Express Link Control 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0



Compliance De-Emphasis

12 This bit sets the de-emphasis level in Polling.Compliance state if the entry occurred due to the Enter Compliance bit being 1. Encodings are as follows:• 1 = –3.5 dB• 0 = –6 dBWhen the Link is operating at 2.5-GT/s speed, the setting of this bit has no effect. Components that support only 2.5-GT/s speed are permitted to hardwire this bit to 0.For a multifunction device associated with an Upstream Port, the bit in Function 0 is of type RWS, and only Function 0 controls the component’s Link behavior. In all other functions of that device, this bit is of type RsvdP.This bit is intended for debug, compliance testing purposes. The system firmware and software are allowed to modify this bit only during debug or compliance testing.The default value of this bit is 0.



Compliance SOS 11 When set to 1, the LTSSM is required to send SKP ordered sets periodically in between the (modified) compliance patterns.For a multifunction device associated with an Upstream Port, the bit in Function 0 is of type RWS, and only Function 0 controls the component’s Link behavior. In all other functions of that device, this bit is Reserved.Components that support only the 2.5-GT/s speed are permitted to hardwire this field to 0.The default value of this bit is 0.

Enter Modified Compliance

10 When this bit is set to 1, the device transmits Modified Compliance Pattern if the LTSSM enters Polling.Compliance substate.Components that support only the 2.5-GT/s speed are permitted to hardwire this bit to 0.For a multifunction device associated with an Upstream Port, the bit in Function 0 is of type RWS, and only Function 0 controls the component’s Link behavior. In all other functions of that device, this bit is Reserved.This register is intended for debug, compliance testing purposes only. The system firmware and software are allowed to modify this register only during debug or compliance testing. In all other cases, the system must ensure that this register is set to the default value.The default value of this bit is 0.

Transmit Margin 9:7 This field controls the value of the non-de-emphasized voltage level at the Transmitter pins. This field is reset to 0b000 on entry to the LTSSM Polling.Configuration substate. Encodings are as follows:• 0b000 = Normal operating range• 0b001 = 800–1200 mV for full swing and 400–700 mV for

half-swing• 0b010 – (n–1) = Values must be monotonic with a non-zero

slope. The value of n must be greater than 3 and less than 7. At least two of these must be below the normal operating range of n: 200–400 mV for full-swing and 100–200 mV for half-swing

• n – 0b111 = ReservedFor a multifunction device associated with an Upstream Port, the field in Function 0 is of type RWS, and only Function 0 controls the component’s Link behavior. In all other functions of that device, this field is Reserved. Components that support only the 2.5-GT/s speed are permitted to hardwire this bit to 0b000.This register is intended for debug, compliance testing purposes only. The system firmware and software are allowed to modify this register only during debug or compliance testing. In all other cases, the system must ensure that this register is set to the default value.The default value of this field is 0b000.




Selectable De-Emphasis

6 When the Link is operating at 5.0-GT/s speed, this bit selects the level of de-emphasis for an Upstream component. Encodings are as follows:• 1 = –3.5 dB• 0 = –6 dBWhen the Link is operating at 2.5-GT/s speed, the setting of this bit has no effect. Components that support only the 2.5-GT/s speed are permitted to hardwire this bit to 0.This bit is not applicable and reserved for Endpoints, PCI Express to PCI/PCI-X bridges, and Upstream Ports of Switches.

Hardware Autonomous Speed Disable

5 When set, this bit disables hardware from changing the Link speed for device specific reasons other than attempting to correct unreliable Link operation by reducing Link speed. Initial transition to the highest supported common link speed is not blocked by this bit.For a multifunction device associated with an Upstream Port, the bit in Function 0 is of type RWS, and only Function 0 controls the component’s Link behavior. In all other functions of that device, this bit is Reserved.Functions that do not implement the associated mechanism are permitted to hardwire this bit to 0.The default value of this bit is 0.

Enter Compliance 4 The software is permitted to force a Link to enter Compliance mode at the speed indicated in the Target Link Speed field by setting this bit to 1 in both components on a Link and then initiating a hot reset on the Link.For a multifunction device associated with an Upstream Port, the bit in Function 0 is of type RWS, and only Function 0 controls the component’s Link behavior. In all other functions of that device, this bit is reserved.Components that support only the 2.5-GT/s speed are permitted to hardwire this bit to 0.The default value of this bit following Fundamental Reset is 0.




3.2.40 PCI Express Link Status 2 Register


Offset: 0x9C–0xA7 (Reserved)


Target Link Speed 3:0 For Downstream Ports, this field sets an upper limit on Link operational speed by restricting the values advertised by the Upstream component in its training sequences.Defined encodings are:• 0b0001 = 2.5 GT/s Target Link Speed• 0b0010 = 5.0 GT/s Target Link SpeedAll other encodings are reserved.If a value written to this field does not correspond to a speed included in the Supported Link Speeds field, the result is undefined.The default value of this field is the highest Link speed supported by the component (as reported in the Supported Link Speeds field of the Link Capabilities register) unless the corresponding platform/form factor requires a different default value.For both Upstream and Downstream Ports, this field sets the target compliance mode speed when the software is using the Enter Compliance bit to force a Link into compliance mode.For a multifunction device associated with an Upstream Port, the field in Function 0 is of type RWS, and only Function 0 controls the component’s Link behavior. In all other functions of that device, this field is Reserved.Components that support only the 2.5-GT/s speed are permitted to hardwire this field to 0b0000.


15 8 7 0

PCI Express Link Status 2

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x



Current De-emphasis Level

0 When the Link is operating at 5-GT/s speed, this bit reflects the level of de-emphasis. The possible encodings are:• 1 = –3.5 dB• 0 = –6 dBThe value in this bit is undefined when the Link is operating at 2.5-GT/s speed. Components that support only the 2.5-GT/s speed are permitted to hardwire this field to 0.



3.2.41 MSI Capability ID Register Offset: 0xA8 (Read Only)

3.2.42 MSI Next Pointer Register Offset: 0xA9 (Read Only)

7 0

MSI Capability ID

0 0 0 0 0 1 0 1


MSI Capability ID 7:0 This register indicates the current data structure type. This register always returns 0x05, indicating Message Signaled Interrupts (MSIs).

7 0

MSI Next Pointer

x x x x x x x x


MSI Next Pointer 7:0 This register points to the next item in the PCI function’s extended capabilities list. The value of this register varies according to system configuration. This register indicates 0x00 if no other items are in the linked list of capabilities.



3.2.43 MSI Message Control Register Offset: 0xAA–0xAB (Read/Write)

15 8 7 0

MSI Message Control

0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0



Per-Vector Masking Capable

8 This bit is set, indicating that the LSISAS2008 controller supports MSI per-vector masking. The default number is set by firmware. This bit is read-only.

64-Bit Address Capable

7 The PCI function sets this read-only bit to indicate support of a 64-bit message address.

Multiple Message Enable

6:4 These read/write bits indicate the number of messages that the host allocates to the LSISAS2008 controller. The host system software allocates all or a subset of the requested messages by writing to this field. The number of allocated request messages must align to a power of 2. Table 3 lists the bit encoding of this field. This field’s state after reset is 0b000.

Table 3: Multiple Message Enable Field Bit Encoding

Bits 6:4 Encoding Number of Allocated Messages

0b000 1

0b001 2

0b010 4

0b011 8

0b100 16

0b101 32

0b110 Reserved

0b111 Reserved


Multiple Message Capable

3:1 These read-only bits indicate the number of messages that the LSISAS2008 controller requests from the host. The host system software reads this field to determine the number of requested messages. The number of requested messages must align to a power of 2. The default setting for the controller is 0b000.

MSI Enable 0 The system software sets this bit to enable MSI. Setting this bit enables the device to use MSI to interrupt the host and request service. Setting this bit to mask INTA/ interrupt messages violates the PCI Express Specification, Revision 2.0.



3.2.44 MSI Lower Address Register Offset: 0xAC–0xAF (Read/Write)

3.2.45 MSI Upper Address Register Offset: 0xB0–0xB3 (Read/Write)

3.2.46 MSI Message Data Register Offset: 0xB4–0xB7 (Read/Write)

31 24 23 16 15 8 7 0

MSI Lower Address

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


MSI Lower Address 31:2 This register contains message address bits 31:2 for the MSI memory write transaction. The host system specifies the message address and aligns it to a DWord boundary. During the address phase, the LSISAS2008 controller drives Message Address 1:0 to 0b00.


31 24 23 16 15 8 7 0

MSI Upper Address

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


MSI Upper Address 31:0 The LSISAS2008 controller supports 64-bit MSI messages. This register contains the upper 32 bits of the 64-bit message address, which the system specifies. The host system software can program this register to 0x0000 to force the PCI function to generate 32-bit message addresses.

31 24 23 16 15 8 7 0

MSI Message Data

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


MSI Message Data 31:0 The system software initializes this register by writing to it. The LSISAS2008 controller sends an interrupt message by writing a DWord to the address held in the MSI Lower Address and MSI Upper Address registers. This register forms bits 15:0 of the DWord message that the PCI function passes to the host. The PCI function drives bits 31:16 of this message to 0x0000.



3.2.47 MSI Mask Bits Register Offset: 0xB8–0xBB (Read/Write)

3.2.48 MSI Pending Bits Register Offset: 0xBC–0xBF (Read Only)

3.2.49 MSI-X Capability ID Register Offset: 0xC0 (Read Only)

31 24 23 16 15 8 7 0

MSI Mask Bits

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


MSI Mask Bits 31:0 For each mask bit that is set, the device is prohibited from sending an associated message. Refer to the PCI Local Bus Specification, Revision 3.0, for a complete description of this register.

31 24 23 16 15 8 7 0

MSI Pending Bits

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


MSI Pending Bits 31:0 For each pending bit that is set, the function has a pending associated message. Refer to the PCI Local Bus Specification, Revision 3.0, for a complete description of this register.

7 0

MSI-X Capability ID

0 0 0 1 0 0 0 1


MSI-X Capability ID 7:0 This register indicates the type of the current data structure. This register always returns 0x11, indicating MSI-X capability.



3.2.50 MSI-X Next Capability Pointer Register

Offset: 0xC1 (Read Only)

3.2.51 MSI-X Message Control Register

Offset: 0xC2–0xC3 (Read/Write)

7 0

MSI-X Next Capability Pointer

x x x x x x x x


MSI-X Next Capability Pointer

7:0 This register points to the next item in the extended capabilities list. The value of this register varies according to system configuration. This register indicates 0x00 if no other items are in the linked list of capabilities.

15 8 7 0

MSI-X Message Control

0 0 0 0 0 x x x x x x x x x x x


MSI-X Enable 15 Setting this bit enables the device to use MSI-X to request service from the host. To enable MSI-X, the MSI Enable bit in the MSI Message Control register must be cleared to 0. Setting this bit to mask INTA/ interrupt messages violates the PCI Express Specification, Revision 2.0.

Function Mask 14 Setting this bit masks all of the reset vectors that are associated with the function. This bit overrides the Per-vector Mask bit settings. Clearing this bit enables the Per-vector Mask bit to determine if a vector is masked.


Table Size 10:0 The host software reads this field to determine the MSI-X table size n, which is encoded as n–1. For example, a value of 0b00000000011 indicates a table size of 4.



3.2.52 MSI-X Table Offset Register Offset: 0xC4–0xC7 (Read Only)

31 24 23 16 15 8 7 0

MSI-X Table Offset

x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x


MSI-X Table Offset 31:3 This field provides an offset from the address held in the base address registers of the device to the base of the MSI-X table.

Table BAR Indicator Register (BIR)

2:0 This field indicates which of the base address registers of the device, which are located at 0x10 in PCI Configuration Space, maps the MSI-X table into memory. Table 4 provides the BIR field definitions.

Table 4: BIR Field Definitions

BIR Value Base Address Register

0 0x10

1 0x14

2 0x18

3 0x1C

4 0x20

5 0x24

6 Reserved

7 Reserved



3.2.53 MSI-X PBA Offset Register Offset: 0xC8–0xCB (Read Only)

Offset: 0xCC–0xCF (Reserved)

This register is reserved.

3.2.54 Vital Product Data Capability ID Register

Offset: 0xD0 (Read Only)

3.2.55 Vita Product Data Next Capability Pointer Register

Offset: 0xD1 (Read Only)

31 24 23 16 15 8 7 0

MSI-X PBA Offset



MSI-X PBA Offset 31:3 This field contains an offset from one of the base address registers of the device that points to the MSI-X Peripheral Bus Access (PBA). The lower 3 bits of this register are cleared to 0 for a 32-bit aligned offset.

PBA BIR 2:0 This field indicates which of the base address registers of the device, which are located at 0x10 in PCI Configuration Space, maps the MSI-X PBA into memory.

7 0

Vital Product Data Capability ID

0 0 0 0 0 0 1 1


Capability ID 7:0 This register indicates the type of the current data structure. This register always returns 0x11, indicating Vital Product Data.

7 0

Vital Product Data Next Capability Pointer

x x x x x x x x


Next Capability Pointer 7:0 This register points to the next item in the extended capabilities list. The value of this register varies according to system configuration. This register indicates 0x00 if no other items are in the linked list of capabilities.



3.2.56 Vital Product Data Control Register

Offset: 0xD2–0xD3 (Read/Write)

3.2.57 Vital Product Data Register Offset: 0xD4–0xD7 (Read Only)

Offset: 0xD8–0xFF (Reserved)


15 8 7 0

Vital Product Data Control

x x x x x x x x x x x x x x x x


Flag 15 This bit indicates when the transfer of data between the Vital Product Data register and the storage component is completed. In addition, refer to the PCI Local Bus Specification, Rev. 3.0.

Vital Product Address

14:0 These bits represent the DWord-aligned byte address of the VPD to be accessed.

31 24 23 16 15 8 7 0

Vital Product Data



Vital Product Data 7:0 VPD data can be read through this register. The least significant byte of this register (at 0xD4) corresponds to the byte of VPD at the address specified by the Vital Product Data Control register. The data read from or written to this register uses the normal PCI byte transfer capabilities. Four bytes are always transferred between this register and the VPD storage component. Reading or writing data outside of the VPD space in the storage component is not allowed. The VPD (both the read-only items and the read/write fields) is stored information that has no direct control of any device operations. The initial value of this register at power up is indeterminate.The VP Data Control field is a byte address but must specify a DWord-aligned location (that is, the bottom two bits must be 0). See also the PCI Local Bus Specification, Rev. 3.0.



3.2.58 PCI Express Advanced Error Reporting Enhanced Capability Header Register


This register provides the PCI Express enhanced capability header for the Advanced Error Reporting capability.

31 24 23 16 15 8 7 0

PCI Express Advanced Error Reporting Enhanced Capability Header

x x x x x x x x x x x x 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1


Next Capability Offset 31:20 This register contains a pointer to the next PCI Express extended capability structure. The offset is relative to the beginning of PCI compatible configuration space. The value of this register varies according to system configuration. This register indicates 0x00 if no other items are in the linked list of capabilities.

Capability Version 19:16 This field indicates the PCI Express capability structure version number as defined by PCI-SIG. This field is set to 0x1.

PCI Express Extended Capability ID

15:0 This field indicates the PCI Express capability structure version number as defined by PCI-SIG. This field is set to 0x0001 to indicate the Advanced Error Reporting capability.



3.2.59 PCI Express Uncorrectable Error Status Register


This register reports the status of uncorrectable errors. A set bit indicates that an uncorrectable error of the given status has been detected. The fields in this register are all read-only, write-1-to-clear. The software can clear the bit by writing 1 to it.

31 24 23 16 15 8 7 0

PCI Express Uncorrectable Error Status

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x



ACS Violation Status 21 —

Unsupported Request Error Status

20 —

ECRC Error Status 19 —

Malformed TLP Status 18 —

Receiver Overflow Status

17 —

Unexpected Completion Status

16 —

Completer Abort Status

15 —

Completion Timeout Status

14 —

Flow Control Protocol Error Status

13 —

Poisoned TLP Status 12 —


Surprise Down Error Status

5 —

Data Link Protocol Error Status

4 —





3.2.60 PCI Express Uncorrectable Error Mask Register

Offset: 0x108–0x10B (Read/Write)

This register masks errors of a given type. A set bit masks errors of the corresponding error type. A masked error is not logged in the PCI Express Header Log register, does not update the first error pointer, and is not reported to the PCI Express root complex.

31 24 23 16 15 8 7 0

PCI Express Uncorrectable Error Mask

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x



ACS Violation Mask 21 —

Unsupported Request Error Mask

20 —

ECRC Error Mask 19 —

Malformed TLP Mask 18 —

Receiver Overflow Mask

17 —

Unexpected Completion Mask

16 —

Completer Abort Mask 15 —

Completion Timeout Mask

14 —

Flow Control Protocol Error Mask

13 —

Poisoned TLP Mask 12 —


Surprise Down Error Mask

5 —

Data Link Protocol Error Mask

4 —





3.2.61 PCI Express Uncorrectable Error Severity Register

Offset: 0x10C–0x10F (Read/Write)

This register maps the severity of errors by determining whether the error type is reported as fatal or nonfatal. An error is reported as fatal when the corresponding bit in this register is set. An error is reported as nonfatal when the corresponding bit in this register is cleared.

31 24 23 16 15 8 7 0

PCI Express Uncorrectable Error Severity

0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 x



ACS Violation Severity 21 —

Unsupported Request Error Severity

20 —

ECRC Error Severity 19 —

Malformed TLP Severity

18 —

Receiver Overflow Severity

17 —

Unexpected Completion Severity

16 —

Completer Abort Severity

15 —

Completion Timeout Severity

14 —

Flow Control Protocol Error Severity

13 —

Poisoned TLP Severity 12 —


Surprise Down Error Severity

5 —

Data Link Protocol Error Severity

4 —





3.2.62 PCI Express Correctable Error Status Register


This register reports the status of correctable errors. A set bit indicates that a correctable error of the given status has been detected. The fields in this register are all read-only, write-1-to-clear. The software can clear the bit by writing 1 to it.

31 24 23 16 15 8 7 0

PCI Express Correctable Error Status

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0



Advisory Nonfatal Error Status

13 —

Replay Timer Timeout Status

12 —


REPLAY_NUM Rollover Status

8 —

Bad DLLP Status 7 —

Bad TLP Status 6 —


Receiver Error Status 0 —



3.2.63 PCI Express Correctable Error Mask Register


This register masks errors of a given type. A set bit masks errors of the corresponding error type. A masked error is not reported to the PCI Express root complex.

3.2.64 PCI Express Advanced Error Capabilities and Control Register


31 24 23 16 15 8 7 0

PCI Express Correctable Error Mask

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0



Advisory Nonfatal Error Mask

13 —

Replay Timer Timeout Mask

12 —


REPLAY_NUM Rollover Mask

8 —

Bad DLLP Mask 7 —

Bad TLP Mask 6 —


Receiver Error Mask 0 —

31 24 23 16 15 8 7 0

PCI Express Advanced Error Capabilities and Control

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0



ECRC Check Enable 8 Setting this bit enables ECRC error checking.

ECRC Check Capable 7 This read-only bit is set to indicate that the device is capable of checking ECRC.

ECRC Generation Enable

6 Setting this bit enables ECRC generation.

ECRC Generation Capable

5 This read-only bit is set to indicate that the device is capable of generating ECRC.

First Error Pointer 4:0 This read-only field identifies the bit position of the first error reported in the PCI Express Uncorrectable Error Status register.



3.2.65 PCI Express Header Log Register

Offset: 0x11C–0x12B (Read Only)

This register captures the Header of the TLP associated with the first logged error. Each of these bits defaults to 0.

Offset: 0x12C–0x137


3.2.66 PCI Express Power Budgeting Enhanced Capability Header Register


31 24 23 16 15 8 7 0

Header Byte 0 Header Byte 1 Header Byte 2 Header Byte 3





Header Log 127:0 —

31 24 23 16 15 8 7 0

PCI Express Power Budgeting Enhanced Capability Header

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0


Next Capability Offset 31:20 This field contains the offset to the next PCI Express capability structure or 000h if no other items exist in the linked list of Capabilities.For Extended Capabilities implemented in Configuration Space, this offset is relative to the beginning of the PCI-compatible Configuration Space. Thus, the offset must always be either 000h (for terminating list of Capabilities) or greater than 0FFh.

Capability Version 19:16 This field is version number defined by the PCI-SIG that indicates the version of the capability structure.The value must be 1h for this version of the specification.


15:0 This field is an ID number defined by the PCI-SIG that indicates the nature and format of the extended capability.The Extended Capability ID for the Power Budgeting capability is 0004h.



3.2.67 PCI Express Power Budgeting Data Select Register

Offset: 0x13C (Read/Write)

This read-write register indexes the Power Budgeting Data reported through the Data register and selects the DWord of the Power Budgeting Data that should appear in the Data register. Index values for this register start at 0 to select the first DWord of Power Budgeting Data; subsequent DWords of Power Budgeting Data are selected by increasing index values.

Offset: 0x13D–0x13F (Reserved)


3.2.68 PCI Express Power Budgeting Data Register


7 0

PCI Express Power Budgeting Data Select

x x x x x x x x

31 24 23 16 15 8 7 0

PCI Express Power Budgeting Data

0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x x x x x x x x x x x x x x



Power Rail 20:18 Specifies the power rail of the operating condition being described. Defined encodings are:• 0b000 = Power (12 V)• 0b001 = Power (3.3 V)• 0b010 = Power (1.8 V)• 0b111 = ThermalAll other encodings are reserved.

Type 17:15 Specifies the type of operating condition being described. Defined encodings are:• 0b000 = PME Aux• 0b001 = Auxiliary• 0b010 = Idle• 0b011 = Sustained• 0b111 = MaximumAll other encodings are reserved.



PM State 14:13 Specifies the Power Management state of the operating condition being described. Defined encodings are:• 0b00 = D0• 0b01 = D1• 0b10 = D2• 0b11 = D3A device returns 0b11 in this field and Aux or PME Aux in the Type register to specify the D3Cold PM State. An encoding of 0b11 along with any other Type register value specifies the D3Hot state.

PM Substate 12:10 Specifies the Power Management substate of the operating condition being described. Defined encodings are:• 0b000 = Default Substate• 0b001 to 0b111 = Device-Specific Substate

Data Scale 9:8 Specifies the scale to apply to the Base Power value. The power consumption of the device is determined by multiplying the contents of the Base Power field with the value corresponding to the encoding returned by this field, except as previously noted. Defined encodings are:• 0b00 = 1.0x• 0b01 = 0.1x• 0b10 = 0.01x• 0b11 = 0.001x

Base Power 7:0 Specifies in Watts the base power value in the given operating condition. This value must be multiplied by the data scale to produce the actual power consumption value, except when the Data Scale field equals 0b00 (1.0x) and Base Power exceeds EFh. The following alternative encodings are used:• F0h = 250 W Slot Power Limit• F1h = 275 W Slot Power Limit• F2h = 300 W Slot Power Limit• F3h to FFh = Reserved




3.2.69 PCI Express Power Budgeting Capability Register

Offset: 0x144 (Read/Write)

Offset: 0x145–0x14F (Reserved)


3.2.70 SR-IOV Extended Capability Header Register


7 0

PCI Express Power Budgeting Capability

x x x x x x x x



System Allocated 0 When set, this bit indicates that the power budget for the device is included within the system power budget. Reported Power Budgeting Data for this device must be ignored by the software for power budgeting decisions if this bit is set.

31 24 23 16 15 8 7 0

SR-IOV Extended Capability Header

0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0


Next Capability Offset 31:20 This field contains the offset to the next PCI Express capability structure or 000h if no other items exist in the linked list of Capabilities. For Extended Capabilities implemented in Configuration Space, this offset is relative to the beginning of PCI-compatible Configuration Space and thus must always be either 000h (for terminating list of Capabilities) or greater than 0FFh. The default value is 12’h190.

Capability Version 19:16 This field is a version number defined by the PCI-SIG that indicates the version of the capability structure present. Must be 1h for this version of the specification.


15:0 This field is an ID number defined by the PCI-SIG that indicates the nature and format of the extended capability. The Extended Capability ID for the SR-IOV Extended Capability is 0010h.



3.2.71 SR-IOV Capabilities Register Offset: 0x0154 (Read Only)

3.2.72 SR-IOV Status/Control Register Offset: 0x0158

31 24 23 16 15 8 7 0

SR-IOV Capabilities

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


VF Migration Interrupt Message Number

31:21 Indicates the MSI/MSI-X vector used for migration interrupts. The value in this field is undefined if bit 0 of this register is clear.


VF Migration Capable 0 If set, the PF is migration capable and is operating under a migration capable MR-PCIM.

31 24 23 16 15 8 7 0

SR-IOV Status/Control

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0



VF Migration Status 16 Indicates a VF Migration In or Migration Out Request has been issued by MR-PCIM. To determine the cause of the event, the software may scan the VF State Array. Default value is 0.


VF ARI Enable 4 PCI Express Endpoint: The device is permitted to locate VFs in function numbers 8 to 255 of the captured bus number. Default value is 0. This field is R/W in the lowest-numbered PF of the device and is read-only 0 in all other PFs. Root Complex Integrated Endpoint: Not applicable: the bit must be hardwired to 0.

VF Memory Space Enable 3 This bit enables Memory Space Enable for virtual functions.

VF Migration Interrupt Enable

2 This bit enables and disables VF Migration State Change Interrupt.

VF Migration Enable 1 This read-only bit enables or disables VF Migration support.

VF Enable 0 This bit enables and disables VFs.



3.2.73 SR-IOV Total/Initial VFs Register

Offset: 0x015C (Read Only)

31 24 23 16 15 8 7 0

SR-IOV Total/Initial VFs



Total Initial VFs 31:16 This field indicates the maximum number of VFs that could be associated with the PF. The minimum value of TotalVFs is 0. For devices operating in single-root mode, this field is HwInit and must contain the same value as InitialVFs. For devices operating in multi-root mode, the value of this field may be changed by MR-PCIM.

Initial VFs 15:0 This field indicates to SR-PCIM the number of VFs that are initially associated with the PF. The minimum value of InitialVFs is 0. For devices operating in single-root mode, this field is HwInit and must contain the same value as TotalVFs. For devices operating in multi-root mode, the value of this field may be changed by MR-PCIM when VF Enable is clear.



3.2.74 SR-IOV Func Dependency Links/ Num VFs Register

Offset: 0x0160

31 24 23 16 15 8 7 0

SR-IOV Func Dependency Links/Num VFs

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0



Function Dependency Link

23:16 This read-only field describes dependencies between PFs. VF dependencies are the same as the dependencies of their associated PFs. If a PF is independent from other PFs of a device, this field contains its own function number. If a PF is dependent on other PFs of a device, this field contains the function number of the next PF in the same function dependency list. The last PF in a function dependency list contains the function number of the first PF in the function dependency list. If PF p and PF q are in the same function dependency list, any SI that is assigned VF p,n is also assigned to VF q,n.

NumVFs 15:0 This field controls the number of VFs that are available. SR-PCIM sets NumVFs as part of the process of creating VFs. This number of VFs is visible in the PCI Express fabric after NumVFs is set to a valid value and VF Enable is set. These VFs respond to PCI Express transactions targeting them, and follow all rules defined by this specification and the base specification. The results are undefined if NumVFs is set to a value greater than TotalVFs. NumVFs may only be written while VF Enable is clear. If NumVFs is written when VF Enable is set, the results are undefined. The initial value of NumVFs is undefined.



3.2.75 SR-IOVx VF Stride/First VF Offset Register


3.2.76 SR-IOV VF Device ID Register Offset: 0x0168 (Read Only)

31 24 23 16 15 8 7 0

SR-IOV VF Stride/First VF Offset

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1


VF Stride 31:16 This field defines the Routing ID offset from one VF to the next one for all VFs associated with the PF that contains this capability structure. The next VF’s 16-bit Routing ID is calculated by adding the contents of this field to the Routing ID of the current VF, ignoring any carry, using unsigned 16-bit arithmetic. This field may change value when the ARI Capable Hierarchy or NumVFs values change. Note: VF Stride is unused if NumVFs is 0 or 1. If NumVFs is greater than 1, VF Stride must not be 0.

First VF Offset 15:0 This field is a constant that defines the Routing ID offset of the first VF that is associated with the PF that contains this capability structure. The first VF’s 16-bit Routing ID is calculated by adding the contents of this field to the Routing ID of the PF containing this field, ignoring any carry, using unsigned, 16-bit arithmetic. Do not locate a VF on a Bus Number that is numerically smaller than its associated PF. This field may change value when the ARI Capable Hierarchy or NumVFs values change.

31 24 23 16 15 8 7 0

SR-IOV VF Device ID

x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1


VF Device ID 31:16 Default value is provided by the input port sc_DeviceId.




3.2.77 SR-IOV Supported Page Sizes Register


3.2.78 SR-IOV System Page Size Register


31 24 23 16 15 8 7 0

SR-IOV Supported Page Sizes

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 1 1


Supported Page Sizes 31:0 This field indicates the page sizes that the PF supports. This PF supports a page size of 2n+12 if bit n is set. For example, if bit 0 is set, the PF supports 4-KB page sizes. PFs must to support 4-KB, 8-KB, 64-KB, 256-KB, 1-MB, and 4-MB page sizes. All other page sizes are optional. The page size describes the minimum alignment requirements for VF BAR resources. The default value is 32’h0553.

31 24 23 16 15 8 7 0

SR-IOV System Page Size

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


System Page Size 31:0 This field defines the page size that the system will use to map the memory addresses of the VFs. The software must set the value of the System Page Size to one of the page sizes set in the Supported Page Sizes field. As with Supported Page Sizes, if bit n is set in System Page Size, the VFs associated with this PF are required to support a page size of 2n+12. For example, if bit 1 is set, the system is using an 8-KB page size. The results are undefined if more than one bit is set in System Page Size. The results are undefined if a bit is set in System Page Size that is not set in Supported Page Sizes. When System Page Size is set, the VF associated with this PF must align all BAR resources on a System Page Size boundary. Each VF BARn or VF BARn pair must be aligned on a System Page Size boundary. Each VF BARn or VF BARn pair defining a non-zero address space must be sized to consume an integer multiple of System Page Size bytes. All data structures requiring page size alignment within a VF must be aligned on a System Page Size boundary. The default is 32’h00.VF Enable must be 0 when System Page Size is written. The results are undefined if System Page Size is written when VF Enable is set.



3.2.79 SR-IOV VF Mem0 Lower BAR Register


3.2.80 SR-IOV VF Mem0 Upper BAR Register


3.2.81 SR-IOV VF Mem1 Lower BAR Register

Offset: 0x017C (Read/Write)

31 24 23 16 15 8 7 0

SR-IOV VF Mem0 Lower BAR

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


VF Mem0 Lower BAR 31:0 The number of writable bits is determined by the FMU PIM0 Size register and by the System Page Size. The default is 32’h00.

31 24 23 16 15 8 7 0

SR-IOV VF Mem0 Upper BAR

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


VF Mem0 Upper BAR 31:0 The default for this register is 32’h00.

31 24 23 16 15 8 7 0

SR-IOV VF Mem1 Lower BAR

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


VF Mem1 Lower BAR 31:0 The number of writable bits is determined by the FMU PIM1 Size register and by the System Page Size. The default value is 32’h00.



3.2.82 SR-IOV VF Mem1 Upper BAR Register


Offset: 0x0184–0x0188 (Reserved)


3.2.83 SR-IOV VF Migration State Array Offset Register


31 24 23 16 15 8 7 0

SR-IOV VF Mem1 Upper BAR

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


VF Mem1 Upper BAR 31:0 The default for this register is 32’h00.

31 24 23 16 15 8 7 0

SR-IOV VF Migration State Array Offset

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


VF Migration State Array Offset

31:3 This field is used as an offset from the address in one of the Base Address registers of the function to point to the base of the VF Migration State Array. The lower three MVF Migration State BIR bits are masked off (set to 0) by software to form a 32-bit QWORD-aligned offset. This field is undefined if TotalVFs is 0.

VF Migration State BIR

2:0 This field indicates which Base Address register of a function, located beginning at 10h in Configuration Space, is used to map the function’s VF Migration State Array into Memory Space.

For a 64-bit BAR, the VF Migration State BIR indicates the lower DWord. This field is undefined if TotalVFs is 0.

BIR Value BAR

0 BAR0 10h

1 BAR1 14h

2 BAR2 18h

3 BAR3 1Ch

4 BAR4 20h

5 BAR5 24h

6 Reserved —

7 Reserved —



3.2.84 ARI Extended Capability Header Register


3.2.85 ARI Control/Capability Register Offset: 0x0194 (Read Only)

Offset: 0x0198–0x019C (Reserved)


31 24 23 16 15 8 7 0

ARI Extended Capability Header

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0


Next Capability 31:20 —

Capability Version 19:16 —

Capability ID 15:0 —

31 24 23 16 15 8 7 0

ARI Control/Capability

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0



Function Group 22:20 —


ACS Function Groups Enable 17 —

MFVC Function Groups Enable 16 —

Next Function Number 15:8 —


ACS Function Groups Capability 1 —

MFVC Function Groups Capability

0 —


LSISAS2008 6Gb/s SAS/SATA Controller Reference Manual Chapter 3: Register Map | System Interface Register Description

3.3 System Interface Register Description

The Fusion-MPT Message Passing Interface definition includes a register-level transport mechanism and a messaging protocol. A system doorbell register and a set of message queues define the MPI transport interface. Request messages, built in host memory, describe operations to be performed by the IOC. These request messages are queued on the Request Queue by the host driver and removed by the IOC. When the IOC completes an operation, it builds a reply message and places it on the Reply Queue, where the host driver will process it. The system doorbell register allows for IOC configuration, reset management, and reporting of IOC state information.

The host communicates with the LSISAS2008 IOC through the System Interface registers. Memory, I/O mapping, or both provide access to these registers. The first memory Base Address register in PCI Configuration Space and the first I/O Base Address register in PCI Configuration Space identify the location of the System Interface register set. The I/O mapping may only be available on the primary function. The host must not read or write any of the reserved words. If the host chooses to poll on any of the registers, it is recommended that a delay be inserted between register reads to avoid monopolizing PCI. This section describes the host interface registers in the PCI Memory Space. Table 5 shows the address map of the System Interface register set.


Chapter 3: Register Map | System Interface Register Description LSISAS2008 6Gb/s SAS/SATA Controller Reference Manual

A bit-level description of the System Interface registers follows.

Table 5: System Interface Register Map

31 16 15 0 Offset

Doorbell 0x00

WriteSequence 0x04

HostDiagnostic 0x08

Reserved 0x0C

DiagRWData 0x10

DiagRWAddressLow 0x14

DiagRWAddressHigh 0x18

Reserved 0x1C

Reserved 0x20

Reserved 0x24

Reserved 0x28

Reserved 0x2C

HostInterruptStatus 0x30

HostInterruptMask 0x34

DCRData 0x38

DCRAddress 0x3C

Reserved 0x40

Reserved 0x44

ReplyFreeHostIndex 0x48

Reserved......

0x4C

0x68

ReplyPostHostIndex 0x6C

Reserved 0x70

HCBSize 0x74

HCBAddressLow 0x78

HCBAddressHigh 0x7C

Reserved......

0x80

0xBC

RequestDescriptorPostLow 0xC0

RequestDescriptorPostHigh 0xC4

Reserved......

0xC8

0xFC



3.3.1 Doorbell Register Offset: 0x00 (Read/Write)

The Doorbell register is a simple message passing mechanism that allows the system to pass single 32-bit word messages to the IOC and vice versa. When the system writes a value to the doorbell, the IOC is notified so that it can read the value. When the IOC writes a value to the doorbell, it generates a maskable interrupt to the system, and the system can read the value.

3.3.2 WriteSequence Register Offset: 0x04 (Read/Write)

The write-only WriteSequence register protects against inadvertent writes to the HostDiagnostic register. A sequence of six data-specific writes must be written into the WriteSequence KeyValue field to enable writes to the Host Diagnostic register. Any incorrectly written data value causes the WriteSequence register to restart by looking for the first sequence value. The host should first write a value of 0x0 to flush out any previous sequence.

31 24 23 16 15 8 7 0

Doorbell

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0


Doorbell 31:0 During a write, this register contains the doorbell value that the host system passes to the IOP. During a read, this register contains the doorbell value that the IOP passes to the host system.

31 24 23 16 15 8 7 0

WriteSequence

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1



Key Value 3:0 The required write data sequence is: 0xF, 0x4, 0xB, 0x2, 0x7, 0xD. After the last value (0xD) is written, the HostDiagnostic register accepts writes until another write of any value occurs to the WriteSequence register. A bit is provided in the HostDiagnostic register, DiagWriteEnable, which indicates if write access is enabled for the HostDiagnostic register. For example, to verify that the WriteSequence data sequence was correct or to verify that writes to the HostDiagnostic register have been disabled. Each function has its own WriteSequence register and logic.



3.3.3 HostDiagnostic Register Offset: 0x08 (Read/Write)

The HostDiagnostic register contains low-level diagnostic control and status information. This register is protected from inadvertent writes by the WriteSequence register. When writing to this register, a read/modify/write process must be used to preserve the contents of reserved fields.

31 24 23 16 15 8 7 0

HostDiagnostic

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 x 0



BootDeviceSelect 12:11 This R/W field indicates which boot media is currently targeted by the IOC. This field is not affected by the setting of ResetAdapter.• 0 = Default Address Map (FLASH)• 1 = Host Code and Data Window (HCDW)• 2 = Reserved• 3 = Reserved

ClearFlashBadSignature 10 Writing a 1 to this bit clears the Flash Bad Signature setting within the LSISAS2008 controller. This bit is self clearing.

ForceHCBonReset 9 The host writes a 1 to this R/W bit to force Host-Controlled Boot mode the next time the ResetAdapter bit is written to one. This bit is cleared by all other non-ICE related resets.

HCB_Mode 8 This read-only bit is set whenever the hardware transitions to Host-Controlled Boot mode after a reset, and can only be set or reset by hardware. When set to 1, this bit indicates that the IOC is held in reset pending host intervention and the host may use Host-Controlled Boot to boot the IOC.

DiagWriteEnable 7 The LSISAS2008 controller sets this read-only bit when the host writes the correct Write I/O Key to the WriteSequence register. • 0 = The IOC ignores writes to the HostDiagnostic register.• 1 = The host has write access to the HostDiagnostic

register.The LSISAS2008 controller clears this bit when the host writes a value other than the Write I/O Key to the WriteSequence register.

FlashBadSignature 6 This read-only bit is set when the IOC is in Boot From Flash mode and the hardware detects a bad signature in the firmware header or footer. In this case, the hardware automatically fails over to Host-Controlled Boot mode, and the HCB_Mode bit is set to 1. During the Host Boot Algorithm, the host clears FlashBadSignature by writing a 1 to the ClearFlashBadSignature bit.



Offset: 0x0C


3.3.4 DiagRWData Register Offset: 0x10 (Read/Write)

The DiagRWData register allows the host to read from or write to a 32-bit word location on the IOC internal bus. Such access is not part of normal MPI operations. To use this functionality, the host must first set the DiagRWEnable bit in the HostDiagnostic register. The location accessed is specified using the DiagRWAddressLow and DiagRWAddressHigh registers.

ResetHistory 5 When set to 1, this bit indicates that a physical reset occurred within the IOC. The host may write this bit to 0 to help coordinate error and reset recovery between multiple driver instances in a multifunction implementation. Writing this bit to 0 also clears the ResetIRQStatus bit in the HostInterruptStatus register.

DiagRWEnable 4 The host sets this R/W bit to 1 to enable reads and writes to the DiagRWData, DiagRWAddressLow, and DiagRWAddressHigh registers. The host clears this bit to 0 to disable access to these three registers; however, reads and writes to those registers will complete successfully but have no affect on the IOC.


ResetAdapter 2 The host writes a 1 to this R/W bit to cause a reset of the adapter. This bit should only be set after activity with the IO Unit is quiesced. After setting this bit, the host must not access the system interface registers for 20 milliseconds, and then the host must poll on this register waiting for the bit to be cleared before accessing any other system interface registers.

HoldIOCReset 1 Setting this R/W bit to 1 causes the IOC processor to be held in a reset state. Writing a 0 to this field when it was previously 1 causes the IOC to begin processing instructions from the memory area specified by the HCB_Mode bit and the BootDeviceSelect bits. Upon chip reset, this bit is automatically set to 1 if the IOC is in Host-Controlled Boot mode. This bit is also automatically set to 1 if the if the IOC is in Boot From Flash mode and FlashSigError is asserted.• 0 = The internal processor is running.• 1 = The internal processor is held in a reset state.



31 24 23 16 15 8 7 0

DiagRWData

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0



3.3.5 DiagRWAddressLow Register Offset: 0x14 (Read/Write)

The DiagRWAddressLow register indexes to a 32-bit word location on the IOC internal bus. This register contains the lower 32 bits of the 64-bit address and is incremented by 4 bytes after every access of the DiagRWData register.

3.3.6 DiagRWAddressHigh Register Offset: 0x18 (Read/Write)

The DiagRWAddressHigh register indexes to a 32-bit word location on the IOC internal bus. This register contains the upper 32 bits of the 64-bit address on the IOC internal bus.

Offset: 0x1C–0x2C


31 24 23 16 15 8 7 0

DiagRWAddressLow

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

31 24 23 16 15 8 7 0

DiagRWAddressHigh

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0



3.3.7 HostInterruptStatus Register Offset: 0x30 (Read/Write)

The HostInterruptStatus register reports interrupt status information to the host. After reading the value from this register, the host must mask off the reserved bits.

31 24 23 16 15 8 7 0

HostInterruptStatus

0 x x x x x x x x x x x x x x x x x x x x x x x x x x x 0 x x 0


Sys2IOCDBStatus 31 This bit is set to 1 when the Doorbell register is written by the host. It is only cleared by the IOC or by an AdapterReset.

ResetIRQStatus 30 When set to 1, this bit indicates that a physical reset occurred within the IOC. If this bit is set to 1 and the corresponding mask bit in the HostInterruptMask register is cleared to 0, an interrupt is generated on the host. The host uses this interrupt to help coordinate reset recovery between multiple driver instances in a multifunction implementation. This bit is cleared by writing a 0 to the ResetHistory bit in the HostDiagnostic register.


ReplyDescriptorInterrupt

3 This bit is set to 1 when a reply descriptor is available on the Reply Descriptor Post Queue. If this bit is set to 1 and the corresponding mask bit in the HostInterruptMask register is cleared to 0, an interrupt is generated on the host. This bit clears when the host empties the Reply Descriptor Post Queue and writes the updated index value to the ReplyPostHostIndex register.


IOC2SysDBStatus 0 This bit is set to 1 whenever the IOC writes a value to the doorbell, and is cleared by a write of any value to this register. If this bit is set to 1 and the corresponding mask bit in the HostInterruptMask register is cleared to 0, an interrupt is generated on the host.



3.3.8 HostInterruptMask Register Offset: 0x34 (Read/Write)

The bits in the HostInterruptMask register mask system interrupts. By default, all interrupts are masked. If a bit in this register is set to 1, an interrupt is not generated on the host regardless of the value in the corresponding bit of the HostInterruptStatus register. If a bit is cleared to 0, a host interrupt occurs when the corresponding bit in the HostInterruptStatus register is set to 1. When writing to this register, a read/modify/write process must be used to preserve the contents of reserved fields.

3.3.9 DCRData Register Offset: 0x38 (Read/Write)

The DCRData register allows the host to read from or write to a 32-bit word location on the IOC internal DCR bus. Such access is not part of normal MPI operations. The location accessed is specified using the DCRAddress register.

31 24 23 16 15 8 7 0

HostInterruptMask

x 1 x x x x x x x x x x x x x x x x x x x x x x x x x x 1 x x 1



ResetIRQMask 30 When set to 1, this bit masks the ResetIRQStatus interrupt.


ReplyIntMask 3 When set to 1, this bit masks the ReplyDescriptorInterrupt interrupt.


IOC2SysDBMask 0 When set to 1, this bit masks the IOC2SysDBStatus interrupt.

31 24 23 16 15 8 7 0

DCRData




3.3.10 DCRAddress Register Offset: 0x3C (Read/Write)

The value in the DCRAddress register specifies the location on the IOC DCR bus that is read from or written to when the host accesses the DCRData register.

Offset: 0x40–0x44


3.3.11 ReplyFreeHostIndex Register Offset: 0x48 (Read/Write)

The host writes the ReplyFreeHostIndex register to indicate to the IOC the location of the last free reply message frame on the Reply Free Queue. The value written is actually the index of the next empty position on the queue.

Offset: 0x4C–0x68


3.3.12 ReplyPostHostIndex Register Offset: 0x6C (Read/Write)

The host writes the ReplyPostHostIndex register after servicing a reply descriptor from the Reply Descriptor Post Queue to notify the IOC of the last location serviced. The value written is the index of the next position in the queue.

Offset: 0x70


31 24 23 16 15 8 7 0

DCRAddress


31 24 23 16 15 8 7 0

ReplyFreeHostIndex


31 24 23 16 15 8 7 0

ReplyPostHostIndex




3.3.13 HCBSize Register Offset: 0x74 (Read/Write)

The host uses the HCBSize register to specify the size of the PCI window used for Host Code/Data Window accesses by the IOC. This register is also used as part of the Host Boot process.

3.3.14 HCBAddressLow Register Offset: 0x78 (Read/Write)

The host writes the HCBAddressLow register to specify the lower 32 bits of the 64-bit address used for the Host Code/Data Window by the IOC. This value must be aligned to a 4-KB page boundary and must only be written while the HCBEnable bit in the HCBSize register is 0. This value is retained across AdapterResets. This register is also used as part of the Host Boot process.

31 24 23 16 15 8 7 0

HCBSize



Size 31:12 This field specifies the size of the HCDW, and must be a power of 2 from 64 KB to 64 MB. To determine the value to program in this field, use the following process:1. Represent the desired size with a 32-bit number. Only one bit is

set because the size is a power of 2.2. Set all of the bits to the left of the set bit.3. Store bits 31:12 of the resulting value in this field.4. The value in this field is retained across AdapterResets.


HCBEnable 0 This bit enables the HCDW and must not be set to 1 until the HCBAddressLow and HCBAddressHigh registers are set.

31 24 23 16 15 8 7 0

HCBAddressLow




3.3.15 HCBAddressHigh Register Offset: 0x7C (Read/Write)

The host writes the HCBAddressHigh register to specify the upper 32 bits of the 64-bit address used for the Host Code/Data Window by the IOC. This value must be written only while the HCBEnable bit in the HCBSize register is 0. This value is retained across AdapterResets. This register is also used as part of the Host Boot process.

Offset: 0x80–0xBC


3.3.16 RequestDescriptorPostLow Register

Offset: 0xC0 (Read/Write)

The host writes the lower 32 bits of a 64-bit Request Descriptor to the RequestDescriptorPostLow register. When possible, this write should be combined with the write to the RequestDescriptorPostHigh register so that it is done as one 64-bit write.

3.3.17 RequestDescriptorPostHigh Register

Offset: 0xC4 (Read/Write)

The host writes the upper 32 bits of a 64-bit Request Descriptor to the RequestDescriptorPostHigh register. When possible, combine this write with the write to the RequestDescriptorPostLow register so that it is done as one 64-bit write.

Offset: 0xC8–0xFC


31 24 23 16 15 8 7 0

HCBAddressHigh


31 24 23 16 15 8 7 0

RequestDescriptorPostLow

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

31 24 23 16 15 8 7 0

RequestDescriptorPostHigh

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1




LSISAS2008 6Gb/s SAS/SATA Controller Reference Manual Chapter 4: Signal Description | Signal Organization

Chapter 4

4.1 Signal Organization The following subsections list the signal descriptions for the LSISAS2008 controller. A slash (/) at the end of the signal name indicates an active-low signal, a – at the end of the signal name indicates the negative half of a differential signal, and a + at the end of the signal name indicates the positive half of a differential signal.

4.1.1 PCI Express Signals This section describes the PCI Express signals. Refer to the PCI Express specification for detailed signal descriptions.

Signal DescriptionThis chapter describes the signals and pinout configuration of the LSISAS2008 controller.

Table 6: PCI Express Signals

Signal Name Type Description

PCE_REF_CLK+ Input This 100-MHz signal provides the PCI Express reference clock positive input.

PCE_REF_CLK– Input This 100-MHz signal provides the PCI Express reference clock negative input.

PCE_RX[7:0]– Input These signals provide the negative serial receiver for PCI Express channels 0 through 7.

PCE_RX[7:0]+ Input These signals provide the positive serial receiver for PCI Express channels 0 through 7.

PCE_TX[7:0]– Output These signals provide the negative serial transmitter for PCI Express channels 0 through 7.

PCE_TX[7:0]+ Output These signals provide the positive serial transmitter for PCI Express channels 0 through 7.


Chapter 4: Signal Description | Signal Organization LSISAS2008 6Gb/s SAS/SATA Controller Reference Manual

4.1.2 6Gb/s SAS Signals This section describes the 6Gb/s SAS interface signals.

4.1.3 External Memory Interface Signals

This section describes the external memory interface signals.

Table 7: 6Gb/s SAS Signals


SAS_CLK_FRQ Input This signal should always be 0, which selects 150 MHz as the SAS clock reference frequency.

SAS_REF_CLK– Input This signal provides the SAS reference clock negative input.

SAS_REF_CLK+ Input This signal provides the SAS reference clock positive input.

SAS_RX[7:0]– Input These signals provide the negative differential receiver inputs for the SAS ports.

SAS_RX[7:0]+ Input These signals provide the positive differential receiver inputs for the SAS ports.

SAS_TX[7:0]– Output These signals provide the negative differential transmitter outputs for the SAS ports.

SAS_TX[7:0]+ Output These signals provide the positive differential transmitter outputs for the SAS ports.

SAS_SS_CLK– Input This signal provides the SAS spread spectrum clock negative input.

SAS_SS_CLK+ Input This signal provides the SAS spread spectrum clock positive input.

Table 8: External Memory Interface Signals


XM_AD[31:00] Input/Output These signals provide multiplexed address and data for the external memory bus.

XM_AP[3:0] Input/Output These signals provide the external memory parity.

XM_BE[3:0]/ Output These signals provide the byte enables.

XM_OE[1:0]/ Output These signals provide the output enables.

XM_WE[1:0]/ Output These signals provide the write enables.

XM_FLASH_CS/ Output This signal provides the flash ROM chip select.

XM_NVSRAM_CS/ Output This signal provides the NVSRAM chip select.

XM_PBSRAM_CS/ Output This signal provides the PBSRAM chip select.

XM_CLK Output This signal provides the clock line for the PBSRAM.

XM_ADV/ Output This signal provides the burst address advance for the PBSRAM.

XM_ADSC/ Output This signal provides the address status controller for the PBSRAM.



4.1.4 UART Signals This section describes the UART signals. The LSISAS2008 controller has one UART.

4.1.5 I2C Signals This section describes the I2C signals. The LSISAS2008 controller has two I2C interfaces.

4.1.6 GPIO Signals This section describes the GPIO signals.

The LED information (nLedActive, nLedError, and nLedStatus) from the SAS core can be sent to the GPIO pins. Firmware can program the device such that the GPIO pins become LED pins. GPIO to LED alignment is as follows:

LedActive [7:0] can be viewed on GPIO[23:16].

LedError [7:0] can be viewed on GPIO[15:8].

LedStatus [7:0] can be viewed on GPIO[7:0].

Table 9: UART Signals


UART_SERCLK Input This signal provides the UART serial clock input.

UART_RX Input This signal provides the data in signal for UART 0.

UART_TX Output This signal provides the data out signal for UART 0.

Table 10: I2C Signals


IIC0_SCL Input/Output This signal provides the clock signal for the I2C 0 interface.

IIC0_SDA Input/Output This signal provides the data signal for the I2C 0 interface.

IIC1_SCL Input/Output This signal provides the clock signal for the I2C 1 interface.

IIC1_SDA Input/Output This signal provides the data signal for the I2C 1 interface.

SBL_SCL Input This signal provides the bootstrap load serial clock for the two-wire serial bus.

SBL_SDA Input This signal provides bootstrap load serial data for the two-wire serial bus.

Table 11: GPIO Signals


GPIO[35:0] Input/Output These signals provide general-purpose I/O signals.



4.1.7 Serial GPIO Signals This section describes the serial GPIO signals. There are two serial GPIO interfaces, SIO0 and SIO1.

4.1.8 ICE Signals This section describes the ICE signals.

Table 12: Serial GPIO Signals


SIO0_CLK Input This is the serial clock signal for serial GPIO interface 0.

SIO0_DIN Input This is the serial data input bit stream for serial GPIO interface 0.

SIO0_DOUT Output This is the serial data output bit stream for serial GPIO interface 0.

SIO0_LOAD Input This is the serial I/O input control signal, indicating the LSISAS2008 controller can start driving on SIO0_DOUT and start receiving on SIO0_DIN.

SIO1_CLK Input This is the serial clock signal for serial GPIO interface 1.

SIO1_DIN Input This is the serial data input bit stream for serial GPIO interface 1.

SIO1_DOUT Output This is the serial data output bit stream for serial GPIO interface 1.

SIO1_LOAD Input This is the serial I/O input control signal, indicating the LSISAS2008 controller can start driving on SIO1_DOUT, and start receiving on SIO1_DIN.

SIO_BLINK Output This signal provides an SIO blink synchronization clock to another device, such as an expander or an enclosure processor. This signal makes it possible to synchronize the phase and frequency of the LED blinking within the system.

Table 13: ICE Signals


ICE_TCK Input This signal provides the ICE test clock.

ICE_TDI Input This signal provides the ICE test data in signal.

ICE_TDO Output This signal provides the ICE test data out signal.

ICE_TMS Input This signal provides the ICE test mode select signal.

ICE_TRST/ Input This signal provides the active-low ICE test reset signal.



4.1.9 Internal Test Signals This section describes the internal test signals.

4.1.10 System Signals This section describes the system signals.

Table 14: Internal Test Signals


TCK Input This signal provides the LSI internal test clock.

TDI Input This signal provides the LSI internal test data in signal.

TDO Output This signal provides the LSI internal test data out signal.

TMS Input This signal provides the LSI internal test mode select signal.

TN/ Input This signal is reserved for internal LSI test purposes only.

TRST/ Input This signal provides the active-low LSI internal test reset signal.

PROCMON Output This signal is reserved for internal LSI test purposes only.

SCAN_ENABLE Input This signal is reserved for internal LSI test purposes only.

IDDT Input This signal is reserved for internal LSI test purposes only.

Table 15: System Signals


SYS_ERROR Output This signal provides the system error status signal.

SYS_HALT/ Input This signal provides the active-low system halt signal. This signal is generated from an external debugger.

SYS_DBMODE[3:0] Input These control inputs enable and select top-level test multiplexer outputs or provide an MDIO interface for debug access to the GigaBlaze SerDes.

SYS_SDATA[3:0] Input These signals provide power-on sense options.

SYS_CLK_SEL Input This signal is used to select between SYS_REF_CLK and the SAS_REF_CLK differential pair as the reference clock for SYS_PLL.

SYS_REF_CLK Input This 133-MHz signal provides the system reference clock.

SYS_PWR_ON_RST/ Input This signal provides the active-low system power-on reset signal.

SYS_RST_N0 Input This signal provides the system reset.

SYS_HB_LED Input This is the system heartbeat LED. Connect it to an LED and pull it up through a 220-W resistor to a 3.3-V resistor for current limiting.

SYS_THERM_DN Input This signal provides the thermal diode emitter.

SYS_THERM_DP Input This signal provides the thermal diode base.

SYS_RTRIM Output This signal is for the calibration resistor. Both the PCI Express core and SAS core reference this resistor.

SYS_RTRIM_N Input This signal is for the calibration resistor. Both the PCI Express core and SAS core reference this resistor.



4.1.11 Power and Ground Signals This section describes the power and ground signals.

Table 16: Power and Ground Signals


VDD Power These signals provide the 1.0-V core supply.

PPC_VDD Power These signals provide the 1.0-V PowerPC 440 supply.

VDDIO10_1, VDDIO10_2

Power These signals provide the 1.0-V analog supply for the reference clock PECL buffers.

VDDIO33 Power These signals provide the 3.3-V supply for the LVTTL I/O buffers.

PCE_AVDD Power These signals provide the 1.0-V PCI Express GigaBlaze analog supply.

PCE_GB_PLL_VDD[1:0] Power These signals provide the 1.8-V PCI Express GigaBlaze TX VCO.

PCE_TXVTERM[3:0] Power These signals provide the 1.8-V supply for the PCI Express transmitter termination.

SAS_AVDD Power These signals provide the 1.0-V SAS GigaBlaze analog supply.

SAS_GB_PLL_VDD[1:0] Power These signals provide the 1.8-V SAS GigaBlaze TX VCO.

SAS_SS_PLL_VDD Power This signal provides the 1.0-V SAS spread spectrum analog supply.

SAS_TXVTERM[3:0] Power These signals provide the 1.0-V supply for the SAS transmitter termination.

SYS_PLL_VDD Power This signal provides the 1.0-V system analog supply.

PROC_SUPP_CELL Power This signal provides the 1.8-V process monitor supply.

VSS, SYS_PLL_VSS, SAS_SS_PLL_VSS

Ground These signals provide ground.


LSISAS2008 6Gb/s SAS/SATA Controller Reference Manual Chapter 4: Signal Description | Pinout and Package Information

4.2 Pinout and Package Information

This section provides pinout information and a package drawing for the LSISAS2008 controller.

4.2.1 Package Drawing The LSISAS2008 controller is packaged in a 490-ball FPBGA package with a 25-mm x 25-mm footprint and 1.0-mm ball pitch. The package code is aa2hh. The package drawing number is JZ01-002072-00.

The following figure shows the LSISAS2008 FPBGA 490-ball mechanical drawing.

Figure 8: 490-Ball FPBGA (aa2hh) Mechanical Drawing (Bottom View)

3_00158-00

Important: This drawing may not be the latest version. For board layout and manufacturing, obtain the most recent engineering drawings from your LSI marketing representative by requesting the outline drawing for package code aa2hh.


Chapter 4: Signal Description | Pinout and Package Information LSISAS2008 6Gb/s SAS/SATA Controller Reference Manual

4.2.2 Pinout The following figure shows the signal locations for the 490 FPBGA package.

Figure 9: LSISAS2008 490-BGA (Top View)

Table 17 lists the LSISAS2008 pinout by BGA position. Table 18 lists the pinout alphabetically by signal name.



THIS PAGE LEFT BLANK INTENTIONALLY



Table 17: Pinout by BGA Position

Pin Signal

A2 SYS_REF_CLK

A3 SIO1_CLK

A4 SAS_CLK_FRQ

A5 SYS_PWR_ON_RST/

A6 SIO_BLINK

A7 SYS_THERM_DP

A8 SYS_THERM_DN

A9 PROC_SUPP_CELL

A10 XM_AD[00]

A11 XM_AD[03]

A12 XM_AD[01]

A13 XM_AD[12]

A14 XM_AD[16]

A15 XM_AD[18]

A16 XM_AD[21]

A17 XM_AD[28]

A18 XM_AD[30]

A19 XM_AP[2]

A20 XM_BE[2]/

A21 XM_FLASH_CS/

A22 XM_WE[1]/

A23 SBL_SDA

B1 SYS_DBMODE[2]

B2 SYS_HB_LED

B3 SYS_ERROR

B4 SIO0_DIN

B5 SIO1_DIN

B6 SIO0_LOAD

B7 SIO1_LOAD

B8 SIO0_CLK

B9 SIO0_DOUT

B10 XM_AD[04]

B11 XM_AD[06]

B12 XM_AD[07]

B13 XM_AD[13]

B14 XM_AD[15]

B15 XM_AD[22]

B16 XM_AD[25]

B17 XM_AD[27]

B18 XM_AP[0]

B19 XM_AP[3]

B20 XM_BE[1]/

B21 XM_OE[0]/

B22 IIC0_SDA

B23 TMS

B24 PROCMON

C1 SYS_CLK_SEL

C2 UART_TX

C3 VDDIO33

C4 VSS

C5 SYS_RST_N0

C6 VSS

C7 VSS

C8 SYS_PLL_VSS

C9 VDDIO33

C10 VDDIO33

C11 XM_AD[10]

C12 VSS

C13 VSS

C14 XM_AD[19]

C15 VDDIO33

C16 VDDIO33

C17 XM_AD[31]

C18 VSS

C19 VSS

C20 XM_CLK

C21 VDDIO33

C22 VDDIO33

C23 TCK

C24 VSS

D1 NC

D2 UART_SERCLK

D3 VDDIO33

D4 VSS

Table 17: Pinout by BGA Position (Continued)

Pin Signal

D5 SYS_DBMODE[1]

D6 VDDIO33

D7 VDDIO33

D8 SYS_PLL_VDD

D9 VSS

D10 VSS

D11 XM_AD[09]

D12 VDDIO33

D13 VDDIO33

D14 XM_AD[24]

D15 VSS

D16 VSS

D17 XM_ADV/

D18 VDDIO33

D19 VDDIO33

D20 XM_OE[1]/

D21 VSS

D22 VSS

D23 TDO

D24 VDDIO33

E1 SYS_SDATA[2]

E2 SYS_SDATA[1]

E3 VSS

E4 VDDIO33

E5 VSS

E6 SYS_DBMODE[0]

E7 VSS

E8 XM_AD[02]

E9 XM_AD[08]

E10 XM_AD[14]

E11 XM_AD[20]

E12 XM_AD[29]

E13 XM_AP[1]

E14 XM_BE[3]/

E15 XM_PBSRAM_CS/

E16 IIC1_SDA

E17 TDI


Pin Signal

E18 VSS

E19 VSS

E20 XM_WE[0]/

E21 IIC1_SCL

E22 SBL_SCL

E23 SCAN_ENABLE

E24 TRST/

F1 GPIO[33]

F2 GPIO[34]

F3 VSS

F4 VDDIO33

F5 SYS_SDATA[3]

F6 SYS_SDATA[0]

F7 SIO1_DOUT

F8 XM_AD[05]

F9 XM_AD[11]

F10 XM_AD[17]

F11 XM_AD[23]

F12 XM_AD[26]

F13 XM_ADSC/

F14 XM_BE[0]/

F15 XM_NVSRAM_CS/

F16 IIC0_SCL

F17 IDDT

F18 TN/

F19 VSS

F20 VSS

F21 VSS

F22 VSS

F23 VSS

F24 VSS

G1 GPIO[31]

G2 GPIO[30]

G3 GPIO[28]

G4 GPIO[27]

G5 GPIO[32]

G6 SYS_DBMODE[3]


Pin Signal



G19 VSS

G20 VSS

G21 VSS

G22 VSS

G23 VSS

G24 VSS

H1 GPIO[25]

H2 GPIO[24]

H3 VDDIO33

H4 VSS

H5 GPIO[26]

H6 UART_RX

H19 PCE_TXVTERM[3]

H20 PCE_AVDD

H21 PCE_AVDD

H22 VSS

H23 PCE_AVDD

H24 PCE_AVDD

J1 GPIO[21]

J2 GPIO[22]

J3 VDDIO33

J4 VSS

J5 GPIO[20]

J6 GPIO[35]

J14 VSS

J15 VDD

J19 PCE_AVDD

J20 PCE_TX[7]–

J21 PCE_TX[7]+

J22 VSS

J23 PCE_RX[7]–

J24 PCE_RX[7]+

K1 GPIO[19]

K2 GPIO[18]

K3 GPIO[16]

K4 GPIO[15]

K5 GPIO[29]


Pin Signal

K6 GPIO[14]

K10 VDD

K11 VSS

K12 VDD

K13 VSS

K14 VDD

K15 VSS

K19 PCE_GB_PLL_VDD[1]

K20 PCE_TX[6]–

K21 PCE_TX[6]+

K22 PCE_AVDD

K23 PCE_RX[6]–

K24 PCE_RX[6]+

L1 GPIO[13]

L2 GPIO[12]

L3 VSS

L4 VDDIO33

L5 GPIO[23]

L6 GPIO[08]

L10 VSS

L11 VDD

L12 VSS

L13 VDD

L14 VSS

L15 VDDIO10_1

L19 PCE_TXVTERM[2]

L20 PCE_TX[5]–

L21 PCE_TX[5]+

L22 PCE_AVDD

L23 PCE_RX[5]–

L24 PCE_RX[5]+

M1 GPIO[09]

M2 GPIO[07]

M3 VSS

M4 VDDIO33

M5 GPIO[17]

M6 GPIO[02]


Pin Signal

M9 VSS

M10 VDD

M11 VSS

M12 VDD

M13 VSS

M14 VDD

M15 VSS

M16 VDD

M19 PCE_TXVTERM[1]

M20 PCE_TX[4]–

M21 PCE_TX[4]+

M22 VSS

M23 PCE_RX[4]–

M24 PCE_RX[4]+

N1 GPIO[10]

N2 GPIO[03]

N3 GPIO[01]

N4 ICE_TMS

N5 GPIO[11]

N6 ICE_TDI

N9 VDD

N10 VSS

N11 VDD

N12 VSS

N13 VDD

N14 VSS

N15 VDD

N16 VSS

N19 PCE_AVDD

N20 PCE_TX[3]–

N21 PCE_TX[3]+

N22 VSS

N23 PCE_RX[3]–

N24 PCE_RX[3]+

P1 GPIO[06]

P2 GPIO[00]

P3 VDDIO33


Pin Signal

P4 VSS

P5 ICE_TCK

P6 GPIO[05]

P9 VSS

P10 PPC_VDD

P11 VSS

P12 VDD

P13 VSS

P14 VDD

P15 VSS

P16 VDD

P19 PCE_GB_PLL_VDD[0]

P20 PCE_TX[2]–

P21 PCE_TX[2]+

P22 PCE_AVDD

P23 PCE_RX[2]–

P24 PCE_RX[2]+

R1 GPIO[04]

R2 ICE_TDO

R3 VDDIO33

R4 VSS

R5 SYS_HALT/

R6 ICE_TRST/

R7 PPC_VDD

R8 VSS

R9 PPC_VDD

R10 VSS

R11 PPC_VDD

R12 VSS

R13 VDD

R14 VSS

R15 VDD

R16 VSS

R19 PCE_TXVTERM[0]

R20 PCE_TX[1]–

R21 PCE_TX[1]+

R22 PCE_AVDD


Pin Signal



R23 PCE_RX[1]–

R24 PCE_RX[1]+

T1 VSS

T2 VSS

T3 VSS

T4 VSS

T5 VSS

T6 PPC_VDD

T7 VSS

T8 PPC_VDD

T9 VSS

T10 PPC_VDD

T15 VSS

T16 VDD

T19 PCE_AVDD

T20 PCE_TX[0]–

T21 PCE_TX[0]+

T22 VSS

T23 PCE_RX[0]–

T24 PCE_RX[0]+

U1 PPC_VDD

U2 VSS

U3 PPC_VDD

U4 VSS

U5 PPC_VDD

U6 VSS

U7 PPC_VDD

U8 VSS

U9 PPC_VDD

U10 VSS

U19 VSS

U20 PCE_AVDD

U21 PCE_AVDD

U22 VSS

U23 PCE_AVDD

U24 PCE_AVDD

V1 VSS


Pin Signal

V2 PPC_VDD

V3 VSS

V4 PPC_VDD

V5 VSS

V6 PPC_VDD

V7 VSS

V8 PPC_VDD

V9 VSS

V10 VDDIO10_2

V19 VSS

V20 VSS

V21 VSS

V22 VSS

V23 VSS

V24 VSS

W1 PPC_VDD

W2 VSS

W3 PPC_VDD

W4 VSS

W5 PPC_VDD

W6 VSS

W7 PPC_VDD

W8 VSS

W9 VSS

W10 VSS

W11 SAS_TXVTERM[3]

W12 VSS

W13 SAS_GB_PLL_VDD[1]

W14 SAS_TXVTERM[2]

W15 SAS_TXVTERM[1]

W16 VSS

W17 SAS_GB_PLL_VDD[0]

W18 SAS_TXVTERM[0]

W19 VSS

W20 VSS

W21 VSS

W22 VSS


Pin Signal

W23 PCE_REF_CLK+

W24 PCE_REF_CLK–

Y1 VSS

Y2 PPC_VDD

Y3 VSS

Y4 PPC_VDD

Y5 VSS

Y6 PPC_VDD

Y7 VSS

Y8 SAS_SS_PLL_VSS

Y9 VSS

Y10 SAS_AVDD

Y11 SAS_RX[7]+

Y12 SAS_RX[6]+

Y13 SAS_RX[5]+

Y14 SAS_RX[4]+

Y15 SAS_RX[3]+

Y16 SAS_RX[2]+

Y17 SAS_RX[1]+

Y18 SAS_RX[0]+

Y19 SAS_AVDD

Y20 VSS

Y21 VSS

Y22 VSS

Y23 VSS

Y24 VSS

AA1 PPC_VDD

AA2 VSS

AA3 PPC_VDD

AA4 VSS

AA5 PPC_VDD

AA6 VSS

AA7 VSS

AA8 SAS_SS_PLL_VDD

AA9 VSS

AA10 SAS_AVDD

AA11 SAS_RX[7]–


Pin Signal

AA12 SAS_RX[6]–

AA13 SAS_RX[5]–

AA14 SAS_RX[4]–

AA15 SAS_RX[3]–

AA16 SAS_RX[2]–

AA17 SAS_RX[1]–

AA18 SAS_RX[0]–

AA19 SAS_AVDD

AA20 VSS

AA21 VSS

AA22 VSS

AA23 SYS_RTRIM_N

AA24 SYS_RTRIM

AB1 VSS

AB2 PPC_VDD

AB3 VSS

AB4 PPC_VDD

AB5 VSS

AB6 VSS

AB7 VSS

AB8 VSS

AB9 VSS

AB10 VSS

AB11 VSS

AB12 SAS_AVDD

AB13 SAS_AVDD

AB14 VSS

AB15 VSS

AB16 SAS_AVDD

AB17 SAS_AVDD

AB18 VSS

AB19 VSS

AB20 VSS

AB21 VSS

AB22 VSS

AB23 VSS

AB24 VSS


Pin Signal



AC1 PPC_VDD

AC2 VSS

AC3 PPC_VDD

AC4 VSS

AC5 VSS

AC6 SAS_SS_CLK–

AC7 VSS

AC8 SAS_REF_CLK–

AC9 VSS

AC10 SAS_AVDD

AC11 SAS_TX[7]+

AC12 SAS_TX[6]+

AC13 SAS_TX[5]+

AC14 SAS_TX[4]+

AC15 SAS_TX[3]+

AC16 SAS_TX[2]+

AC17 SAS_TX[1]+

AC18 SAS_TX[0]+

AC19 SAS_AVDD

AC20 VSS

AC21 VSS

AC22 VSS

AC23 VSS

AC24 VSS

AD2 PPC_VDD

AD3 VSS

AD4 PPC_VDD

AD5 VSS

AD6 SAS_SS_CLK+

AD7 VSS

AD8 SAS_REF_CLK+

AD9 VSS

AD10 SAS_AVDD

AD11 SAS_TX[7]–

AD12 SAS_TX[6]–

AD13 SAS_TX[5]–

AD14 SAS_TX[4]–


Pin Signal

AD15 SAS_TX[3]–

AD16 SAS_TX[2]–

AD17 SAS_TX[1]–

AD18 SAS_TX[0]–

AD19 SAS_AVDD

AD20 VSS

AD21 VSS

AD22 VSS

AD23 VSS


Pin Signal

Table 18: Pinout by Signal Name

Signal Pin

GPIO[00] P2

GPIO[01] N3

GPIO[02] M6

GPIO[03] N2

GPIO[04] R1

GPIO[05] P6

GPIO[06] P1

GPIO[07] M2

GPIO[08] L6

GPIO[09] M1

GPIO[10] N1

GPIO[11] N5

GPIO[12] L2

GPIO[13] L1

GPIO[14] K6

GPIO[15] K4

GPIO[16] K3

GPIO[17] M5

GPIO[18] K2

GPIO[19] K1

GPIO[20] J5

GPIO[21] J1

GPIO[22] J2

GPIO[23] L5

GPIO[24] H2

GPIO[25] H1

GPIO[26] H5

GPIO[27] G4

GPIO[28] G3

GPIO[29] K5

GPIO[30] G2

GPIO[31] G1

GPIO[32] G5

GPIO[33] F1

GPIO[34] F2

GPIO[35] J6

ICE_TCK P5

ICE_TDI N6

ICE_TDO R2

ICE_TMS N4

ICE_TRST/ R6

IDDT F17

IIC0_SCL F16

IIC0_SDA B22

IIC1_SCL E21

IIC1_SDA E16

NC D1

PCE_AVDD H20

PCE_AVDD H21

PCE_AVDD H23

PCE_AVDD H24

PCE_AVDD J19

PCE_AVDD K22

PCE_AVDD L22

PCE_AVDD N19

PCE_AVDD P22

PCE_AVDD R22

PCE_AVDD T19

PCE_AVDD U20

PCE_AVDD U21

PCE_AVDD U23

PCE_AVDD U24

PCE_GB_PLL_VDD[0] P19

PCE_GB_PLL_VDD[1] K19

PCE_REF_CLK– W24

PCE_REF_CLK+ W23

PCE_RX[0]– T23

PCE_RX[0]+ T24

PCE_RX[1]– R23

PCE_RX[1]+ R24

PCE_RX[2]– P23

PCE_RX[2]+ P24

PCE_RX[3]– N23

PCE_RX[3]+ N24

Table 18: Pinout by Signal Name (Continued)

Signal Pin



PCE_RX[4]– M23

PCE_RX[4]+ M24

PCE_RX[5]– L23

PCE_RX[5]+ L24

PCE_RX[6]– K23

PCE_RX[6]+ K24

PCE_RX[7]– J23

PCE_RX[7]+ J24

PCE_TX[0]– T20

PCE_TX[0]+ T21

PCE_TX[1]– R20

PCE_TX[1]+ R21

PCE_TX[2]– P20

PCE_TX[2]+ P21

PCE_TX[3]– N20

PCE_TX[3]+ N21

PCE_TX[4]– M20

PCE_TX[4]+ M21

PCE_TX[5]– L20

PCE_TX[5]+ L21

PCE_TX[6]– K20

PCE_TX[6]+ K21

PCE_TX[7]– J20

PCE_TX[7]+ J21

PCE_TXVTERM[0] R19

PCE_TXVTERM[1] M19

PCE_TXVTERM[2] L19

PCE_TXVTERM[3] H19

PPC_VDD P10

PPC_VDD R7

PPC_VDD R9

PPC_VDD R11

PPC_VDD T6

PPC_VDD T8

PPC_VDD T10

PPC_VDD U1

PPC_VDD U3


Signal Pin

PPC_VDD U5

PPC_VDD U7

PPC_VDD U9

PPC_VDD V2

PPC_VDD V4

PPC_VDD V6

PPC_VDD V8

PPC_VDD W1

PPC_VDD W3

PPC_VDD W5

PPC_VDD W7

PPC_VDD Y2

PPC_VDD Y4

PPC_VDD Y6

PPC_VDD AA1

PPC_VDD AA3

PPC_VDD AA5

PPC_VDD AB2

PPC_VDD AB4

PPC_VDD AC1

PPC_VDD AC3

PPC_VDD AD2

PPC_VDD AD4

PROC_SUPP_CELL A9

PROCMON B24

SAS_AVDD Y10

SAS_AVDD Y19

SAS_AVDD AA10

SAS_AVDD AA19

SAS_AVDD AB12

SAS_AVDD AB13

SAS_AVDD AB16

SAS_AVDD AB17

SAS_AVDD AC10

SAS_AVDD AC19

SAS_AVDD AD10

SAS_AVDD AD19


Signal Pin

SAS_CLK_FRQ A4

SAS_GB_PLL_VDD[0] W17

SAS_GB_PLL_VDD[1] W13

SAS_REF_CLK– AC8

SAS_REF_CLK+ AD8

SAS_RX[0]– AA18

SAS_RX[0]+ Y18

SAS_RX[1]– AA17

SAS_RX[1]+ Y17

SAS_RX[2]– AA16

SAS_RX[2]+ Y16

SAS_RX[3]– AA15

SAS_RX[3]+ Y15

SAS_RX[4]– AA14

SAS_RX[4]+ Y14

SAS_RX[5]– AA13

SAS_RX[5]+ Y13

SAS_RX[6]– AA12

SAS_RX[6]+ Y12

SAS_RX[7]– AA11

SAS_RX[7]+ Y11

SAS_SS_CLK– AC6

SAS_SS_CLK+ AD6

SAS_SS_PLL_VDD AA8

SAS_SS_PLL_VSS Y8

SAS_TX[0]– AD18

SAS_TX[0]+ AC18

SAS_TX[1]– AD17

SAS_TX[1]+ AC17

SAS_TX[2]– AD16

SAS_TX[2]+ AC16

SAS_TX[3]– AD15

SAS_TX[3]+ AC15

SAS_TX[4]– AD14

SAS_TX[4]+ AC14

SAS_TX[5]– AD13

SAS_TX[5]+ AC13


Signal Pin

SAS_TX[6]– AD12

SAS_TX[6]+ AC12

SAS_TX[7]– AD11

SAS_TX[7]+ AC11

SAS_TXVTERM[0] W18

SAS_TXVTERM[1] W15

SAS_TXVTERM[2] W14

SAS_TXVTERM[3] W11

SBL_SCL E22

SBL_SDA A23

SCAN_ENABLE E23

SIO_BLINK A6

SIO0_CLK B8

SIO0_DIN B4

SIO0_DOUT B9

SIO0_LOAD B6

SIO1_CLK A3

SIO1_DIN B5

SIO1_DOUT F7

SIO1_LOAD B7

SYS_CLK_SEL C1

SYS_DBMODE[0] E6

SYS_DBMODE[1] D5

SYS_DBMODE[2] B1

SYS_DBMODE[3] G6

SYS_ERROR B3

SYS_HALT/ R5

SYS_HB_LED B2

SYS_PLL_VDD D8

SYS_PLL_VSS C8

SYS_PWR_ON_RST/ A5

SYS_REF_CLK A2

SYS_RST_N0 C5

SYS_RTRIM AA24

SYS_RTRIM_N AA23

SYS_SDATA[0] F6

SYS_SDATA[1] E2


Signal Pin



SYS_SDATA[2] E1

SYS_SDATA[3] F5

SYS_THERM_DN A8

SYS_THERM_DP A7

TCK C23

TDI E17

TDO D23

TMS B23

TN/ F18

TRST/ E24

UART_RX H6

UART_SERCLK D2

UART_TX C2

VDD J15

VDD K10

VDD K12

VDD K14

VDD L11

VDD L13

VDD M10

VDD M12

VDD M14

VDD M16

VDD N9

VDD N11

VDD N13

VDD N15

VDD P12

VDD P14

VDD P16

VDD R13

VDD R15

VDD T16

VDDIO10_1 L15

VDDIO10_2 V10

VDDIO33 C3

VDDIO33 C9


Signal Pin

VDDIO33 C10

VDDIO33 C15

VDDIO33 C16

VDDIO33 C21

VDDIO33 C22

VDDIO33 D3

VDDIO33 D6

VDDIO33 D7

VDDIO33 D12

VDDIO33 D13

VDDIO33 D18

VDDIO33 D19

VDDIO33 D24

VDDIO33 E4

VDDIO33 F4

VDDIO33 H3

VDDIO33 J3

VDDIO33 L4

VDDIO33 M4

VDDIO33 P3

VDDIO33 R3

VSS C4

VSS C6

VSS C7

VSS C12

VSS C13

VSS C18

VSS C19

VSS C24

VSS D4

VSS D9

VSS D10

VSS D15

VSS D16

VSS D21

VSS D22

VSS E3


Signal Pin

VSS E5

VSS E7

VSS E18

VSS E19

VSS F3

VSS F19

VSS F20

VSS F21

VSS F22

VSS F23

VSS F24

VSS G19

VSS G20

VSS G21

VSS G22

VSS G23

VSS G24

VSS H4

VSS H22

VSS J4

VSS J14

VSS J22

VSS K11

VSS K13

VSS K15

VSS L3

VSS L10

VSS L12

VSS L14

VSS M3

VSS M9

VSS M11

VSS M13

VSS M15

VSS M22

VSS N10

VSS N12


Signal Pin

VSS N14

VSS N16

VSS N22

VSS P4

VSS P9

VSS P11

VSS P13

VSS P15

VSS R4

VSS R8

VSS R10

VSS R12

VSS R14

VSS R16

VSS T1

VSS T2

VSS T3

VSS T4

VSS T5

VSS T7

VSS T9

VSS T15

VSS T22

VSS U2

VSS U4

VSS U6

VSS U8

VSS U10

VSS U19

VSS U22

VSS V1

VSS V3

VSS V5

VSS V7

VSS V9

VSS V19

VSS V20


Signal Pin



VSS V21

VSS V22

VSS V23

VSS V24

VSS W2

VSS W4

VSS W6

VSS W8

VSS W9

VSS W10

VSS W12

VSS W16

VSS W19

VSS W20

VSS W21

VSS W22

VSS Y1

VSS Y3

VSS Y5

VSS Y7

VSS Y9

VSS Y20

VSS Y21

VSS Y22

VSS Y23

VSS Y24

VSS AA2

VSS AA4

VSS AA6

VSS AA7

VSS AA9

VSS AA20

VSS AA21

VSS AA22

VSS AB1

VSS AB3

VSS AB5


Signal Pin

VSS AB6

VSS AB7

VSS AB8

VSS AB9

VSS AB10

VSS AB11

VSS AB14

VSS AB15

VSS AB18

VSS AB19

VSS AB20

VSS AB21

VSS AB22

VSS AB23

VSS AB24

VSS AC2

VSS AC4

VSS AC5

VSS AC7

VSS AC9

VSS AC20

VSS AC21

VSS AC22

VSS AC23

VSS AC24

VSS AD3

VSS AD5

VSS AD7

VSS AD9

VSS AD20

VSS AD21

VSS AD22

VSS AD23

XM_AD[00] A10

XM_AD[01] A12

XM_AD[02] E8

XM_AD[03] A11


Signal Pin

XM_AD[04] B10

XM_AD[05] F8

XM_AD[06] B11

XM_AD[07] B12

XM_AD[08] E9

XM_AD[09] D11

XM_AD[10] C11

XM_AD[11] F9

XM_AD[12] A13

XM_AD[13] B13

XM_AD[14] E10

XM_AD[15] B14

XM_AD[16] A14

XM_AD[17] F10

XM_AD[18] A15

XM_AD[19] C14

XM_AD[20] E11

XM_AD[21] A16

XM_AD[22] B15

XM_AD[23] F11

XM_AD[24] D14

XM_AD[25] B16

XM_AD[26] F12

XM_AD[27] B17

XM_AD[28] A17

XM_AD[29] E12

XM_AD[30] A18

XM_AD[31] C17

XM_ADSC/ F13

XM_ADV/ D17

XM_AP[0] B18

XM_AP[1] E13

XM_AP[2] A19

XM_AP[3] B19

XM_BE[0]/ F14

XM_BE[1]/ B20

XM_BE[2]/ A20


Signal Pin

XM_BE[3]/ E14

XM_CLK C20

XM_FLASH_CS/ A21

XM_NVSRAM_CS/ F15

XM_OE[0]/ B21

XM_OE[1]/ D20

XM_PBSRAM_CS/ E15

XM_WE[0]/ E20

XM_WE[1]/ A22


Signal Pin


LSISAS2008 6Gb/s SAS/SATA Controller Reference Manual Chapter 5: AC, DC, and Timing Specifications | DC Characteristics

Chapter 5

Refer to the PCI Express Specification, Revision 2.0 and the Serial Attached SCSI - 2 (SAS-2) specification for timing information. The LSISAS2008 timings conform to the information that these specifications provide.

5.1 DC Characteristics This section describes the LSISAS2008 DC characteristics, and the tables in this section give current and voltage specifications.

Stresses beyond those listed in the following table can damage the device. These are stress ratings only; functional operation of the device at or beyond these values is not implied.

AC, DC, and Timing SpecificationsThis chapter describes DC characteristics, AC characteristics, and external timing diagrams.

Table 19: Absolute Maximum Stress Ratings

Symbol Parameter Min Max Unit Test Conditions

TSTG Storage Temperature (Plastic)

–65 150 °C —

VDD-3.3 3.3 V DC Supply Voltage –0.3 3.63 V —



ESD Electrostatic Discharge — 2000 V MIL-STD 883C, Method 3015.7


Chapter 5: AC, DC, and Timing Specifications | DC Characteristics LSISAS2008 6Gb/s SAS/SATA Controller Reference Manual

Conditions that exceed the operating limits listed in the following table can cause the device to function incorrectly.

There is no particular timing sequence or ordering scheme required between digital and analog power supplies. Customers should follow a design practice of first powering up core voltage and then I/O voltage. On powerdown, the reverse sequence is advised (I/O first, then core). To improve efficiency, LSI recommends using a switching voltage regulator instead of linear regulators.

5.1.1 PCI Express Transceiver Signal Characteristics

For more information concerning the PCI Express transceivers, refer to the PCI Express Specification, Revision 2.0. The following tables show PCI_Express transceiver signal characteristics.

Table 20: Operating Conditions

Symbol Parameter Min Nominal Max UnitTest

Conditions

VDD-3.3 DC Supply Voltage @ 3.3 V typical 3.14 3.3 3.46 V —



Tj Junction Temperature 0 — 115 °C —

TA Operating Free Air 0 — 70 °C —

JA Theta Junction to Ambient Air — 10.9 — °C/W 0 Linear Feet/Minute





JB Theta Junction to Board — 8.6 — °C/W To board

JC Theta Junction to Case — 0.84 — °C/W To case

Table 21: PCI Express GigaBlaze Transmitter Voltage Characteristics—P_TX[7:0]

Symbol ParameterSpeed and Technology

Min Vp-p Max Vp-p Unit

Vp-p Peak-to-Peak Voltage PCI Express – 2.5 GB/s

815 1135 mV

Vp-p Peak-to-Peak Voltage PCI Express – 5.0 GB/s

815 1060 mV



5.1.2 6Gb/s SAS Transceiver Signal Characteristics

For more information concerning the SAS/SATA transceivers, refer to the Serial Attached SCSI - 2 (SAS-2) specification. The following tables show 6Gb/s SAS transceiver signal characteristics.

Table 22: PCI Express GigaBlaze Receiver Voltage Characteristics—P_RX[7:0]

Symbol Parameter Min Max Unit Condition

Vp-p Minimum Input Receiver Sensitivity

175 — mV Inside the EYE

Table 23: PCI Express GigaBlaze Transceiver Rise/Fall Characteristics—P_TX[7:0], P_RX[7:0]

Speed Minimum Rise/Fall Time Maximum Rise/Fall TimeSpecified

RangeUnit

2.5 Gb/s 50 79.6 Minimum 50 ps

5.0 Gb/s 31 54 Minimum 30 ps

Table 24: SAS/SATA GigaBlaze Transmitter Voltage Characteristics—TX[7:0]

Symbol ParameterSpeed and Technology

Min Vp-p Inside EYE

Max Vp-p Outside EYE

Unit

Vp-p Peak-to-Peak Voltage SAS – 1.5Gb/s 681 1128 mV

Vp-p Peak-to-Peak Voltage SAS – 3Gb/s 710 1238 mV

Vp-p Peak-to-Peak Voltage SATA – 1.5Gb/s — 544 mV

Vp-p Peak-to-Peak Voltage SATA – 3Gb/s — 612 mV

Table 25: 6Gb/s SAS Transmitter Voltage Characteristics—TX[7:0]

Symbol Parameter Speed and Technology Min Max Unit

Vp-p Peak-to-Peak Voltage SAS – 6Gb/s 1024 1096 mV

Vvma Voltage Modulation Amplitude

SAS – 6Gb/s 808 848 mV

Table 26: SAS/SATA GigaBlaze Receiver Voltage Characteristics—RX[7:0]

Parameter Parameter Min Max Unit Condition

Vp-p Out of Band 150 — mV Inside the EYE

Vp-p Normal Operation 275 — mV Inside the EYE



5.1.3 External Memory Signal Characteristics

The following tables show external memory signal characteristics.

Table 27: SAS/SATA GigaBlaze Transceiver Rise/Fall Characteristics—TX[7:0], RX[7:0]

Speed and Technology

Min Rise/Fall Time Max Rise/Fall Time Specified Range Unit

SAS – 1.5Gb/s 80.8 86.2 67–273 ps

SAS – 3Gb/s 64.3 82.2 67–137 ps

SAS – 6Gb/s 59.5 65 41.6 min ps

SATA – 1.5Gb/s 110.3 119.4 100–273 ps

SATA – 3Gb/s 95.6 106.3 67–273 ps

Table 28: Bidirectional Signals—XM_AD[63:0], XM_AP[3:0]

Symbol Parameter Min Nominal Max Unit Test Conditions

Vt Schmitt trigger switching threshold

0.8 1.0 2.0 V —

Vt+ Schmitt trigger positive-going threshold

— 1.6 2.0 V —

Vt- Schmitt trigger negative-going threshold

1.0 1.2 — V —

VHYST Schmitt trigger hysteresis 0.15 0.2 — V —

VOH Output high voltage 2.4 — — V —

VOL Output low voltage — — 0.4 V —

IOZ 3-state leakage –10 1.0 10 A —

CIO Input capacitance of I/O pads

— — 3.5 pF —

Table 29: Output Signals—XM_BE[3:0]/, XM_OE[1:0]/, XM_WE[1:0]/, XM_FLASH_CS/, XM_NVSRAM_CS/, XM_PBSRAM_CS/, XM_CLK, XM_ADV/, XM_ADSC/







5.1.4 UART, System, and Other Signal Characteristics

The following tables show UART, system, and other signal characteristics.

Table 30: Output Signals—UART0_TX, SYS_ERROR, SYS_HB_LED, ICE_TDO, TDO, PROCMON

Symbol Parameter Min Max Unit Test Conditions

VOH Output high voltage 2.4 — — —

VOL Output low voltage — — 0.4 —

IOZ 3-state leakage –10 1.0 10 —

Table 31: Input Signals—UART_SERCLK, UART0_RX, SYS_HALT/, SYS_DBMODE[3:0], SYS_SDATA[3:0], SYS_CLK_SEL, SAS_CLK_FRQ, SYS_PWR_ON_RST/, SYS_RST_0/, SCAN_ENABLE

Symbol Parameter Min Nominal Max Unit

Vt Schmitt trigger switching threshold 0.8 1.0 2.0 V

Vt+ Schmitt trigger positive-going threshold — 1.6 2.0 V

Vt- Schmitt trigger negative-going threshold 1.0 1.2 — V

VHYST Schmitt trigger hysteresis 0.15 0.2 — V

IIN Input current –10 1.0 10 A

CIO Input capacitance of I/O pads — — 3.5 pF

Table 32: Input Signal—SYS_REF_CLK

Symbol Parameter Min Nominal Max Unit

VIL Input low voltage VSS - 0.5 — 0.8 V

VIH Input high voltage 2.0 — VDDIO33 + 0.3 V

Vt Switching threshold 0.8 1.0 2.0 V

IIN Input current –10 1.0 10 A

Table 33: Input Signals with Pullups—ICE_TCK, ICE_TDI, ICE_TMS, ICE_TRST/, TCK, TDI, TMS, TRST/

Symbol Parameters Min Nominal Max Unit Test Conditions


0.8 1.0 2.0 V —


— 1.6 2.0 V —


1.0 1.2 — V —


IIN 3-state leakage –70 –217 –450 A @ Vin = Vss



5.1.5 I2C Signal Characteristics The following tables show I2C signal characteristics.

5.1.6 GPIO and Serial GPIO Signal Characteristics

The following tables show GPIO and serial GPIO signal charactersitcs.

Table 34: I2C Signals—IIC0_SCL, IIC0_SDA, IIC1_SCL, IIC1_SDA, SBL_SCL, SBL_SDA



0.8 1.0 2.0 V —


— 1.6 2.0 V —


1.0 1.2 — V —





CIO Input capacitance of I/O pads — — 3.5 pF —

Table 35: GPIO and Serial GPIO Bidirectional Signals—GPIO[35:0], SIO_BLINK



0.8 1.0 2.0 V —


— 1.6 2.0 V —


1.0 1.2 — V —






Table 36: GPIO and Serial GPIO Outputs—SIO0_DOUT, SIO1_DOUT, SIO0_LOAD, SIO1_LOAD, SIO0_CLK, SIO1_CLK






LSISAS2008 6Gb/s SAS/SATA Controller Reference Manual Chapter 5: AC, DC, and Timing Specifications | AC Characteristics: Reset Timing Parameters

5.2 AC Characteristics: Reset Timing Parameters

The following figure and table show the reset timing requirements for the LSISAS2008 controller.

Figure 10: Reset Timing Parameters

5.3 External Memory Timing Diagrams

The LSISAS2008 controller provides direct attachment to external flash ROM, NVSRAM, or PBSRAM through the Peripheral Bus Access Module (PBAM) core. The PBAM interface can operate an 8-bit flash ROM, an SRAM data bus, or an NVSRAM data bus. The PBAM interface provides 26 address signals and individual chip select signals. The XM_FLASH_CS/ chip select signal selects the flash memory, XM_NVSRAM_CS/ selects the NVSRAM, and XM_PBSRAM_CS/ selects the PBSRAM. External bus masters in addition to the LSISAS2008 controller are not permitted.

The figures in this section provide external memory timing waveforms, and the tables in this section list the timings.

Table 37: GPIO and Serial GPIO Signals—SIO0_DIN, SIO1_DIN



0.8 1.0 2.0 V —


— 1.6 2.0 V —


1.0 1.2 — V —


IIN Input current –10 1.0 10 A —


SYS_PWR_ON_RST/

SYS_RST_1/

t3

t1

VCC

Table 38: Reset Timing Parameters

Symbol Parameter Min Max

t1 SYS_RST_0/ pulse width 3 SAS_REF_CLK cycles —

t3 SYS_PWR_ON_RST/ pulse width (if asserted) See I/O timing —


Chapter 5: AC, DC, and Timing Specifications | External Memory Timing Diagrams LSISAS2008 6Gb/s SAS/SATA Controller Reference Manual

5.3.1 PBSRAM Timings The following figure shows the PBSRAM timing waveforms, and the following table lists the timings.

Figure 11: PBSRAM Read/Write/Read Timing Waveforms

XM_CLK

tcyc

twdh

Addr(y)ADSC Addr(y) Addr

(y+1)Addr(z)ADSC Addr(z) Addr(z) Addr (z+2)Addr

(z+1)Addr(x)ADSCXML_AD[23:00]/CTL

Invalid Data(y) Data (y+1)

ReadData

ReadData(z)

ReadData(z+1)

ReadData(z+2)XM_AD[31:00]

XM_OE[0]/

Rd Deselectand Bus

Turnaround

Wr Address

and Select

Wr Data

Wr Deselect,

Rd Address, and Select

Rd Pipe Wait

Rd Data

twdv

trsu

trhtohz

toev

tolz

Wr Data

Rd Data

3_00378-00

Table 39: PBSRAM Read/Write/Read Timingsa

Symbol Parameter Min Max Unit

tcyc XM_CLK cycle time (programmable) 11.25b 11.25b ns

16.88c 16.88c ns

trsu Read setup time 5.25 — ns

trh Read hold time 0 — ns

twdv Write valid time XM_AD[31:0], XM_AP[3:0] — 9.00 ns

XM_AD[23:0] — 9.00 ns

Control Signalsd — 9.00 ns

twdh Write hold time XM_AD[31:00], XM_AP[3:0] 1.00 — ns

XM_AD[23:0] 1.00 — ns

Control Signalsd 1.00 — ns

toev Output enable valide — 0.75 ns

tolz Data low impedance 0.5 2.5 ns

tohz Data high impedance 0 1.75 ns

a. Refer to the LSISAS2008 Design Considerations Systems Engineering Note for more information about the memory interface.b. tcyc is programmed to PLB_CLK/2. Contact your LSI FAE for more information.c. tcyc is programmed to PLB_CLK/3. Contact your LSI FAE for more information.d. Control signals include XM_WE[1:0]/, XM_BE[3:0]/, XM_NVSRAM_CS/, XM_PBSRAM_CS/, XM_ADSC/, and XM_ADV/.e. OE for PBSRAM is asserted one clock earlier.


LSISAS2008 6Gb/s SAS/SATA Controller Reference Manual Chapter 5: AC, DC, and Timing Specifications | External Memory Timing Diagrams

5.3.2 Flash ROM Read Timings The following figure and table show the Flash ROM read timings.

Figure 12: Flash ROM Read Timing Waveforms

NOTE: Contact your LSI FAE for more detailed information about the programmable values.

XM_CLK

XM_A[25:0]

XM_OE_N

XM_D[15:0]

XM_FLASH_CS_N

tas tah

tcyc

tdh

tds

XXXX

tdz

XM_D[7:0]

Table 40: Flash ROM Read Timings


tcyc XM_CLK cycle time (programmable) 11.25a 11.25a ns

16.88b 16.88b ns

tas Address setup time (programmable) (n1 * tcyc) – 5c (n1 * tcyc)c ns

tah Address hold time 5.0 — ns

tcs Flash CS width (programmable) (n2 * tcyc)d (n2 * tcyc)d ns

tds Read setup time 16.1 — ns

tdh Read hold time 0 — ns

tdz Data high impedance 22.5e — ns

a. tcyc is programmed to PLB_CLK/2. Contact your LSI FAE for more information.b. tcyc is programmed to PLB_CLK/3. Contact your LSI FAE for more information.c. n1 can be programmed from 1 to 4 (default = 3). The same n1 parameter controls the address setup times for both read and write.d. n2 can be programmed from 1 to 31 (default = 31). Be sure the Flash CS width is > (Flash access time from CS + tds + 8 ns).e. Read recovery at least 2 clocks after a write.


Chapter 5: AC, DC, and Timing Specifications | External Memory Timing Diagrams LSISAS2008 6Gb/s SAS/SATA Controller Reference Manual

5.3.3 Flash ROM Write Timings The following figure and table show the Flash ROM write timings.

Figure 13: Flash ROM Write Timing Waveforms

5.3.4 NVSRAM Timings NVSRAM timings are similar to Flash ROM timings. See Section 5.3.2, Flash ROM Read Timings, and Section 5.3.3, Flash ROM Write Timings .

3_00379-00

tcyc

XM_CLK

XM_A[25:0]

XM_WE_N

XM_BE[1:0]_N

XM_D[7:0]

XM_FLASH_CS_Ntas

tws

tah

twh

Table 41: Flash ROM Write Timings


tcyc XM_CLK cycle time 11.25a 11.25a ns

16.88b 16.88b ns

tas Address setup time (programmable) (n1 * tcyc) – 5c (n1 * tcyc)c ns

tah Address hold time 5.0 — ns

tws Write setup time (programmable) (n3 * tcyc) – 5d (n3 * tcyc)d ns

twh Write hold time (programmable) (n4 * tcyc) – 5e (n4 * tcyc)e ns

a. tcyc is programmed to PLB_CLK/2. Contact your LSI FAE for more information.b. tcyc is programmed to PLB_CLK/3. Contact your LSI FAE for more information.c. n1 can be programmed from 1 to 4 (default = 3). The same n1 parameter controls the address setup times for both read and write.d. n3 can be programmed from 1 to 31 (default = 31). There is no specific register location to read or write this value.e. n4 can be programmed from 1 to 7 (default = 7).


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LSISAS2008 6Gb/s SAS/SATA Controller Reference Manualread.pudn.com/downloads701/doc/project/2821052/LSISAS2008... · 2015. 8. 21. · LSISAS2008 6Gb/s SAS/SATA Controller Reference