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LOW POWER VLSI DESIGN
1. What are the advantages of CMOS over BIPOLAR?
A: 1. Low power dissipation.
2. No static power dissipation.
3. High packing density.
4. High noise margin.
2. What is the equation for power dissipation in CMOS?
A: P = PSC+Ps+Pd
Psc : short circuit power.
Ps : static power.
Pd : dynamic power.
3.What is short circuit power?
A: Existence of a direct path from the power supply to ground and the output node switches.
4. What is static power?
A: The power consumed during the intervels when the logic states remains constant.
5. What are the conventional CMOS logic gates?
A: 1.Complementatary MOS inverter.
2.Basic NOR gate.
3.Basic NAND gate.
6. What is advantage of BICMOS inverter?
A: High current driving capability.
LOW POWER VLSI DESIGN
7. What is the disadvantage of BICMOS inverter?
A: Higher costs due to the added process complexicity.
8. What are the advantages of BIPOLAR circuit?
A: 1. Good noise performance.
2.High driving capability.
3.High switching and I/O speed.
9. What are the different basic driver configarations?
A: They are 3 types:
1.Comman emitter (CE).
2.Gated diode (GD).
3.Emitter follower (Ef).
10. What is the disadvantage of comman emitter driver configuration?
A: Static power dissipation.
11. What is the difference between latches and flip flops?
A: The difference between latches and flip flops is the position of the clock at which the input is
transmitted to the output.
12. What are the different types of latches?
A : 1. Positive level sensitive latches.
2.negative level sensitive latches.
13. Define positive level sensitive latch?
A: The positive level sensitive latch is transparent when the clock is high.
LOW POWER VLSI DESIGN
14. Define negative level sensitive latch?
A: The negative level sensitive latch is transparent when the clock is low.
15. What are the uses of latches and flip flops?
A: An important use of latch and flip flops is in the design of synchronous instruction and
arithmetic pipelines.
16. What are the themes used for evolution of latches and flip flops?
A: 1.Functionality theme.
2. synchronous theme.
3. optimization theme.
4.performence theme.
5.pipeline theme.
6.high performance and low power theme.
17. Define functionality theme?
A: It is defined as functionality model of latchs and flip flops was fully defined i.e at gate level.
18. What is the Difference between static circuits and dynamic circuits?
A: Static Circuits
1.It uses the feedback arrangement to store the I/P
2.It is slow.
3.Not sensitive to noise
4.does not have refreshing property.
LOW POWER VLSI DESIGN
Dynamic Circuits
1.It does not uses feedback it stores the charging in capacitor.
2.It is fast.
3.Sensitive to noise.
4.It uses refreshing property
19. Define pipeline theme?
A: In Pipeline theme the total task can be divided in to a number of sub tasks and overlap the
execution of the subtasks.
20. What is domino logic?
A: All the logic inputs are present in the n-logic blocks.
21. What is the NORA logic?
A: All the inputs are pleased alternatively between n and p logic blocks.
22. What are the conditions provided by NORA logic?
A: there are two conditions
1. The number of static inversions between two C2MOS latches should be even.
2. The number of static inventions between a C2MOS latch and a dynamic gate should
be even.
23. What is wave pipelining?
A: The logic element delays can be used as a delay elements.
24. What is the advantage of self timed ciruits ?
A: The switching activity is minimized in the absence of the data.
LOW POWER VLSI DESIGN
25. What are the quality measures for latch and flip-flop?
A: 1.Performance measures.
2.Power dissipation
3.Area measures
4.Sensitivity to voltage & technology scaling.
26. What is MOCF(Maximum operating clock frequency)?
A: MOCF is the highest clock frequency at which a flip-flop can be clocked while still delivering
full swing at the output.
27. How can you measure the MOCF?
A: It can be measured by connection on the output of the flip-flop to its input through an odd
number of inverts and the flip-flop is clocked at the maximum frequency.
28. What are the cases to be considered while measuring MOCF for double edge triggered
flip-Flop?
A: There are two cases.
1. The input makes a high to low transition when the clock is low and a low to high
transition when the clock is high.
2. The input makes a high to low transition when the clock is high and a low to high
transition when the clock is low.
29. On which bases the setup and hold time can be defined?
A: Based on structure of flip-flops.
30. What is setup time?
A: Flip flop latch the input data on the active edge of the clock.The data must be stable for a
minimum time.
LOW POWER VLSI DESIGN
31. What is the hold time?
A: Flip flop latch the input data on the active edge of the clock.As soon as the clock has made its
transition the input must be stable for a period.
32. In how many phases the dynamic circuits operate?
A: 1.Pre-charge phase.
2. Evolution phase.
33. What is pre charged phase?
A: The output node is charged to login 1
34. What is Evolution phase?
A: The output node is conditionally discharged.
35. What is static flip-flop?
A: It follow the principle of regeneration, the output of the every stage is either pulled up to
VDD or Pull down to GND.
36. What is semi static flip flop?
A. It is can be constructed by using a dynamic master latch with a static slave latch or vice versa.
37. What is the diff between single edge triggered and double edge triggered flips flop?
A: Single Edge triggered.
1.It uses single clock Edge
2.The data rate is low.
3.The area is less.
Double edge triggered
1.It used both clock edges
LOW POWER VLSI DESIGN
2.the data rate is twice that of the single edge .
3.The area is twice that of the single edge.
38. What are the advantages SOI(Silicon on Insulator)?
A:1 .High packing density.
2. High speed
3.Lower power operation.
39. What is the disadvantage of retrograde –well CMOS?
A: Increases the junction capacitance .
40. Give the equation for saturation drain current of a MOSFET?
A: IDSAT=1/2n UCox W/L(VGs-VT)2
U=Effective mobility
Cox=Gate oxide capacitance.
VGs=Gate to srouce bias
VT =T hreshold voltage
W and L=Width and Length of the device.
41. What are the advanced MOSFET models?
A: 1 HSPICE level 50
2 The EVK MOSFET models (EVK--- Enx-krummenacher-vittoz)
42. Mention some bi-polar spice models?
A: 1.Ebers-Moll model
2.Gummel- Poon model
LOW POWER VLSI DESIGN
3.Modified Gummel- Poon model
4.MEXTRAM model
5.HICUM model
6.VBIC95 model
43. What are the Low-Voltage, Low-Power Design Limitations?
A. The Low-Voltage, Low-Power Design Limitations are as follows:
1) Power Supply Voltage
2) Threshold Voltage
3) Scaling
4) Interconnect Wires.
44. What are the benefits of Scaling?
A. Scaling has the benefit of Improved interconnect technology and Higher density of
integration.
45. What are Latches and Flip-Flops?
A. Latches and flip-flops are basic sequential elements commonly used to store logic values and
are always associated with the use of clock and clocking networks.
46. What are the layout methodologies for physical implementation of complex circuits?
A. Three layout methodologies are commonly used for physical implementation of complex
circuits as follows:
1) Full- custom design
2) The gate array approach
3) The standard– cell approach.
LOW POWER VLSI DESIGN
47. What are the BICOMS Processes technologies?
A. The BICOMS technologies can be broadly classified into three groups:
a. Low cost, medium – speed, 5-V digital
b. High- performance, high- cost, 5-V digital
c. Analog/Digital
The first two processes involve the addition of a few extra mask sets to the conventional COMS
process.
48. What are the approaches of production of Graded- Drain Structures?
A. The Graded- Drain regions that help to minimize electric field distribution in the areas can be
created in a number of ways. The approaches include:
1) Phosphorus-Drain Structure.
2) Double- Diffused Drain.
3) Lightly- Doped Drain.
49. What are the major uses of Latches and Flip- Flops?
A. An important use of latches and flip- flops is in the design of synchronous instruction and
arithmetic pipelines.
50. What are the Quality Measures for Latches and Flip- Flops?
A. The Quality Measures described in four main categories:
1) Performance measures
2) Power dissipation measures
3) Area measures
4) Sensitivity to voltage and technology Scaling.
LOW POWER VLSI DESIGN
51. What are the categories of latches and flip- flops?
A. The study of latches and flip- flops will be divided into two categories:
1) Single edge- triggered flop- flop
2) Double edge- triggered flip- flop
52. What are Sensitivity to clock Skew?
A. Clock skew is singularly the most ominous problem the design of large VLSI circuits.
53. What is the equation of the power dissipation measures in swings?
A. A reduced voltage swing reduced the power dissipation according to the following equation:
P=α×f×C× ×ΔV.
54. What are the making MOCF calculations of double edge triggered flip flops?
A. For double edge triggered flip- flops two cases are to be considered while making MOCF
calculations:
Case 1: The input makes a high to low transition when the clock is a low, and a low to high
transition when clock is a high.
Case 2: The input makes a high to low transition when the clock is a high and a low to high
transition when the clock is a low.
55. What is the advantage of Dynamic circuits in performance theme?
A. The biggest advantage of dynamic cir. is that they are faster and smaller than static circuits.
56. What are the features of HICUM?
A. The main features of HICUM is
1) The high current operating region.
2) Weak avalanche breakdown is available.
LOW POWER VLSI DESIGN
57. What are the advantages of HICUM?
A. HICUM‘s major advantages over other bipolar models are
1) Scalability
2) Fairly simple and process- based/related parameter extraction.
3) Predictive capability in terms of process and layout variations
58. What is the difference between LOCOS and Shallow Trench?
A. The only difference between LOCOS and Shallow trench is deposition in STI thermal oxide
is used to fill the field regions.
59. What are the features of BIPOLAR?
A. 1) high power dissipation
2) Low input impedance
3) Low packing density
60. What is the Disadvantage of LOCOS?
A. Disadvantage of LOCOS is min isolation distance is about 0.8µm from edge of
n/p junction to another. This min isolation is not possible for many applications.
61. What are the technologies introduced to overcome LOCOS?
A. a) Shallow trench Isolation
b) Deep trench Isolation
c) SOI
62. What is SOI?
A.SOI is Silicon –on-Insulator. SOI technology offers high packing density as well as
high speed and low power Operations.
LOW POWER VLSI DESIGN
63. What is the role of Interconnect wires in power consumption?
A. Interconnect wires are responsible for increase in power consumption and they attribute to
90% of dissipation in FPGAs
64. What are the basic steps involved in Performance measures?
1. Maximum operating clock frequency
2. Full swing considerations
3. Setup/hold time considerations
4. Sensitivity to clock skew
5. Sensitivity to input and clock skew rate
65. What is Maximum operating clock frequency?
A: MOCF is the highest clock frequency at which a flip-flop can be clocked while still delivering
full swing at the output.
67. Define Clock skew?
Clock skew (sometimes timing skew) is a phenomenon in synchronous circuits in which
the clock signal (sent from the clock circuit) arrives at different components at different times.
68. What is meant by Sensitivity to clock Skew?
A. Clock skew is singularly the most ominous problem the design of large VLSI circuits.
