LOW POWER WIRELESS DATA ACQUISITION ASIC - IISc · INDIAN INSTITUTE OF SCIENCE, BANGALORE BANGALORE - 560012, INDIA CERTIFICATE This is to certify that the project report entitled

LOW POWER WIRELESS DATA ACQUISITION ASIC

A dissertation submitted to

Indian Institute of Science, Bangalore

in partial fulfillment for the award of the degree of

Master of Technology

in

MICRO ELECTRONICS

by

RAGHUNATH K P

(14577)

Under the supervision of

Prof. BHARADWAJ AMRUTUR

Department of Electrical Communication

Indian Institute of Science, Bangalore

2018-19

June 2019

DECLARATION

I certify that

(a) The work contained in this report has been done by me under the guidance of

my supervisor.

(b) The work has not been submitted to any other Institute for any degree or

diploma.

(c) I have conformed to the norms and guidelines given in the Ethical Code of

Conduct of the Institute.

(d) Whenever I have used materials (data, theoretical analysis, figures, and text)

from other sources, I have given due credit to them by citing them in the text

of the thesis and giving their details in the references. Further, I have taken

permission from the copyright owners of the sources, whenever necessary.

Date: June 2019 RAGHUNATH K P

Place: Bangalore 14577

i

DEPARTMENT OF ELECTRICAL COMMUNICATION

INDIAN INSTITUTE OF SCIENCE, BANGALORE

BANGALORE - 560012, INDIA

CERTIFICATE

This is to certify that the project report entitled “LOW POWER WIRELESS

DATA ACQUISITION ASIC ” submitted by RAGHUNATH K P (Roll No.

14577) to Indian Institute of Science, Bangalore towards partial fulfillment of require-

ments for the award of degree of Master of Technology in MICRO ELECTRONICS

is a record of bona fide work carried out by him under my supervision and guidance

during 2018-19.

Prof. BHARADWAJ AMRUTUR

Date: June 2019 Department of Electrical Communication

Place: Bangalore Indian Institute of Science, Bangalore

Bangalore - 560012, India

ii

http://www.iisc.ac.in/department/ece

http://www.iisc.ac.in

Abstract

Low power wireless data acquisition system has a wide range of applications in areas

like IoT based wireless sensor networks, High reliability Avionics, defense application

etc. The wireless interface provides reliable communication with reduced weight and

power. In this paper a wireless data acquisition system for the MEMS based sensor

typically used in the aerospace application is discussed. The ASIC will be attached to

the sensor, which acquires data from the sensor and transmit via wireless link to other

sub systems. Usage of such systems in energy harvested applications require low

power consumption, minimum sensitivity and easy integration. Major components

in these systems are Analog to Digital Converter along with a Micro Controller

and wireless transceivers. Conventional analog to digital converters consume a lot

of power and is sensitive to supply voltage, process and temperature. Since power

optimization and miniaturization is an active area of research, this work attempts

to design a data acquisition system which is an all-digital solution with reduced

power consumption. Design of a Time to Digital Converter based ADC was carried

out to convert direct sensor output to digital format with around 20 bit resolution.

This avoids the usage of analog front end circuits such as amplifiers and filters.

A micro-controller is used for data acquisition which consumes less power and has

low power modes. A backscatter communication interface on 2.4GHz provides low

power communication interface of approximately 10m distance. Physical design of

the mixed signal chip has been done in UMC180nm technology node.

iii

Acknowledgements

First and foremost, I thank God almighty for providing me with the strength, con-

fidence and positive energy to complete my work successfully. I would like to thank

my advisor and mentor Prof. Bharadwaj Amrutur for choosing me as his student

to do this work. He has been kind, supportive and has shown immense trust on

me throughout the schedule. His ideas, insights and timely suggestions has been

a great source of inspiration to me always. I would like to thank The Ministry of

Electronics and Information Technology (MeitY) for providing the software tools for

design, namely Cadence and Mentor Graphics. I would like to thank Dr.Nagamani,

for helping me with the physical design related aspects in the project. I would like

to thank Dept. of Electrical Communication for providing me with the facilities

to do the project. Thanks to Olivier Girard for providing the msp430 based micro

controller code for implementation in the system. I would like to thank Indian Space

Research Organization (ISRO) for sponsoring me to do the M.Tech programme at

IISc. Thanks to all my friends whose affection and friendship has made my life at

IISc memorable. I thank my wife, Padmaprabha V R and my son Srihari P R for

their love and patience during the different stages of my project. Last but not the

least, I am eternally indebted to my parents Padmanabhan P and Karthiayani K P

for their love, encouragement and support. This dissertation is dedicated to them.

iv

Contents

Declaration i

Certificate ii

Abstract iii

Acknowledgements iv

Contents v

List of Figures viii

List of Tables xi

Abbreviations xii

1 Introduction 1

2 System Design Requirements 6

2.1 MEMS sensor interface requirement . . . . . . . . . . . . . . . . . . . 6

2.2 ADC resolution requirement . . . . . . . . . . . . . . . . . . . . . . . 7

2.3 Peripheral requirement . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.4 Processor and interface requirement . . . . . . . . . . . . . . . . . . 8

2.5 IO PAD requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.6 Wireless Transceiver requirement . . . . . . . . . . . . . . . . . . . . 9

2.7 Packaging requirement . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.8 Power requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3 Literature Survey 10

3.1 Processor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.2 Analog data acquisition system . . . . . . . . . . . . . . . . . . . . . 11

3.2.1 Minimalistic design . . . . . . . . . . . . . . . . . . . . . . . . 12

3.2.2 Digitally-assisted analog design . . . . . . . . . . . . . . . . . 12

3.2.3 Time domain analog processing . . . . . . . . . . . . . . . . . 12

v

Contents vi

3.2.4 Time to Digital converter (TDC) . . . . . . . . . . . . . . . . 12

3.3 Back scatter communication . . . . . . . . . . . . . . . . . . . . . . . 13

3.3.1 Ambient Backscatter . . . . . . . . . . . . . . . . . . . . . . . 14

3.3.2 Wi-Fi Backscatter . . . . . . . . . . . . . . . . . . . . . . . . 15

3.3.3 BackFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.3.4 LoRea . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.3.5 LoRa Backscatter . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.3.6 RFID Back scatter . . . . . . . . . . . . . . . . . . . . . . . . 17

4 System Design 18

5 Data acquisition system 21

5.1 Voltage Controlled Oscillator (VCO) . . . . . . . . . . . . . . . . . . 22

5.1.1 VCO Data Acquisition scheme . . . . . . . . . . . . . . . . . . 26

5.2 Vernier Delay Line (VDL) . . . . . . . . . . . . . . . . . . . . . . . . 29

5.3 Sample and Hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.4 Band Gap Reference (BGR) . . . . . . . . . . . . . . . . . . . . . . . 33

5.5 Design of Level Translator . . . . . . . . . . . . . . . . . . . . . . . . 39

5.6 Design of Delay Locked Loop . . . . . . . . . . . . . . . . . . . . . . 42

5.6.1 Design of Phase detector circuit . . . . . . . . . . . . . . . . 44

5.6.2 Design of Charge Pump circuit . . . . . . . . . . . . . . . . . 47

5.6.3 Design of Loop filter . . . . . . . . . . . . . . . . . . . . . . . 48

6 Wireless Transceiver 49

6.1 Receiver power computation . . . . . . . . . . . . . . . . . . . . . . . 50

6.2 Design of Low Noise Amplifier . . . . . . . . . . . . . . . . . . . . . 52

6.3 Envelope Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

6.4 Base band amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

6.5 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

6.6 Integrated Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . 61

6.7 Back Scatter Transmitter . . . . . . . . . . . . . . . . . . . . . . . . 62

7 Energy Measurement Circuit 65

8 Temperature measurement Circuit 70

8.1 On-chip Temperature measurement . . . . . . . . . . . . . . . . . . . 71

8.2 Off-chip Temperature measurement . . . . . . . . . . . . . . . . . . . 72

9 Processor and Interface Design 73

9.1 Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

9.2 Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

9.2.1 Interrupts and peripheral mapping . . . . . . . . . . . . . . . 75

9.2.2 ADC interface and Address Mapping . . . . . . . . . . . . . . 76

Contents vii

9.3 PWM interface and Address Mapping . . . . . . . . . . . . . . . . . . 77

9.4 UART interface and Address Mapping . . . . . . . . . . . . . . . . . 77

9.5 RF base band processing interface and Address Mapping . . . . . . . 78

9.6 Flash Chip interface and Address Mapping . . . . . . . . . . . . . . . 78

9.7 Program and Data memory Interface and Address Mapping . . . . . 79

9.7.1 MSP430 MEMORY interface . . . . . . . . . . . . . . . . . . 79

9.8 Processor Debug Interface . . . . . . . . . . . . . . . . . . . . . . . . 81

9.9 Processor Boot chip Interface . . . . . . . . . . . . . . . . . . . . . . 82

9.10 SECDED Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

10 Physical Design 85

10.1 Chip Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

10.2 Encounter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

10.3 Custom Cell Placement with IO . . . . . . . . . . . . . . . . . . . . . 92

10.4 IO and Power planner . . . . . . . . . . . . . . . . . . . . . . . . . . 93

10.5 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

11 Conclusion 97

12 References 98

A Mixed Signal Chip Design 102

A.1 LEF generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

A.2 Lib generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

A.3 Memory Compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

A.4 Innovus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

A.5 Virtuoso . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

A.6 Calibre . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

List of Figures

1.1 Top level Avionics system . . . . . . . . . . . . . . . . . . . . . . . . 2

1.2 TM and TC wires on a Satcom Payload interface unit [1] . . . . . . . 2

1.3 Wiring inside payload [2] . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.4 MEMS Sensor with ASIC attached for distributed sensing . . . . . . 4

1.5 Proposed system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.1 MEMS Sensor with differential input . . . . . . . . . . . . . . . . . . 7

2.2 Exploded view of the MEMS sensor . . . . . . . . . . . . . . . . . . 7

4.1 System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.1 Block Diagram of Data Acquisition System . . . . . . . . . . . . . . . 21

5.2 Delay Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

5.3 VCO Data Acquisiton scheme . . . . . . . . . . . . . . . . . . . . . . 26

5.4 VCO Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.5 VCO Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.6 VCO Frequency Variation with input voltage . . . . . . . . . . . . . . 28

5.7 VCO Simulated output across corners . . . . . . . . . . . . . . . . . . 28

5.8 Basic building block of VDL circuit . . . . . . . . . . . . . . . . . . . 29

5.9 VDL circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.10 VDL simulated output . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.11 VDL Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

5.12 Sample and Hold Circuit . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.13 Sample ad Hold simulation . . . . . . . . . . . . . . . . . . . . . . . . 32

5.14 Sample and hold Layout . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.15 VREF generation from PTAT and CTAT . . . . . . . . . . . . . . . . 33

5.16 Band Gap Reference V1 is CTAT and VR is PTAT . . . . . . . . . . 35

5.17 Current mirror circuit providing equal current to both arms . . . . . 35

5.18 PTAT output VR2 by pumping same current through R1 through R2 36

5.19 Band Gap Reference by adding PTAT and CTAT in series(VR2 andVD5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

5.20 Band Gap Reference using PNP transistor . . . . . . . . . . . . . . . 37

5.21 Band Gap Reference Simulation (1) . . . . . . . . . . . . . . . . . . . 37

5.22 Band Gap Reference Simulation (2) . . . . . . . . . . . . . . . . . . . 38

viii

List of Figures ix

5.23 Band Gap Reference circuit Layout . . . . . . . . . . . . . . . . . . . 38

5.24 Level Translator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . 39

5.25 Level Converter opamp . . . . . . . . . . . . . . . . . . . . . . . . . . 40

5.26 Level Translator Simulated Output . . . . . . . . . . . . . . . . . . . 40

5.27 Level Translator Layout . . . . . . . . . . . . . . . . . . . . . . . . . 41

5.28 Block diagram of DLL . . . . . . . . . . . . . . . . . . . . . . . . . . 42

5.29 DLL model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

5.30 DLL in locking state . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

5.31 DLL loop filter output build up . . . . . . . . . . . . . . . . . . . . . 43

5.32 DLL Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

5.33 VDL Delay with temperature . . . . . . . . . . . . . . . . . . . . . . 44

5.34 Performance comparison DLL locked VDL and VDL with temperature 44

5.35 PFD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

5.36 Phase detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

5.37 Phase detector output Ref clock locking . . . . . . . . . . . . . . . . 46

5.38 Phase detector output Ref clock leading . . . . . . . . . . . . . . . . 46

5.39 Phase detector output Ref clock lagging . . . . . . . . . . . . . . . . 46

5.40 Charge Pump Schematics . . . . . . . . . . . . . . . . . . . . . . . . 47

5.41 Charge Pump Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

5.42 Loop filter circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

6.1 Wireless Transceiver Block Diagram . . . . . . . . . . . . . . . . . . . 50

6.2 Wireless Receiver Outputs . . . . . . . . . . . . . . . . . . . . . . . . 51

6.3 Low Noise Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

6.4 S12 plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

6.5 S11 plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

6.6 Simulated Low Noise Amplifier output . . . . . . . . . . . . . . . . . 53

6.7 Noise Figure of the LNA . . . . . . . . . . . . . . . . . . . . . . . . . 54

6.8 IIP3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

6.9 Low Noise Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

6.10 Envelope Detector Block diagram . . . . . . . . . . . . . . . . . . . . 56

6.11 Four stage voltage multiplier[17] . . . . . . . . . . . . . . . . . . . . . 56

6.12 Voltage multiplier Equivalent during Off stage[17] . . . . . . . . . . . 57

6.13 Voltage multiplier Equivalent during On[17] . . . . . . . . . . . . . . 57

6.14 Envelope Detector Output . . . . . . . . . . . . . . . . . . . . . . . . 57

6.15 Envelope Detector Layout . . . . . . . . . . . . . . . . . . . . . . . . 57

6.16 Baseband Amplifier circuit . . . . . . . . . . . . . . . . . . . . . . . . 58

6.17 Baseband Amplifier circuit . . . . . . . . . . . . . . . . . . . . . . . . 59

6.18 Baseband Amplifier Layout . . . . . . . . . . . . . . . . . . . . . . . 59

6.19 Comparator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

6.20 Comparator Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

6.21 Comparator Simulated output . . . . . . . . . . . . . . . . . . . . . . 61

List of Figures x

6.22 Integrated simulated output with 1 mV input . . . . . . . . . . . . . 61

6.23 Backscatter Circuit with open termination[20] . . . . . . . . . . . . . 62

6.24 Backscatter Circuit with matched termination[20] . . . . . . . . . . . 62

6.25 Backscatter Circuit with shorted termination[20] . . . . . . . . . . . . 63

6.26 Backscatter Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

6.27 Backscatter modulation . . . . . . . . . . . . . . . . . . . . . . . . . 64

6.28 Backscatter Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

7.1 Circuit for energy measurement[21] . . . . . . . . . . . . . . . . . . . 66

7.2 Droop detection timing diagram[21] . . . . . . . . . . . . . . . . . . 67

7.3 Minimum energy tracking loop block diagram[22] . . . . . . . . . . . 67

7.4 Energy measurement circuit[22] . . . . . . . . . . . . . . . . . . . . . 68

7.5 VCO for Energy Measurement . . . . . . . . . . . . . . . . . . . . . . 69

7.6 Energy Measurement block . . . . . . . . . . . . . . . . . . . . . . . . 69

7.7 Frequency variation with capacitor voltage . . . . . . . . . . . . . . . 69

8.1 Temperature measurement block . . . . . . . . . . . . . . . . . . . . 71

8.2 VCO Simulated output across temperature . . . . . . . . . . . . . . . 71

8.3 External Temperature Measurement block . . . . . . . . . . . . . . . 72

8.4 Frequency variation with external temperature . . . . . . . . . . . . . 72

9.1 openMSP connection diagram with peripherals[24] . . . . . . . . . . . 75

9.2 Memory Map[25] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

9.3 Memory Read timing[26] . . . . . . . . . . . . . . . . . . . . . . . . . 80

9.4 Memory Write timing[26] . . . . . . . . . . . . . . . . . . . . . . . . . 81

10.1 Physical Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

10.2 Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

10.3 Chip Encounter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

10.4 Layout Encounter View . . . . . . . . . . . . . . . . . . . . . . . . . . 91

10.5 Custom library Placement with IO . . . . . . . . . . . . . . . . . . . 92

10.6 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

A.1 GDS export from Innovus . . . . . . . . . . . . . . . . . . . . . . . . 106

A.2 GDS import to Virtuoso . . . . . . . . . . . . . . . . . . . . . . . . . 107

List of Tables

6.1 Gain scheduling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

9.1 Peripheral Interrupt map . . . . . . . . . . . . . . . . . . . . . . . . . 76

9.2 ADC Address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

9.3 PWM Address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

9.4 UART Address map . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

9.5 UART-RF Address map . . . . . . . . . . . . . . . . . . . . . . . . . 78

9.6 Flash chip address map . . . . . . . . . . . . . . . . . . . . . . . . . . 78

10.1 Chip Pin out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

xi

Abbreviations

ADC Analog to Digital Converter

ALU Arithmetic Logic Unit

ASIC Application Specific Integrated Circuit

ASK Amplitude Shift Keying

CMOS Complementary Metal Oxide Semiconductor

DLL Delay Locked Loop

DMA Direct Memory Access

EIRP Equivalent Isotropically Radiated Power

ENOB Effective Number of Bits

FOM Figure Of Merit

GPIO General Purpose Input Output

IC Integrated Circuit

I2C Inter-integrated Circuit

LEF Library Exchange Format

LNA Low Noise Amplifier

MEMS Micro Electro Mmechanical Systems

PVT Process Voltage Temperature

RF Radio Frequency

RFID Radio Frequency Identification

SOC System On a Chip

SPI Serial Peripheral Interface

UART Universal Asynchronous Receiver Transmitter

UHF Ultra High Frequency

VCO Voltage Ccontrolled Oscillator

VDL Vernier Delay Line

VLSI Very Large Scale Integration

xii

Chapter 1

Introduction

The prime design requirement of avionics and defence electronics system is low

weight, low power and high reliability. Avionics systems incorporates large num-

ber of modules or subsystems which are connected through wired interfaces. Power

requirement of each module will be different. Hence, along with the design of sub-

systems, power design is also to be done. As shown in Figure 1.1, there is a Master

system which is connected to several subsystems (with individual power supply for

driving them) through interfaces. Hence for such systems, a low power design can

drastically reduce the overall weight of the payload.

Figure 1.2 and 1.3 shows an avionics system with interconnected modules through

highly complex wired interfaces. This makes the system huge and demands high

integration complexity. Also wired interfaces are prone to harness defects and fail-

ures in adverse environmental condition which is a major drawback. Certain serial

bus topologies require bus termination network which are bulky. The wireless com-

munication interface is also useful in human space mission where weight and power

reduction is critical. The mission involves various separation systems whose data

has to be monitored during separation events, where wired interface cannot be used

[3]. A wireless interface between the different modules eliminates the bus wiring

complexity. However the subsystem power transfer has to be wired. Hence for low

1

Chapter 1. Introduction 2

Figure 1.1: Top level Avionics system

Figure 1.2: TM and TC wires on a Satcom Payload interface unit [1]


Figure 1.3: Wiring inside payload [2]

power systems, a wireless power transfer scheme has to be implemented which can

be done through energy harvesting using RF or other sources. This thesis work

includes the design and implementation of an Application specific integrated circuit

(ASIC) for a low power wireless data acquisition system with 8-channel analog data

acquisition capability. This chip features a wireless interface design between subsys-

tems and is targeted towards low weight, low power acquisition subsystems. This

chip can be attached to various sensors as shown in Figure 1.4 of the avionics sys-

tems and thereby enables data acquisition through distributed sensing. This design

can provide improved reliability compared to the existing wired systems which are

bulky and complex.

Figure 1.5 shows the top level diagram of the avionics system with a master system

and several subsystems without any wire interface. The master system provides RF

energy for harvesting as well as wireless signal interface to subsystems. In this work,

wireless interface circuit for data acquisition circuit for MEMS pressure sensor is

presented, typically suitable for the avionics application.


Figure 1.4: MEMS Sensor with ASIC attached for distributed sensing

Figure 1.5: Proposed system

The key contributions in this thesis work are given below:

• Time to Digital converter based ADC for acquisition of pressure sensor output


which included a differential Voltage Controlled Oscillator (VCO) and Vernier

Delay line (VDL) to measure the VCO frequency. Differential configuration

and Delay locked loop (DLL) for the VDL made the design less sensitive to

PVT and noise variations.

• Low power wireless transceiver which includes low power Back scatter trans-

mitter and low power ASK receiver.

• Micro controller based on MSP430 architecture - an error correction scheme

for the on-board memory based on SECDED for high reliability. RS485 com-

patible UART based serial link was provided for transmission of data output.

SPI based external flash memory interface is also provided.

• New scheme for on-chip energy measurement. This is required to sense energy

consumed by the chip so that closed loop energy control can be implemented

to minimize energy consumption.

• New scheme for on-chip and off-chip temperature measurement, which helps

for compensation of ADC and sensor data with temperature.

• Layout of all modules, module integration and physical design was carried out

for the mixed signal chip in UMC180nm technology node.

The chapters of this thesis is organized as follows Chapter 2 discusses the litera-

ture survey for low power wireless data acquisition system components. Chapter

3 discusses the design of analog data acquisition system. Chapter 4 discuses the

wireless transceiver design. Chapter 5 covers temperature measurement. Chapter 6

discusses energy measurement circuit for energy minimization. Chapter 7 discusses

the physical design.

Chapter 2

System Design Requirements

This chapter discusses the details on System design aspects covered in this project.

2.1 MEMS sensor interface requirement

The MEMS transducer [4] provides a differential analog output, hence requires an

Analog to Digital Converter for acquiring pressure data. MEMS transducer consists

of piezo resistor deposited on the diaphragm which detects the pressure change.

Figure 2.2 shows the structure of MEMS transducer [4]. It is a Wheatstone kind

of arrangement. The sensitivity of the sensor is 15mV/bar/V to 25mV/bar/V. The

supply provided for the sensor is 5V. Hence the maximum signal swing is expected

to be around 150mV/2bar pressure with a 2.5V common mode output. The chip

should be able to process the analog voltage levels of the sensor and convert the

analog data to digital and interface to the processor.

6

Chapter 2. System Design requirement 7

Figure 2.1: MEMS Sensor with differential input

Figure 2.2: Exploded view of the MEMS sensor

2.2 ADC resolution requirement

• The ADC should provide minimum of 14-bit resolution at 5KHz of operation

with a programmable sampling frequency change and should have a 20-bit

resolution at 100Hz of operation.

2.3 Peripheral requirement

• All the peripherals should be processor controlled.


• The system should support single channel PWM with adjustable duty cycle

and period. It should have higher drive strength in order to drive a switching

MOSFET.

• The system should have a minimum of 2 GPIOs configurable through program.

• The system should support single channel UART serial communication proto-

col supporting data rate upto 1Mbps and configurable baud rate.

2.4 Processor and interface requirement

• The system require computation and compensation of analog data from the

sensor and output serially based on the requirement.

• A 16 bit processor with minimum 16 KB of Program memory and 2 KB of

Data memory.

• The memory read write error detection and error correction logic is required.

• Frequency of operation of the processor should be 100MHz frequency.

• It should have an External programming interface for the processor.

• It should have Flash interface for external program storage.

• It should support both internal program execution as well as external program

load and execution.

2.5 IO PAD requirement

• The IO of the SOC should be 5V tolerant 3.3V


2.6 Wireless Transceiver requirement

• The architecture of the transceiver should be low power.

• To reduce the power consumption of the transmitter, back scatter communi-

cation can be used.

• The frequency of operation is 2.4GHz ISM band.

2.7 Packaging requirement

• SOC should be packaged in surface mount ceramic chip package for defense/avion-

ics usage.

2.8 Power requirement

• The SOC should work with supply of 3.3V and 1.8V

Chapter 3

Literature Survey

3.1 Processor selection

Several 16-bit processor architectures are available for low power applications. Pro-

cessor selected should be silicon proven and available as opensource. The Open-

MSP430 processor is ASIC synthesizable and verilog code is available for opensource

usage. The architecture of the processor for peripheral interfacing, programming,

memory interfacing is matches with the proposed system requirements because of

the features listed below. Following are the features of openMSP430 processor.

• ASIC synthesizable version

• Multiple times Silicon Proven.

• Two-wire Serial Debug Interface (I2C or UART based)

• Scalable peripheral address space.

• Configurable memory size for both program and data.

• DMA interface.

10

Chapter 3. Literature Survey 11

• Built-in power and clock management options.

• Low Power Modes (LPMx).

• Hardware and software tools available for evaluation of-the-shelf

3.2 Analog data acquisition system

The FOM of the ADC is key factor of selecting the ADC for the low power data ac-

quisition system. It is mainly a trade-off between resolutions, frequency of operation

and Power dissipation.

FOM =Power

2ENOBfs(pJ/step) (3.1)

Power dissipation is one of the most important concerns in ADCs used for battery

operated devices. It is important to track the trends in ADC power efficiency during

the past years. In an ADC survey, Murmann [5] has gathered ADC performance

data from the International Solid State Circuit Conference (ISSCC) and the VLSI

Symposium on Circuits during the past fifteen years. The data in this survey shows

that the power dissipation of ADCs halves approximately every two years, over the

past decade. Study on ADC architectures shows that the power efficiency improve-

ment is mostly due to the new design trends coming with scaling [5] such as:

• Minimalistic design

• Digitally-assisted analog design

• Time domain analog processing


3.2.1 Minimalistic design

The goal of minimalistic design is to improve power efficiency by simplifying the

analog sub circuits of the ADCs.

3.2.2 Digitally-assisted analog design

The rationale behind digitally-assisted analog design is to move the accuracy burden

from the realm of analog design to the digital domain. Relaxing the precision of the

analog circuitry reduces power consumption significantly

3.2.3 Time domain analog processing

One way to overcome the challenge of low-voltage design is to process a signal in

the time-domain. Time resolution has been improved in nanometer-scale devices

due to the reduction of gate delay, despite the reduction in supply voltage. Hence,

time-domain processing potentially offers a better solution compared to voltage-

based methods, when implemented in deep sub-micron VLSI fabrication processes.

In this work, a low power ADC is proposed based on the Time domain analog

signal processing technique. This kind of architecture is known as Time to digital

converter.

3.2.4 Time to Digital converter (TDC)

TDC’s are generally highly digital structures. As a result, many aspects of their

performance benefit from technology scaling: speed, time resolution, power con-

sumption and area. Any feature of the overall ADC that is dominated by the TDC

will therefore inherently improve with newer CMOS technology. Besides this, highly

digital structures are often easily implemented and ported to newer technologies.


Another interesting aspect is the following: given that the TDC can achieve a cer-

tain time resolution, there exists an interesting trade-off: if more time is available

for the conversion, more levels can be calculated. Such reconfigurability is much less

trivial in conventional ADC’s; the analog-to-time-to-digital converter may prove

useful in the following areas:

• Inherent improvement with technology

• Ease of implementation

• Chip area consumption

• Reconfigurability

• Power consumption

Various architectures of TDC are discussed in [6]

3.3 Back scatter communication

In [7], system redesign for the battery-free low power communication system archi-

tecture has been discussed. This architecture proposes

• Communication by means of power efficient back scatter

• Avoid use of power hungry ADC, FPGA’s and microcontrollers

In [8], back scatter communication and its history has been studied. The concept

of modulating backscatter for communication was first introduced by Stockman

in 1948 and promptly received a lot of attention from researchers and developers

owing to its potential advantages. Basically, backscatter communication is a tech-

nique that allows wireless nodes to communicate without requiring any active radio


frequency (RF) components on the tag. In a conventional backscatter communica-

tion system (CBCS), there are two main components, called the wireless tag reader

device (WTRD) and the wireless tag device (WTD). The WTD in the CBCS is

able not only to harvest energy from the received signals, but also to modulate

and reflect the signals back to the WTRD. The signal reflection is caused by the

intentional mismatch between the antenna and the load impedance at the WTD.

Theoretically, when the load impedance is varied, it will generate the complex scat-

ter coefficient which can be used to modulate the reflected signal with information

bits. The WTRD then uses the receive antenna to receive reflected signals from

the WTD and demodulate these signals to obtain the useful information. In con-

ventional backscattering communication systems, there are two special features that

differ from traditional communication systems. First, in conventional backscatter-

ing communication systems, the receivers (i.e., WTRDs) have to be equipped with

a power source to transmit RF signals to the transmitter (i.e., WTDs). Second,

the transmitters do not need to be equipped with a power source to transmit data

because they will reflect signals received by the receivers instead of generating their

own signals. The second feature is the most important characteristic and also the

main objective for the development of conventional backscattering communication

systems. This special communication feature of CBCSs has received a great deal of

attention, mainly because of the successful implementation of RFID systems and the

potential use in sensor devices that are small in size and have a low power supply.

3.3.1 Ambient Backscatter

This paper [9] describes the design of a communication system that enables two de-

vices to communicate using ambient RF as the only source of power. This approach

leverages existing TV and cellular transmissions to eliminate the need for wires and

batteries, thus enabling ubiquitous communication where devices can communicate

among themselves at unprecedented scales and in locations that were previously


inaccessible. Ambient backscatter, a new communication primitive where devices

communicate by backscattering ambient RF signals. This design avoids the expen-

sive process of generating radio waves; backscatter communication is orders of mag-

nitude more power-efficient than traditional radio communication. Further, since

it leverages the ambient RF signals that are already around us, it does not require

a dedicated power infrastructure as in traditional backscatter communication.[10]

describes the performance modeling of ambient back scatter communication

3.3.2 Wi-Fi Backscatter

This paper [11] describes communication system that bridges RF-powered devices

with the Internet. It shows the reuse existing Wi-Fi infrastructure to provide Inter-

net connectivity to RF-powered devices. To show Wi-Fi Backscatter’s feasibility, It

build a hardware prototype and demonstrate the first communication link between

an RF-powered device and commodity Wi-Fi devices. The use off-the-shelf Wi-Fi

devices including Intel Wi-Fi cards, Linksys Routers, and our organizations Wi-Fi

infrastructure achieves communication rates of up to 1 kbps and ranges of up to 2.1

meters

3.3.3 BackFI

This paper [12] presents novel communication system that enables high throughput,

long range communication between very low power backscatter IoT sensors and WiFi

APs using ambient WiFi transmissions as the excitation signal. Specifically, it show

that it is possible to design IoT sensors and WiFi APs such that ,the WiFi AP in the

process of transmitting data to normal WiFi clients can decode backscatter signals

which the IoT sensors generated by modulating information on to the ambient WiFi

transmission. It show via prototypes and experiments that it is possible to achieve

communication rates of up to 5 Mbps at a range of 1 m and 1 Mbps at a range of 5


meters. Such performance is an order to three orders of magnitude better than the

best known prior WiFi backscatter system [10a]. BackFi design is energy efficient,

as it relies on backscattering alone and needs insignificant power, hence the energy

consumed per bit is very less

3.3.4 LoRea

There is the long-standing assumption that radio communication in the range of

hundreds of meters needs to consume mWs of power at the transmitting device.

This paper [13], demonstrate that this is not necessarily the case for some devices

equipped with backscatter radios. LoRea an architecture consisting of a tag, a reader

and multiple carrier generators overcomes the power, cost and range limitations of

existing systems such as Computational Radio Frequency Identification (CRFID).

LoRea achieves this by: First, generating narrow-band backscatter transmissions

that improve receiver sensitivity. Second, mitigating self-interference without the

complex designs employed on RFID readers by keeping carrier signal and backscat-

tered signal apart in frequency. Finally, decoupling carrier generation from the

reader and using devices such as WiFi routers and sensor nodes as a source of the

carrier signal. LoRea’s range scales with the carrier strength, and proximity to the

carrier source and achieves a maximum range of 3.4 km when the tag is located at 1

m distance from a 28 dBm carrier source while consuming 70 W at the tag. When

the tag is equidistant from the carrier source and the receiver, we can communicate

up to 75 m, a significant improvement over existing RFID readers

3.3.5 LoRa Backscatter

The vision of embedding connectivity into billions of everyday objects runs into

the reality of existing communication technologies — there is no existing wireless


technology that can provide reliable and long-range communication at tens of mi-

crowatts of power as well as cost less than a dime. While backscatter is low-power

and low-cost, it is known to be limited to short ranges. This paper [14] overturns this

conventional wisdom about backscatter and presents the first wide-area backscatter

system. This design can successfully backscatter from any location between an RF

source and receiver, separated by 475 m, while being compatible with commodity

LoRa hardware. Further, when the backscatter device is co-located with the RF

source, the receiver can be as far as 2.8 km away. Finally, it present a design sketch

of a LoRa backscatter IC that costs less than a dime at scale and consumes only

9.25 W of power, which is more than 1000x lower power than LoRa radio chipsets.

3.3.6 RFID Back scatter

The papers [15-18] present a method for measuring signal back scattering from RFID

tags, and for calculating a tag’s radar cross section (RCS). It derives a theoretical

formula for the RCS of an RFID tag with a minimum-scattering antenna. It de-

scribes an experimental measurement technique, which involves using a network

analyzer connected to an anechoic chamber with and without the tag. The return

loss measured in this way allows us to calculate the backscattered power and to

find the tag’s RCS. Measurements were performed using an RFID tag operating in

the UHF band. To determine whether the tag was turned on, we used an RFID

tag tester. The tag’s RCS was also calculated theoretically, using electromagnetic

simulation software. The theoretical results were found to be in good agreement

with experimental data.

Chapter 4

System Design

The system which is considered in this thesis is a wireless data acquisition system

for MEMS pressure sensor primarily targeted for avionics application. Figure 4.1

details the internals of the proposed design. Major subsystems in this design are

• 16-bit Processor

• Data acquisition system

• Energy measurement system

• Temperature measurement system

• Wireless communication module

• Serial interfaces like UART, SPI

• PWM module

• On-chip Program and Data memory

• Single error correction and Double error detection (SECDED)

• Debug and Bootchip interface

18

Chapter 4. System Design 19

Figure 4.1: System Block Diagram

The system consists of 8 channel analog to digital converter. The ADC data is ac-

quired using data acquisition digital logic and acquired data is interfaced to the

processor through the processor-peripheral interface. Frequency of operation of

OpenMSP430 processor used here is 100MHz. The system consists of a wireless

interface module using back scatter transmitter and ASK receiver. The system sup-

ports UART protocol compatible to RS485 voltage level. The SPI interface serves

as the flash chip interface for the external program and data storage. Bootchip

and debug interface logic will do the program load and execution during the power

on. The system consists of a single channel PWM module with adjustable duty

cycle and period by the processor. The PWM output has been given higher drive

strength by using IO pad with higher current drive. The processor is associated

with 8Kx 22-bits of program and 1Kx 22-bits of data memory. Error detection and

correction logic has been introduced between processor and memory for higher reli-

ability requirement of avionics/defence requirement. The system consists of energy

measurement circuit for measuring the on-chip energy usage. The algorithm for the

energy computation is residing in the processor. The measurement of both on-chip

and off-chip temperature is also enabled by an on-chip temperature measurement

circuit.

Chapter 4. System Design 20

The key features of the design are

• 8-channel analog data acquisition module

• Analog data acquisition is based on time to digital converter ADC

• ADC has 20 bit resolution in 100Hz periodicity.

• The sampling frequency is programmable through processor up to 5KHz

• Resolution based on the sampling frequency

• The non linearity correction of the ADC based on initial frequency mode ac-

quisition

• The stability of the ADC ensured by Delay locked loop

• The temperature variation correction by on chip temperature measurement

• RF transceiver in ISM bad of 2.4GHZ

• Backscatter communication based RF transceiver

• Receiver is ASK-UART encoded.

• Baud rate programmable upto 1Mbps

• Energy measurement circuit for on-chip power measurement and optimization

• On-chip and off-chip temperature measurement

The detailed design of all the blocks are presented in the following chapters

Chapter 5

Data acquisition system

Figure 5.1 details the internal blocks in the proposed data acquisition system. Major

blocks are

Figure 5.1: Block Diagram of Data Acquisition System

• 8-channel level translator

• 8-channel sample and hold

• 8-channel dual Voltage Controlled Oscillator (VCO)

• 8-channel dual Vernier Delay Line (VDL)

21

Chapter 5. Data acquisition system 22

• ADC Time acquisition logic

• ADC Frequency acquisition logic

• Processor interface

• Energy VCO measurement logic

• Temperature VCO measurement logic

The system consists of 8 analog data acquisition channels. The ADC is a simple

time to digital converter based. The Level converter circuit converts the 2.5V com-

mon mode signal to 0.9V. The sample and hold circuit hold the input during the

conversion process. It consists Voltage controlled oscillator(VCO) and Vernier delay

line (VDL) circuit. The VCO converts the analog input data from voltage domain

to time domain. VDL measures the subclock delay of VCO which is asynchronous

to the system clock and converts it into thermometer encoded digital data. The

ADC acquisition block calculates the actual VCO period adding the number of sys-

tem clock cycles in the period with the VDL data. To maintain the stability of

the ADC against PVT corners, a closed loop biasing is done for vernier delay line

and VCO is configured in differential configuration. A band gap reference (BGR)

and delay locked loop (DLL) circuits are used for this purpose. The outputs of the

ADC is interfaced to processor peripheral address space periodically updated using

interrupt. The period of data acquisition is made programmable through the pro-

cessor. On-chip temperature measurement and off-chip temperature measurement

were incorporated to the chip based on the VCO.

5.1 Voltage Controlled Oscillator (VCO)

VCO in this design is based on dual Ring oscillator as shown in Figure 5.4. The

frequency of oscillation of the VCO is controlled by the voltage derived from the


Level Translator. The voltage controlling elements of the two VCOs are connected

in the reverse order to cancel out common mode variation. Ring oscillator employs

delay elements. Figure 5.2 shows the current controlled delay cell used in this design.

Figure 5.2: Delay Cell

Frequency of oscillation depends on delay introduced by each inverter stage, so

delay should be voltage controlled. One way to control the delay is to control the

amount of current available to charge or discharge the capacitive load of each stage.

This type of circuit is called a current starved ring VCO. In this VCO basically


the control voltage modulates the turn-on resistances of the pull-down transistor

and pull-up transistors through a current source. These variable resistances control

the current available to charge or discharge the load capacitances. Large value of

control voltage allows a large current to flow, producing a small resistance resulting

in a small delay. Current starved ring VCO uses variable bias currents to control its

oscillation frequency

PMOS ‘Q3’and NMOS ‘Q4’which operate as inverter while PMOS ‘Q1’and NMOS

‘Q3’act as current source. The current source limits the current applied to the

inverter. In other words, the inverter is starved for current. PMOS ‘Q1’and NMOS

‘Q3’drain currents are the resemblance and are set by the input control voltage.

The oscillations of the VCO for N stages is F = 1/NTd, where N is the Number of

delay stage and Td is the delay produced by each stage. We know that the current

supplied to the inverter stages is used for building up the voltage. Hence I = C d(V )dt

.

The variation of control voltage (C1, C2) determines the frequency range and lin-

earity of VCO. The major drawback of this stage is longer rise/fall time when bias

current is quite small, because the voltage swing of the VCO becomes slower. In

addition to this, if bias current is increased then the voltage headroom of the current

source MOS transistors becomes narrow. The oscillation frequency (Fosc) can be

calculated as follows

Ctotal = Cout + Cin (5.1)

Ctotal = Cox(WpLp +WnLn) +3

2Cox(WpLp +WnLn) (5.2)

where Cin, Cout, Cox, Ctotal are the input capacitance, output capacitance, oxide re-

lated capacitance and total capacitance respectively. The total capacitance is the


sum of output and input capacitance of the inverter, and is given by

Ctotal =5

2Cox(WpLp +WnLn) (5.3)

The oscillation frequency is determined by the bias current (Id), number of stages

(N), total capacitance (Ctotal) and control voltage (Vctrl)

Fosc =I

2NCtotalVcntrl(5.4)

I =1

2unCox(Vgs − Vth)2 (5.5)

dI

dVgs= unCox(Vgs − Vth) (5.6)

and is linear. Hence Fosc = K(Vgs − Vth) is also linear. However, the required

resolution can be met using a larger sampling time, if frequency measurement is

employed. Hence period measurement logic is chosen which requires short window

of sampling. The frequency and process variations with respect to temperature

variation is cancelled by two VCOs with current controlling input connected in

opposite as shown in Figure 5.4.

The 100MHz clock frequency of the chip is used for VCO period measurement. The

maximum sensor output is 150mV indicating 2Bar pressure. The required ENOB

for this application is 14bit at the sampling frequency of 100Hz. The minimum input

voltage to be measured is 150mV/214, i.e. approximately 10uV. The minimum VCO

delay that can be measured using 100MHz clock is 10ns. Hence the scale factor of

VCO required is 10ns/10uV change in input voltage. A ring oscillator with 31-stage

delay line is designed for the above purpose. However this circuit is able to achieve

only 1us change for 10mV change. Hence for getting the scale factor of the order of

10us/10mV it requires large number of delay elements in the ring oscillator, hence


realization and characterization is complex. Alternately, VCO frequency scaling is

attempted. The output of the ring oscillator is fed to a divide by N counter. ’N’

can be programmed from the processor based on sampling frequency requirement

and resolution. For minimizing the effect of delay variation due to process variation,

bias and common mode variable parameters of the delay line, two VCOs are used

and the current controlling elements of them are connected in the reverse order. As

a result, output period of one VCO will be increased and other will decrease. By

adding both, bias and other common mode effects will get cancelled.

5.1.1 VCO Data Acquisition scheme

Figure 5.3: VCO Data Acquisiton scheme

VCO’s output frequency variation with input variation is shown in Figure 5.6. and

the variation of the output frequency with process corners is shown in 5.7.

VCO has two modes of acquisition - time mode and frequency mode. The mode

selection can be controlled by the processor.

• Time mode acquisition : In this mode, the sample and hold circuit will be

periodically kept in the hold mode during the conversion period. Figure 5.3

describes the VCO data acquisition timing. The number of system clock cy-

cles in the positive and negative cycles of VCO are counted continuously. T

indicates the time period during which the measurement has been done using


Figure 5.4: VCO Block Diagram

Figure 5.5: VCO Layout

clock. TA and TB shows the sub clock period which cannot be measured by

clock using VCO measurement scheme.

• Frequency mode acquisition : As discussed earlier, the frequency mode mea-

surement require larger time window for meeting the required resolution. Hence

for the systems requiring lower band width, higher resolution can be provided


Figure 5.6: VCO Frequency Variation with input voltage

Figure 5.7: VCO Simulated output across corners

by frequency mode measurement. Also, the ADC error during characteriza-

tion in time mode measurement can be compensated by using frequency mode

measurement at the power on. In this mode, VCO pulse frequency for a fixed

time is counted to measure the frequency. The logic is used in the energy and

temperature measurement circuits discussed in the chaptes 7 and 8.

The performance of the VCO is affected by the flicker noise of the transistors in the

ring oscillator. The flicker noise effects in the VCO output in time and frequency

and design procedures for reducing the flicker noise effects are discussed in the [19].

The layout of VCO is done in cadence virtuoso and shown in Figure 5.5


5.2 Vernier Delay Line (VDL)

As discussed earlier, the VCO output period is measured by 100MHz clock. VCO

being asynchronous with system clock, there exists a delay between VCO input rising

edges in the beginning and the end with respect to clock rising edge; say TA and TB,

which cannot be measured using this method. The actual output to be measured is

T + TA + TB.

Figure 5.8: Basic building block of VDL circuit

The concept of VDL based time measurement logic is introduced for this as shown

in Figure 5.9. The measurement of TA and TB is done by using VDL. VCO output

is directly connected to START pin and sampled VCO output with system clock

is connected to STOP pin of the delay element. The START pulse is given as the

D input and STOP pulse as clock to VDL. A positive constant differential delay is

provided between start and stop delay cell of all N stages. So until the STARTN


pulse crosses the STOPN pulse, the output will be in ‘1’ state and later it will be

‘0’ state (Figure 5.10). Hence based on the delay, a thermometer encoded output

pattern will be generated. The differential delay and number of stages is designed

based on the minimum resolution of the delay. The resolution of the delay cell is

250ps. The basic building block of the VDL delayline is shown in Figure 5.8. The

delay line is voltage controlled delay element. The start and stop delay elements

are same, but controlled by different voltage sources. However this delay depends

on temperature and process variation. Hence the actual resolution of the ADC with

VDL is highly dependent on the stability of delay of this delay cell. To nullify the

effect of delay variation, a biasing scheme which constantly tracks the Vernier delay

line delay in close loop is required. The Delay Locked loop is introduced for this

purpose. The top delay line is controlled by DLL bias voltage and BGR and the

bottom delay line is controlled by BGR alone. The layout of VDL is done in cadence

virtuoso and shown in Figure 5.11

Figure 5.9: VDL circuit


Figure 5.10: VDL simulated output

Figure 5.11: VDL Layout

5.3 Sample and Hold

For any sampled data by the analog to digital converter, it is required to hold it

during the conversion process. The sample and hold circuit is shown in Figure 5.12

with a maximum sampling frequency of 5KHz for the ADC. The digital logic will

periodically control the PMOS based on the sampling frequency set on the processor.

Simulation output of the circuit is shown in Figure 5.13. Layout of sample and hold

circuit done using cadence virtuoso is shown in Figure 5.14


Figure 5.12: Sample and Hold Circuit

Figure 5.13: Sample ad Hold simulation

Figure 5.14: Sample and hold Layout


5.4 Band Gap Reference (BGR)

Band gap reference is the reference voltage which is independent of temperature

and supply variation. Band gap reference is designed in this circuit for following

purposes

• Maintaining the Level translator output in the 0.9V common mode swing from

2.5V.

• Bias the vernier delay controlling element.

• Delay locked loop.

• On-chip temperature measurement.

The principle of BGR is based on the cancellation of temperature variation by nul-

lifying the effect using scaled addition of Proportional To Absolute Temperature

(PTAT) and Complementary To Absolute Temperature (CTAT) sources as shown

in the figure 5.15.

The voltage across a diode with a constant current through it behaves as a CTAT

as shown in the equation we know

VD = VT ln(IoIs

) (5.7)

Figure 5.15: VREF generation from PTAT and CTAT


d

dt(VD) = VD − (4 +m)VT − Eg

kT 2= −1.6mV/oc (5.8)

However the VT variation of the transistor is PTAT as shown in the equation

VT =kT

q(5.9)

so

d

dt(VT ) =

k

q(5.10)

In order to make reference voltage constant, both PTAT and CTAT voltages are to

be generated. A PTAT device is implemented with N parallel diodes connected to a

constant current source[5.16].The voltage drop across the diode in this configuration

is

VD = VT ln(I

Is) (5.11)

VD1 = VT ln(I0Is

) (5.12)

Hence VD − VD1 = VT ln(N) is a PTAT device. By making V2 = V1 using pump-

ing equal current to the both arms, PTAT voltage can be measured across resistor.

This can be achieved using a current mirror circuit as shown in Figure 5.17. This

voltage can be measured across R2 by providing additional mirroring as shown in

figure 5.18. PTAT and CTAT is added by connecting the diode (CTAT source) in

series with R2 as shown in figure 5.19. The scaling of PTAT and CTAT is done

by scaling R2, R1 and N. N is taken as 8 in this design. Output voltage scaling

is done by putting R4 from output to Ground as shown in Figure 5.20. The sim-

ulated output voltages VR2(PTAT) , VQ8(CTAT) and reference voltage(VREF) is


shown in Figure 5.21. Figure 5.22 shows the output voltage variation with temper-

ature.approximately 700uV changes in the vref is observed with 125 deg variation

in temperature.

Figure 5.16: Band Gap Reference V1 is CTAT and VR is PTAT

Layout of the band gap reference is shown in Figure 5.23.

Figure 5.17: Current mirror circuit providing equal current to both arms


Figure 5.18: PTAT output VR2 by pumping same current through R1 throughR2

Figure 5.19: Band Gap Reference by adding PTAT and CTAT in series(VR2and VD5)


Figure 5.20: Band Gap Reference using PNP transistor

Figure 5.21: Band Gap Reference Simulation (1)


Figure 5.22: Band Gap Reference Simulation (2)

Figure 5.23: Band Gap Reference circuit Layout


5.5 Design of Level Translator

The input of the chip is a differential signal varying at maximum of 150mV at 2.5V

common mode. The output of this module is interfaced to VCO working with 1.8V.

Hence common mode voltage is to be reduced. The Level translator module reduces

the common mode of the sensor output to around 0.9V, which provides equal bias

supply for PMOS and NMOS current source of VCO delay cell. Here a precision level

translator is designed using a band gap reference, Opamp and differential amplifier.

The Opamp always tries to make the common mode of the differential stage to 0.9V.

Figure 5.24: Level Translator Circuit

The schematics and layout of the level converter circuit is shown in figure 5.24 and

5.27 respectively.The level translator opamp circuit and simulated waveform shown

in figure 5.25 and 5.26.


Figure 5.25: Level Converter opamp

Figure 5.26: Level Translator Simulated Output


Figure 5.27: Level Translator Layout


5.6 Design of Delay Locked Loop

The function of delay locked loop circuit in this design is to stabilize the delay

variation of the two delay lines in the VDL used in the ADC with respect to PVT.

One of the 32 stage vernier delay line is used for the Delay locked loop. As we are

measuring the sub resolution of 10ns, 32 stages should provide 10ns delay. The 10ns

delay is introduced between START and STOP using digital logic. System clock is

divided by two using a flip flop to obtain the START pulse. The inverse of START

pulse is the STOP pulse. The STOP delay line is controlled by BGR and is constant

irrespective of PVT variation. The START delay line is controlled by DLL output

voltage and BGR voltage. Hence on PVT variation when delay varies, DLL charge

pump output will adjust the Bias voltage (VBIAS P) to make the DLL in locked

state. The block diagram of the delay locked loop is shown in Figure 5.28 below . It

consists of VDL, Phase detector, charge pump and a loop filter. Figure 5.29 shows

the Delay locked loop model. Figure 5.30 and 5.31 shows the DLL Locking, DLL

bias, Locking between DLL and PFD respectively. Figure 5.32 shows the model of

the delay locked loop.

Figure 5.28: Block diagram of DLL

Figure 5.29: DLL model


Figure 5.30: DLL in locking state

Figure 5.31: DLL loop filter output build up

Figure 5.32: DLL Layout

The performance comparison of the VDL with and without DLL is shown in Figure

5.33 and 5.34 respectively.The VDL delay varies from 13ns to 5ns when the temper-

ature change from 0 to 125 degree.However the Delay locked loop VDL maintains

the delay with 250ps for the same temperature variation.


Figure 5.33: VDL Delay with temperature

Figure 5.34: Performance comparison DLL locked VDL and VDL with temper-ature

5.6.1 Design of Phase detector circuit

A phase detector generates an output signal that is proportional to the phase differ-

ence of two inputs. A D flip flop based phase detector is implemented as shown in

Figure 5.35. The simulated output for the input clock leading, lagging and locked

are shown in the Figure 5.37, 5.38 and 5.39. The layout is shown in Figure 5.36


Figure 5.35: PFD

Figure 5.36: Phase detector


Figure 5.37: Phase detector output Ref clock locking

Figure 5.38: Phase detector output Ref clock leading

Figure 5.39: Phase detector output Ref clock lagging


5.6.2 Design of Charge Pump circuit

The function of the charge pump is to convert the Delay variation to a proportional

voltage for closed loop control. This delay line provides delay to attain phase lock

between reference clock and input clock. The first stage of charge pump is current

mirror stage, which decides the current flow and the second stage is the drive stage,

which source or sink the current to loop filter. The circuit is designed for 10uA of

current. The W/L ratios of the transistors were designed based on this. Figure 5.40

and 5.41 shows the schematics and layout of the charge pump.

Figure 5.40: Charge Pump Schematics


Figure 5.41: Charge Pump Layout

5.6.3 Design of Loop filter

The function of the loop filter is to convert error current into control voltage. Integral

control is normally recommended for delay locked loop. Typically uses a capacitor

as the loop filter. Figure 5.42 shows the circuit.

∆Vctrl(s)

Ipd(s)=KI

s=

1

sC(5.13)

Figure 5.42: Loop filter circuit

Chapter 6

Wireless Transceiver

Figure 6.1 details the internal blocks in the proposed wireless Transceiver. Major

blocks are

• Low noise amplifier

• Envelope detector

• Baseband amplifier

• Comparator

• UART Transceiver

• Back scatter transmitter

• Matching network

• Processor

It consists of a matching network for the impedance matching of the antennae.

The matching network is connected to a Low noise amplifier (LNA) which provides

sufficient gain to weak RF signal. The Envelope detector will convert the 2.4GHz

49

Chapter 6. Wireless Transceiver 50

Figure 6.1: Wireless Transceiver Block Diagram

RF signal to base band signal.The digital communication used here is Amplitude

Shift keying (ASK), in which data bits are encoded in UART protocol. The ASK

protocol allows to demodulate RF signal without using energy consuming oscillator

and mixer blocks and UART encoding will help to decode the baseband signal reusing

the existing logic. The envelope detector output is further amplified by a base band

amplifier and the compactor converts the amplifier pulses to sequence of 0’s and

1’s. This is taken by the UART receiver which feeds the stream to processor. An

interrupt is generated whenever UART receiver is ready to send data to processor.

Processed data will be send sequentially by the UART transmitter to the Back

scatter Transmitter unit and further to the matching network.The pictorial view of

the Wireless Receiver output on various blocks is shown in Figure 6.2.

6.1 Receiver power computation

The received power on an antennae when the transmitter sends maximum EIRP

power is given by

Pr(effective) =EIRP.Gr.λ

2

4.π.r2(6.1)


where λ is wavelength, EIRP is the effective isotropic power, Gr is the gain of

the receiver antennae. For a gain of 1.64, 4W EIRP Power at 10m distance, the

received power of an antennae is 7uW. Based on the received input power gain, gain

scheduling has to be done for various blocks. Voltage across the antennae for input

power of 100nW (ie 1/70), if matched perfectly, is 2mV. Hence overall gain of 900

is provided by various blocks to the converted digital domain. A gain of 5000 has

been provided here considering all loss factor. The gain scheduling of the various

blocks are as given in table

Table 6.1: Gain scheduling

Module Gain

LNA 10

Envelope detector 0.7

Base band amplifier 50

Comparator 100

Figure 6.2: Wireless Receiver Outputs


6.2 Design of Low Noise Amplifier

Figure 6.3: Low Noise Amplifier

Cascode LNA structure with common source amplifier Q4 and Common gate ampli-

fier Q3 is used in this design. The L1 and C3 forms the tuned circuit for 2.4GHz ISM

band. L2 is the degenerative inductor, C4, L3, C2 and L2 were used for the input

matching of Antennae impedance. The NMOS current mirror Q1 is used to bias

the Q3 current source. Q2 and R2 forms the input biasing for the common source

amplifier. RF components in the PDK are used for the LNA design. The circuit

is working with 3mA current with 18dB gain. Figure 6.3 shows the schematics.The

S21, S11 plots are given in the Figure 6.4 and 6.5 respectively. Figure 6.6 6.76 and

6.8 shows the simulated time domain output,noise figure and IIP3 plots. The layout

of the LNA is shown in Figure 6.9


Figure 6.4: S12 plot

Figure 6.5: S11 plot

Figure 6.6: Simulated Low Noise Amplifier output


Figure 6.7: Noise Figure of the LNA

Figure 6.8: IIP3


Figure 6.9: Low Noise Amplifier


6.3 Envelope Detector

The envelope of the ASK signal is extracted using an envelope detector. A 4-stage

simple voltage doubler architecture based envelope detector presented in the pa-

per[17] used in this design. The NMOS ZERO VT transistor from the UMC180nm

is used for this purpose. Since the Vt of the transistor is near to zero, it will provide

very good rectification efficiency. Figure 6.10 shows the envelope detector block dia-

gram. Figure 6.11 shows the 4 stage voltage multiplier. Figure 6.12 and 6.13 shows

the single stage voltage multiplier during on and off stage. Figure 6.14 shows the

envelope detector simulated output. Figure 6.15 shows the layout.

Figure 6.10: Envelope Detector Block diagram

Figure 6.11: Four stage voltage multiplier[17]


Figure 6.12: Voltage multiplier Equivalent during Off stage[17]

Figure 6.13: Voltage multiplier Equivalent during On[17]

Figure 6.14: Envelope Detector Output

Figure 6.15: Envelope Detector Layout


6.4 Base band amplifier

The function of the base band amplifier is to enhance the signal level of the de-

modulated RF signal.The base band amplifier is a two stage amplifier as shown in

Figure 6.16. The sizing of the transistor is done using gm/id method. 6.18 showing

the layout. Figure 6.17 showing Frequency response of the amplifier. Amplifier is

having 31dB gain and corner frequency is at 8MHz.

Figure 6.16: Baseband Amplifier circuit


Figure 6.17: Baseband Amplifier circuit

Figure 6.18: Baseband Amplifier Layout

6.5 Comparator

The purpose of the comparator is to convert the analog output from the amplifier

to digital format to interface to the processor. The input of the RF receiver is


expected to ASK encoded UART digital data. Hence the comparator output will be

UART data. The circuit is simple differential amplifier connection with an inverter

in the output stage. The output of the comparator is inverted and fed to the UART

Receiver. Figures 6.19, 6.20, 6.21 shows the comparator circuit, layout and simulated

output.

Figure 6.19: Comparator Circuit

Figure 6.20: Comparator Layout


Figure 6.21: Comparator Simulated output

6.6 Integrated Simulation

The simulation has been done by feeding 1mV (approximately 20nW of power from

the RF receiver) input to the LNA. Figure 6.22 shows the output at various stages

of the wireless receiver.

Figure 6.22: Integrated simulated output with 1 mV input


6.7 Back Scatter Transmitter

The back scatter modulator can be visualized as a switch which will turn on and

off based on the modulating signal. The effect of turning on and off the impedance

across the antenna terminals makes the scatter aperture to vary and thus the power

Ps reflected by antennae. Figure 6.23, 6.24 and 6.25 shows the reflected and trans-

mitted power with open, matched and shorted impedance matching. Figure 6.26

shows the back circuit with modulator switch. Figure 6.27 shows the simulated

backscatter output with the open and shorting of impedance in the matching net-

work. Figure 6.27 shows the layout of the back scatter modulator.

Figure 6.23: Backscatter Circuit with open termination[20]

Figure 6.24: Backscatter Circuit with matched termination[20]


Figure 6.25: Backscatter Circuit with shorted termination[20]

Figure 6.26: Backscatter Circuit


Figure 6.27: Backscatter modulation

Figure 6.28: Backscatter Layout

Chapter 7

Energy Measurement Circuit

Energy consumption in digital circuits depends on supply voltage, switching activity,

capacitance and frequency. Reducing the supply voltage can help in minimizing the

dynamic power, but it will increase the leakage power beyond a limit. Hence there

is a trade-off between these parameters hence keeping the energy consumption at

a low profile. To reduce the power consumption, it is necessary to have an energy

monitoring system which can provide accurate data regarding the energy utilization

by the circuit at different stages of operation, based on which dependent parameters

can be set, thereby reducing the overall energy consumption. This section details

such a system, which has been integrated in the chip, for monitoring the energy

consumption and based on which the operating voltage is set. A closed loop control

system ensures that the system always operate at the set voltage.

A low-power data acquisition system requires to operate at Minimum Energy Point

(MEP) to optimize the energy consumption at the operating point. The MEP

works by sensing and tracking a close loop system. The DC-DC converter switch-

ing frequency will be adjusted for the minimum energy measurement. The energy

measurement is a convex function as discussed earlier and hence gradient descent

method is a suitable choice for this. The MEP lowers the voltage until the energy

65

Chapter 7. Energy Measurement Circuit 66

starts reducing. The loop will continue to push the DC-DC converter to work at

MEP. Several researches has been done for the MEP system.

The system consists of a DC-DC converter, energy tracking loop and the digital

load whose power consumption has to be minimized. In [22], a closed loop energy

minimum energy scheme is reported. In this scheme, MEP is achieved by turning

of the DC-DC converter during energy sensing. Let the voltage across the load

capacitor(C) V1 reduced to V2 during N cycles of operation. The energy consumed is

computed by (Cload∗(V 21 −V 2

2 ))/2N and is approximated as (Cload∗2V1(V1−V2))/2N

for small differences of V1 and V2. The circuit for measuring is as shown in Figure

7.1.

Figure 7.1: Circuit for energy measurement[21]

Here the DC-DC converter charges C1 and is disconnected for N cycles of operation.

After N clock cycles, the voltage in C1oad capacitor is sampled across C2. Further

DC-DC converter is connected back to normal mode. The C1 voltage is connected

to the current drain out circuit. The energy consumed during N cycle is same as

the number of clock cycle to drop C1 to C2. This circuit involves a pre-amplifier,

comparator, fixed clock frequency generator, counter and energy computation logic.

Alternatively a new circuit is proposed in [16] where the energy is measured per


operation by keeping Vdroop fixed and computing V1/Nop as a measure of energy.

This is shown in Figure 7.2.

Figure 7.2: Droop detection timing diagram[21]

Figure 7.3: Minimum energy tracking loop block diagram[22]

A new droop detection method uses a counter incrementing logic for a fixed Vdroop.

Two delays chains are available in this circuit. One among them is a ring oscillator

which is powered(VDD) by the capacitor used for the digital load. This delay line

also provides the clock input to the D-flip flop i.e CLK. The second delay line

(Delay chain) provides D-input to the flip flop i.e CLKd. As the energy consumption

increases, CLK delay to the flip flop increases. Until Vdroop reaches a constant value,

CLKd will be sampled high on every rising edge of CLK line as shown in Figure

7.4. The time period during which Y output is low gives the direct measure of the

energy consumption.


Figure 7.4: Energy measurement circuit[22]

In [23], another method has been proposed which has been implemented in this de-

sign. Given below are the details of the implementation in UMC180nm technology

node. Figure 7.5 shows the VCO for energy measurement and Figure 7.6 shows

the block diagram, of energy measurement logic Here the concept of Energy mea-

surement is based on the frequency of the ring oscillator, as we know the output

oscillation frequency of ring oscillator directly depends on the input voltage. Ini-

tially battery is connected to a capacitor and charged full. The entire chip is powered

from the capacitor. As the energy consumption starts, capacitor slowly starts dis-

charging and hence decreases the frequency of oscillation. Frequency variation of

ring oscillator output can be observed during the drain of the capacitor voltage. As

the supply voltage is reduced, energy consumed reduces and hence the digital load

takes more time to drain the same amount of charge from the capacitor. Hence

the time required for a fixed frequency drop increases indicating reduction of energy


consumption.

Figure 7.5: VCO for Energy Measurement

Figure 7.6: Energy Measurement block

Figure 7.7: Frequency variation with capacitor voltage

This measurement can be made at every set voltage and the measured time for

frequency drop can be used to estimate whether energy consumption increases or

decreases. Using a standard energy measurement algorithm we can compute power

consumption of the chip. For the digital circuit under consideration voltage required

ranges from 0.45V (threshold) to 1.8V (supply). Hence the energy measurement

should be done over the entire range. Figure 7.7 shows the energy VCO output with

various supply voltages from 0.6V to 1.8V.

Chapter 8

Temperature measurement Circuit

Temperature measurement circuit is an essential requirement of any data acquisition

system. On-chip temperature measurement is used for

• Getting the vital information about the health of the chip in terms of power

dissipation.

• Performance enhancement of analog subsystems inside the chip which are tem-

perature dependant.

External temperature measurement is used for the following purposes.

• Conversion of sensor output to physical information like altitude computation

from temperature and pressure data.

• It is required for the sensor error compensation where performance of sensor

degrades with temperature.

70

Chapter 8. Temperature measurement Circuit 71

8.1 On-chip Temperature measurement

The working of on-chip temperature measurement scheme is based on the output

frequency variation of the VCO with temperature at a constant input voltage. This

scheme uses the temperature independent voltage reference (BGR) for biasing the

VCO. Hence the frequency variation is dependant only on the the delay variation

with temperature. On chip temperature measurement block diagram is shown in

Figure 8.1. It consists of BGR, VCO, Frequency measurement logic and processor.

Figure 8.1: Temperature measurement block

Figure 8.2: VCO Simulated output across temperature

Figure 8.2 shows variation of VCO output frequency with temperature. We can see

that there is a 500Hz variation with 10oC variation. Frequency acquisition logic will

measure this variation and sends it to processor. The temperature of the chip can

be extracted by simple program inside MSP430.

Chapter 8. Temperature measurement Circuit 72

8.2 Off-chip Temperature measurement

The off-chip temperature measurement is implemented using a VCO. The external

temperature sensor output is given as the input to the temperature VCO. The algo-

rithm for temperature measurement is implemented using openMSP430 processor.

Figure 8.3 shows the measurement block diagram.

Figure 8.3: External Temperature Measurement block

Figure 8.4 shows the frequency variation with respect to voltage. For every 10mV

change in voltage, frequency changes by 1.5KHz. By using commercially available

temperature sensor like LM35[24] whose output voltage change is 10mV/oC, external

temperature measurement can be done with fine accuracy.

Figure 8.4: Frequency variation with external temperature

Chapter 9

Processor and Interface Design

9.1 Processor

openMSP430[25] is a 16 bit processor based on Von Neumann architecture. It has

a single shared memory space for data, program and peripherals. This enables easy

addition of multiple peripherals. It has an inbuilt hardware multiplier, watchdog and

interrupts. Micro controller has a debug interface which provides access to registers

and memory space for real time debugging of the operation. The tool chain for the

micro controller is compatible with MSP430.

The architecture of the processor consists of

• Frontend: This module performs the instruction Fetch and Decode tasks. It

also contains the execution state machine.

• Execution unit: Containing the ALU and the register file, this module executes

the current decoded instruction according to the execution state.

• Serial Debug Interface: Contains all the required logic for standard two-wire

interface following either the UART 8N1 or I2C serial protocol.

73

Chapter 9. Processor and Interface Design 74

• Memory backbone: This block performs a simple arbitration between the fron-

tend, execution-unit, DMA and Serial-Debug interfaces for program, data and

peripheral memory accesses.

• Basic Clock Module: Generates MCLK, ACLK, SMCLK and manage the low

power modes.

• SFRs: The Special Function Registers block contains diverse configuration

registers (NMI, Watchdog, ...).

• Watchdog: Although it is a peripheral, the watchdog is directly included in

the core because of its tight links with the NMI interrupts and the PUC reset

generation.

9.2 Peripheral Interface

The protocol between the openMSP430 core and its peripherals is exactly same as

all peripherals for write access. The read access of the program and data memory is

slightly different with other peripherals. The read data bus of all peripherals should

be ORed together before being connected to the core, as showed in the Figure 9.1.

The signal description for peripheral interface

• PER EN: when this signal is active, read access are executed during the current

MCLK cycle while write access will be executed with the next MCLK rising

edge.

• PER ADDR: Peripheral register address of the 16 bit word which is going to

be accessed.

• PER DOUT: The peripheral output word will be updated with every valid

read/write access, it will be set to 0 otherwise.


Figure 9.1: openMSP connection diagram with peripherals[24]

• PER WE: This signal selects which byte should be written during a valid

access.

• PER WEN[0] will activate a write on the lower byte, PER WEN[1] a write on

the upper byte.

• PER DIN: the peripheral input word will be written with the valid write access

according to the PER WEN value.

9.2.1 Interrupts and peripheral mapping

Interrupts Vector Adress Priority Peripheral

RESET N 0xFFFE 15 (highest)

NMI 0xFFFC 14

IRQ[13] 0xFFFA 13 mem err pmem double


IRQ[12] 0xFFF8 12 mem err dmem double

IRQ[11] 0xFFF6 11 mem err pmem single

IRQ[10] 0xFFF4 10

IRQ[9] 0xFFF2 9 mem err dmem single

IRQ[8] 0xFFF0 8 uart received485

IRQ[7] 0xFFEE 7 adc interrupt

IRQ[6] 0xFFEC 6 uart transmitted485

IRQ[5] 0xFFEA 5 uart receivedRF

IRQ[4] 0xFFE8 4 uart transmitted RF

IRQ[3] 0xFFE6 3

IRQ[2] 0xFFE4 2

IRQ[1] 0xFFE2 1

IRQ[0] 0xFFE0 0 (lowest)

Table 9.1: Peripheral Interrupt map

Table 9.1 shows the Peripheral Interrupt map.

9.2.2 ADC interface and Address Mapping

SI

No

Channel Address

1 Channel1-TDC 0x170








9 Channel1-Freq 0x186








16 Channel8-Freq 0x19A

Table 9.2: ADC Address map

Table 9.2 shows the ADC address map.

9.3 PWM interface and Address Mapping

SI

No

Channel Address Function

1 PWM1 0x100 PWM Duty Cycle

1 PWM1 0x102 PWM period

Table 9.3: PWM Address map

Pulse width modulation (PWM) is used to control analog circuits with a processor’s

digital outputs. PWM is used for the duty cycle adjustment for the closed loop

systems like DC-DC converter,temperature controller etc. It can also used for the

waveform generation.Table 9.3 shows the PWM address map.

9.4 UART interface and Address Mapping

SI

No

Channel Address

1 RS485 0x1A0

Table 9.4: UART Address map

UART based serial link is added to the micro controller for transmitting compensated

ADC data to other systems. Protocol for the serial link is 8 bits, no parity and 1


stop bit. LSB is transmitted first. Idle transmit bus is always kept high and hence

a low on the receive signal indicates start of data on the bus. It sends two stop bits

to alert the receiver that the data transmission is complete, and expects at least one

stop bit while receiving.Table 9.4 shows the UART address map.

9.5 RF base band processing interface and Ad-

dress Mapping

SI

No

Channel Address function

1 PWM1 0x1C0

Table 9.5: UART-RF Address map

The RF protocol followed for this design is UART-ASK. Hence demodulated base

band output is processed using additional UART instance(RF UART).The base-

band uart encoded RF signals RF UART is mapped to interrupt vector location.The

UART verilog logic instance will acquire data as and when available and interrupt

the processor when ready.The baudrate of the data transmission is programmable

through processor. Table 9.5 shows the UART RF address map.

9.6 Flash Chip interface and Address Mapping

SI

No

Channel Address Description

1 SPI 0190 addr FMA high

2 SPI 0x192 addr FMA low

3 SPI 0x194 addr FMC

Table 9.6: Flash chip address map


Table 9.6 shows the Flash chip interface address map.

Non volatile memory for storing the program and data is required for running the

program every power on without programming ,Hence the interface to Flash chip is

provided in the SOC using SPI interface logic and interfacing with MSP430 periph-

eral interface.The interface signal for the SPI flash memory is scl,si and so.

9.7 Program and Data memory Interface and Ad-

dress Mapping

The non synthesizable Digital memory library generated from the memory compiler

from the Faraday IP provider is used for the program and data memory. Program

memory is 8Kx22 bit long and data memory is 1K x22 bit long. Each peripheral

data is 16 bit long 6 bits of SECDED parity bits will be added into the logic and

stored in the memory.

Figure 9.2 shows the memory map of openMSP430 processor.

9.7.1 MSP430 MEMORY interface

• DMEM CEN: when this signal is active, the read/write access will be executed

with the next MCLK rising edge.

• DMEM ADDR: Memory address of the 16 bit word which is going to be ac-

cessed.

• DMEM DOUT: the memory output word will be updated with every valid

read/write access.


Figure 9.2: Memory Map[25]

Figure 9.3: Memory Read timing[26]

• DMEM WEN: this signal selects which byte should be written during a valid.

access. DMEM WEN[0] will activate a write on the lower byte, DMEM WEN[1]

a write on the upper byte.

• DMEM DIN: the memory input word will be written with the valid write

access according to the DMEM WEN value.

The interface to program and data memory is similar to generic interface to memory


Figure 9.4: Memory Write timing[26]

provided by the open MSP430 processor.During write and read OEB signal is high

and hence connected to logical high.WEB signal for the memory is same as the WE

signal of the MSP430 interface.CS signal of the memory is the complement of CS

signal logic of the MSP430 interface provided.Figure 9.3 and 9.4 showing read and

write timing of the UMC180nm memory.

9.8 Processor Debug Interface

dbguartrxd/dbguarttxd - This is serial link to program the debug mod ule. Debug

interface has UART and I2C link, from which UART link is selected for this project.

Serial link is configured for 8 bit data length, no parity. Baud rate will be determined

by the core by a sync data that is to be transmitted at the beginning. The procedure

to read/write to a memory/register is : send a command to read/write followed by

the address from which to read/write. If it is a write, the write operation is carried

out. In case of a read, the core sends the data requested over the transmit line.

Operation can be carried out in terms of 8 bits or 16 bits.


9.9 Processor Boot chip Interface

To ensure that the system can start operation at power ON, the program for op-

eration needs to be loaded immediately after self test. The chip contains a volatile

SRAM memory. Hence, a NVRAM or a flash memory needs to be integrated with

it. The program should be transferred to the SRAM after memory self test. For this

purpose, a hardware boot code module is designed as a state machine. It controls

the overall operation of the chip by generating cpu-en, reset-n and dbg-en for the

core. The operation is done in the following phases. Module waits for power on

reset from external. Soon after receiving this, it needs to start memory self test.

dbg-en = 1, cpu-en = 1 and reset-n is given to start memory self test. Once this is

done,core starts memory self test by using the corresponding module.

Wait for memory check done signal and if memory error is reported, raise a signal

and it will stop operation of chip by disabling the cpu-en.

Once memory selftest is over.We can make start load active then load program into

program memory through debug interface.Chip has provided dbg-en control input

Once program is completely loaded we can make program loaded as active.The chip

has two modes of operation

1.Program mode:In program mode whatever program loaded into program memory

is transfered into serial flash through SPI module.The details of module is given

later.We will operate Program mode only for initial operation of chip.In order to

program serial flash

2.Normal mode:The chip normally operates in normal mode.In which program from

serial flash has to be loaded back into Program memory.This transfer also taken care

by SPI module. Once this is complete, dbg-en is made 0, and reset-n is given to

start execution of the processor. Processor will start execution from the reset vector

loaded in the program.


9.10 SECDED Logic

To increase the robustness of the micro controller, Hamming code based SECDED

(Single Error Correction and Double Error Detection) module was added to the

memory. It acts as a wrapper for the memory. The core read/writes 16 bits to the

memory. The SECDED module computes 6 bits of parity from the 16 bit input from

core to generate 22 bits of data, which is written to the memory. Every time data is

read back from the memory, the parity is computed from the data bits, compared to

the parity bits read from the memory to detect errors. In case of a single bit error,the

bit error is corrected and the correct 16 data bits is given to the core.In addition,

an interrupt is raised to correct the wrong data in the memory.In case of a double

bit error, an interrupt is raised to stop the execution of the core. Corresponding

modules of SECDED is added for both the data and program memory.

Parity 0 = xor (D15, D13, D11, D10, D8, D6, D4, D3, D1, D0)

Parity 1 = xor (D13, D12, D10, D9, D6, D5, D3, D2, D0)

Parity 2 = xor (D15, D14, D10, D9, D8, D7, D3, D2, D1)

Parity 3 = xor (D10, D9, D8, D7, D6, D5, D4)

Parity 4 = xor (D15, D14, D13, D12, D11)

Parity 5 = xor (D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13,

D14, D15,Parity0, Parity1, Parity2, Parity3, Parity4)

To ensure health of the memory, program and data, at power ON, a self test module

is added. At power ON, the module uses the debug interface of the core to write

bits to the memory. The process followed is described below. All memory locations

are written with 0. Each memory location is first written with 1 and then the same

memory location is read back. This is continued for the whole memory. At the end

of this, whole memory is written with 1. Each memory location is first written with

0 and then the same memory location is read back. This is continued for the whole

memory. A flag is raised once memory check is done and also in case of error. The

above process ensures that all memory locations can be written with 1 and 0 and also

that once a memory location is written, the same data is retained by the memory.


Once this whole process is completed, core raises a signal ensuring the health of the

memory. This is followed by programming the memory with the actual program

followed by CPU execution. This procedure is commonly called RAM March test.

Chapter 10

Physical Design

Physical design has been carried out UMC180nm mixed mode RF process library.

Analog modules are

• VCO

• VDL

• Level translator

• Sample and Hold

• Delay Locked Loop

• LNA

• Band gap reference

• Envelope Detector

• Base band amplifier

• Comparator

85

Chapter 10. Physical Design 86

Digital modules are

• MSP430 processor and interface modules

• ADC data acquisition modules

• SECDED for program and data memory module

• Serial Flash interface modules

• PWM interface module

• clock generation module

• UART interface module

• Bootchip interface module

Following is the procedure for this chip design

Analog Design

• Schematics design of analog modules

• simulation and performance evaluation

• Layout generation of analog modules using Cadence Virtuoso

• Module level DRC/LVS clearance Calibre

• Post layout simulation and matching with pre-layout performance using calibre

• Generate the Library exchange Format(.lef) of all analog modules using Ab-

stract generation tool.

• Create library(.lib) using Liberty tool. If the design is completely analog

dummy library generation will be sufficient.


Digital Design

• Design digital logic in verilog.

• Create timing constraints File.

• Simulation in NCSIM.

• Synthesize in RTL compiler.

Memory generation

• Generate required memory using memory compiler

Mixed signal Integration

• Create an interface verilog file for Analog library cells,memory and top digital

verilog file.

• Create timing constraints file for the design

• Create a top verilog file for adding IO pad interfaces.

• Synthesize the top verilog.

• Add power pad on the synthesized verilog file

Physical Design

Figure 10.1 shows the physical design flow


Figure 10.1: Physical Design Flow


10.1 Chip Diagram

Figure 10.2: Chip


10.2 Encounter

Figure 10.3: Chip Encounter


Figure 10.4: Layout Encounter View


10.3 Custom Cell Placement with IO

Figure 10.5: Custom library Placement with IO


10.4 IO and Power planner

PIN

No

Designation IOPAD Description Type

RCUT3D 18VESD 1.8V power supply Power

1 AVDDH VCC3ACUTD 3.3V power supply Power

2 AVSS GNDACUTD 3.3V/1.8V ground Ground

3 Ch1 1 in XSIOCUTD Differential sensor input Ch1 High Input

4 Ch1 2 in XSIOCUTD Differential sensor input Ch1 Low Input















19 EVCO POWER XSIOCUTD 3.3V/1.8V Ground supply Ground


21 EVCO GROUND XSIOCUTD 3.3V/1.8V Ground supply Ground

CORNER PAD CORNERD Power/Ground continuity Corner

pad


23 AVSS GNDACUTD 3.3V/1.8V Ground supply Ground

24 RING Out 1 XSIOCUTD Test output from the ring oscillator

1

Ground

25 RING Out 2 XSIOCUTD Test output from the ring oscillator

2

Ground

26 BBOUT pad XSIOCUTD Baseband output pad Ground

27 AVDD CORE XSIOCUTD Analog 1.8V power Power

28 AVSS CORE XSIOCUTD Analog 1.8V ground Ground


29 BGROUT pad XSIOCUTD Band gap reference output Ground

30 DLLOUT PAD XSIOCUTD Delay Locked loop output Ground

31 AVDD CORE XSIOCUTD Analog 1.8V power Power

32 AVSS CORE XSIOCUTD Analog 1.8V ground Ground

33 RFOUT pad XSIOCUTD RFoutput from LNA Ground

34 RFOUT pad XSIOCUTD RF bias monitoring output Ground

35 RFBIAS pad XSIOCUTD 1.8V analog power Ground

36 AVDD CORE XSIOCUTD Analog 1.8V ground Power

37 AVSS CORE XSIOCUTD RF input pad Ground

38 RFIN2 Pad XSIOCUTD RF input pad Power

39 RFIN1 Pad XSIOCUTD 1.8V analog power Power

40 AVDD CORE XSIOCUTD 1.8V analog ground Power

41 AVSS CORE XSIOCUTD 1.8V power supply Power

42 VSS CORE XSIOCUTD 1.8V ground Power

RCUT3D GNDA 1.8V Ground Ground


pad

43 VDD CORE VCCKD 3.3V Power for 1.8V core Power

44 VSS CORE GNDKD Ground for core Power

45 Rx pad XFMD Receiver pad input UART Power

46 Rxbar pad XFMD Not used Power

47 Tx pad YFA28SD Transmit pad for UART Power

48 Txbar pad YFA28SD Transmitbar pad for UART Power

49 VDDO CORE VCC3IOD 3.3V Digital IO power Power

50 VSSO CORE GNDIOD Digital IO Ground Ground

51 VDD CORE VCCKD 1.8V core power Ground

52 VSS CORE GNDKD 1.8V core ground Ground

53 timing error pad YFA28SD 1.8V power supply Power

54 memory error pad YFA28SD Memory error during secded checks Power

55 gpio pad[1] ZFMA28SD MSP430 GPIO-0 Inout

56 gpio pad[0] ZFMA28SD MSP430 GPIO-1 Inout

57 dbg en pad XFMD Debug enable pad for MSP430 Input

58 dbg uart rxd in pad XFMD Debug uart receive pin Input

59 dbg uart txd pad YFA28SD Debug uart transmit pin input

60 Cen pad YFA28SD Chip enable pad Output

61 Sin pad YFA28SD Serial input to Flash chip Output

62 So pad XFMD Serial Output from Flash chip Input


63 sclk pad YFA28SD Serial clock to Flash chip Output


pad

64 VDD CORE VCCKD 1.8V core power Power

65 VSS CORE GNDKD 1.8V core ground Ground

66 VDD CORE VCCKD 1.8V core power Power

67 VSSO CORE GNDIOD Digital IO Ground Ground

68 VDDO CORE VCC3IOD 3.3V Digital IO powe Power

69 pllin pad XFMD Pll input pad Input

70 program loaded pad XFMD Program load enable pad Input

71 start load pad XFMD Start of program load Input

72 poweron reset pad XFMD Power on reset Input

73flash program mode

padXFMD Flash Program mode Input

74 VSSO CORE GNDIOD IO ground Ground

75 VDDO CORE VCC3IOD IO power Power

76 VSS CORE GNDKD Core Ground Ground

77 VDD CORE VCC3KD Core Power Power

78 normal mode pad XFMD Normal mode Input

79 pwm out pad YFA28SD PWM OUTPUT Output

80 VSS CORE GNDKD Core Ground Ground

81 VDD CORE VCCKD Core Power Power

82 VSSO CORE GNDIOD IO ground Ground

83 VDDO CORE VCC3IOD IO power Power

84 VDD CORE VCCKD Core power Power


pad

Table 10.1: Chip Pin out


10.5 Package

The figure 10.6 shows the footprint and mechanical dimension of the package Ce-

ramic Leadless Chip Carrier(CLCC) 84

Figure 10.6: Package

Chapter 11

Conclusion

Low power and light weight subsystems are increasingly getting demanded for Avion-

ics and Defence applications. An ASIC based wireless data acquisition system with

low power and reduced weight particularly suitable for such areas has been designed

and implemented. Physical design of the chip has undergone all the processes us-

ing various IC design softwares. The verification and validation of the designs were

fully carried out. The chip is ready for the tapeout with UMC180nm process. By

adding Energy harvesting features into this ASIC, it will completely avoid the sys-

tem interfaces. This chip can be attached to high performance sensors thereby

enabling wireless interface to main system. As the sensors are electrically isolated,

noise coupling and interference will be greatly reduced. Missions like Human space

programme, distributed sensor data acquisition and performance monitoring during

separation systems will be greatly demanding in the near future. Wireless energy

harvested data acquisition system will be useful for this application. Hence this is a

promising candidate for the high performance system for the future.

97

Chapter 12

References

[1] https://www.sac.gov.in/Vyom/CommNavPayloads.jsp

[2] Space Harness Design Optimization Opportunities on ECSS derating rules Marc

Malagoli, Laurence Cosqueric Astrium Satellite 31 rue des Cosmonautes Z.I. du

Palays 31402 Toulouse Cedex 4 France

[3] Wireless Data Acquisition System for Launch Vehicles Sabooj Ray*, Jeba Arul

Doss, Sheena Abraham,Pradeep N. and S. Prem Kumar Vikram Sarabhai Space

Centre, Trivandrum – 695 022, India

[4] Bhat, K.N. and Nayak, M.M.. (2013). MEMS pressure sensors - An overview of

challenges in technology and packaging. J. ISSS. 2. 39-71.

[5] B. Murmann, “A/D Converter Trends: Power Dissipation, Scaling and Digitally

Assisted Architectures,” IEEE 2008 Custom Integrated Circuits Conference (CICC),

pp. 105-112, Sep. 2008.

[6] Shahrzad Naraghi A “Time-Based Analog To Digital Converters” by dissertation

submitted in partial fulfillment of the requirements for the degree of Doctor of Phi-

losophy (Electrical Engineering) in The University of Michigan.

[7] Battery-Free Cellphone Vamsi Talla, Bryce Kellogg, Shyamnath Gollakota And

Joshua R. Smith, Paul G. Allen School Of Computer Science And Engineering And

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[8] Hoang, D. (2016). Backscattering Wireless-Powered Communications. In D.

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Communication Networks: Architectures, Protocols, and Applications (pp. 217-

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[9] Ambient Backscatter: Wireless Communication Out of Thin Air Vincent Liu,

Aaron Parks, Vamsi Talla, Shyamnath Gollakota, David Wetherall, Joshua R. Smith

SIGCOMM, August 2013

[10] Lu, Xiao Jiang, Hai Niyato, Dusit In Kim, Dong Han, Zhu. (2017). Wireless-

Powered Device-to-Device Communications with Ambient Backscattering: Perfor-

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[11] Bryce Kellogg, Aaron Parks, Shyamnath Gollakota, Joshua R. Smith, and David

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[12] Dinesh Bharadia, Kiran Raj Joshi, Manikanta Kotaru, and Sachin Katti. 2015.

BackFi: High Throughput WiFi Backscatter. SIGCOMM Comput. Commun. Rev.

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[13] Ambuj Varshney, Oliver Harms, Carlos Perez-Penichet, Christian Rohner, Fred-

erik Hermans, and Thiemo Voigt. 2017. LoRea: A Backscatter Architecture that

Achieves a Long Communication Range. In Proceedings of the 15th ACM Con-

ference on Embedded Network Sensor Systems(SenSys ’17), Rasit Eskicioglu (Ed.).

ACM, New York, NY, USA, Article 18, 14 pages.

[14] Vamsi Talla, Mehrdad Hessar, Bryce Kellogg, Ali Najafi, Joshua R. Smith, and

Shyamnath Gollakota. 2017. LoRa Backscatter: Enabling The Vision of Ubiquitous

Connectivity. Proc. ACM Interact. Mob. Wearable Ubiquitous Technol. 1, 3,

Article 105 (September 2017), 24 pages.

[15] K. V. S. Rao, P. V. Nikitin, K. V. S. Rao and P. V. Nikitin, ”Theory and mea-

surement of backscattering from RFID tags,” in IEEE Antennas and Propagation

Magazine, vol. 48, no. 6, pp. 212-218, Dec. 2006.

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[16] U. Karthaus and M. Fischer, ”Fully integrated passive UHF RFID transponder

IC with 16.7-/spl mu/W minimum RF input power,” in IEEE Journal of Solid-State

Circuits, vol. 38, no. 10, pp. 1602-1608, Oct. 2003

[17] M. Tabesh and S. Hamedi-Hagh, ”An efficient 2.4GHz radio frequency identifi-

cation (RFID) in a standard CMOS process,” in Canadian Journal of Electrical and

Computer Engineering, vol. 36, no. 3, pp. 93-101, Summer 2013

[18] K. V. S. Rao, P. V. Nikitin, K. V. S. Rao and P. V. Nikitin, ”Theory and mea-

surement of backscattering from RFID tags,” in IEEE Antennas and Propagation

Magazine, vol. 48, no. 6, pp. 212-218, Dec. 2006

[19]Jitter in Oscillators with 1/f Noise Sources and Application to True RNG for

Cryptography by Chengxin Liu A Dissertation Submitted to the Faculty of the

worcester polytechnic institute in partial fulfillment of the requirements for the De-

gree of Doctor of Philosophy in Electrical Engineering.

[20] RFID Tag Design and Range Improvement By Rijwal Chirammal Ramakrishnan

Thesis submitted to The Faculty of Graduate and Postdoctoral Studies In Electrical

and Computer Engineering Ottawa-Carleton Institute for Electrical and Computer

Engineering School of Electrical Engineering and Computer Science University of

Ottawa Ottawa, Ontario, Canada.

[21]Y. K. Ramadass and A. P. Chandrakasan, ”Minimum Energy Tracking Loop

With Embedded DC–DC Converter Enabling Ultra-Low-Voltage Operation Down

to 250 mV in 65 nm CMOS,” in IEEE Journal of Solid-State Circuits, vol. 43, no.

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[23] Thesis work on ”low power data acquisition system for mems sensors”, Sreejith

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[24] LM35 precision temperature sensor data sheet.

[25]openMSP430 Documentation.

[26] FSA0M A Memaker CompilerOverview 1.0

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[27] https://amleceiiscac.in/indexphp/IEP RTL to GDSII

[28]Top-Down Digital Design Flow-ersion 6.0, October 2011 Alain Vachoux Micro-

electronic Systems Lab STI-IEL-LSM

[29] AMS-Manual -Analog Mixed Signal Labs-cadence Revision 4.0, Developed By

University Support Team Cadence Design Systems, Bangalore

[30]A Tutorial On Advanced Analysis For Cadence Spectre by Rishi Todani

[31]ASIC Lab Manual Developed By University Support Team Cadence Design Sys-

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[32] usage of memaker eda deliverable-faraday

Appendix A

Mixed Signal Chip Design

Mixed signal design flow,The design procedures and advanced simulations described

in [27],[28],[29],[30],[31],[32].

A.1 LEF generation

Library Exchange Format (LEF) is a specification for representing the physical lay-

out of an integrated circuit in an ASCII format. It includes design rules and abstract

information about the cells. It only gives the idea about PR boundary, pin position

and metal layer information of a cell. In this 3 sections are defined, i.e. technology,

site, macros. In the technology part layers, design rules, via definitions and metal

capacitance are defined. In the site, site extension is defined and in the macros

the information about cell description, dimension, layout of pins and blockages and

capacitance are defined. For every technology the layer and the via statements are

different. So for the layer and via, the type of the layer (layer may be routing type,

master slice or overlap), width/pitch and spacing, direction, resistance, capacitance,

and antenna factor are defined.

102

Appendix A. Mixed Signal Chip Design 103

A.2 Lib generation

Lib is basically a timing model contains cell delays, transition, setup and hold time

requirements. liberate tool is used for generating the library file. Look Up table

templates are defined for different parameters like delay, hold, passive energy, re-

covery, removal, setup, with different matrix. For each cell following attributes are

defined:

• Area of cell

• Leakage power

• Capacitance

• Rise and fall capacitance

• Direction of the pin

A.3 Memory Compiler

[26][32]

Each memory compiler is a set of various, parameterized generators. The generators

are:

• Layout Generator : generates an array of custom, pitch-matched leaf cells.

• Schematic Generator Netlister : extracts a netlist which can be used for both

LVS check and functional verification.

• Function Timing Model Generators : for gate level simulation, dynamic/static

timing analysis and synthesis

• Symbol Generator : for schematic capture


• Critical Path Generator ETC : there are many special purpose generators

such as critical path generator used for both circuit design and AC timing

characterization

A.4 Innovus

• Importing the design to encounter/Innovus

Following are the input to the innovus for starting the Physical design in

encounter/Innovus

– Synthesized net list

– Library data of all standard cell/IO pad/Memory etc

– LEF data of Analog Library modules

– Synthesized Timing Constraint’s file

– IO file

• Floor plan

– Setting the Die area

• Placing Analog Library Cells and memory

• Power plan

– Power Ring for Digital core power

– Power Ring for Analog Cells

– Vertical Stripe for power distribution

– Follow pin for standard cells power

– Global Net connection for logical nets to power

• Power route for IO pad(Sroute/Pad pins)


• Power route for Analog Library(Sroute/Block pins)

• Standard cell placement

• Timing Analysis for post placement

• Optimize placement for timing closure(Setup)

• Clock tree synthesis

• Timing checks after Clock tree synthesis

• Optimize CTS for post CTS timing closure(Setup and hold)

• Nano route for net list connection

• Timing verification

• Optimize routing for timing closure(Setup and hold)

• Fill the IO pad with IO filler

• Fill the core area with dummy cells

• Check for DRC and violations

• Generate the GDS file

– Provide the Output GDS file name.GDS

– Provide Streamout file for Encounter

• Generate the Encounter netlist

A snapshot of the GDS export from the innovus/encounter is shown in figure A.1


Figure A.1: GDS export from Innovus

A.5 Virtuoso

• Input the GDS file generated

• Provide The Library to which GDS imported

• Provide the attached technology lib file

• Provide streamin file for GDS import

• Provide the Reference library list having the reference

layout of Analog Lib cells/Memory/Standard cell/IO pad

A snapshot of the GDS import in virtuoso is shown in figure A.2


Figure A.2: GDS import to Virtuoso

A.6 Calibre

1. DRC Verification

• Load the DRC rule file

• Run DRC

2. LVS Verification

• Load the LVS rule file

• Load Verilog file for schematic netlist for digital design

• Load spice file for analog design


• Load Mixed(Spice/Verilog) for mixed signal design

• Run LVS

3. ESD/Antennae Verification

• Load the ESD rule file

• Run DRC

4. PEX Extraction

• Load the PEX rule file

• select the output netlist view for simulation.Calibre view for spectre simula-

tion. Spice for Hspice simulation.

• Run PEX

5. Dummy Fill

• Addition of dummy metal needs to be done for density rule. The script for

the same is provided by the foundry. For this, the final layout needs to be

streamed out and saved as a gds file. The dummy file will be generated by

invoking the terminal

calibre -drc -hier *.dummyrulefile.

The generated dummy file to be merged with original GDS layout to get the

final GDS for the tapeout. DRC,LVS,ESD checks need to be carried out on

the final GDS in chip level for signoff clearance and tapout to foundry.

Documents

LOW POWER WIRELESS DATA ACQUISITION ASIC - IISc · INDIAN INSTITUTE OF SCIENCE, BANGALORE BANGALORE - 560012, INDIA CERTIFICATE This is to certify that the project report entitled