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Sean kim (hskim@ansoft.co.kr)

Application Engineer

Low Noise Amplifier DesignLow Noise Amplifier Designfor the 1900MHz Applicationfor the 1900MHz Application

Ansoft Korea

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introductionintroduction

This presentation was developed for Samsung Electronics train center. They want to Step –by step serenade training material with practical circuit (for the Handset ) : total page is 72.

This low noise amplifier design procedure was optimized to increase amplifier linearity.( e.g IP3 point , IMD, P1 dB )

Selected device is SiGe NPN TR BFP620 which was not included for ADS 1.5 Device Library.

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AgendaAgenda Overall Requirements Amplifier Design Using Harmonica

Low noise amplifier design procedure Device selection Improvement IP3 & Stability (Series negative feedback using inductor) Matching Circuit Design using the Smith Toolthe Smith Tool PCB Layout generation. Simulation & measured data comparison.

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1. Linearity (IMD3, IP3, G1 dB)& DC. Bias consumption (Vce, Ic,)

2. Stability (K, B1)

3. Noise figure(NF,Fmin)

4. Standing wave ratio (VSWR, S11,S22)

Overall RequirementOverall RequirementDesign goal of Low Noise Amplifier

Frequency Range 1900Mhz

Gain(dB) 14dB

NF(dB) 1dB

P1 (dBm) 4dBm

OIP3(dBm) 23dBm

Return loss <10dB

Bias (Vce, Ic)Low power (2V,

8mA)Component

No.~ 12 component

Design Consideration of Low noise Amplifier using Non-linear model.

: the order of priority => Must be trade off other conditions

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Low noise amplifier design procedure Device selection. Package element included nonlinear model construction. Bias circuit decision. Nonlinear Harmonic balance simulation.(P1 dB,IP3) Improvement Stability K & IP3 using inductor. S-parameter extraction Power Gain circle & Noise figure matching using Smith

tool Input Output matching circuit generation Low frequency stability increase Lumped inductor to microstrip line inductor Printed Circuit Board layout using S2A Small signal analysis & Input Output VSWR, K, B1 Nonlinear analysis [Transduce Gain, G1dB, IMD3, IP3,

ACPR, Spurious Emission analysis] Compare to Measured data.

Low noise amplifier designLow noise amplifier design

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Device selection Using Siemens(infineon) SiGe bipolar TR BFP620

Low noise amplifier designLow noise amplifier design

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Improvement IP3 D.C bias consumption was declined that a decrease of ½ (40mw -> 16mW) Consist negative feed back circuit using serial inductor

degeneration.( Gain decrease, IP3 increase) Two Inductor add on each lead frame.

Low noise amplifier designLow noise amplifier design

Turning Inductor

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Low noise amplifier designLow noise amplifier design Improvement Stability K (small signal analysis)

L value of 1.5 nH as changing the inductor value until K value becomes 1.(up to K=1)

L value is 1.5nH, K=1, B1>0 (Unconditional stability) Turn the inductor value.(L value is 1.5nH, IP3 : ~ 23dBm.)

K=1

IP3

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Improvement IP3, decrease Gain simulation Gain decrease 4.5dB and IP3 increase 4 dBm, when

added 1.5nH inductor.

Low noise amplifier designLow noise amplifier design

IP3Emitter inductor added.

VCE=2V, 8mA

VCE=2V, 20mA

GAIN

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Low noise amplifier designLow noise amplifier design Matching circuit design using Smth tools. bias circuit and matching circuit is same topology used.

Serial capacitor and parallel inductor is match network. It also provides a convenient form of DC bias feed-through for the device.

Power gain circle and noise figure circle is used for the good input VSWR.

Power Gain (s-plan) circle and NF circle cross point

GPCS GPCL

14.814.5

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KCS

KCL

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Low noise amplifier designLow noise amplifier design Translate Lumped to Microstrip for PCB board Layout. Input ,Output matching circuit added Bypass Capacitor(0.1uF) is added for the improvement IMD.

Input matching Output matching

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Low noise amplifier designLow noise amplifier design Printed Circuit Board layout using S2A Via is fenced around circuit using S2A. D.C noise bypass Capacitor(10uF) was added.

Filled screen

Unfilled screen

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Low noise amplifier designLow noise amplifier design Serenade layout data was transformed to PADS Power

PCB ascii file format Using to S2A.

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Low noise amplifier designLow noise amplifier design Fabricated Low noise Amplifier PCB board.

1Cm

1Cm

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Low noise amplifier designLow noise amplifier design Compare simulation and measured data.

Fc=(1950MHz) S21:14.6(serenade) 14.16 dB(measured), S12:-17.4(serenade) -

19.17dB(measured) S11:-27 (serenade) -25.4dB (measured), ,S22:-11 (serenade) -7.9dB

(measured)

S21 S11 S22 S12Diff.

(measured)

(measured)

(measured)

(serenade)

(serenade)

(serenade)

(serenade)

(serenade)

(measured)

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Low noise amplifier designLow noise amplifier design Compare simulation and measured data. (Wide range)

NF value is measured 1.1~ 1.2 dB. (0.3 dB increase) => It cause for Q value input matching circuit L, C. IMD3 is measured 51dBc when each tone ouput is 0dBm ,So IP3 is

25.5dBm. ( OIP3 = output power(each tone) +1/2* (IMD3) )

S21 S11 S22 S12

(serenade)

(measured)

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Low noise amplifier designLow noise amplifier design Summary

1. Serenade was used to model the performance of a 1950 MHz DCS band Low noise amplifier.

2. RF single-tone, RF two-tone and digital modulation simulation data were presented.

3. A comparison between simulated and measured performance characteristics of the LNA to be in good agreement.

reference

Gerard Wevers, Infineon Technologies, “A High IIP3 Low Noise Amplifier for 1900 MHz Applications Using the SiGe BFP620 Transistor”