Low-Dropout Linear Regulator - A MarketPlace of Ideas...Low-Dropout Linear Regulator 137 1 20.0U 60.0U 100.0U 140U 180U Time in Secs 9.00 7.00 5.00 3.00 1.00 +8 in Volts Figure 6.5

P1: IML/OVY P2: IML/OVY QC: IML/OVY T1: IML

MHBD017-06 Sandler MHBD017-Sandler-v4.cls November 2, 2005 11:50

Chapter

6Low-Dropout Linear Regulator

Power converters typically have multiple outputs. In some cases, theregulation is good enough, so that postregulation is not required. Inmany applications, the regulation requirement demands the use ofpostregulators for the secondary outputs. Simple three-terminal regu-lators may be used in the vast majority of applications; however, manyapplications are sensitive to the efficiency of the converter. A good ex-ample of this can be seen in the notebook computer and other battery-powered equipment.

The circuit in Fig. 6.1 demonstrates a MOSFET low-dropout regu-lator. The MOSFET is controlled by a TL431 shunt regulator IC. In atypical three-terminal regulator, the use of the MOSFET reduces theminimum input-to-output differential voltage (headroom) from a valueof 1.5 to 2 V to the product of the output current and the MOSFET’son-resistance. It is possible to reduce the headroom requirement to tensof millivolts in many cases. The operation of the circuit is very simpleand straightforward.

The circuit uses the MOSFET as a source follower. This causes thedominant pole to occur at the corner frequency that is created bythe source impedance, 1/Gfs and the output capacitor. A second high-frequency pole exists at the corner frequency that is created by theMOSFET’s Ciss and its driving impedance (the 1-k� resistor in parallelwith the 10-k� bias resistor).

The compensation adds a low-frequency pole and a zero at the dom-inant pole frequency. At low currents, the IRF140 has a Gfs of approx-imately 4 m �. This translates to a source resistance of 0.25 �. Thedominant pole frequency is therefore at

12π (0.25)(33 µF)

= 19,000 Hz

133



134 Chapter Six

R2 10K

V115

R32.49K

R4 5.49K

R58

V(11)+8

V29

X5 IRF140

X6TL431

R61K C1

3.3N

R72.49K

I1PWL

C233U14

2

7 116

3

Figure 6.1 Schematic of a low-dropout regulator.

The zero that is added by the compensation is at a frequency of

12π (2.49k)(3.3 nF)

= 19,000 Hz

Because the bandwidth is relatively low, the high-frequency pole fromCiss is not canceled. If greater bandwidth is necessary, this pole maybe canceled via the placement of a small capacitor across the 5.49-k�

divider resistor.Note that this circuit requires a bias voltage for the MOSFET gate

that is at least several volts greater than the output voltage. In mostpower converters, this bias voltage is available. In cases where the biasvoltage is not available, a CMOS charge pump circuit is often used togenerate it.

The circuit shown in Fig. 6.1 was used to simulate the transient re-sponse, turn-on, headroom, and ripple rejection performance of the low-dropout regulator. The results are shown in Fig. 6.2.

LDO: LOW DROPOUT REGULATOR.AC DEC 10 100HZ 1000KHZ.DC V2 5 10 .1.TRAN 1U 1M 500u UIC.PROBE∗V(11)=+8.PRINT AC V(11) VP(11).PRINT DC V(11).PRINT TRAN V(11)



Low-Dropout Linear Regulator 135

8.097.99<

x

>1

5.50 6.50 7.50 8.50 9.50

V2 in Volts

8.50

7.50

6.50

5.50

4.50

+8

in V

olts

Figure 6.2 Headroom measurement graph.

V1 4 0 15R3 7 0 2.49KR4 7 11 5.49KR5 11 0 8V2 2 0 9 AC 1X5 2 1 11 IRF140X6 6 0 7 TL431R6 1 6 1KC1 3 7 3.3NR7 3 6 2.49KI1 11 0 PWL 0 0 500U 0 510U 2 750U 2+ 760U 0C2 11 0 33UR2 1 4 10K.END

The headroom measurements indicate that the dropout voltage (theminimum voltage across the pass element) at 1 A is 90 mV. The useof a MOSFET with a lower on-resistance will further reduce theheadroom.

Transient Response

The graph in Fig. 6.3 shows the response to a 2-A step load. The circuithas a recovery time of approximately 50 µs and a transient impedanceof 10 m�.



136 Chapter Six

1

550U 650U 750U 850U 950U

Time in Secs

8.40

8.20

8.00

7.80

7.60

+8

in V

olt

Figure 6.3 Response curve generated by a 2-A step change in the load.

1

200 500 1K 2K 5K 10K 20K 50K

FREQUENCY in Hz

20.0

-20.0

-60.0

-100.0

-140

+8v

in d

B (

Vol

ts)

Figure 6.4 Frequency domain ripple rejection analysis results.




1

20.0U 60.0U 100.0U 140U 180U

Time in Secs

9.00

7.00

5.00

3.00

1.00

+8

in V

olts

Figure 6.5 Transient turn-on response of the linear regulator.

Ripple Rejection

The ability of the linear regulator to reject input perturbations (suchas ripple) is shown in Fig. 6.4. This characteristic is equivalent to theCS-0X audio susceptibility requirements of the military standard MIL-STD 461. The ripple rejection is primarily a function of the closed-loopbandwidth of the regulator.

Figure 6.5 shows the transient turn-on response of the linearregulator.

Control Loop Stability

Feedback stability is an important issue for all closed-loop systems. Thesimple modification that has been added to the circuit in Fig. 6.1 (L1,C3) allows us to measure the open-loop gain and phase of the systemwhile the circuit loop is still closed (see Fig. 6.6). This method is verysimilar to the method used by most modern network analyzers, such asthe Veneable and the Hewlett Packard model 3577.

LDO2: LOW DROPOUT.AC DEC 10 100HZ 1MEG.PROBE∗V(8)=+8.PRINT AC V(8) VP(8) V(1) VP(1)V1 7 0 15



138 Chapter Six

R2 3 0 2.49KR3 3 4 5.49KR4 8 0 8V2 2 0 9X1 2 1 8 IRF140X2 5 0 3 TL431R5 1 5 1KC1 6 3 3.3NR6 6 5 2.49KC2 8 0 33UC3 4 9 1L1 8 4 1V3 9 0 AC 1R1 1 7 10K.END

Figure 6.7 shows the Bode plot of the feedback loop. The graph in-dicates a 7.5-kHz bandwidth with a phase margin of nearly 90◦ and again margin of 45 dB.

The simulation results of the MOSFET LDO are very much depen-dent on the accurate representation of the MOSFET Gfs over the oper-ating load current range. In many cases the models provided by manu-facturers (which are also the models included in many SPICE programmodel libraries) may not accurately represent this parameter.

The next example is a similar regulator, designed to provide 2.5-V output at up to 1 A. The simulations were performed with two

R1 10K

V115

R22.49K

R3 5.49K

R48

V(8)+8

V29

X1 IRF140

X2TL431

R51K C1

3.3N

R62.49K

C233U

C31

L11

V3AC

17

2

3 4

8

5

6

9

Figure 6.6 Feedback stability schematic uses a large-value inductor and capacitor to allowclosed-loop measurements.




2

7.50K143M<

x

>

376K-44.8<

x

>

1K 10K 100K

Frequency in Hz

117

27.3

-62.7

-153

-243

Wfm

1

-O

pen

Loop

Gai

n in

dB

(V

olts

)

273

183

93.3

3.28

-86.7

Wfm

2

-P

hase

in D

eg

∆x = 368K ∆y = -45.0

1

Figure 6.7 Bode plot of the feedback loop, node 8.

MOSFET models. The first model is provided by the manufacturerand is available as a “free” download from their Web site. I wrote thesecond MOSFET model using measured data for the device and im-plementing it in a unique MOSFET subcircuit topology. (This modelis included in the new Power IC Library for PSpice, available fromAEi Systems.) The regulator was also constructed so that the correla-tion results between the measured data using the two MOSFET mod-els could be shown. Figure 6.8 shows the schematic of the exampleregulator.

LDO3: LOW DROPOUT.TRAN .1u 1m .5m 1u.PROBE.PRINT TRAN V(3)C3 1 2 100pX1 11 1 3 AEI57230L2 5 3 10pC1 5 6 10pV1 6 0 AC=1R1 4 0 30mV2 11 0 DC=3.3 AC=1C2 3 4 680uI2 3 0 DC=25m PULSE 1m 1 100u .1u .1u 250u 500uV5 16 0 DC=15



140 Chapter Six

11

V23.3

3

4

C2680u I2

25m

16

V515

V_out

1

R715k

2

X4TL431AILP

15

C6470p

R815k

5

R91.2k

L210p

6

C110p

V1

C3220p

R130m

X1AEi57230

Figure 6.8 2.5-V LDO circuit.

R7 16 1 15kX4 1 0 2 TL431AILPC6 1 15 470pR8 15 2 15kR9 2 5 1.2k.END

The models show significantly different responses (see Figs. 6.9 and6.10), with the AEi Systems model being much closer to the measured

Figure 6.9 Measured pulse load responses.




1 v(3) 3 v(3)#b

550.0u 650.0u 750.0u 850.0u 950.0uTime in Secs

2.355

2.455

2.555

2.655

2.755v(

3) in

vol

ts

2.372

2.412

2.452

2.492

2.532

v(3)

#b in

vol

tsP

lot1

3

1

Manufacturer model

AEi Model

Figure 6.10 Simulated pulse load responses, node 3.

response. The only difference between the two simulations is theMOSFET model. Measurements of the MOSFET transconductancewere made at various load currents, and the results were comparedwith the results from the two models. These results are shown below.

Manufacturer Model AEi ModelMeasured Result Results Results

Id(mA) Vgs Reff Gfs Vgs Reff Gfs Vgs Reff Gfs

1 3.25 148.784 0.007 4.44 1 1.000 3.210 156.00 0.0062 3.34 77.243 0.013 4.44 0.645 1.550 3.320 78.300 0.0135 3.45 36.653 0.027 4.45 0.447 2.237 3.470 31.470 0.032

10 3.57 17.257 0.058 4.45 0.351 2.849 3.570 15.820 0.06325 3.7 7.357 0.136 4.45 0.261 3.831 3.720 6.406 0.15650 3.82 3.621 0.276 4.46 0.221 4.525 3.830 3.250 0.308

100 3.93 1.799 0.556 4.46 0.19 5.263 3.940 1.667 0.600200 4.03 0.940 1.064 4.49 0.168 5.952 4.060 0.868 1.152500 4.15 0.449 2.228 4.53 0.149 6.711 4.230 0.383 2.611

Measured and simulated results are shown for loop gain measure-ments at 1-mA and 1-A load currents. These results are shown in Figs.



142 Chapter Six

2

627.2238.4N<

x>

1K 10K 100KFrequency in Hz

40.00

20.00

0

-20.00

-40.00

Gai

n in

dB

(V

olts

)

480.0

360.0

240.0

120.0

0

Pha

se in

Deg

∆x = 0 ∆y = 0

Figure 6.11 Loop gain results (1-mA load).

6.11 and 6.12, respectively. All the simulations use the AEi SystemsMOSFET model.

These results show that the regulator loop gain bandwidth variesfrom approximately 650 Hz at 1 mA to 45 kHz at 1 A, representing amultiplying factor of 69 all because of the MOSFET transconductance.The AEi Systems model proved to be quite accurate over the entire loadcurrent range.

A similar effect exists with bipolar junction transistors (BJTs). Thetransconductance of the BJT device is much more predictable, making ita somewhat simpler simulation. The transconductance of a BJT deviceis

Gfs = 1re + R

where re is defined by Shockley’s relation

re = 26 mVIe

and R is the internal bulk resistance of the emitter. The BJT SPICEmodels are generally very accurate because the model topology is fixed,and there is really only one variable controlling Gfs. The BJT generally

139.82K98.76<

x>

550.5K9.537U<

x>

2

1K 10K 100KFrequency in Hz

480.0

360.0

240.0

120.0

0

Pha

se in

Deg

100.00

60.00

20.00

-20.00

-60.00

Gai

n in

dB

(V

olts

)

∆x = 510.7K ∆y = -98.76

Figure 6.12 Loop gain results (1-A load).




19

V4

5

12

C3680u

R530m

I21

7

R7470

X2TIP32

2 18

R91k

3

16

Q52N2222A

R1168

1

V52.5

V11

L2100p

20

C4100p

V6AC = 1

4

V15

6

R1100k

C2100p

8

V2-5

VCC

VEE

X3FETAMPLGAIN = 1kFT = 10megVOS = 1m

3.30 2.50

0

2.45

2.50 2.50

1.93

1.24

2.50

0

5.

2.50

Figure 6.13 PNP BJT regulator circuit.

results in a higher frequency pole, because of the higher Gfs; however,the MOSFET regulator can operate with a lower input-output differen-tial voltage.

There are also several low-dropout voltage regulators that utilize aPNP transistor or a P-channel MOSFET. These configurations can oftenoperate with a single supply voltage and the BJT version can operatewith an input-output voltage differential as low as a few hundred milli-volts, depending on Vce(sat). An example of a PNP BJT voltage regulatoris shown in Fig. 6.13.

PNPLDO.CIR.AC DEC 20 10 1meg.PROBE.PRINT AC Vdb(5).OPTIONS GMIN=1n



144 Chapter Six

X3 4 2 3 1 8 OPA27BX1 5 7 19 TIP42V1 1 0 DC=-5R1 2 6 10kC2 6 8 1nILoad 5 0 DC=1mV2 3 0 DC=3.3Q2 7 8 9 QN2222AV3 4 0 DC=2.5V4 19 0 DC=3.3C3 5 12 680uR5 12 0 30mR7 19 7 4.7kL2 5 18 100C4 18 20 100V6 20 0 AC=1R9 2 18 1kR11 9 0 100.END

In this case the PNP transistor is driven by a current source (Q5). If welook at the base of Q5 as the control voltage, then the transfer functionfrom Vc to Vout is

Vout ≈ Vc

R11

HfeX2

Zout

where Zout is the impedance of the output capacitor (and its ESR) alongwith the external load impedance. In this configuration the transferfunction is not dependent on the transconductance of the output tran-sistor, but primarily on the Hfe of the output transistor. The transistorHfe is dependent on the load current, the operating temperature, andthe relatively wide initial production tolerances. Nuclear radiation willalso have a significant impact on Hfe.

Driving the output transistor from a voltage rather than a currentchanges the transfer function to

Vout ≈ VcG fs

Zout

which is dependent on the transistor G fs. A final and more complicatedconfiguration using a P-channel MOSFET is shown in Fig. 6.14.

PFETLDO.CIR.AC DEC 20 10 1meg.OPTIONS GMIN=1n.NODESET V(5)=2.5.NODESET V(8)=0.603




.PRINT AC Vdb(5)

.PROBEX3 4 2 3 1 8 OPA27BX1 5 7 19 SI4463DYV1 1 0 DC=-5R1 2 6 10kC2 6 8 1nILoad 5 0 DC=1V2 3 0 DC=3.3Q2 7 8 9 QN2222AV3 4 0 DC=2.5V4 19 0 DC=3.3C3 5 12 680uR5 12 0 30mR7 19 7 4.7kL2 5 18 100C4 18 20 100V6 20 0 AC=1R9 2 18 1k

19

V4

5

12

C3680u

R530m

7

R74.7k

2 18

R91k9

R11100

8

V11

L2100

20

C4100

V6AC = 1

6

R110k

C21n

Q22N2222A

ILoad1

X1SI4463DY

VCC

VEE

4

3

1

X3OPA27

V1

V2

V3

3.30 2.50

0

1.83

2.50 2.50

31.4m

02.500.603

2.50

3.30

-5.00

Figure 6.14 P-channel MOSFET regulator circuit.



146 Chapter Six

1 ph_v(5) 2 db_v(5) 3 vdb11 4 ph_v11

10 100 1k 10k 100k 1MegFrequency in Hz

0

90.0

180

270

360ph

_v(5

), p

h_v1

1 in

deg

rees

-150

-50.0

50.0

150

250

db_v

(5),

vdb

11 in

db(

volts

)P

lot1

2

3

4

1

x = 3.31k hertz, y = 152m db(volts)

x = 3.31k hertz, y = -2.01 degrees

1mA Load

1 Amp Load

x = 316k hertz, y = 146m db(volts)

x = 316k hertz, y = 58.2 degrees

Figure 6.15 P-channel MOSFET regulator loop gain, node 5.

R11 9 0 100.END

Considering the base of Q2 as the control voltage Vc, we can see thatthe current through Q2 is a function of the gate-source voltage requiredto obtain the output current, which is a nonlinear variable. The re ofQ2 is a function of this current and influences the voltage gain of theloop. The relationship is

Vout = VcR7

R11 + re′ Gfs Zout

For clarity I left out the pole created by the input capacitance of theMOSFET, Ciss. By inspection of this equation it is clear that the gainterm is dependent on the operating current of Q2, which is dependent onthe load current, Gfs, and the threshold voltage of the MOSFET. Thereare also two poles, one from Ciss and the other from the output capacitor.The loop gain plots for load currents of 1 mA and 1 A are shown inFig. 6.15. You can see that there is a 3-decade change in bandwidth as aresult of the load current change and also that the circuit is not stableat 1-mA load.




1 vdb11 2 vdb11#a

10 100 1k 10k 100k 1MegFrequency in Hz

-140

-100

-60.0

-20.0

20.0

vdb1

1, v

db1

1#a

in d

b(v

olts

)P

lot1

12

x = 3.23k hertz, y = -5.13 db(volts)

1mA Load

1 Amp Load

x = 3.23k hertz, y = -82.3 db(volts)

Figure 6.16 P-channel MOSFET regulator output impedance.

The poor stability at 1 mA is also evident from the output impedanceof the regulator, shown in Fig. 6.16.

This circuit can be stabilized over a wide operating load current; how-ever, it is important to consider the effects of the MOSFET and thedriving transistor on the overall regulator stability. In any case thevery large variations make it a difficult and certainly less than idealchoice as well as a significant challenge to simulate.

The most common topology of the three-terminal regulator uses anNPN BJT as the output series pass element. Some of the newer de-vices use power MOSFETs, which would then be very similar to theexample shown in Fig. 6.8. The basic structure of the most commonthree-terminal voltage regulator is shown in Fig. 6.17.

The output transistor, Q1, has an effective emitter resistance that isrelated to the emitter current by Shockley’s equation:

re = 26 mVIe

This relationship is valid at low emitter currents, and at higher currentsre is limited by the internal bulk resistances of the transistor as well asany external resistors, such as emitter current-limiting sense resistors.



148 Chapter Six

Q1

OPAMP

D1

Input Output

Adjustment

R3

Figure 6.17 A typical three-terminal regulator.

At very low currents, an upper resistance limit may be imposed dueto the use of a base-emitter resistor. The overall resistance, includingthese limits, is defined by the term Reff.

The effect of this Reff is to combine with the output capacitor, resultingin a frequency pole in the feedback path that is defined by

Fpole = 12π Reff Cout

This frequency pole is in addition to the typical dominant pole compen-sation of the voltage regulator, which results in conditional stabilityof the voltage feedback loop. This additional pole is further compli-cated by the fact that it has a load-dependent corner frequency andalso that it is proportional to load capacitance. Devices may also vary

1

C110u

2

R1220

R23.9k

R32.2k

3

V128 I1

V1IN OUT

ADJUST

X2LM317TI

Figure 6.18 LM317 Three-terminal regulator test circuit.




Figure 6.19 LM317 three-terminal regulator test circuit response.

from manufacturer to manufacturer because the internal feedback loopcharacteristics are generally not specification controlled.

The use of a MOSFET in place of a BJT has a similar effect, butShockley’s equation does not apply. The effective resistance of theMOSFET device is typically much greater than that of the BJT.

An example circuit, shown in Fig. 6.18, was constructed. A 0- to100-mA step load was applied in addition to the 2.2K resistor loadin order to see the effects of the moving frequency pole and the poorresulting phase margin.

LM317TI.cir.TRAN 1u 10m 0 10u.PRINT TRAN V(1).PROBEC1 1 0 10uR1 1 2 220R2 2 0 3.9kR3 1 0 2.2kV1 3 0 DC=28I1 1 0 PULSE 0 .1 2m 1u 1u 5m 10mX2 3 2 1 AEILM317TI.END



150 Chapter Six

1.00m 3.00m 5.00m 7.00m 9.00mTime in Secs

22.0

23.0

24.0

25.0

26.0v1

in v

olts

Plo

t1

1

Figure 6.20 LM317 Three-terminal regulator simulated response.

Figure 6.21 Three-terminal regulator test circuit with 2.2K load.




The measured step load response is shown in Fig. 6.19, and the SPICEmodel simulation result is shown in Fig. 6.20.

Although the models do not agree all that well, both the measuredresult and the simulated result indicate poor stability. The loop gainof the test circuit was measured with only the 2.2K load resistor. Themeasured result is shown in Fig. 6.21.



152

Documents

Low-Dropout Linear Regulator - A MarketPlace of Ideas...Low-Dropout Linear Regulator 137 1 20.0U 60.0U 100.0U 140U 180U Time in Secs 9.00 7.00 5.00 3.00 1.00 +8 in Volts Figure 6.5