Low Current Switching Behavior of IGBT andAssociated Spurious Tripping in Inverters Employing

VCE De-saturation ProtectionVenkatramanan D, Anil Kumar Adapa, Kapil Upamanyu, Vinod John

Department of Electrical EngineeringIndian Institute of Science

Bangalore, Karnataka, IndiaEmail: venkat86ram@ee.iisc.ernet.in, aniladapa@ee.iisc.ernet.in

Abstract—Insulated gate bipolar transistors (IGBT) haveevolved significantly and become exceedingly fast. Today, theirtypical switching speeds are of the order of 100ns. The resultingdvdt

is considerably large and when employed in a variable speedmotor drive inverter, ringing over-voltages occur at the motorterminals even with cable as short as 1 meter in length. Inany such power converter system, protection of IGBT in theevent of a fault is an essential requirement. An effective wayof protection is by detecting IGBT de-saturation, which occursduring device over-current or short-circuit, using sensed collector-emitter voltage (VCE). Several commercial isolated gate-driverICs are available today in the market with integrated VCE de-saturation protection feature. Such a protection scheme whenemployed in a modern IGBT based power converter and usedfor motor drive applications can lead to spurious trips. Thispaper investigates and reports the reasons for such spurious faultsensing by IGBT gate-drivers employed in two-level inverters.The circuit conditions are analyzed and it is shown that theIGBTs essentially act as capacitors while switching low currents.This behavior in combination with other factors such as fastdevice switching times, load power factor, and dead-time, isshown to cause spurious VCE fault trips. Two simple and cost-effective circuit modifications are suggested which ensure thatsuch spurious fault sensing is avoided in power converters.

Keywords—IGBT de-saturation protection, VCE sensing, gate-driver, motor cable, voltage doubling, low-current switching, spuri-ous trips.

I. INTRODUCTION

IGBT based PWM power converters are widely employedtoday in a variety of medium and high power conversionapplications, which typically include adjustable speed motordrives, off-grid or grid-tied renewable energy based DG sys-tems, power quality conditioners, and static UPS systems [1],[2]. IGBTs have themselves evolved considerably over the pastdecade and have become exceedingly fast [3]. Protection ofsuch an IGBT in case of a fault such as load short-circuit,is paramount. A variety of fault diagnostic and protectionschemes for IGBT exist in literature [4]. Protection by detect-ing device de-saturation (DESAT) with the help of sensed VCE

voltage is a popular scheme for identifying faults due to over-current, load short-circuit and dc-bus shoot-through [5], [6].

This work was supported by CPRI, Ministry of Power, Government of India,under the project Power conversion, control, and protection technologies formicrogrid.

Fig. 1: Power circuit schematic of drive system showing three-phase inverter, motor and interconnecting cable.

TABLE I: Drive system ratings

Item Value

Power converter rating 15 kVA

Motor rating 30 hp

Rated dc-bus voltage VDC 680 V

Rated output voltage (l-l RMS) 415 V

Output current (RMS) 23 A

Nominal modulation index ma 1

Switching frequency fsw 10 kHz

Several commercial isolated gate-driver ICs as well as gate-drive boards are available today with integrated VCE DESATprotection feature [7]–[9].

Spurious converter fault trips have been observed to oc-cur consistently in three-level neutral point clamped (NPC)inverters that employ VCE DESAT protection, as reported inliterature [5]. However, studies on spurious trip occurrences intwo-level inverters are rather limited. In this work, it is shownthat spurious VCE DESAT fault trips can occur consistently intwo-level inverters as well, due to reasons distinct from thatpointed out in [5], when a motor load is employed. Fig. 1shows power circuit schematic of experimental setup, where athree-phase PWM inverter powers a 30 hp three-phase squirrel-cage motor. Table. I lists the drive system ratings.

Fig. 2(a) shows three-phase line currents of motor operatingat no load, with 70% inverter dc-bus voltage and modulationindex (ma) of 1. It can be seen that DESAT-fault signalVCE−FLT is asserted by the processor in the course ofoperation during R-phase current zero crossing, even before100% system voltage is reached. It is pointed out that such978-1-4673-8888-7/16/$31.00 c© 2016 IEEE

(a)

(b)

Fig. 2: Motor line currents showing (a) occurrence of spuriousDESAT fault at R-phase current zero-crossing and (b) High-frequency ringing in line current and motor terminal voltagedue to cable voltage-doubling effect.

a fault is spurious in nature and occurs frequently at zero-crossings of the motor phase currents.

The investigations carried out in this work show thatdiverse factors such as fast turn-off times of modern IGBTs,modulation index, load power factor, dc-bus voltage and low-current IGBT switching characteristics play a key role in thespurious fault tripping. To begin with, effects of fast devicetransition times on motor and PWM inverter are explained.Then, the concept of VCE DESAT sensing based protectionis introduced briefly, which is essential for understandingspurious fault sensing. Subsequently, low-current switchingcharacteristics of IGBTs, which is distinct from that duringnominal current switching due to influence of device collector-emitter capacitance, is explained. Experimental results arepresented that illustrate the phenomena, which are used toexplain the root-cause of spurious VCE DESAT fault. Twocost-effective circuit modifications are suggested that can beemployed to avoid such spurious fault tripping. Experimentalresults validating the same are presented followed by conclu-sion.

II. EFFECT OF IGBT TRANSITION TIME

A state-of-the-art IGBT has a switching time that couldbe as low as 100ns [3]. Owing to fast transition time andresultant large dv

dt , even a short cable of 1m length could causevoltage overshoot at the motor terminals due to wave reflectionphenomena [10]. Fig. 2(b) illustrates the voltage excursionsand oscillations occurring at 2.9 MHz on a 30 hp induction

Fig. 3: DESAT protection circuit using HPCL-316J.

(a) (b)

Fig. 4: (a) Standard double-pulse test circuit and (b) Turn-offtransient of IGBT SB during double pulse test at 750V and25A, without complementary pulse command to ST .

motor terminals, for 3m cable length and 100 ns voltagerise time at the inverter end. It can be seen that the motorcurrent also carries a high-frequency oscillatory componentaside from switching ripple and fundamental components.This high-frequency current must be catered to by the powerconverter, and has a bearing on spurious VCE fault at currentzero-crossing.

III. VCE DESATURATION BASED PROTECTION

The concept of VCE DESAT protection is discussed thor-oughly in [6]–[9] and is briefly explained in this section.Fig. 3 shows the DESAT fault detection circuit employed incommercial IC HPCL-316J [11]. DESAT-fault is detected bysensing the voltage across 100 pF blanking capacitor Cblank,which is connected to DESAT pin of IC as well as the IGBTcollector. A fault is declared by the IC when this voltageexceeds an internal reference of 7 V. An internal current sourceof 250 µA is present that continuously tends to charge Cblank.However when IGBT turns on, this voltage is clamped to on-state voltage drop of device, which is 2 V typically. Cblank’svoltage is expected to exceed 7 V only in case of over-currentor IGBT short-circuit condition. It is shown in this work that ifcertain extraneous circuit condition disturbs Cblank’s voltagebeyond 7 V, a spurious fault declaration can occur.

IV. LOW-CURRENT IGBT SWITCHING CHARACTERISTICS

Switching characteristics of IGBT at nominal or rated op-erating conditions is well discussed in literature [12]. Whereas,reports are rather limited for low or near-zero-current switch-ing characteristics of IGBT [13]. It is however important tounderstand the same in the present case, as spurious faultsare observed to occur at current zero-crossings. Fig. 4(a)

(a)

(b)

(c)

Fig. 5: Double-pulse test result at large DUT voltage and near-zero current showing (a) transitions without complementarypulse to ST , (b) transitions with complementary pulse appliedto ST , and (c) transitions at large DUT voltage and zero currentwith complementary pulse applied to ST .

shows standard double-pulse test circuit employed, wheredevice under test (DUT) is bottom IGBT SB . In this work,tests are conducted with complementary gate-pulses appliedto top device ST as well, in contrast to the conventional testprocedure wherein the top device is kept turned off [14]. A1200V, 40A, TO-247 package IGBT is used in this work [15]and Rogowski coil based current probe CWT ultra mini isemployed for measuring device source current, as indicatedby Fig. 4(a).

The typical turn-off switching characteristics of DUT isshown in Fig. 4(b), indicating device voltage VDS,B andcurrent IDS,B profiles at large voltage and current, duringthe second turn-off pulse of the double-pulse test withoutcomplementary pulse applied to ST . It can be seen that thevoltage rise time of the device is about 100ns.

Fig. 5(a) shows switching characteristics of DUT at largevoltage but near-zero current, without complementary pulseto ST . It can be seen that the DUT voltage VDS,B during thefirst turn-off pulse, takes about 1.5µs to reach VDC . During thesecond turn-off pulse, when the switching current is relatively

Fig. 6: Equivalent circuit model of an inverter leg during lowcurrent switching when both devices are turned off.

larger, the DUT takes lesser time of about 600ns to reachVDC , which suggests the actual value of (low) current hasa bearing on voltage rise time. It may be noted that VDS,B

continues rise slowly even after gate voltage VGS,B has fallenbelow 0V, when the electron channel below the gate in thedevice is completely cut-off. This is possible when the devicedrain-source capacitance dominates the switching operationand governs the voltage profile during turn-off.

Fig. 5(b) shows switching characteristics of DUT at largevoltage and near-zero current, but with complementary gate-pulse given to top device ST . The dead-time provided in thepresent case is 750ns. It can be noted that after first turn-offpulse, VDS,B begins to rise slowly, but quickly charges to VDC

as soon as ST is turned-on after the preset dead-time. Also, thecorresponding charging surge current is seen in the measuredIDS,B waveform.

Fig. 5(c) shows switching characteristics of DUT at largevoltage and at zero current, with complementary gate-pulsegiven to top device ST . It can be seen that VDS,B rises quicklyto VDC from 0 V only after ST is turned on. The correspondingcharging surge current is seen in the device current trace. ST

acts as a capacitor and gets charged to VDC during first turn-on command of SB . ST ’s capacitor discharges only when itreceives a turn-on pulse, post to turn-off of SB .

From these experimental observations, it can be surmisedthat the switching behavior of device at low currents is unlikethat during nominal operating conditions. The manifested(slow) device voltage rise profile is not due to extension ofinherent device transition time, but rather due to charging anddischarging of device parasitic capacitances CDS,B and CDS,T

respectively. The device would actually turns off soon after thegate-source voltage VGS,B falls below gate threshold value,as the conducting channel between drain and source due tothe field effect, no longer exists. Fig. 6 shows a capacitiveequivalent circuit model of the inverter leg that can be used toanalyze spurious tripping issue at motor current zero-crossings,where essentially low-current switching of the devices occur.

V. SPURIOUS VCE DESAT FAULT

Few experimental observations are presented in this sectionthat illustrate the behavior of various circuit quantities onmotor and converter side, that lead to a spurious VCE faultdeclaration. It is remarked that fault repeatedly occurs atcurrent zero-crossings, which is captured and presented. Thecapacitor model of the device described in Section IV is usedto explain the observed behavior. Unless indicated otherwise,in all the observations made, dc-bus voltage is 500 V. Sine-triangle PWM technique is employed on the inverter with 750

ns dead-time, ma equals unity and a 15 m cable is employedto connect to the induction motor.

A. Experimental Observations

Fig. 7(a) provides a close-up view of the line-line voltagesat motor and converter sides, at the instant of spurious faultdeclaration. It can be noticed that fault is detected nearcurrent zero-crossing of IR. Also, voltage VRG−INV appearsdisturbed, which coincides with high-frequency oscillationsthat rides over IR due to reasons pointed out in Section II.

Fig. 7(b) provides a zoomed view of R-phase devicevoltages VDS,S1

and VDS,S2along with zero-crossing of motor

line current IR, just prior to fault detection. It can be noticedthat the turning-on of top device S1 during R-phase currentzero-crossing initiates high-frequency oscillation in the same.The oscillations in current continue to exist even after S1 isturned off. During the dead-time period when both devices areoff, the device voltages jitter at high frequency along with linecurrent oscillation following which a fault is declared. Notethat such a jitter can occur only during the dead-time periodwhen both devices are turned-off, since at all other times, gate-voltage drive is present which essentially determine the devicestates and hence their VCE voltages.

The observed jitter during current zero-crossing can beexplained using the capacitor model of inverter leg describedin Section IV and Fig. 8(a). When S1 turns on during currentzero-crossing, the capacitor CS1 is completely discharged andcapacitor CS2 is charged to VDC , as indicated in Fig. 7(b).Alongside this, high-frequency oscillations are initiated aswell, which during the dead-time period and before the subse-quent turn-on of S2, discharge CS2 and charges CS1 and vice-versa alternatively as illustrated by Fig. 8(a), till the oscillationsdie-out. The charging and discharging of device capacitors bythe high-frequency current oscillation is manifested as the jitterin the device collector-emitter voltages in Fig. 7(b).

The device capacitances being very small in value, typicallyranging in few hundred picofarads, are charged and dischargedby the oscillatory current at a rather fast rate, thus causing fastchanges in voltage VCE . The desat-diode DD recommendedin the IC data-sheet is MURS120T3G, which is a ultrafastdiode carrying a junction capacitance CD of about 45pF [16].The recommended value of Cblank is 100pF , for 3µs blankingtime [11]. Fast VCE changes thus results in a capacitive currentbeing injected into Cblank through CD, thereby disturbing thevoltage at DESAT pin as shown in Fig. 8(b). This disturbancecould exceed 7 V, which is sensed by the gate-driver IC anda fault is subsequently declared that is spurious in nature.Fig 9(a) shows the gate-emitter voltages of the devices justprior to spurious DESAT-fault declaration during R-phase cur-rent zero-crossing. The corresponding disturbances occurringin Cblank voltage during the dead-time period prior to turn-onof S2, which is due to high-frequency resonant line currentringing, is illustrated in Fig 9(b).

B. Inference

In essence, when power factor is close to zero, current zero-crossing coincides with phase voltage peak, wherein PWMturn-off pulse width durations are rather small, and particularlyso when modulation index is close to unity. When motor

(a)

(b)

Fig. 7: Spurious VCE fault declaration in R-phase deviceshowing (a) line current zero-crossing and line-line PWMvoltages on converter and motor side and (b) line-current zero-crossing and collector-emitter device voltages of R-phase legjust prior to fault declaration.

(a)

(b)

Fig. 8: (a) Charging and discharging of device capacitancesby high-frequency ringing in R-phase line current during zero-crossing and (b) capacitive charging current disturbing Cblank

voltage in DESAT circuit.

(a)

(b)

Fig. 9: Spurious VCE fault declaration in R-phase deviceshowing (a) gate-emitter device voltages of R-phase leg anddead-time during current zero-crossing, just prior to spuriousfault declaration and (b) disturbance caused in Cblank voltageduring the dead-time period leading to spurious fault detection.

loads are employed, an additional high-frequency resonancecurrent component flows in the line currents due to cableand motor parasitics. Since IGBTs behave like capacitors atthe time of current zero-crossing, the high-frequency currentcomponent causes jitters in device collector-emitter voltagesduring the dead-time periods, as in Fig. 7(b). This jittercorrupts the sensed blanking capacitor Cblank voltage dueto capacitive coupling through junction capacitance of desat-diode. During turn-on command post to dead-time, if Cblank’svoltage happens to exceed 7V due to corruption by rising edgeof VCE jitter, as in Fig 9(b), then a spurious DESAT fault isdeclared.

VI. MITIGATION TECHNIQUES

There are different ways in which the spurious trip issuecan be dealt with. Increasing the device transition timesby increasing gate-resistance or with additional gate-sourcecapacitance would mitigate the high-frequency oscillationsinduced in line current, however this also would increasedevice switching losses and affect the converter efficiency. Useof output filters or dv

dt filters also mitigates the problem of high-frequency ringing in line currents [17]. However, this methodis not only expensive but also an over-design if employedjust for mitigation of spurious trip problem. Experimentalresults show that increasing the dead-time to 2µs or moreappears to eliminate spurious trip occurrence. The reason for

Fig. 10: Experimental setup showing three-phase inverter,controller and 30 hp induction motor.

Fig. 11: Ferrite bead arrangement at the inverter three-phaseoutput lines.

this behavior is that increased dead-time provides additionalroom for oscillations to die down, and hence by the timethe next turn-on pulse arrives, the Cblank voltage is settled.However, increasing dead-time could introduce other issues inmotor loads such as lower order harmonics and sub-harmonicoscillations [18]. In this section, two simple and inexpensivesolutions are presented for addressing the issue of spurioustrip, which are validated through experiments. Fig 10 showsthe experimental setup consisting of three-phase inverter and30hp induction motor.A. Output ferrite beads

Addition of ferrite cores or beads in the output lineseffectively dampens out high-frequency ringing in load current,and thus avoids spurious trips. Note that ferrite cores wouldsaturate at higher values of load current and cease to providedamping, but this is inconsequential to the problem in question,which occurs only at zero-crossings, where the ferrites remainfunctional. Fig. 11 shows the physical arrangement of ferritebeads at the inverter AC output lines. With ferrite-beadsin place, motor operation at 15 kVA power level has beenexperimentally verified through an 8-hour burn-in test withoutspurious trips.

Fig. 12: Modification in de-saturation detection circuit ofHPCL-316J.

Fig. 13: Three-phase motor line currents and line-line voltageVRG at rated inverter operating conditions of 15 kVA duringburn-in test.

B. Filter in DESAT protection circuit

The disturbance in Cblank voltage is caused primarily dueto capacitive coupling between Cblank and device collector,and the capacitive current injected during fast collector-emittervoltage changes. The magnitude of injected current can bedecreased by increasing the resistance in the charging path.An additional resistor RF of 1kΩ and capacitor CF of 100pFin the DESAT-circuit can be used, as indicated in Fig.12.This circuit in effect acts as a low pass filter and preventsexcessive voltage excursions in Cblank. Although the additionof 1kΩ filter resistance in DESAT-circuit is at variance withthe data-sheet recommendation [11], it does not hamper theshort-circuit detection capability of the circuit, which has beenverified experimentally. With filter in place, spurious trips arecompletely eliminated and the same has been experimentallyverified through an 8-hour burn-in test where motor is operatedby the inverter at 15kVA power level, as indicated by Fig.13.

VII. CONCLUSION

Spurious trips have been observed to occur in two-levelpower converters powering motor loads, that employ IGBTde-saturation based fault detection scheme. It was noticedthat the high-frequency resonance component present in themotor line currents, due to fast switching of IGBTs, causedDESAT-fault to occur repeatedly at current zero-crossings.From experimental observations, it has been inferred thatIGBTs behave as capacitors while switching low currents, andthe resonance component of load current causes fast devicevoltage transitions. These transitions are found to corrupt theDESAT sense voltage, due to capacitive coupling through the

DESAT diode’s junction capacitance, and thus result in aspurious DESAT-fault. Two simple and inexpensive mitigationtechniques are suggested that address the problem of inauthen-tic fault detection, which are verified experimentally and areseen to be effective methods to prevent spurious tripping ofthe power converter.

REFERENCES

[1] K. Hatua, A. K. Jain, D. Banerjee, and V. T. Ranganathan, “Activedamping of output LC filter resonance for vector-controlled VSI-fedAC motor drives,” IEEE Trans. Ind. Electron., vol. 59, no. 1, pp. 334–342, Jan 2012.

[2] D. Venkatramanan and V. John, “Integrated higher-order pulse-widthmodulation filter–transformer structure for single-phase static compen-sator,” IET Power Electron., vol. 6, no. 1, pp. 67–77, Jan 2013.

[3] D. Chiola, E. Griebl, and H. Husken, “Fast IGBT and diode tech-nologies achieve platinum efficiency standard in commercial SMPSapplications,” in IEEE 28th Appl. Power Electron. Conf. and Expo.(APEC), Mar 2013, pp. 2461–2465.

[4] B. Lu and S. K. Sharma, “A literature review of IGBT fault diagnosticand protection methods for power inverters,” IEEE Trans. Ind. Applicat.,vol. 45, no. 5, pp. 1770–1777, Sep 2009.

[5] A. K. Jain and V. T. Ranganathan, “Vce sensing for IGBT protectionin NPC three level converters - Causes for spurious trippings and theirelimination,” IEEE Trans. Power Electron., vol. 26, no. 1, pp. 298–307,Jan 2011.

[6] J. N. Khan, “Design considerations in using the inverter gate driveroptocouplers for variable speed motor drives,” White Paper, AvagoTechnologies, Mar 2010.

[7] H. Ruedi and P. Kohli, “Driver solutions for high-voltage IGBTs,” PCIMEurope - Power Electron. Mag., Apr 2002.

[8] “Desaturation fault detection,” Application Note 5324, Avago Technolo-gies, Jan 2012.

[9] “Eicedriver: High voltage gate drive IC,” Application Note, InfineonTechnologies, Jul 2014.

[10] A. von Jouanne, D. A. Rendusara, P. N. Enjeti, and J. W. Gray, “Filteringtechniques to minimize the effect of long motor leads on PWM inverter-fed AC motor drive systems,” IEEE Trans. Ind. Applicat., vol. 32, no. 4,pp. 919–926, Jul 1996.

[11] “HCPL-316J datasheet,” Avago Technologies, last accessed on May2016. [Online]. Available: http://www.avagotech.com

[12] F. Blaabjerg, U. Jaeger, and S. Munk-Nielsen, “Power losses in PWM-VSI inverter using NPT or PT IGBT devices,” IEEE Trans. PowerElectron., vol. 10, no. 3, pp. 358–367, May 1995.

[13] A. Guha, A. Datta, C. R. Babu, and G. Narayanan, “Experimentalinvestigation on switching characteristics of high-current insulated gatebipolar transistors at low currents,” in IEEE 2nd Int. Conf. Elect. EnergySyst. (ICEES), SSN College of Eng., Chennai, India, Jan 2014, pp. 171–176.

[14] D. Xiao, I. Abuishmais, and T. Undeland, “Switching characteristics ofNPT-IGBT power module at different temperatures,” in 14th Int. PowerElectron. and Motion Control Conf. (PEMC), Sep 2010, pp. T1–17–T1–22.

[15] D. Venkataramanan, A. K. Adapa, and V. John, “Design and compar-ative study of discrete and module based IGBT power converters,” inNat. Power Electron. Conf. (NPEC), IIT Bombay, Mumbai, India, Dec2015.

[16] “Datasheet of MURS120T3G,” ON Semiconductor, last accessed onMay 2016. [Online]. Available: http://www.onsemi.com

[17] J. K. Steinke, “Use of an LC filter to achieve a motor-friendly per-formance of the PWM voltage source inverter,” IEEE Trans. EnergyConvers., vol. 14, no. 3, pp. 649–654, Sep 1999.

[18] A. Guha and G. Narayanan, “Small-signal stability analysis of an open-loop induction motor drive including the effect of inverter dead-time,” inIEEE 14th Int. Conf. Power Electron. Drives and Energy Syst. (PEDES),Mumbai, India, Dec 2014, pp. 1–6.