Long Cables Test

Liverpool VELO Workshop

1Guido Gagliardi IPHE Lausanne Liverpool dec.. 2000

Long Cables TestLong Cables Test

Upgrade of SCTA test setupMoved hardware to VELOLAB

Added soft reset to TTC chip in the RB2

One clock from SEQSI drives all boards

40 MHz Read-out

VME BUS

TTCviTTCrx

Seqsi RB2

Hybrid Repeater Board

trigger

Ck

triggertrigger

Ck trigger

data

Ck



SCTA data read-out Short cable


2 chip daisy chain read hybrid “short cable” readout without the Line Equalizer Probing the signal before the ADC

RepeaterBoard

Flat cable Patch box

~50 cm

Bipolar LemoFADC + RB2

No Line Equalizer

~30 cm





Deformed header @ 40 MHz 1 MIP injected



SCTA data read-out Long cable no

equalizer

SCTA data read-out Long cable no

equalizer 60 m cable (see Raymond talk) between the

Repeater Board and the ADC No attempt to recover the signal



SCTA data read-out Long cable


60 m cable Line equalizer Standalone FADC outside of the RB2

RepeaterBoard

Pair of Lemo Patch Panel

~50 cm

Bipolar LemoStandalone FADC

Line Equalizer

~30 cmPatch Panel

60 m





Deformed Header - Repeater Board drivers are too weak

RC behavior after the header (line mismatch?)





Added a buffer stage before the cable Same drivers used in the Raymond tests Header fully recovered - Amplifier chain gain ~ 0.5

RepeaterBoard


~50 cm

Bipolar LemoStandalone FADC

Line Equalizer

~30 cmPatch Panel

60 m

Line Drivers



SCTA data read-out Long cable + RB2


Inserted the FADC into the RB2 Pick up of noise when inserted into RB2


~50 cm

Bipolar LemoFADC + RB2

Line Equalizer

~30 cmPatch Panel

60 m

Line Drivers

RepeaterBoard

Line Drivers

FADC Input





Data seen in the Oscilloscope

Line Drivers

FADC Input

FADC Input

Averaged FADC Input



SCTA read-outRB2

SCTA read-outRB2

Pedestal Check the effect of high frequency noise

Delay scan The RB2 has one 5 bit PDU with 1 ns time resolution Not all the delay settings are allowed

Delay between the RB2 FPGA input register and the FADC

Writing to FIFO a non stable FADC value

Injected charge scan Up to 1 MIP injected charge

Signal to noise ratio, linearity and significance The signal to noise ratio is (<signal> - pedestal) / noise Significance is defined as signal / sigma(signal) and gives an hint of how stable

are the signals



SCTA read-outRB2

SCTA read-outRB2

Pedestal plots are sensible The pedestal sigma is greater

The noise is as usual

Chip 1 Pedestal

0

5

10

15

20

25

30

35

40

45

50

180 184 188 192 196 200 204 208 212 216 220

ADC counts

Fre

qu

en

cy

Mean 196.96Sigma 16.58

Chip 1 Noise

0

5

10

15

20

25

30

35

0 0.8 1.6 2.4 3.2 4 4.8 5.6 6.4 7.2 8

ADC counts

Fre

qu

en

cy

Mean .92Sigma .43



SCTA read-outRB2 - Short cable

SCTA read-outRB2 - Short cable

ADC value vs. PDU delay for half a Mip and 1 Mip injected for one “typical” channel

FADC data instability?

Injected charge 4 time scan

185

190

195

200

205

210

215

220

225

230

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

PDU delay (ns)


190

195

200

205

210

215

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

PDU delay (ns)



SCTA read-out RB2 - Short cable


Signal linearity is good once you selected the proper time slot

ADC vs Charge plateau

190

200

210

220

230

240

250

1 2 3 4 5 6 7 8 9

injected charge

adc

cou

nts

ADC vs Charge edge plateau

190

195

200

205

210

215

220

1 2 3 4 5 6 7 8 9

injected charge

adc

cou

nts





Signal to noise ratio

The signal significance

is greater than 10

over more than 10 ns

1 MIP Signal to noise

0

5

10

15

20

25

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

pdu value

1 MIP Signal significancy

0

5

10

15

20

25

1 3 5 7 9 11 13 15 17 19

pdu delay

sig

nal

/ s

igm

a(s

ign

al)



SCTA read-outRB2 - long cableSCTA read-out

RB2 - long cable ADC value vs. PDU delay for (about) half a Mip and

1 Mip injected


194

196

198

200

202

204

206

208

210

212

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

PDU delay (ns)


190

195

200

205

210

215

220

225

230

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

PDU delay (ns)



SCTA read-out RB2 - Long cable


Signal linearity is like expected from SCTA

Cross check that data are sensible

ADC vs Charge plateau

200

205

210

215

220

225

230

235

1 2 3 4 5 6 7 8 9

injected charge

adc

cou

nts





The signal to noise ratio is 10% less than the one measured with the short cable

gain uncertainty - linearity

The signal significance

is good over ~ 15 ns

The signal slope is

significant

1 MIP Signal significancy

0

5

10

15

20

25

30

1 3 5 7 9 11 13 15 17 19

pdu delay

sig

nal

/ s

igm

a(s

ign

al)

1 MIP Signal to noise

-5

0

5

10

15

20

25

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

pdu value



ConclusionsConclusions

First measurements of SCTA at 40 MHz highlighted some limits of the system

Weak line driver in the repeater board

Pick up noise into the RB2

RC behavior

Reduced PDU delay range

The showed results are “typical”… Some problems with many channels, PDU delays, timing of the system indeed.

Some check still to do

Data are there, however It is possible to read data with long cables

The chosen cable is not the best on the market...

The line equalizer can be even better optimized

End of exerciseCross talk

Signal to noise for a particle (laser)

Resolution (difficult to do without a beam…)

Documents

Long Cables Test