COMP103 – L11 Fast Logic.1

COMP 103

Lecture 11

Logical Effort for Sizing Complex Gates

Chapter 6pp. 251-256

[All lecture notes are adapted from Mary Jane Irwin, Penn State, which were adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

COMP103 – L11 Fast Logic.2

Fast Networks: Back of the envelope calculation The optimum fan-out for a chain of N inverters driving a load CL is

f = √(CL/Cin) = √F

Also, we learned that a fan-out of 3.6 per stage is desirable

For Complex Logic, it is reasonable: maintain a fan-out of 4 for other types of logic.

N N

0

1

2

3

4

5

6

7

1 1.5 2 2.5 3 3.5 4 4.5 5f

norm

a liz

e d d

e lay

2.5

3

3.5

4

4.5

5

0 0.5 1 1.5 2 2.5 3γ

f opt

f = e (1+ γ/f)

COMP103 – L11 Fast Logic.3

A More Systematic Approach Can the same approach that utilizes Cext, Cint, and Cg be used for any combinational circuit?

For a complex gate, we expand the inverter equation

tp = tp0 (1 + Cext/ γCg) = tp0 (1 + f/γ)to

tp = tp0 (p + g f/γ)

tp0 is the intrinsic delay of an inverterp is the ratio of the instrinsic (unloaded) delay of the complex gate and a simple inverter (a function of the gate topology and layout style)f is the effective fan-out (Cext/Cg) – also called the electrical effort

COMP103 – L11 Fast Logic.4

Intrinsic Delay Term, pThe more involved the structure of the complex gate, the higher the intrinsic delay compared to an inverter

n 2n-1XOR, XNOR2nn-way muxnn-input NORnn-input NAND1InverterpGate Type

Ignoring second order effects such as internal node capacitances

COMP103 – L11 Fast Logic.5

Logical Effort Term, gg represents the fact that, for a given load, complex gates have to work harder than an inverter to produce a similar (speed) response

the logical effort of a gate tells how much worse it is at producing an output current than an inverter (how much more input capacitance a gate presents to deliver it same output current)

2(2n+1)/3(n+2)/3

4

122

7/35/3

3

42

5/34/3

21

XORmuxNOR

NAND1Inverter

g (for 1 to 4 input gates)Gate Type

COMP103 – L11 Fast Logic.6

Example of Logical EffortAssuming a pmos/nmos ratio of 2, the input capacitance of a minimum-sized inverter is three times the gate capacitance of a minimum-sized nmos (Cunit)

A + B

A

B

A B

A

B

A • B

A B

AA

A

COMP103 – L11 Fast Logic.7

Delay as a Function of Fan-Out

The slope of the line is the logical effort of the gate

The y-axis intercept is the intrinsic delay

0

1

2

3

4

5

6

7

0 1 2 3 4 5

norm

aliz

ed d

elay

fan-out f

NAND2: g=4/3, p

= 2

INV: g=1, p=1

intrinsic delay

effort delayCan adjust the delay by adjusting the effective fan-out (by sizing) or by choosing a gate with a different logical effort

Gate effort: h = fg

COMP103 – L11 Fast Logic.8

Path Delay of Complex Logic Gate NetworkTotal path delay through a combinational logic block

tp = ∑ tp,j = tp0 ∑(pj + (fj gj)/γ )

So, the minimum delay through the path determines that each stage should bear the same gate effort

f1g1 = f2g2 = . . . = fNgN

Consider optimizing the delay through the logic network

how do we determine a, b, and c sizes?

1a b c

CL5

COMP103 – L11 Fast Logic.9

Path Delay Equation DerivationThe path logical effort, G = ∏ gi

And the path effective fan-out (path electrical effort) is F = CL/g1

The branching effort accounts for fan-out to other gates in the network

b = (Con-path + Coff-path)/Con-path

The path branching effort is then B = ∏ bi

And the total path effort is then H = GFB

So, the minimum delay through the path is

D = tp0 ( ∑pj + (N √H)/ γ)N