A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon,9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging

K. Mistry, C. Allen, C. Auth, B. Beattie, D. Bergstrom, M. Bost, M. Brazier, M. Buehler, A. Cappellani, R. Chau*, C.-H. Choi,G. Ding, K. Fischer, T. Ghani, R. Grover, W. Han, D. Hanken, M. Hattendorf, J. He#, J. Hicks , R. Huessner, D. Ingerly,

P. Jain, R. James, L. Jong, S. Joshi, C. Kenyon, K. Kuhn, K. Lee, H. Liu, J. Maiz#, B. McIntyre, P. Moon, J. Neirynck, S. Pae,C. Parker, D. Parsons, C. Prasad#, L. Pipes, M. Prince, P. Ranade, T. Reynolds, J. Sandford, L. Shifren°, J. Sebastian, J. Seiple,

D. Simon, S. Sivakumar, P. Smith, C. Thomas, T. Troeger, P. Vandervoorn, S. Williams, K. Zawadzki

Logic Technology Development, *Components Research, #QRE, OOTCAD, Intel Corp., Hillsboro, OR, U.S.A.

ABSTRACTA 45nm logic technology is described that for the first time

incorporates high-k ± metal gate transistors in a high volumemanufacturing process. The transistors feature 1 .Onm BOT6high-k gate dielectric, dual band edge workfunction metalgates and third generation strained silicon, resulting in thehighest drive currents yet reported for NMOS and PMOS.The technology also features trench contact based localrouting, 9 layers of copper interconnect with low-k ILD, lowcost 1 93nm dry patterning, and 1000o Pb-free packaging.Process yield, performance and reliability are demonstratedon 153Mb SRAM arrays with SRAM cell size of 0.346gtm2, Fig. 2 TEM of High-k + Metal Gate transistor stackand on multiple microprocessors. KEY DESIGN RULES & TECHNOLOGY FEATURES

INTRODUCTION TABLE I summarizes key design rules & layer thicknesses.Since the advent of MOS devices over 40 years ago, Contacted gate pitch - a key measure of front end density - is

SiO2 has served as the transistor gate insulator of choice. scaled to 160nm, maintaining 0.7x scaling trend (Fig. 3). ThisElectrical oxide thickness (Tox(e)) was scaled at -0.7x per is the most aggressive CGP reported for 45nm highgeneration up to the 130nm node, but scaling slowed at the performance logic technologies. Conventional contacts have90nm and 65nm nodes as SiO2 ran out of atoms and gate been replaced with trench contacts for lower series resistance.leakage power limited further scaling (Fig. 1). High-k gate Trench contact based local routing improves layout density,dielectric materials have held the promise of continued especially for cross-coupled inverter pairs that are veryscaling at low gate leakage. Many challenges with high-k common in microprocessor SRAM and register file arrays.integration have included VT pinning, mobility degradation Tight pitches and trench contacts allow SRAM cell size to bedue to soft optical phonons, and poor reliability [1-3]. Metal scaled to 0.346gm2 (Fig. 4).gate electrodes not only eliminate the poly depletion effect, Innovative processes for 0.92NA 193nm dry patterningbut enable high-k dielectrics by screening the SO phonons allow for low cost & robust patterning, as demonstrated bythat cause mobility degradation [4]. High performance high-k the fidelity of the poly lines in Fig. 4. Metal gate materials are+ metal gate transistors have been demonstrated using band chosen with optimal workfunctions for NMOS and PMOSedge workfunction metal gate electrodes [5]. However, performance. The transistor process flow, described next, ischallenges have remained in finding a compatible integration chosen so as to maintain the workfunction ofthe metal gates.scheme that addresses thermal budget concerns. In this work TABLE I: Layer Pitch, thickness and aspect ratiohigh-k + metal gate integration challenges are overcome (Fig. l2), enabling a return to 0.7X Tox(e) scaling while Layer Pitch(nm) Thick(nm) AspectRatiosimultaneously reducing gate leakage >25X. Isolation 200 200

10 1000 Contacted Gate Pitch 160 60

10 |Metal 1 160 144 1.8E 100 _

Metal2 160 144 1.810 Metal 3 160 144 1.8

Metal 4 240 216 1.8Metal 5 280 252 1.8

_ 0.1t Metal 6 360 324 1.8/ ~~~~~~Metal7 560 504 1.8

1 l l|1 0.01 Mea1 810 72 1.8350nm 250nm 180nm 130nm 90nm 65nm 45nm Mtl| 81 72 1.

Fig. I Intel scaling trend for Inversion electrical Tox Mtl93.tm 2~m .

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10000 10 STI, Wells, and VT Implants

SRAM Cell Area ALD deposition of high-k gate dielectric- ~~~~~~~~~0.5xevery 2 years N

0.5x every 2 years Polysilicon deposition and gate patterning

S/D extensions, spacer, Si Recess & SiGe deposition*~1000

° < 0 O t S/D Formation, Ni Salicidation, ILDO Deposition

Poly Opening Polish, Poly RemovalContacted Gate Pitch n

(- 0.7x every 2 years PMOS workfunction metal deposition

100 - l l l l l - 0.1 Metal gate patterning, NMOS WF metal deposition250nm 180nm 130nm 90nm 65nm 45nm

Technology Node Metal gate fill and polish, ESL deposition

Fig. 3 Intel contacted gate pitch and SRAM cell scaling trend Fig.5 Transistor process flow highlighting differences from [6,7]

Fig. 4 Diffusion and poly layers of 0.346 urM2 6-T SRAM cell

TRANSISTOR PROCESS FLOWStrained silicon mobility enhancement techniques have Fig.6 TEM micrograph of high-k + metal gate PMOS transistor.

dramatically improved transistor performance recently [6-8]. 100In this work, we further enhance the strained silicon SiON/Poly 65nm[7]

a) 10techniques we first introduced at the 90nm and 65nm nodes. m 0A key challenge was to simultaneously integrate high-k gate \dielectrics, optimal workfunction metal gate electrodes and

aSiON/Poly 65nm[7]

highly strained silicon channels. Transistors feature 160nm , 0.1gate pitch, 35nm physical gate length, hafnium-based 1.Onm 0.01\EOT high-k gate dielectric, dual workfunction metal gate *electrodes, enhanced channel strain, ultra shallow junctions & E 0.001 HiK+MG 45nm HiK+MG 45nmnickel silicide. z 0.0001-

Fig. 5 describes the transistor formation process, which - PMOS NMOSfeatures high-k first and metal gate last. The process flow up 0.000 -to and including salicidation is similar to 9m and 65m -1.2 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 1.2[6,7], except that SiO2 growth is replaced by hafnium-based VGS (V)high-k gate dielectric formation using atomic layer deposition. Fig.7 HiK+MG enables 25-100OX gate leakage reduction.After ILDO deposition, a polish step exposes poly gates and 0.50the dummy poly is removed. The PMOS workfunction metal 0.45is deposited. A patterning step removes the PMOS metal 0.40 IVDS1=0.06Vfrom NMOS areas and the NMOS workfunction metal is 5 0. X *%81%00deposited. Gate trenches are filled with Al for low gate 0.30 c, oresistance; innovative techniques allow robust gapfill down to >0.25630nm gate length. Finally, the gate trenches are planarized 0via a metal polish step, followed by contact etch stop layer n 0deposition. Fig.6 shows a TEM of the high-k/metal gate f 0 15PMOS transistors with SiGe strain layer and Ni salicide. 0.0vDS=1

TRANSISTOR CHARACTERISTICS _________________

High-k ± metal gate provides dramatic gate leakage 0.030 0.035 0.040 0.045 0.050 0.055 0.060reduction: relative to 65nam transistors [7], gate leakage is LGATE (gin)reduced by >25X for NMOS & by 1000X for PMOS (Fig. 7). Fig.8 NMOS VT vs. LGATE showing good VT rolloff & DIBL

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Excellent short channel characteristics are observed due to The transistor performance gains are reflected in ringTox scaling and optimal workfunction metal gates (Fig. 8,9). oscillator performance. Fanout=2 gate delay is benchmarkedPMOS performance is improved by using high-k+MG as at a low 1OnA/tm IOFF each for NMOS and PMOS, at 1.2V

well as by increasing the Ge content of the embedded SiGe to for 65nm [8] and a lower 1. 1V for 45nm. The ring oscillators3000 from 23% (65nm [8]) and 17% (90nm [6]) and by use the minimum contacted gate pitch (220nm and 160nm)for each technology. Despite the scaling of both voltage andreducimg SiGe proxmty to the channel. Drive currents are contacted gate pitch, FO=2 gate delay is reduced from 6.65pSbenchmarked at 1.OV, a low 100nA/glm IOFF and at 160nlm (65nm) to SipS (45nm) a gain of230o(Fig. 12).contacted gate pitch. PMOS drive current (Fig. 10) of 1.07mA/tm demonstrates 51% improvement over 65nm [8]. 9

NMOS drive current (Fig. 11) is 1.36mA/tm, 12% better cn 8than our 65nm transistors [8]. The average drive current 0m, o 0 65nm@1.2Vimprovement over 65nm is 32% at the same voltage and IOFF 0 7 0 0° Odespite scaled transistor pitch. These represent the best drive ,,currents reported to date for 45nm technology at low IOFF. 2 6 000

0.00 5 ---------------

-0.05 5L

-0.10 IVDSI= 1.OV 445nm@~1.1V

co020 °' 3' -0.25 1 M;,OO 10 100 1000 10000-0.25o 0 30 2 %0 0 8j>°<<>0o 0 IOFFN + IOFFP (nAlum)~-0.30 Q~0 00

~~~ 035*~~~~~~~~00-0.314 oOo o Fig.12 FO=2 ring oscillator delay vs leakage for 45nm vs 65nm-0.40 - 00 **S.0b 45 X7we *I TRANSISTOR RELIABILITY-0.45 DS TDDB and bias-temperature reliability of high-k + metal0.C0 0 0.05 transistors have been a concern [3], driven in part by the0.030 0.035 0.040 0.045 0.050 0.055 0.060

LGATE (gim) propensity for oxygen vacancy formation [9]. By carefulFig. 9 PMOS VT vs. LGATE showing good VT rolloff & DIBL engineering and optimization ofthe gate stack, the reliability1000

VDD=1.OV 1.E+09+* S 1.E+08

^100 /* *| 1E0 \ 45nmE 65nm1[8] 4D HK6MG

/ * ~~~~~~~~~~~~~?-~2n,1.E+06HKMU- 1. E+05 SiON/Poly-U-

0 4t ~~~~~~~~~~~~-1.+465nm [7]

/ +<+ 1.E+031.E+02 -

1 I * 4 6 8 10 12 14 160.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 Field (MV/cm)

IDSAT (mAgm)Fig.10 PMOS IDSAT VS. IOFF shows 1 .07mA/tm at 1 .V & I 0OnA Fig. 13 NMOS TDDB time to fail vs. electric field1000 50

VDD =1.OVPMOS NBTI

100~~ ~ ~ ~ ~ ~ ~ ~ ~ $4100 ~~~ ~ ~ ~ ~ ~ ~ ~ ~ 30~~~~C SiON/PolyE| ES~~~~6nm [8 3zr tsE 0

,' CD 65nm [7]U_ ~~~~~~~~20

- 1010 45nmHK+MG

1 5 ~ ~ ~ ~ ~~7911 130.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 SiO2 equivalent EField (MV/cm)

IDSAT (mAlgm)Figli1 NMOS IDSAT VS. IOFF shows 1.36mA/im at 1.0V& 1I00nA Fig. 14 PMOS NBTI VT- shift vs. electric field

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50 The SRAM has demonstrated 3.8 Ghz operating frequency at

z -NMOS PBTI 1. 1V power supply and stable low voltage operation (Fig. 17).High yield has also been demonstrated on microprocessors

40 for server, desktop, mobile & handheld applications (Fig. 18).E

4.7GHzcn 30-

1. 3v 1 - - --

t' 20-- SiON/Poly / 365nm [7] 1 2vF - nm]y g ~~~~~~~~~~~~~~~~~~~~~~~~~~~3.8 G lSz

10 -M1. lv *** **** ****10 _t45nm HK+MG

____. ~~~~~~~~~~1. Ov I******* *****

5 7 9 11 13 o.9v I*SiO2 equivalent EField (MV/cm) ,Z 2 G H z

0.8v I* *Fig. 15 NMOS PBTI VT shift vs. electric field +-------+---------+-----------+

concerns have been overcome. Oxide breakdown (Fig. 13) is 1. 8GHZ 2 . 3GHZ 3. 2GHZ 5 . 3GHZimproved relative to 65nm SiON transistors, supporting 30% Fig. 17 Voltage-Frequency shmoo for 153Mb SRAMhigher B-field. PMOS NBTI (Fig. 14) is improved comparedto 65nm SiON transistors at the same B-field and is matchedat 50%0 higher E-field. NMOS PBTI (Fig. 15) is better than65nm and supports 150o higher B-field; the net BT shift forNMOS and PMOS is matched to 65nm at 3000 higher field.Note that while NMOS transistors are considered stable forSiON/Poly, they actually show PBTI at very high B-fields.

INTERCONNECTSNine layers of copper interconnect are employed along Fig. 18 Die photos of single core & dual core microprocessors

with low-k CDO dielectrics (Fig. 16). Lower layer metalpitches are matched to the contacted gate pitch, while upper

FCONCLUSIONS

layer metal pitches increase progressively to optimize density For the first time, high-k ± metal gate transistors have beenand performance. Compared to 65nm [7] interconnect integrated into a manufacturable 45nm process. Combinedcapacitance is reduced by aggressive scaling of the SiCN etch with third generation strained silicon these transistors providestop layer, and by extending the use of CDO to more layers, record drive current at low leakage and at tight contacted gateincluding Metal-1. The Metal-9 layer is very thick and is used pitch. Ring oscillators demonstrate 23% gate delay reductionfor improved on-die power distribution. Packaging is 100% compared to 65nm [8] at the same lOFF and 10% lower VDD.Pb-free with Cu bumps and SnAgCu solder. Interconnects are Low-k CDO is employed for low interconnect RC delayoptimized to reliably withstand the added stress of Pb-free and is integrated with 100% Pb-free packaging. Aggressivepackaging on CDO films. pitch scaling and trench contact based local routing achieve

good layout density, while low cost is maintained using novel-1 493nm dry pattering techniques for critical layers. The

technology maintains historical scaling trends forperformance and density. Mature yield has been demonstratedand the technology is now in high volume manufacturing.

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Trans. on Device and Materials Rel., vol. 5, no. 1, pp. 5-19, 2005.4. R. Kotlyar et al., "Inversion Mobility and Gate Leakage in

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SR'-AM AN PRODUCTSII'I--' 7. P. Bai et al., "A 6-5nm Logic Technology Featuring 315nm Gate

in Ja 206 yild aenw tmtuelvs. 9. H Takeuchi et al., "Impact of Oxygen Vacancies on High-k Gatewas reported nJa206 elsaenwamaueevs. Stack Engineering"' IEDM Tech. Dig., pp. 829-832, 2004.

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