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Pocket Data Book
2003 SLL
Digital Logic
Digital LogicPocket Data Book
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,enhancements, improvements, and other changes to its products and services at any time and to discontinueany product or service without notice. Customers should obtain the latest relevant information before placingorders and should verify that such information is current and complete. All products are sold subject to TI’s termsand conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale inaccordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TIdeems necessary to support this warranty. Except where mandated by government requirements, testing of allparameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible fortheir products and applications using TI components. To minimize the risks associated with customer productsand applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or processin which TI products or services are used. Information published by TI regarding third–party products or servicesdoes not constitute a license from TI to use such products or services or a warranty or endorsement thereof.Use of such information may require a license from a third party under the patents or other intellectual propertyof the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is withoutalteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproductionof this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable forsuch altered documentation.
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Mailing Address:
Texas InstrumentsPost Office Box 655303Dallas, Texas 75265
Copyright 2002, Texas Instruments Incorporated
Series Supply Voltage VCC (V)Operating Free-air
Temperature Ta ()
SN74AUC1G/2G/3G 0.8~2.7 –40~85
SN74LVC1G/2G/3G 1.65~5.5 –40~85
SN74AHC1G 2.0~5.5 –40~85
SN74AHC1GxxH 2.0~5.5 –40~85
SN74AHC2GxxH 2.0~5.5 –40~85
SN74AHCT1G 4.5~5.5 –40~85
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.Production processing does not necessarily include testing of all parameters.See www.ti.com/sc/logic for the most current data sheets.
Little Logic
Series Supply Voltage VCC (V)Operating Free-air
Temperature Ta ()
SN74ABT 4.5~5.5 –40~85
SN74BCTSN74FSN74ALS
4.5~5.5 0~70
SN74AS
SN74LSSN74S 4.75~5.25 0~70SN74xx(STD)
SN74ACSN74AC11 2.0~5.5 –40~85SN74AHC
SN74HC 2.0~6.0 –40~85
SN74LV 2.0~5.5 –40~85
SN74LVC 2.0~3.6 –40~85
SN74LVT 2.7~3.6 –40~85
SN74ALVC 1.65~3.6 –40~85
SN74ALVT 2.3~3.6 –40~85
SN74AVC 1.4~3.6 –40~85
GATE/OCTAL/WidebusTM/Widebus+
INDEX
3
Page
TTLCMOS SN74BiCMOS
Device Function
Page
TTLCMOS SN74BiCMOS
Device Function
00 QUAD 2-INPUT NAND 139
01 QUAD 2-INPUT NAND O.C. 140
02 QUAD 2-INPUT NOR 141
03 QUAD 2-INPUT NAND O.C. 142
04 HEX INVERTERS 143
U04 HEX INVERTERS 144
05 HEX INVERTERS O.C 144
06 HEX INVERTER BUFFERS/DRIVERS O.C 145
07 HEX BUFFERS/DRIVERS O.C 145
08 QUAD 2-INPUT AND 146
09 QUAD 2-INPUT AND O.C 147
10 TRIPLE 3-INPUT NAND 148
11 TRIPLE 3-INPUT AND 149
14 HEX SCHMITT-TRIGGER INVERTERS 150
16 HEX INVERTER BUFFERS/DRIVERS O.C 151
17 HEX BUFFERS/DRIVERS O.C 151
19 HEX SCHMITT-TRIGGER INVERTERS 152
20 DUAL 4-INPUT NAND 153
21 DUAL 4-INPUT AND 154
25 DUAL 4-INPUT NOR WITH STROBE 154
26 QUAD 2-INPUT HIGH VOLTAGE INTERFACE NAND 155
27 TRIPLE 3-INPUT NOR 155
30 8-INPUT NAND 156
31 DELAY ELEMENTS 156
32 QUAD 2-INPUT OR 157
33 QUAD 2-INPUT NOR BUFFERS O.C. 158
35 HEX NON-INVERTERS WITH O.C. 158
37 QUAD 2-INPUT NAND BUFFERS 159
38 QUAD 2-INPUT NAND BUFFERS O.C. 159
42 4-LINE TO 10-LINE DECODER 160
45 BCD-TO-DECIMAL DECODER/DRIVER 162
47 BCD-TO-SEVEN SEGMENT DECODERS/DRIVERS 164
51 AND-OR-INVERT 166
64 4-2-3-2 INPUT AND-OR-INVERT 167
73 DUAL J-K FLIP-FLOPS 168
74 DUAL D-TYPE FLIP-FLOPS 170
75 4-BIT BISTABLE LATCHES 172
85 4-BIT COMPARATORS 173
86 QUAD 2-INPUT EXCLUSIVE-OR 174
90 DECADE COUNTER 175
92 DIVIDE-BY-12 COUNTERS 176
93 4-BIT BINARY COUNTERS 177
97 SYNCHRONOUS 6-BIT BINARY RATE MULTIPLIER 178
107 DUAL J-K FLIP-FLOPS 180
109 DUAL J-K FLIP-FLOPS 182
112 DUAL J-K FLIP-FLOPS 184
121 MONOSTABLE MULTIVIBRATORS 186
122 MONOSTABLE MULTIVIBRATORS 187
123 DUAL MONOSTABLE MULTIVIBARATORS 188
124 DUAL VOLTAGE-CONTROLLED OSCILLATORS 189
125 QUAD BUS BUFFER GATES 3-STATE 190
126 QUAD BUS BUFFER GATES 3-STATE 191
128 LINE DRIVER 192
1G00 SINGLE 2-INPUT POSITIVE-NAND GATE 27
1G02 SINGLE 2-INPUT POSITIVE-NOR GATE 27
1G04 SINGLE INVERTER GATE 28
1GU04 SINGLE INVERTER GATE 28
1G06 SINGLE BUFFER/DRIVER WITH OPEN-DRAIN OUTPUT 29
1G07 SINGLE BUFFER/DRIVER WITH OPEN-DRAIN OUTPUT 29
1G08 SINGLE 2-INPUT POSITIVE-AND GATE 30
1G14 SINGLE SCHMITT-TRIGGER INVERTER 30
1G17 SINGLE SCHMITT-TRIGGER BUFFER 31
1G18 1-OF-2 NONINVERTING DEMULTIPLEXER 31WITH 3-STATE DESELECTED OUTPUT
1G32 SINGLE 2-INPUT POSITIVE-OR GATE 32
1G66 SINGLE ABILATERAL ANALOG SWITCH 32
1G79 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP 33
1G80 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP 33
1G86 SINGLE 2-INPUT EXCLUSIVE-OR GATE 34
1G125 SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT 34
1G126 SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT 35
1G240 SINGLE BUFFER/DRIVER WITH 3-STATE OUTPUT 35
2G00 DUAL 2-INPUT POSITIVE-NAND GATE 36
2G02 DUAL 2-INPUT POSITIVE-NOR GATE 36
2G04 DUAL INVERTER GATE 37
2GU04 DUAL INVERTER GATE 37
2G06 DUAL BUFFER/DRIVER WITH OPEN-DRAIN OUTPUTS 38
2G07 DUAL BUFFER/DRIVER WITH OPEN-DRAIN OUTPUTS 38
2G08 DUAL 2-INPUT POSITIVE-AND GATE 39
2G14 DUAL SCHMITT-TRIGGER INVERTER 39
2G17 DUAL SCHMITT-TRIGGER BUFFER 40
2G32 DUAL 2-INPUT POSITIVE-OR GATE 40
2G34 DUAL BUFFER GATE 41
2G53 DUAL ANALOG MULTIPLEXER/DEMULTIPLEXER 41
2G66 DUAL BILATERAL ANALOG SWITCH 42
2G74SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE
42FLIP-FLOP WITH CLEAR AND PRESET
2G86 DUAL 2-INPUT EXCLUSIVE-OR GATE 43
2G125 DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS 43
2G126 DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS 44
2G157 SINGLE 2-LINE TO 1-LINE DATA SELECTOR/MULTIPLEXER 44
2G240 DUAL BUFFER/DRIVER WITH 3-STATE OUTPUTS 45
2G241 DUAL BUFFER/DRIVER WITH 3-STATE OUTPUTS 45
3G04 TRIPLE INVERTER GATE 46
3G06TRIPLE INVERTER BUFFER/DRIVER
46WITH OPEN-DRAIN OUTPUTS
3G07 TRIPLE BUFFER/DRIVER WITH OPEN-DRAIN OUTPUTS 47
3G14 TRIPLE SCHMITT-TRIGGER INVERTER 47
3G17 TRIPLE SCHMITT-TRIGGER BUFFER 48
3G34 TRIPLE BUFFER GATE 48
4
Page
TTLCMOS SN74BiCMOS
Device Function
Page
TTLCMOS SN74BiCMOS
Device Function
132 QUAD 2-INPUT NAND SCHMITT TRIGGERS 192
133 13-INPUT NAND 193
136 QUAD EXCLUSIVE-OR O.C. 193
137 3-TO-8 LINE DECODERS/DEMULTIPLEXERS LATCH 194
138 3-TO-8 LINE DECODERS/DEMULTIPLEXERS 196
139 DUAL 2-TO-4 LINE DECODERS/DEMULTIPLEXERS 198
140 DUAL 4-INPUT NAND LINE DRIVERS 200
145 BCD-TO-DECIMAL DECODERS/DRIVERS 201
147 10-TO-4 LINE PRIORITY ENCODER 202
148 8-TO-3 LINE PRIORITY ENCODERS 204
150 1-OF-16 DATA SELECTOR 206
151 8-TO-1 LINE DATA SELECTORS/MULTIPLEXERS 208
153 DUAL 4-TO-1 LINE DATA SELECTORS/MULTIPLEXERS 210
154 4-TO-16 LINE DECODERS/DEMULTIPLEXER 212
155 DUAL 2-TO-4 LINE DECODERS/DEMULTIPLEXERS 214
156 DUAL 2-TO-4 LINE DECODERS/DEMULTIPLEXERS 216
157 QUAD 2-TO-1 LINE DATA SELECTORS/MULTIPLEXERS 218
158 QUAD 2-TO-1 LINE DATA SELECTORS/MULTIPLEXERS 220
159 4-TO-16 LINE DECODER/MULTIPLEXER 222
161 SYNCHRONOUS BINARY COUNTERS 224
163 SYNCHRONOUS BINARY COUNTERS 226
164 8-BIT SHIFT REGISTERS (P-OUT SERIAL) 228
165 8-BIT SHIFT REGISTERS (P-LOAD) 230
166 8-BIT SHIFT REGISTERS (P-LOAD) 232
169 UP-DOWN SYNCHRONOUS BINARY COUNTERS 234
170 4-BY-4 REGISTER FILES 236
173 4-BIT D-TYPE REGISTERS 238
174 HEX D-TYPE FLIP-FLOPS 240
175 QUAD D-TYPE FLIP-FLOPS 241
181 4-BIT ALU/FUNCTION GENERATORS 242
182 LOOK-AHEAD CARRY GENERATORS 244
190 SYNCHRONOUS UP/DOWN DECADE COUNTER 246
191 SYNCHRONOUS UP/DOWN COUNTERS 248
192 PRESETTABLE SYNCHRONOUS 4-BIT UP/DOWN COUNTERS 250
193 SYNCHRONOUS UP/DOWN DUAL CLOCK COUNTERS 252
194 4-BIT BIDIRECTIONAL SHIFT REGISTERS 254
195 4-BIT PARALLEL ACCESS SHIFT REGISTERS 256
221 DUAL MONOSTABLE MULTIVIBRATORS 258
237 3-TO-8 LINE DECODER DEMULTIPLEXER 260
238 3-TO-8-LINE DECODERS/DEMULTIPLEXERS 262
240 OCTAL BUS DRIVERS 3-STATE 264
240-1 OCTAL BUS DRIVERS /IOL=48mA 3-STATE 264
241 OCTAL BUS DRIVERS 3-STATE 266
243 QUADRUPLE BUS TRANSCEIVERS 268
244 OCTAL BUS DRIVERS 3-STATE 270
244-1 OCTAL BUS DRIVERS /IOL=48mA 3-STATE 270
245 OCTAL BUS TRANSCEIVERS 3-STATE 272
245-1 OCTAL BUS TRANSCEIVERS /IOL=48mA 3-STATE 272
247 BCD-TO-SEVEN SEGMENT DECODERS/DRIVERS 274
250 1-OF-16 GENERATORS/MULTIPLEXER 3-STATE 276
251 DATA SELECTORS/MULTIPLEXERS 3-STATE 278
253DUAL 4-TO-1 LINE DATA SELECTOR/
280MULTIPLEXERS 3-STATE
257 QUAD 2-TO-1 DATA SELECTOR/MULTIPLEXERS 3-STATE 282
258 QUAD 2-TO-1 DATA SELECTOR/MULTIPLEXERS 3-STATE 284
259 8-BIT ADDRESSABLE LATCHES 286
260 DUAL 5-INPUT NOR GATES 288
265 QUAD COMPLEMENTARY-OUTPUT ELEMENTS 289
266 QUAD 2-INPUT EXCLUSIVE-NOR O.C. 290
273 OCTAL D-TYPE FLIP-FLOPS 291
276 QUAD J-K FLIP-FLOPS 292
279 QUAD S-R LATCHES 293
280 9-BIT PARITY GENERATORS/CHECKERS 294
283 4-BIT FULL ADDERS 296
286 9-BIT PARITY GENERATORS/CHECKERS 298
292 PROGRAMMABLE FREQUENCY DIVIDER/DIGITAL TIMER 300
293 4-BIT BINARY COUNTERS 302
294 PROGRAMMABLE FREQUENCY DIVIDER/DIGITAL TIMER 304
297 DIGITAL PLL FILTERS 306
298 QUAD 2-INPUT MULTIPLEXERS WITH STORAGE 308
299 8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS 310
321 CRYSTAL-CONTROLLED OSCILLATOR 312
323 8-BIT BIDIRELTIONAL SHIFT/STORAGE REGISTERS 314
348 8-TO-3 LINE PRIORITY ENCODER 316
354 8-INPUT MULTIPLEXERS/REGISTERS 3-STATE 318
356 8-INPUT MULTIPLEXERS/REGISTERS 3-STATE 320
365 HEX BUS DRIVERS HEX BUFFERS/LINE DRIVERS 3-STATE 322
366 HEX BUS DRIVERS HEX BUFFERS/LINE DRIVERS 3-STATE 323
367 HEX BUS DRIVERS HEX BUFFERS/LINE DRIVERS 3-STATE 324
368 HEX BUS DRIVERS HEX BUFFERS/LINE DRIVERS 3-STATE 324
373 OCTAL D-TYPE LATCHES 3-STATE 325
374 OCTAL D-TYPE FLIP-FLOPS 3-STATE 326
375 QUAD LATCHES 327
377 OCTAL D-TYPE FLIP-FLOPS CLOCK 328
378 HEX D-TYPE FLIP-FLOPS CLOCK 329
390 DUAL DECADE COUNTERS 330
393 DUAL BINARY COUNTERS 331
395 4-BIT CASCADABLE SHIFT REGISTER 3-STATE 332
399 QUAD 2-INPUT MULTIPLEXER WITH STORAGE 334
423 MONO-STABLE MULTIVIBRATOR 335
442 QUADRUPLE TRIDIRECTIONAL BUS TRANSCEIVERS 336
465 OCTAL BUFFERS 3-STATE 338
518 8-BIT IDENTITY COMPARATOR 340
520 8-BIT IDENTITY COMPARATOR 342
521 8-BIT IDENTITY COMPARATOR 344
533 OCTAL D-TYPE LATCHES 346
534 OCTAL D-TYPE FLIP-FLOPS 347
540 OCTAL BUFFERS/DRIVERS 3-STATE 348
540-1 OCTAL BUFFERS/DRIVERS (IOL=48mA) 348
541 OCTAL BUFFERS/DRIVERS 3-STATES 349
541-1 OCTAL BUFFERS/DRIVERS (IOL=48mA) 349
543 OCTAL REGISTERED TRANSCEIVERS 350
561 SYNCHRONOUS 4-BIT COUNTER 352
563 OCTAL TRANSPARENT LATCHES 354
564 OCTAL D-TYPE FLIP-FLOPS 355
569 SYNCHRONOUS BINARY COUNTER 3-STATE 356
5
Page
TTLCMOS SN74BiCMOS
Device Function
Page
TTLCMOS SN74BiCMOS
Device Function
686 8-BIT IDENTITY COMPARATOR 426
688 8-BIT IDENTITY COMPARATOR 428
697 SYNCHRONOUS UP-DOWN COUNTERS 430
699 SYNCHRONOUS UP-DOWN COUNTERS 432
756 OCTAL BUFFER/LINE DRIVER WITH O.C. OUTPUTS 434
757 OCTAL BUFFER/LINE DRIVER WITH O.C. OUTPUTS 435
760 OCTAL BUFFER/LINE DRIVER WITH O.C. OUTPUTS 436
804 HEX 2-INPUT NAND DRIVERS 437
805 HEX 2-INPUT NOR DRIVERS 438
808 HEX 2-INPUT AND DRIVERS 438
821 10-BIT BUS INTERFACE FLIP-FLOPS 439
823 9-BIT BUS INTERFACE FLIP-FLOP 440
825 8-BIT BUS INTERFACE FLIP-FLOP 442
827 10-BIT BUFFERS/BUS DRIVERS 444
828 10-BIT BUFFERS/BUS DRIVERS 444
832 HEX 2-INPUT OR DRIVERS 445
833 10-BIT TO 9-BIT PARITY BUS TRANSCEIVERS 446
841 10-BIT BUS INTERFACE LATCHES 448
843 9-BIT BUS INTERFACE LATCHES 450
853 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS 452
857 HEX 2-TO-1 UNIVERSAL MULTIPLEXERS 454
861 10-BIT TRANSCEIVERS WITH 3-STATEOUTPUTS 456
863 9-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS 457
867 8-BIT SYNCHRONOUS COUNTER 458
869 8-BIT SYNCHRONOUS COUNTER 460
870 DUAL 16-BY 4-BIT REGISTER FILES 462
873 DUAL 4-BIT D-TYPE LATCHES 464
874 DUAL 4-BIT D-TYPE FLIP-FLOPS 465
876 DUAL 4-BIT D-TYPE FLIP-FLOPS466
WITH INVERTED OUTPUTS
885 8-BIT MAGNITUDE COMPARATOR 468
990 8-BIT D-TYPE TRANSPARENT READ-BACK LATCHES 470
992 9-BIT D-TYPE TRANSPARENT471
READ-BACKLATCHES 3-STATE
994 10-BIT D-TYPE TRANSPARENT READ-BACK LATCHES 472
996 8-BIT D-TYPE EDGE-TRIGGERED READ-BACK LATCHES 474
1000 QUAD 2-INPUT NAND BUFFERS/DRIVERS 476
1004 HEX INVERTER 476
1005 HEX INVERTER O.C. 477
1008 QUAD 2-INPUT AND BUFFERS/DRIVERS 477
1032 QUAD 2-INPUT OR BUFFERS/DRIVERS 478
1034 HEX DRIVERS 478
1035 HEX BUFFERS O.C. 479
1240 OCTAL BUS DRIVER 479
1244 OCTAL BUS DRIVER 3-STATE 480
1245 OCTAL BIDIRECTIONAL BUS TRANSCEIVER 3-STATE 480
1640 OCTAL BIDIRECTIONAL BUS TRANSCEIVER 3-STATE 481
1645 OCTAL BIDIRECTIONAL BUS TRANSCEIVER 3-STATE 481
2240OCTAL BUFFERS AND LINE DRIVERS
482MOS DRIVERS WITH 3-STATE OUTPUTS
2241OCTAL LINE MOS DRIVERS WITH SERIES
483DUMPING REGISTER, NON-INVERTING
573 OCTAL D-TYPE LATCHES 358
574 OCTAL D-TYPE FLIP-FLOPS 359
575 OCTAL D-TYPE FLIP-FLOPS 360
576 OCTAL D-TYPE FLIP-FLOPS 361
577 OCTAL D-TYPE FLIP-FLOPS 362
580 OCTAL D-TYPE LATCHES 363
590 8-BIT COUNTER/OUTPUT REGISTER 3-STATE 364
592 8-BIT BINARY COUNTERES 366
593 8-BIT BINARY COUNTERES 368
594 8-BIT SHIFT REGISTERS 370
595 8-BIT SHIFT REGISTERS 372
596 8-BIT SHIFT REGISTERS 374
597 8-BIT SHIFT REGISTERS 376
598 8-BIT SHIFT REGISTERS 378
620 OCTAL BUS TRANSCEIVERS 3-STATE 380
621 OCTAL BUS TRANSCEIVERS O.C. 381
621-1 OCTAL BUS TRANSCEIVERS/IOL=48mA 381
623 OCTAL BUS TRANSCEIVERS 382
624 VOLTAGE CONTROLLED OSCILLATORS 383
628 VOLTAGE CONTROLLED OSCILLATORS 384
629 VOLTAGE CONTROLLED OSCILLATORS 385
638 OCTAL BUS TRANSCEIVERS 386
638-1 OCTAL BUS TRANSCEIVERS/IOL=48mA 386
639 OCTAL BUS TRANSCEIVERS 387
639-1 OCTAL BUS TRANSCEIVERS/IOL=48mA 387
640 OCTAL BUS TRANSCEIVERS 3-STATE 388
640-1 OCTAL BUS TRANSCEIVERS/IOL=48mA 3-STATE 388
641 OCTAL BUS TRANSCEIVERS O.C. 389
641-1 OCTAL BUS TRANSCEIVERS/IOL=48mA O.C. 389
642 OCTAL BUS TRANSCEIVERS O.C. 390
642-1 OCTAL BUS TRANSCEIVERS/IOL=48mA O.C. 390
645 OCTAL BUS TRANSCEIVERS 3-STATE 391
645-1 OCTAL BUS TRANSCEIVERS/IOL=48mA 3-STATE 391
646 OCTAL BUS TRANSCEIVERS AND REGISTERS 392
646-1 OCTAL BUS TRANSCEIVERS AND REGISTERS/IOL=48mA 392
647 OCTAL BUS TRANSCEIVERS AND REGISTERS 394
648 OCTAL BUS TRANSCEIVERS AND REGISTERS 396
651 OCTAL BUS TRANSCEIVERS AND REGISTERS 398
651-1 OCTAL BUS TRANSCEIVERS AND REGISTERS/IOL=48mA 398
652 OCTAL BUS TRANSCEIVERS AND REGISTERS 400
653 OCTAL BUS TRANSCEIVERS AND REGISTERS 402
654 OCTAL BUS TRANSCEIVERS AND REGISTERS 404
657OCTAL TRANSCEIVERS WITH PARITY
406GENERATORS/CHECKERS 3-STATE
666 8-BIT D-TYPE TRANSPARENT READ-BACK LATCHES 408
667 8-BIT D-TYPE TRANSPARENT READ-BACK LATCHES 410
669 SYNCHRONOUS UP/DOWN BINARY COUNTER 412
670 4 x 4 REGISTER FILE 414
673 16-BIT SHIFT REGISTER 416
674 16-BIT SHIFT REGISTER 418
679 ADRESS COMPARATOR 420
682 8-BIT IDENTITY COMPARATOR 422
684 8-BIT IDENTITY COMPARATOR 424
6
Page
TTLCMOS SN74BiCMOS
Device Function
Page
TTLCMOS SN74BiCMOS
Device Function
2244OCTAL LINE/MOS DRIVERS WITH SERIES
484DUMPING REGISTER, NON-INVERTING
2245OCTAL TRANSCEIVER AND LINE/MOS DRIVERS
485WITH 3-STATE OUTPUTS
237325-Ω OCTAL TRANSPARENT D-TYPE LATCH
486WITH 3-STATE OUTPUTS
2414 MEMORY DECODER WITH ON-CHIP VCC MONITOR 488
2541OCTAL LINE DRIVERS/MOS DRIVERS
490WITH 3-STATE OUTPUTS
2827 10-BIT BUS/MOS MEMORY DRIVERS 490
2828 10-BIT BUS/MOS MEMORY DRIVERS INVERTING 491
2952 REGISTERED TRANSCEIVERS (2mA, 24mA, 48mA, 64mA) 492
2953 REGISTERED TRANSCEIVERS (2mA, 24mA, 48mA, 64mA) 494
3245 OCTAL BUS TRANSCEIVER 3-STATE 496
4002 DUAL 4-INPUT POSITIVE-NOR GATES 497
4015 DUAL 4-STAGE STATIC SHIFT REGISTER 498
4016 QUAD BILATERAL SWITCH 499
4017 DECADE COUNTERS/DRIVERS 500
4020 14-STAGE BINARY COUNTERS 502
4024 7-STAGE BINARY COUNTERS 503
4040 12-STAGE BINARY COUNTERS 504
4046 PHASE-LOCKED-LOOP WITH VCO 505
4049 HEX INVERTING BUFFERS 506
4050 HEX NON-INVERTING BUFFERS 506
4051 8-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS 507
4052 DUAL 4-CHANNEL ANALOG508
MULTIPLEXERS/DEMULTIPLEXERS
4053 TRIPLE 2-CHANNEL ANALOG509
MULTIPLEXERS/DEMULTIPLEXERS
4059 CMOS PROGRAMMABLE DIVIDE-BY-N COUNTER 510
4060ASYNCHRONOUS 14-STAGE BINARY COUNTERS
511AND OSCILLATORS
4066 QUAD BILATERAL SWITCHES 512
4067 16-CHANNEL ANALOG MULTIPLEXER/DEMULTIPLEXER 513
4075 TRIPLE 3-INPUT OR GATES 514
4094 8-STAGE SHIFT AND STORE BUS REGISTER, THREE-STATE 516
4245OCTAL BUS TRANSCEIVER AND 3.3-V TO 5-V SHIFTER
518WITH 3-STATE OUTPUTS
4316 QUAD ANALOG SWITCH WITH LEVEL TRANSLATION 519
4351 ANALOG MULTIPLEXERS/DEMULTIPLEXERS WITH LATCH 520
4352 ANALOG MULTIPLEXERS/DEMULTIPLEXERS WITH LATCH 521
4374OCTAL EDGE-TRIGGERED D-TYPE DUAL-
522RANK FLIP-FLOP WITH 3-STATE OUTPUTS
4511 BCD-TO-7 SEGMENT LATCH/DECODER/DRIVERS 523
45144-LINE TO 16-LINE DECODERS/DEMULTIPLEXERS
524WITH INPUT LATCHES
45154-LINE TO 16-LINE DECODERS/DEMULTIPLEXERS
526WITH INPUT LATCHES
4518 DUAL SYNCHRONOUS COUNTERS 528
4520 DUAL SYNCHRONOUS COUNTERS 529
4538DUAL RETRIGGERABLE PRECISION
530MONOSTABLE MULTIVIBRATOR
4543 BCD-TO-7 SEGMENT LATCH/DECODER/DRIVERS 532
5400 11-BIT LINE/MEMORY DRIVERS WITH 3-STATE OUTPUTS 534
5401 11-BIT LINE/MEMORY DRIVERS WITH 3-STATE OUTPUTS 534
5402 12-BIT LINE/MEMORY DRIVERS WITH 3-STATE OUTPUTS 535
5403 11-BIT LINE/MEMORY DRIVERS WITH 3-STATE OUTPUTS 535
7001QUAD POSITIVE-AND GATES
536WITH SCHMITT-TRIGGER INPUTS
7002QUAD POSITIVE-NOR GATES
536WITH SCHMITT-TRIGGER INPUTS
7032QUAD 2-INPUT POSITIVE-OR GATES
537WITH SCHMITT-TRIGGER INPUTS
7046 PHASE-LOCKED LOOP WITH VCO AND LOCK DETECTOR 538
7266 QUAD 2-INPUT EXCLUSIVE-NOR GATES 539
8003 DUAL 2-INPUT NAND GATES 539
16240 16-BIT BUS BUFFERS/DRIVERS WITH 3-STATE OUTPUTS 540
16241 16-BIT BUS BUFFERS/DRIVERS WITH 3-STATE OUTPUTS 542
16244 16-BIT BUS BUFFERS/DRIVERS WITH 3-STATE OUTPUTS 544
16245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS 546
1626012-BIT TO 24-BIT MULTIPLEXES D-TYPE
548LATCH WITH 3-STATE OUTPUTS
1626912-BIT TO 24-BIT REGISTERED BUS
550TRANSCEIVER WITH 3-STATE OUTPUTS
1627012-BIT TO 24-BIT REGISTERED BUS EXCHANGER
552WITH 3-STATE OUTPUTS
1627112-BIT TO 24-BIT MULTIPLEXED BUS EXCHANGER
554WITH 3-STATE OUTPUTS
1628218-BIT TO 36-BIT REGISTERED BUS EXCHANGER
556WITH 3-STATE OUTPUTS
16334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS 558
16344 1-BIT TO 4-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS 560
16373 16-BIT TRANSPARENT LATCHES WITH 3-STATE OUTPUTS 562
1637416-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
564WITH 3-STATE OUTPUTS
164099-BIT, 4-PORT UNIVERSAL BUS EXCHANGER
566WITH 3-STATE OUTPUTS
164604-TO-1 MULTIPLEXED/DEMULTIPLEXED
568TRANSCEIVERS WITH 3-STATE OUTPUTS
1647016-BIT REGISTERED TRANSCEIVERS
570WITH 3-STATE OUTPUTS
1650018-BIT UNIVERSAL BUS TRANSCEIVER
572WITH 3-STATE OUTPUTS
1650118-BIT UNIVERSAL BUS TRANSCEIVER
574WITH 3-STATE OUTPUTS
1652418-BIT REGISTERED BUS TRANSCEIVER
576WITH 3-STATE OUTPUTS
1652518-BIT REGISTERED BUS TRANSCEIVER
578WITH 3-STATE OUTPUTS
16540 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS 580
16541 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS 581
1654316-BIT REGISTERED TRANSCEIVERS
582WITH 3-STATE OUTPUTS
1660018-BIT UNIVERSAL BUS TRANSCEIVERS
584WITH 3-STATE OUTPUTS
1660118-BIT UNIVERSAL BUS TRANSCEIVERS
586WITH 3-STATE OUTPUTS
16620 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS 588
16623 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS 590
7
Page
TTLCMOS SN74BiCMOS
Device Function
Page
TTLCMOS SN74BiCMOS
Device Function
16640 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS 591
1664616-BIT BUS TRANSCEIVERS AND REGISTERS
592WITH 3-STATE OUTPUTS
1665116-BIT BUS TRANSCEIVERS AND REGISTERS
594WITH 3-STATE OUTPUTS
1665216-BIT BUS TRANSCEIVERS AND REGISTERS
596WITH 3-STATE OUTPUTS
1665716-BIT TRANSCEIVERS WITH PARITY GENERATORS/
598CHECKERS AND 3-STATE OUTPUTS
16721 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS 600
16722 22-BIT FLIP-FLOP WITH 3-STATE OUTPUTS 601
1682010-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
602WITH DUAL OUTPUTS
1682120-BIT BUS INTERFACE FLIP-FLOPS
603WITH 3-STATE OUTPUTS
1682318-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
604WITH DUAL OUTPUTS
16825 18-BIT BUS BUFFERS/DRIVERS WITH 3-STATE OUTPUTS 605
16827 20-BIT BUS BUFFERS/DRIVERS WITH 3-STATE OUTPUTS 606
168311-TO-4 ADDRESS REGISTER/DRIVER
607WITH 3-STATE OUTPUTS
168321-TO-4 ADDRESS REGISTER/DRIVER
608WITH 3-STATE OUTPUTS
16833 DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS 610
1683416-BIT UNIVERSAL BUS DRIVER
612WITH 3-STATE OUTPUTS
168353.3-V ABT 18-BIT UNIVERSAL BUS DRIVER
613WITH 3-STATE OUTPUTS
1684120-BIT BUS INTERFACE D-TYPE LATCHES
614WITH 3-STATE OUTPUTS
1684318-BIT BUS INTERFACE D-TYPE LATCHES
615WITH 3-STATE OUTPUTS
16853 DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS 616
16861 20-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS 618
16863 18-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS 619
1690118-BIT UNIVERSAL BUS TRANSCEIVER
620WITH PARITY GENERATORS/CHECKERS
169033.3-V 12-BIT UNIVERSAL BUS DRIVER WITH
622PARITY CHECKER AND DUAL 3-STATE OUTPUTS
1695216-BIT REGISTERED TRANSCEIVERS
624WITH 3-STATE OUTPUTS
2524425Ω OCTAL BUS BUFFERS/DRIVERS
626WITH 3-STATE OUTPUTS
2524525Ω OCTAL BUS TRANSCEIVERS
627WITH 3-STATE OUTPUTS
25642 25-Ω OCTAL BUS TRANSCEIVER 628
2982110-BIT BUS-INTERFACE FLIP-FLOPS
629WITH 3-STATE OUTPUTS
298258-BIT BUS-INTERFACE FLIP-FLOPS
630WITH 3-STATE OUTPUTS
2982710-BIT BUFFERS AND BUS DRIVERS
631WITH 3-STATE OUTPUTS
2982810-BIT BUFFERS AND BUS DRIVERS
632WITH 3-STATE OUTPUTS
2984110-BIT BUS INTERFACE D-TYPE LATCHES
633WITH 3-STATE OUTPUTS
298439-BIT BUS INTERFACE D-TYPE LATCHES
634WITH 3-STATE OUTPUTS
29854 8-BIT TO 9-BIT PARITY BUS TRANSCEIVER 636
29863 9-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS 638
29864 9-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS 639
32240 32-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS 640
32244 36-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS 642
32245 36-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS 644
32316 16-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS 646
32318 18-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS 648
3237332-BIT TRANSPARENT D-TYPE LATCH
650WITH 3-STATE OUTPUTS
3237432-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
652WITH 3-STATE OUTPUTS
3250136-BIT UNIVERSAL BUS TRANSCEIVERS
654WITH 3-STATE OUTPUTS
3254336-BIT REGISTERED BUS TRANSCEIVERS
656WITH 3-STATE OUTPUTS
40103 8-STAGE SYNCHRONOUS DOWN COUNTERS 658
1622403.3-V ABT 16-BIT BUFFERS/DRIVERS
659WITH 3-STATE OUTPUTS
1622413.3-V ABT 16-BIT BUFFERS/DRIVERS
660WITH 3-STATE OUTPUTS
162244 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS 661
162245 16-BIT TRANSCEIVER WITH 3-STATE OUTPUTS 662
16226012-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH
664WITH 3-STATE OUTPUTS
16226812-BIT TO 24-BIT REGISTERED BUS EXCHANGER
666WITH 3-STATE OUTPUTS
16228016-BIT TO 32-BIT REGISTERED BUS EXCHANGER
668WITH BYTE MASKS AND 3-STATE OUTPUTS
16228218-BIT TO 36-BIT REGISTERED BUS EXCHANGER
670WITH 3-STATE OUTPUTS
162334 16-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS 672
162344 1-BIT TO 4-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS 674
1623733.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHES
676WITH 3-STATE OUTPUTS
1623743.3-V ABT 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
677WITH 3-STATE OUTPUTS
1624604-TO-1 MULTIPLEXED/DEMULTIPLEXED REGISTERED
678TRANSCEIVERS WITH 3-STATE OUTPUTS
16250018-BIT UNIVERSAL BUS TRANSCEIVER
680WITH 3-STATE OUTPUTS
16250118-BIT UNIVERSAL BUS TRANSCEIVERS
682WITH 3-STATE OUTPUTS
16252516-BIT REGISTERED BUS TRANSCEIVER
684WITH 3-STATE OUTPUTS
1625413.3-V ABT 16-BIT BUFFERS/DRIVERS
686WITH 3-STATE OUTPUTS
16260118-BIT UNIVERSAL BUS TRANSCEIVER
688WITH 3-STATE OUTPUTS
162721 3.3-V 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS 690
1628203.3-V 10-BIT FLIP-FLOP WITH DUAL OUTPUTS
691AND 3-STATE OUTPUTS
16282318-BIT BUS-INTERFACE FLIP-FLOPS
692WITH 3-STATE OUTPUTS
8
Page
TTLCMOS SN74BiCMOS
Device Function
162825 18-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS 693
162827 20-BIT BUS BUFFERS/DRIVERS WITH 3-STATE OUTPUTS 694
162830 1-BIT TO 2-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS 695
1628311-BIT TO 4-BIT ADDRESS REGISTER/DRIVER
696WITH 3-STATE OUTPUTS
1628321-BIT TO 4-BIT ADDRESS REGISTER/DRIVER
697WITH 3-STATE OUTPUTS
162834 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS 698
162835 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS 699
162836 20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS 700
16284120-BIT BUS-INTERFACE D-TYPE LATCH
701WITH 3-STATE OUTPUTS
16424516-BIT TRANSCEIVER AND 3.3-V TO 5-V
702SHIFTER WITH 3-STATE OUTPUTS
3223743.3-V ABT 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
703WITH 3-STATE OUTPUTS
FUNCTION1G / 2G / 3G
11
LITTLE LOGIC GATE (AND/NAND/OR/NOR/EX-OR)
CMOS BiCMOS Advanced CMOS
HC
HC
T
BC
T
AB
T
LV
T
AL
VT
AC
AC
T
AH
C
AH
CT
LV
LV
C
AL
VC
AV
C
AU
C
1 1G08
2 2G08 *
1 1G00
2 2G00 *
1 1G32
2 2G32 *
1 1G02
2 2G02 *
1 1G86 *
2 2G86 *
Explanatory notes [Input] SCH:Schmitt-Trigger InputsExplanatory notes [Output] BUF:Buffered Output OC:Open-Collector Output 3S:3-State OutputStatus :Product available in technology indicated *:New product planned in technology indicated ×:Discontinued
LITTLE LOGIC GATE (INVERTER/NONINVERTER)
CMOS BiCMOS Advanced CMOS
HC
HC
T
BC
T
AB
T
LV
T
AL
VT
AC
AC
T
AH
C
AH
CT
LV
LV
C
AL
VC
AV
C
AU
C
1G04 UBF 1GU04 OC 1G06
SCH 1G14 2G04 *
UBF 2GU04 *
OC 2G06 *
SCH 2G14 *
2G04 *
3G04 *
UBF 3GU04 *
OC 3G06 *
SCH 2G14 *
SCH 3G14 *
OC 1G07 SCH 1G17
1G66 OC 2G07 *
SCH 2G17 *
2G34 *
2G66 *
OC 3G07 *
SCH 3G17 * *
2G34 *
3G34 *
Explanatory notes [Input] SCH:Schmitt-Trigger InputsExplanatory notes [Output] BUF:Buffered Output OC:Open-Collector Output 3S:3-State OutputStatus :Product available in technology indicated *:New product planned in technology indicated ×:Discontinued
Technology
Technology
Description No. ofInput Curcuit Input Output Type
Description No. ofInput
3
1NON-INVERTING
1
2
1
2
3
1INVERTING
Curcuit Input Output Type
POSITIVE- OR
EXCLUSIVE-OR
2
POSITIVE-NAND
POSITIVE-AND
2
2
2
2
POSITIVE- NOR
12
LITTLE LOGIC BUFFER/DRIVER
CMOS BiCMOS Advanced CMOS
HC
HC
T
BC
T
AB
T
LV
T
AL
VT
AC
AC
T
AH
C
AH
CT
LV
LV
C
AL
VC
AV
C
AU
C
1G125
1G126
2G125 *2G126 *2G241 *
1G240
Explanatory notes Output 3S:3-State Output R3S:Series Resistor and 3-State output OC:Open-Collector OutputStatus :Product available in technology indicated *:New product planned in technology indicated ×:Discontinued
LITTLE LOGIC D-TYPE FLIP-FLOP
CMOS BiCMOS Advanced CMOS
HC
HC
T
BC
T
AB
T
LV
T
AL
VT
AC
AC
T
AH
C
AH
CT
LV
LV
C
AL
VC
AV
C
AU
C
2S Q 1G79 *2S /Q 1G80 *
B 2S B 2G74 *
Explanatory notes [Trigger] POS:POSITIVE EDGE、NEG:NEGATIVE EDGEExplanatory notes [PRE・CLR] B:Preset and Clear、 C:Clear onlyExplanatory notes [Output] 2S:Totem pole Output 3S:3-State OutputExplanatory notes [Q・/Q] B:Q・/Q-Output Q:Q-Output /Q:/Q-OutputStatus :Product available in technology indicated *:New product planned in technology indicated ×:Discontinued
LITTLE LOGIC Data Selectors/Multiplexers
CMOS BiCMOS Advanced CMOS
HC
HC
T
BC
T
AB
T
LV
T
AL
VT
AC
AC
T
AH
C
AH
CT
LV
LV
C
AL
VC
AV
C
AU
C
2G157 *
Explanatory notes [Output] 2S:Totem Pole Output 3S:3-State Output OC:Open-Collector OutputStatus :Product available in technology indicated *:New product planned in technology indicated ×:Discontinued
Technology
Technology
Technology
Q・/Q Type
Type
3S
3S
3S
OutputDescription
NON-INVERTING
2
1INVERTING
Curcuit
1
No. ofInput/Output
2/1
Output TypeCurcuit
2S 1
3S
3S
3S
Trigger Output
POS
Curcuit
1
PRE・
CLR
13
LITTLE LOGIC ANALOG SWITCH
CMOS BiCMOS Advanced CMOS
HC
HC
T
BC
T
AB
T
LV
T
AL
VT
AC
AC
T
AH
C
AH
CT
LV
LV
C
AL
VC
AV
C
AU
C
1G66
1G18
2G53 *
2G66 *
Status :Product available in technology indicated *:New product planned in technology indicated ×:Discontinued
SINGLE 2-CHANNELANALOGMULTIPLEXERS/DEMULTIPLEXERS
DUAL ANALOG SWITCH
Technology
TypeDescription
SINGLE ANALOG SWITCH
One of Two Noninverting Demultiplexer with 3-StateDeselected Output
PIN ASSIGNMENTS1G / 2G / 3G
17
Pin Assinments
1G00SINGLE 2-INPUT POSITIVE-NAND GATEY = AB
See page 27
1G02SINGLE 2-INPUT POSITIVE-NOR GATEY = A + B
1G04SINGLE INVERTER GATEY = A
1GU04SINGLE INVERTERY = A
1G08SINGLE 2-INPUT POSITIVE-AND GATEY = AB
1G14SINGLE SCHMITT-TRIGGER INVERTER GATEY = A
See page 30
See page 30
See page 27
See page 28
See page 28
1 2 3
5 4
A B GND
VCC Y
1 2 3
5 4
A B GND
VCC Y
1 2 3
5 4
NC A GND
VCC Y
1 2 3
5 4
NC A GND
VCC Y
1 2 3
5 4
A B GND
VCC Y
1 2 3
5 4
NC A GND
VCC Y
1G06SINGLE INVERTER BUFFER/DRIVERWITH OPEN-DRAIN OUTPUT
1G07SINGLE BUFFER/DRIVERWITH OPEN-DRAIN OUTPUT
See page 29
See page 29
1 2 3
5 4
NC A GND
VCC Y
1 2 3
5 4
NC A GND
VCC Y
NC – No internal connection
NC – No internal connection
NC – No internal connection
NC – No internal connectionNC – No internal connection
18
Pin Assinments
1G125SINGLE BUS BUFFER GATEWITH 3-STATE OUTPUTY = A
See page 34
1 2 3
5 4
OE A GND
VCC Y
1G32SINGLE 2-INPUT POSITIVE-OR GATEY = A + B
1G86SINGLE 2-INPUT EXCLUSIVE-OR GATEY = A ⊕ B = AB + AB
See page 32 See page 34
1 2 3
5 4
A B GND
VCC Y
1 2 3
5 4
A B GND
VCC Y
1G17SINGLE SCHMITT-TRIGGER BUFFER
1G66SINGLE ABILATERAL ANALOG SWITCH
1G79SINGLE POSITIVE-EDGE-TRIGGEREDD-TYPE FLIP-FLOP
1G80SINGLE POSITIVE-EDGE-TRIGGEREDD-TYPE FLIP-FLOP
See page 31
See page 33
See page 32
See page 33
1 2 3
5 4
NC A GND
VCC Y
1 2 3
5 4
A B GND
VCC C
1 2 3
5 4
D
D
CLK
CK
GND
VCC Q
Q
1 2 3
5 4
D CLK GND
VCC Q
QD
CK
1G181-OF-2 NONINVERTING DEMULTIPLEXERWITH 3-STATE DESELECTED OUTPUT
See page 31
1 2 3
6 4
S GND A
Y0
5
VCC Y1
NC – No internal connection
19
Pin Assinments
1G240SINGLE BUFFER/DRIVER WITH 3-STATE OUTPUT
2G00DUAL 2-INPUT POSITIVE-NAND GATE
2G02DUAL 2-INPUT POSITIVE-NOR GATE
2G04DUAL INVERTER GATE
See page 37
See page 36
See page 36
See page 35
2GU04DUAL INVERTER GATE
See page 37
1 2 3
5 4
OE A GND
VCC Y
1 2 4
8 5
1A 1B GND
VCC
7
1Y 2A
3
6
2Y
2B
1 2 4
8 5
1A 1B GND
VCC
7
1Y 2A
3
6
2Y
2B
1 2 3
6 4
1A GND 2A
1Y
5
VCC 2Y
1 2 3
6 4
1A GND 2A
1Y
5
VCC 2Y
1G126SINGLE BUS BUFFER GATEWITH 3-STATE OUTPUTY = A
See page 35
1 2 3
5 4
OE A GND
VCC Y
20
Pin Assinments
2G17DUAL SCHMITT-TRIGGER BUFFER
2G14DUAL SCHMITT-TRIGGER INVERTER
See page 39
2G32DUAL 2-INPUT POSITIVE-OR GATE
See page 40
See page 40
1 2 3
6 4
1A GND 2A
1Y
5
VCC 2Y
1 2 3
6 4
1A GND 2A
1Y
5
VCC 2Y
1 2 4
8 5
1A 1B GND
VCC
7
1Y 2A
3
6
2Y
2B
2G06DUAL INVERTER BUFFER/DRIVERWITH OPEN-DRAIN OUTPUTS
2G07DUAL BUFFER/DRIVERWITH OPEN-DRAIN OUTPUTS
2G08DUAL 2-INPUT POSITIVE-AND GATE
See page 39
See page 38
See page 38
1 2 3
6 4
1A GND 2A
1Y
5
VCC 2Y
1 2 3
6 4
1A GND 2A
1Y
5
VCC 2Y
1 2 4
8 5
1A 1B GND
VCC
7
1Y 2A
3
6
2Y
2B
21
Pin Assinments
2G53DUAL ANALOG MULTIPLEXER/DEMULTIPLEXER
See page 41
2G66DUAL BILATERAL ANALOG SWITCH
2G86DUAL 2-INPUT EXCLUSIVE-OR GATE
2G74SINGLE POSITIVE-EDGE-TRIGGEREDD-TYPE FLIP-FLOP WITH CLEAR AND PRESET
2G34DUAL BUFFER GATE
See page 42
See page 42See page 41
See page 43
1 2 3
6 4
1A GND 2A
1Y
5
VCC 2Y
1 2 4
8 5
COM INH GNDGND
VCC
7
Y1 A
3
6
Y2
1 2 4
8 5
CLK
CK
D
D
GND
VCC Q
Q
3
6
Q
CLR
7
Q
PRE
PRE
CLR
1 2 4
8 5
1A 1B GND
VCC
7
1C 2A
3
6
2C
2B
1 2 4
8 5
1A 1B GND
VCC
7
1Y 2A
3
6
2Y
2B
2G125DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS
See page 43
1 2 4
8 5
1OE 1A GND
VCC 2A
3
6
2Y
1Y
7
2OE
22
Pin Assinments
2G157SINGLE 2-LINE TO 1-LINE DATASELECTOR/MULTIPLEXER
2G240DUAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
2G241DUAL BUFFER/DRIVER WITH 3-STATE OUTPUTS
3G04TRIPLE INVERTER GATE
3G06TRIPLE INVERTER BUFFER/DRIVERWITH OPEN-DRAIN OUTPUTS
See page 45
See page 46See page 44
See page 46See page 45
1 2 4
8 5
A B GND
VCC Y
3
6
Y
A/B
7
G
1 2 4
8 5
1OE 1A GND
VCC 2A
3
6
2Y
1Y
7
2OE
2 4
8 5
1OE 1A GND
VCC 2A
3
6
2Y
1Y
7
2OE
1
1 2 4
8 5
1A 3Y GND
VCC
7
1Y 2Y
3
6
2A
3A
1 2 4
8 5
1A 3Y GND
VCC
7
1Y 2Y
3
6
2A
3A
2G126DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS
See page 44
1 2 4
8 5
1OE 1A GND
VCC 2A
3
6
2Y
1Y
7
2OE
23
Pin Assinments
3G17TRIPLE SCHMITT-TRIGGER BUFFER
3G34TRIPLE BUFFER GATE
See page 48
See page 48
1 2 4
8 5
1A 3Y GND
VCC
7
1Y 2Y
3
6
2A
3A
1 2 4
8 5
1A 3Y GND
VCC
7
1Y 2Y
3
6
2A
3A
3G14TRIPLE SCHMITT-TRIGGER INVERTER
See page 47
1 2 4
8 5
1A 3Y GND
VCC
7
1Y 2Y
3
6
2A
3A
3G07TRIPLE BUFFER/DRIVERWITH OPEN-DRAIN OUTPUTS
See page 47
1 2 4
8 5
1A 3Y GND
VCC
7
1Y 2Y
3
6
2A
3A
FUNCTION
AND
ELECTRICAL
CHARACTERISTICS1G / 2G / 3G
27
1G00SINGLE 2-INPUT POSITIVE-NAND GATE
Y = AB
1G02SINGLE 2-INPUT POSITIVE-NOR GATE
Y = A + B
1
24A
BY
Logic Diagram
INPUT
L
BA
L
OUTPUTYL
HX
X
HHH
FUNCTION TABLE
A
BY
1
24
Logic Diagram (positive logic)
INPUTBA
L
OUTPUTY
HL
XX HH
L
L
FUNCTION TABLE
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN AHC AHCT LVC5V
LVC3.3V
LVC2.5V
LVC1.8V
AUC2.5V
AUC1.8V UNIT
ICC MAX 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 mAIOH MAX -8 -8 -32 -24 -8 -4 -9 -8 mAIOL MAX 8 8 32 24 8 4 9 8 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT AHC AHCT LVC5V
LVC3.3V
LVC2.5V
LVC1.8V
AUC2.5V
AUC1.8V
tPLH 8.5 9 4 4.7 5.5 8 2 2.2tPHL 8.5 9 4 4.7 5.5 8 2 2.2UNIT:ns
MAX or MIN
MAX
OUTPUT
YA or B
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN AHC AHCT LVC5V
LVC3.3V
LVC2.5V
LVC1.8V
AUC2.5V
AUC1.8V UNIT
ICC MAX 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 mAIOH MAX -8 -8 -32 -24 -8 -4 -9 -8 mAIOL MAX 8 8 32 24 8 4 9 8 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT AHC AHCT LVC5V
LVC3.3V
LVC2.5V
LVC1.8V
AUC2.5V
AUC1.8V
tPLH 8.5 8.5 4 4.5 5.5 8 2.1 2.4tPHL 8.5 8.5 4 4.5 5.5 8 2.1 2.4UNIT:ns
MAX or MIN
MAX
OUTPUT
YA or B
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
28
A2 4
Y
Logic Diagram
OUTPUTY
INPUTA
HLH
L
FUNCTION TABLE
1G04SINGLE INVERTER GATE
Y = A
A2 4
Y
Logic Diagram
OUTPUTY
INPUTA
LHL H
FUNCTION TABLE
1GU04SINGLE INVERTER
Y = A
Unbuffered Output
Supply Voltage Renge : 2V ~ 5.5V
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN AHC AHCT LVC5V
LVC3.3V
LVC2.5V
LVC1.8V
AUC2.5V
AUC1.8V UNIT
ICC MAX 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 mAIOH MAX -8 -8 -32 -24 -8 -4 -9 -8 mAIOL MAX 8 8 32 24 8 4 9 8 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT AHC AHCT LVC5V
LVC3.3V
LVC2.5V
LVC1.8V
AUC2.5V
AUC1.8V
tPLH 8.5 8.5 3.7 4.2 5.2 7.5 1.9 2.2tPHL 8.5 8.5 3.7 4.2 5.2 7.5 1.9 2.2UNIT:ns
MAX or MIN
MAXA
OUTPUT
Y
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN AHC LVC5V
LVC3.3V
LVC2.5V
LVC1.8V
AUC2.5V
AUC1.8V UNIT
ICC MAX 0.01 0.01 0.01 0.01 0.01 0.01 0.01 mAIOH MAX -8 -32 -24 -8 -4 -9 -8 mAIOL MAX 8 32 24 8 4 9 8 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT AHC LVC5V
LVC3.3V
LVC2.5V
LVC1.8V
AUC2.5V
AUC1.8V
tPLH 8 3 3.7 4 5 2.1 2.4tPHL 8 3 3.7 4 5 2.1 2.4UNIT:ns
OUTPUT
Y
MAX or MIN
MAXA
29
A2 4
Y
Logic Diagram
OUTPUTY
INPUTA
HLH
L
FUNCTION TABLE
1G06SINGLE INVERTER BUFFER/DRIVER WITH OPEN-DRAIN OUTPUT
A2 4
Y
Logic Diagram
OUTPUTY
INPUTA
HL
HL
FUNCTION TABLE
1G07SINGLE BUFFER/DRIVER WITH OPEN-DRAIN OUTPUT
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LVC5V
LVC3.3V
LVC2.5V
LVC1.8V
AUC2.5V
AUC1.8V UNIT
ICC MAX 0.01 0.01 0.01 0.01 0.01 0.01 mAVO MAX 5.5 5.5 5.5 5.5 2.7 2.7 VIOL MAX 32 24 8 4 9 8 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT LVC5V
LVC3.3V
LVC2.5V
LVC1.8V
AUC2.5V
AUC1.8V
tPLH 3 4 4 5.6 1.8 2.5tPHL 3 4 4 5.6 1.8 2.5UNIT:ns
MAX or MIN
Y MAXA
OUTPUT
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LVC5V
LVC3.3V
LVC2.5V
LVC1.8V
AUC2.5V
AUC1.8V UNIT
ICC MAX 0.01 0.01 0.01 0.01 0.01 0.01 mAIOH MAX 5.5 5.5 5.5 5.5 2.7 2.7 VIOL MAX 32 24 8 4 9 8 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT LVC5V
LVC3.3V
LVC2.5V
LVC1.8V
AUC2.5V
AUC1.8V
tPLH 3.5 4.2 5.5 8.3 1.8 2.5tPHL 3.5 4.2 5.5 8.3 1.8 2.5UNIT:ns
MAX
OUTPUT MAX or MIN
A Y
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
30
1
24A
BY
Logic Diagram
INPUT
L
BA
L
OUTPUTYH
LX
X
HHL
FUNCTION TABLE
1G08SINGLE 2-INPUT POSITIVE-AND GATE
Y = AB
A Y2 4
Logic Diagram
OUTPUTY
INPUTA
LHL H
FUNCTION TABLE
1G14SINGLE SCHMITT-TRIGGER INVERTER GATE
Y = A
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN AHC AHCT LVC5V
LVC3.3V
LVC2.5V
LVC1.8V
AUC2.5V
AUC1.8V UNIT
ICC MAX 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 mAIOH MAX -8 -8 -32 -24 -8 -4 -9 -8 mAIOL MAX 8 8 32 24 8 4 9 8 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT AHC AHCT LVC5V
LVC3.3V
LVC2.5V
LVC1.8V
AUC2.5V
AUC1.8V
tPLH 9 9 4 4.5 5.5 8 2 2.4tPHL 9 9 4 4.5 5.5 8 2 2.4UNIT:ns
OUTPUT
Y
MAX or MIN
MAXA or B
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN AHC AHCT LVC5V
LVC3.3V
LVC2.5V
LVC1.8V
AUC2.5V
AUC1.8V UNIT
ICC MAX 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 mAIOH MAX -8 -8 -32 -24 -8 -4 -9 -8 mAIOL MAX 8 8 32 24 8 4 9 8 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT AHC AHCT LVC5V
LVC3.3V
LVC2.5V
LVC1.8V
AUC2.5V
AUC1.8V
tPLH 12 9 5 5.5 6.5 11 2.5 2.5tPHL 12 9 5 5.5 6.5 11 2.5 2.5UNIT:ns
MAX or MIN
Y MAXA
OUTPUT
31
A Y2 4
Logic Diagram
OUTPUTY
INPUTA
HL
HL
FUNCTION TABLE
1G17SINGLE SCHMITT-TRIGGER BUFFER
AY 13
S1
Y06
4
Logic Diagram
FUNCTION TABLEINPUTSS
ZH
LLH
A
HL
LLHZ
H
HL
ZZ
OUTPUTY1Y0
1G181-OF-2 NONINVERTING DEMULTIPLEXERWITH 3-STATE DESELECTED OUTPUT
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LVC5V
LVC3.3V
LVC2.5V
LVC1.8V
AUC2.5V
AUC1.8V UNIT
ICC MAX 0.01 0.01 0.01 0.01 0.01 0.01 mAIOH MAX -32 -24 -8 -4 -9 -8 mAIOL MAX 32 24 8 4 9 8 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT LVC5V
LVC3.3V
LVC2.5V
LVC1.8V
AUC2.5V
AUC1.8V
tPLH 5 5.5 6.5 11 2.5 2.4tPHL 5 5.5 6.5 11 2.5 2.4UNIT:ns
MAX
OUTPUT MAX or MIN
YA
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LVC5V
LVC3.3V
LVC2.5V
LVC1.8V UNIT
ICC MAX 0.01 0.01 0.01 0.01 mAIOH MAX -32 -24 -8 -4 mAIOL MAX 32 24 8 4 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT LVC5V
LVC3.3V
LVC2.5V
LVC1.8V
tPLH 3.2 4.2 5 9.3tPHL 3.2 4.2 5 9.3tPZL 3.4 4.6 5.6 10.2tPZH 3.4 4.6 5.6 10.2tPLZ 3.3 4.9 5.3 12.7tPHZ 3.3 4.9 5.3 12.7UNIT:ns
MAX or MIN
MAX
MAX
MAX
OUTPUT
Y
Y
Y
A
S
S
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
32
1
24A
BY
Logic Diagram
INPUTBA
L
OUTPUTY
LH
XX HH
L
H
FUNCTION TABLE
1G32SINGLE 2-INPUT POSITIVE-OR GATE
Y = A + B
B
C
A1
4
2
Logic Diagram
SWITCHICONTROL
INPUT(C)
ONOFFL
H
FUNCTION TABLE
1G66SINGLE ABILATERAL ANALOG SWITCH
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN AHC AHCT LVC5V
LVC3.3V
LVC2.5V
LVC1.8V
AUC2.5V
AUC1.8V UNIT
ICC MAX 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 mAIOH MAX -8 -8 -32 -24 -8 -4 -9 -8 mAIOL MAX 8 8 32 24 8 4 9 8 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT AHC AHCT LVC5V
LVC3.3V
LVC2.5V
LVC1.8V
AUC2.5V
AUC1.8V
tPLH 8.5 9 4 4.5 5.5 8 2.1 2.4tPHL 8.5 9 4 4.5 5.5 8 2.1 2.4UNIT:ns
OUTPUT
Y
MAX or MIN
MAXA or B
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LVC AUC1.8V UNIT
ICC MAX 0.01 0.01 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT LVC5V
LVC3.3V
LVC2.5V
LVC1.8V
AUC2.5V
AUC1.8V
tPLH 0.6 0.8 1.2 2 0.1 0.2tPHL 0.6 0.8 1.2 2 0.1 0.2tPZH 4.2 5 6.5 12 1 1.1tPZL 4.2 5 6.5 12 1 1.1tPHZ 5 6.5 6.9 10 2.2 2.9tPLZ 5 6.5 6.9 10 2.2 2.9UNIT:ns
MAX or MIN
B or A
B or A
B or A
MAX
MAX
MAX
A or B
OUTPUT
C
C
33
C
C
CLK2
Logic Diagram
INPUT OUTPUTD Q
LX
LH
Q0
HCLK
L
→→
FUNCTION TABLE
1G79SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
C
C
CLK 2
Logic Diagram
INPUT OUTPUTD Q
LX
LH
Q0
H
CLK
L
→→
FUNCTION TABLE
1G80SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LVC5V
LVC3.3V
LVC2.5V
LVC1.8V UNIT
ICC MAX 0.01 0.01 0.01 0.01 mAIOH MAX -32 -24 -8 -4 mAIOL MAX 32 24 8 4 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT LVC5V
LVC3.3V
LVC2.5V
LVC1.8V
fmax 160 160 160 160tw 2.5 2.5 2.5 2.5
1.2 1.3 1.4 2.21.2 1.3 1.4 2.6
th 0.5 1.0 0.4 0.3tPLH 4.5 5.2 7 9.9tPHL 4.5 5.2 7 9.9UNIT fmax : MHz other : ns
Data after CLK
MINMIN
MIN
MIN
OUTPUT MAX or MIN
tsu
CLK MAXQ
CLK high or lowBefore CLK , Data highBefore CLK , Data low
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LVC5V
LVC3.3V
LVC2.5V
LVC1.8V UNIT
ICC MAX 0.01 0.01 0.01 0.01 mAIOH MAX -32 -24 -8 -4 mAIOL MAX 32 24 8 4 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT LVC5V
LVC3.3V
LVC2.5V
LVC1.8V
fmax 160 160 160 160tw 2.5 2.5 2.5 2.5
1.1 1.3 1.5 2.31.1 1.3 1.5 2.5
th 0.4 0.9 0.2 0tPLH 4.5 5.2 7 9.9tPHL 4.5 5.2 7 9.9UNIT fmax : MHz other : ns
MAX
MIN
MIN
OUTPUT MAX or MIN
CLK high or lowMINMIN
tsu Before CLK , Data highBefore CLK , Data lowData after CLK
QCLK
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
34
Logic Diagram
INPUT
L
BA
H
H
OUTPUTYL
HL
L
H
L
HL
L H
FUNCTION TABLE
1G86SINGLE 2-INPUT EXCLUSIVE-OR GATE
Y = A ⊕ B = AB + AB
A
OE1
2 4Y
Logic Diagram
INPUT
L
AOE
L
OUTPUTYH
ZX
L H
HL
FUNCTION TABLE
1G125SINGLE BUS BUFFER GATEWITH 3-STATE OUTPUT
Y = A
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN AHC AHCT LVC5V
LVC3.3V
LVC2.5V
LVC1.8V UNIT
ICC MAX 0.01 0.01 0.01 0.01 0.01 0.01 mAIOH MAX -8 -8 -32 -24 -8 -4 mAIOL MAX 8 8 32 24 8 4 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT AHC AHCT LVC5V
LVC3.3V
LVC2.5V
LVC1.8V
tPLH 10 9 4 5 5.5 9.9tPHL 10 9 4 5 5.5 9.9UNIT:ns
OUTPUT
Y
MAX or MIN
MAXA or B
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN AHC AHCT LVC5V
LVC3.3V
LVC2.5V
LVC1.8V
AUC2.5V
AUC1.8V UNIT
ICC MAX 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 mAIOH MAX -8 -8 -32 -24 -8 -4 -9 -8 mAIOL MAX 8 8 32 24 8 4 9 8 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT AHC AHCT LVC5V
LVC3.3V
LVC2.5V
LVC1.8V
AUC2.5V
AUC1.8V
tPLH 8.5 8.5 4 4.5 5.5 8 1.7 2.5tPHL 8.5 8.5 4 4.5 5.5 8 1.7 2.5tPZH 8 8 5 5.3 6.5 9.4 1.9 2.6tPZL 8 8 5 5.3 6.5 9.4 1.9 2.6tPHZ 10 10 4.2 5 5 9.2 1.7 3.1tPLZ 10 10 4.2 5 5 9.2 1.7 3.1UNIT:ns
MAX
MAX
MAX
MAX or MINOUTPUT
Y
Y
Y
A
OE
OE
An exclusive-OR gate has many applications, some of whichcan be represented better by alternative logic symbols.
=1
EXCLUSIVE OR
35
A
OE1
2 4Y
Logic Diagram
INPUT
H
AOE
L
OUTPUTYH
ZX
H H
LL
FUNCTION TABLE
1G126SINGLE BUS BUFFER GATEWITH 3-STATE OUTPUT
Y = A
A
OE1
2 4Y
Logic Diagram
INPUT
L
AOE
L
OUTPUTY
HZX
L H
H
L
FUNCTION TABLE
1G240SINGLE BUFFER/DRIVER WITH 3-STATE OUTPUT
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN AHC AHCT LVC5V
LVC3.3V
LVC2.5V
LVC1.8V
AUC2.5V
AUC1.8V UNIT
ICC MAX 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 mAIOH MAX -8 -8 -32 -24 -8 -4 -9 -8 mAIOL MAX 8 8 32 24 8 4 9 8 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT AHC AHCT LVC5V
LVC3.3V
LVC2.5V
LVC1.8V
AUC2.5V
AUC1.8V
tPLH 8.5 8.5 4 4.5 5.5 8 1.7 2.5tPHL 8.5 8.5 4 4.5 5.5 8 1.7 2.5tPZH 8 8 5 5.3 6.6 9.4 1.9 2.5tPZL 8 8 5 5.3 6.6 9.4 1.9 2.5tPHZ 10 10 4.2 5.5 5.5 9.8 1.7 3.1tPLZ 10 10 4.2 5.5 5.5 9.8 1.7 3.1UNIT:ns
MAX or MIN
MAX
MAX
MAX
OUTPUT
Y
Y
Y
A
OE
OE
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LVC5V
LVC3.3V
LVC2.5V
LVC1.8V
AUC2.5V
AUC1.8V UNIT
ICC MAX 0.01 0.01 0.01 0.01 0.01 0.01 mAIOH MAX -32 -24 -8 -4 -9 -8 mAIOL MAX 32 24 8 4 9 8 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT LVC5V
LVC3.3V
LVC2.5V
LVC1.8V
AUC2.5V
AUC1.8V
tPLH 4 4.5 5.5 8 1.7 2.5tPHL 4 4.5 5.5 8 1.7 2.5tPZH 5.2 5.4 6.5 9.4 1.9 2.6tPZL 5.2 5.4 6.5 9.4 1.9 2.6tPHZ 4.1 5.2 4.9 9.4 1.7 3.1tPLZ 4.1 5.2 4.9 9.4 1.7 3.1UNIT:ns
MAX
OE
OE
MAX or MIN
Y MAX
Y MAX
OUTPUT
Y
A
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
36
1
271A
1B1Y
5
632A
2B2Y
Logic Diagram
INPUT
L
BA
L
OUTPUTYL
HX
X
HHH
FUNCTION TABLE(each gate)
2G00DUAL 2-INPUT POSITIVE-NAND GATE
1A
1B1Y
1
27
2A
2B2Y
5
63
Logic Diagram
INPUTBA
L
OUTPUTY
HL
XX HH
L
L
FUNCTION TABLE(each gate)
2G02DUAL 2-INPUT POSITIVE-NOR GATE
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LVC5V
LVC3.3V
LVC2.5V
LVC1.8V UNIT
ICC MAX 0.01 0.01 0.01 0.01 mAIOH MAX -32 -24 -8 -4 mAIOL MAX 32 24 8 4 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT LVC5V
LVC3.3V
LVC2.5V
LVC1.8V
tPLH 3.3 4.3 4.8 8.6tPHL 3.3 4.3 4.8 8.6UNIT:ns
A or B
OUTPUT
Y
MAX or MIN
MAX
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LVC5V
LVC3.3V
LVC2.5V
LVC1.8V UNIT
ICC MAX 0.01 0.01 0.01 0.01 mAIOH MAX -32 -24 -8 -4 mAIOL MAX 32 24 8 4 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT LVC5V
LVC3.3V
LVC2.5V
LVC1.8V
tPLH 4.4 4.9 5.4 8.9tPHL 4.4 4.9 5.4 8.9UNIT:ns
A or B
OUTPUT MAX or MIN
Y MAX
37
1A 1Y1
2A 2Y3
6
4
OUTPUTY
INPUTA
HLH
L
FUNCTION TABLE(each inverter)
2G04DUAL INVERTER GATE
Logic Diagram
1A 1Y1
2A 2Y3
6
4
OUTPUTY
INPUTA
LHL H
FUNCTION TABLE(each inverter)
2GU04DUAL INVERTER GATE
Logic Diagram
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LVC5V
LVC3.3V
LVC2.5V
LVC1.8V UNIT
ICC MAX 0.01 0.01 0.01 0.01 mAIOH MAX -32 -24 -8 -4 mAIOL MAX 32 24 8 4 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT LVC5V
LVC3.3V
LVC2.5V
LVC1.8V
tPLH 3.2 4.1 4.4 8tPHL 3.2 4.1 4.4 8UNIT:ns
A Y MAX
OUTPUT MAX or MIN
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LVC5V
LVC3.3V
LVC2.5V
LVC1.8V UNIT
ICC MAX 0.01 0.01 0.01 0.01 mAIOH MAX -32 -24 -8 -4 mAIOL MAX 32 24 8 4 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT LVC5V
LVC3.3V
LVC2.5V
LVC1.8V
tPLH 3 3.7 4 5.5tPHL 3 3.7 4 5.5UNIT:ns
A
OUTPUT MAX or MIN
Y MAX
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
38
1A 1Y1
2A 2Y3
6
4
Logic Diagram
OUTPUTY
INPUTA
HLH
L
FUNCTION TABLE(each inverter)
2G06DUAL INVERTER BUFFER/DRIVER WITH OPEN-DRAIN OUTPUTS
1A 1Y1
2A 2Y3
6
4
Logic Diagram
OUTPUTY
INPUTA
HL
HL
FUNCTION TABLE(each buffer/deiver)
2G07DUAL BUFFER/DRIVER WITH OPEN-DRAIN OUTPUTS
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LVC5V
LVC3.3V
LVC2.5V
LVC1.8V UNIT
ICC MAX 0.01 0.01 0.01 0.01 mAVO MAX 5.5 5.5 5.5 5.5 VIOL MAX 32 24 8 4 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT LVC5V
LVC3.3V
LVC2.5V
LVC1.8V
tPLH 2.9 3.4 3.9 7.2tPHL 2.9 3.4 3.9 7.2UNIT:ns
A
OUTPUT MAX or MIN
Y MAX
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LVC5V
LVC3.3V
LVC2.5V
LVC1.8V UNIT
ICC MAX 0.01 0.01 0.01 0.01 mAVO MAX 5.5 5.5 5.5 5.5 VIOL MAX 32 24 8 4 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT LVC5V
LVC3.3V
LVC2.5V
LVC1.8V
tPLH 2.9 3.7 4.4 8.6tPHL 2.9 3.7 4.4 8.6UNIT:ns
A Y MAX
OUTPUT MAX or MIN
39
1
271A
1B1Y
5
632A
2B2Y
Logic Diagram
INPUT
L
BA
L
OUTPUTYH
LX
X
HHL
FUNCTION TABLE(each gate)
2G08DUAL 2-INPUT POSITIVE-AND GATE
1A 1Y1
2A 2Y3
6
4
OUTPUTY
INPUTA
LHL H
FUNCTION TABLE(each inverter)
Logic Diagram2G14DUAL SCHMITT-TRIGGER INVERTER
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LVC5V
LVC3.3V
LVC2.5V
LVC1.8V UNIT
ICC MAX 0.01 0.01 0.01 0.01 mAIOH MAX -32 -24 -8 -4 mAIOL MAX 32 24 8 4 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT LVC5V
LVC3.3V
LVC2.5V
LVC1.8V
tPLH 3.8 4.7 5.1 9tPHL 3.8 4.7 5.1 9UNIT:ns
A or B
OUTPUT MAX or MIN
Y MAX
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LVC5V
LVC3.3V
LVC2.5V
LVC1.8V UNIT
ICC MAX 0.01 0.01 0.01 0.01 mAIOH MAX -32 -24 -8 -4 mAIOL MAX 32 24 8 4 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT LVC5V
LVC3.3V
LVC2.5V
LVC1.8V
tPLH 4.3 5.4 5.7 9.5tPHL 4.3 5.4 5.7 9.5UNIT:ns
A
OUTPUT MAX or MIN
Y MAX
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
40
1A 1Y1
2A 2Y3
6
4
Logic Diagram
OUTPUTY
INPUTA
HL
HL
FUNCTION TABLE(each inverter)
2G17DUAL SCHMITT-TRIGGER BUFFER
1
271A
1B1Y
5
632A
2B2Y
Logic Diagram
INPUTBA
L
OUTPUTY
LH
XX HH
L
H
FUNCTION TABLE(each gate)
2G32DUAL 2-INPUT POSITIVE-OR GATE
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LVC5V
LVC3.3V
LVC2.5V
LVC1.8V UNIT
ICC MAX 0.01 0.01 0.01 0.01 mAIOH MAX -32 -24 -8 -4 mAIOL MAX 32 24 8 4 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT LVC5V
LVC3.3V
LVC2.5V
LVC1.8V
tPLH 4.3 5.4 5.7 9.3tPHL 4.3 5.4 5.7 9.3UNIT:ns
A Y MAX
OUTPUT MAX or MIN
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LVC5V
LVC3.3V
LVC2.5V
LVC1.8V UNIT
ICC MAX 0.01 0.01 0.01 0.01 mAIOH MAX -32 -24 -8 -4 mAIOL MAX 32 24 8 4 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT LVC5V
LVC3.3V
LVC2.5V
LVC1.8V
tPLH 3.2 3.8 4.4 8tPHL 3.2 3.8 4.4 8UNIT:ns
A or B
OUTPUT
Y
MAX or MIN
MAX
41
1A 1Y1
2A 2Y3
6
4
OUTPUTY
INPUTA
LHL
H
FUNCTION TABLE(each gate)
Logic Diagram2G34DUAL BUFFER GATE
CONTROL INPUT
LL
AINHL
ONCHANNELY1
NoneXH
HY2
FUNCTION TABLE
2G53DUAL ANALOG MULTIPLEXER/DEMULTIPLEXER
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LVC5V
LVC3.3V
LVC2.5V
LVC1.8V UNIT
ICC MAX 0.01 0.01 0.01 0.01 mAIOH MAX -32 -24 -8 -4 mAIOL MAX 32 24 8 4 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT LVC5V
LVC3.3V
LVC2.5V
LVC1.8V
tPLH 3.2 4.1 4.4 8.6tPHL 3.2 4.1 4.4 8.6UNIT:ns
A
MAX or MIN
Y MAX
OUTPUT
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LVC5V UNIT
ICC MAX 0.01 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT LVC5V
LVC3.3V
LVC2.5V
LVC1.8V
tPLH 0.6 0.8 1.2 2tPHL 0.6 0.8 1.2 2tPZH 4.5 5.4 6.1 9tPZL 4.5 5.4 6.1 9tPHZ 8 8.1 8.3 10.9tPLZ 8 8.1 8.3 10.9tPZH 5.4 5.8 7.2 10.3tPZL 5.4 5.8 7.2 10.3tPHZ 5 7.2 7.9 9.4tPLZ 5 7.2 7.9 9.4UNIT:ns
A
COM or Y
INH
OUTPUT MAX or MIN
MAX
MAX
Y or COM
COM or Y
COM or Y
MAX
Y2
A
INH
Y1
COM
5
2
7
6
1
SW
SW
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
42
1B
1C
1A 1
7
2
One of Two Switches
Logic Diagram, each switch
SWITCHICONTROL
INPUT(C)
ONOFFL
H
FUNCTION TABLE(each section)
2G66DUAL BILATERAL ANALOG SWITCH
2G74SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
RECOMMENDED OPERATING CONDITIONS
PARAMETER LVC UNIT
ICC 0.01 mA
MAX or MIN
MAX
SWITCHING CHARACTERISTICS
PARAMETER LVC5V
LVC3.3V
LVC2.5V
LVC1.8V
tPLH 0.6 0.8 1.2 2tPHL 0.6 0.8 1.2 2tPZH 3.9 4.4 5.6 10tPZL 3.9 4.4 5.6 10tPHZ 6.3 7.2 6.9 10.5tPLZ 6.3 7.2 6.9 10.5UNIT:ns
C
C
MAX
OUTPUT
B or A
A or B
A or B
MAX or MIN
MAX
MAX
INPUT
A or B
RECOMMENDED OPERATING CONDITIONS
PARAMETER LVC5V
LVC3.3V
LVC2.5V
LVC1.8V UNIT
ICC 0.01 0.01 0.01 0.01 mAIOH -32 -16 -8 -4 mAIOL 32 16 8 4 mAMAX
MAX or MIN
MAXMAX
SWITCHING CHARACTERISTICS
PARAMETER LVC5V
LVC3.3V
LVC2.5V
LVC1.8V
fmax 200 175 175 802 2.7 2.7 6.22 2.7 2.7 6.2
1.1 1.3 1.7 2.91 1.2 1.4 1.9
th 0.5 1.2 0.3 0tPLH 4.1 5.9 7.1 13.4tPHL 4.1 5.9 7.1 13.4tPLH 4.4 6.2 7.7 14.4tPHL 4.4 6.2 7.7 14.4tPLH 4.1 5.9 7 12.9tPHL 4.1 5.9 7 12.9UNIT:ns
MAX
MIN
MIN
MIN
MIN
PRE or CLR low
OUTPUT
PRE or CLR inactive
INPUT
CLK
MAX or MIN
Q or Q
MAX
MAX
tsu Data
tw
CLK
CLK
PRE or CLR
Q
Q
† This configuration is nonstable; that is, it does not persist when PRE or CLR returns to its inactive (high) level.
PRE QCLRINPUT
XH
D QCLK
H
X
OUTPUT
H
H†X
L
H
X
LXX
L
H
H
HLH
HLH
X Q0H
LL
→→
LL
H†LHQ0
H
FUNCTION TABLE
TG
C
C
TG
C
C
TG
C
C
C
TG
C
C
PRE
CLK
D
CLR
Q
QC
7
2
6
5
3
1
Logic Diagram
43
2G86DUAL 2-INPUT EXCLUSIVE-OR GATE
1A 1Y
1OE1
2
2A 2Y
2OE7
5
6
3
Logic Diagram
INPUT
L
AOE
L
OUTPUTYH
ZX
L H
HL
FUNCTION TABLE(each buffer)
2G125DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS
RECOMMENDED OPERATING CONDITIONS
PARAMETER LVC5V
LVC3.3V
LVC2.5V
LVC1.8V UNIT
ICC 0.01 0.01 0.01 0.01 mAIOH -32 -24 -8 -4 mAIOL 32 24 8 4 mAMAX
MAX or MIN
MAXMAX
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LVC5V
LVC3.3V
LVC2.5V
LVC1.8V UNIT
ICC MAX 0.01 0.01 0.01 0.01 mAIOH MAX -32 -24 -8 -4 mAIOL MAX 32 24 8 4 mA
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LVC5V
LVC3.3V
LVC2.5V
LVC1.8V UNIT
ICC MAX 0.01 0.01 0.01 0.01 mAIOH MAX -32 -24 -8 -4 mAIOL MAX 32 24 8 4 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT LVC5V
LVC3.3V
LVC2.5V
LVC1.8V
tPLH 3.7 4.3 4.8 9.1tPHL 3.7 4.3 4.8 9.1tPZH 3.8 4.7 5.6 9.9tPZL 3.8 4.7 5.6 9.9tPHZ 3.4 4.6 5.8 11.6tPLZ 3.4 4.6 5.8 11.6UNIT:ns
OE
A
OUTPUT
Y
Y
Y
MAX or MIN
MAX
MAX
MAX
OE
INPUT
L
BA
H
H
OUTPUTYL
HL
L
H
L
HL
L H
FUNCTION TABLE(each gate)
Logic Diagram
An exclusive-OR gate has many applications, some of whichcan be represented better by alternative logic symbols.
=1
EXCLUSIVE OR
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
44
1A 1Y
1OE1
2
2A
2OE7
52Y
6
3
Logic Diagram
INPUT
H
AOE
L
OUTPUTYH
ZX
H H
LL
FUNCTION TABLE(each buffer)
2G126DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS
2G157SINGLE 2-LINE TO 1-LINE DATA SELECTOR/MULTIPLEXER
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LVC5V
LVC3.3V
LVC2.5V
LVC1.8V UNIT
ICC MAX 0.01 0.01 0.01 0.01 mAIOH MAX -32 -24 -8 -4 mAIOL MAX 32 24 8 4 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT LVC5V
LVC3.3V
LVC2.5V
LVC1.8V
tPLH 3.2 4 4.9 9.8tPHL 3.2 4 4.9 9.8tPZH 3.1 4.1 5 10tPZL 3.1 4.1 5 10tPHZ 3.3 4.4 5.7 12.6tPLZ 3.3 4.4 5.7 12.6UNIT:ns
OE Y MAX
Y MAX
OUTPUT MAX or MIN
Y MAX
OE
A
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LVC5V
LVC3.3V
LVC2.5V
LVC1.8V UNIT
ICC MAX 0.01 0.01 0.01 0.01 mAIOH MAX -32 -24 -8 -4 mAIOL MAX 32 24 8 4 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT LVC5V
LVC3.3V
LVC2.5V
LVC1.8V
tPLH 4 6 8 14tPHL 4 6 8 14tPLH 4 6 9 16tPHL 4 6 9 16tPLH 4 6 8 14tPHL 4 6 8 14UNIT:ns
A or B
A/B
G
OUTPUT
Y or Y
Y or Y
Y or Y
MAX or MIN
MAX
MAX
MAX
1
2
7
6G
A/B
B
A
5Y
Y3
Logic Diagram
G YA/BINPUT
XHB YA
L
X
OUTPUT
L
H
H
XL
X
LLL
XX
HL
X
HH
LH
LL L
L
L
LH
H
FUNCTION TABLE
45
1
2
7
5 3
61A 1Y
2A 2Y
1OE
2OE
Logic Diagram2G240DUAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
1
2 61Y
1OE
1A
7
5 32Y
2OE
2A
Logic Diagram
INPUT
L
1A1OE
L
OUTPUT1YH
ZX
L H
HL
INPUT
L
2A2OE
L
OUTPUT2YH
ZX
HHH
L
FUNCTION TABLE
2G241DUAL BUFFER/DRIVER WITH 3-STATE OUTPUTS
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LVC5V
LVC3.3V
LVC2.5V
LVC1.8V UNIT
ICC MAX 0.01 0.01 0.01 0.01 mAIOH MAX -32 -24 -8 -4 mAIOL MAX 32 24 8 4 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT LVC5V
LVC3.3V
LVC2.5V
LVC1.8V
tPLH 4 4.6 5.5. 11.3tPHL 4 4.6 5.5 11.3tPZH 5 5.4 6.6 11.7tPZL 5 5.4 6.6 11.7tPLZ 4.2 5.5 5.7 12.8tPHZ 4.2 5.5 5.7 12.8UNIT:ns
OE
A
OE
OUTPUT
Y
Y
Y
MAX or MIN
MAX
MAX
MAX
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LVC5V
LVC3.3V
LVC2.5V
LVC1.8V UNIT
ICC MAX 0.01 0.01 0.01 0.01 mAIOH MAX -32 -24 -8 -4 mAIOL MAX 32 24 8 4 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT LVC5V
LVC3.3V
LVC2.5V
LVC1.8V
tPLH 3.7 4.3 4.8 8.8tPHL 3.7 4.3 4.8 8.8tPZL 3.8 4.7 5.6 9.9tPZH 3.8 4.7 5.6 9.9tPLZ 3.4 4.4 5.8 11.6tPHZ 3.4 4.4 5.8 11.6tPZL 3.3 4.1 4.7 8.8tPZH 3.3 4.1 4.7 8.8tPLZ 3.3 4.2 5.2 12.5tPHZ 3.3 4.2 5.2 12.5UNIT:ns
A
OE Y
YOE
OE
OE
Y
Y
MAX or MIN
MAX
OUTPUT
Y
MAX
MAX
MAX
MAX
INPUT
L
AOE
L
OUTPUTY
HZX
L H
H
L
FUNCTION TABLE(each buffer)
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
46
1A 1Y1
2A 2Y3
3A 3Y6
7
5
2
Logic Diagram
OUTPUTY
INPUTA
HLH
L
FUNCTION TABLE(each inverter)
3G04TRIPLE INVERTER GATE
1A 1Y1
2A 2Y3
3A 3Y6
7
5
2
Logic Diagram
OUTPUTY
INPUTA
HLH
L
FUNCTION TABLE(each inverter)
3G06TRIPLE INVERTER BUFFER/DRIVER WITH OPEN-DRAIN OUTPUTS
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LVC5V
LVC3.3V
LVC2.5V
LVC1.8V UNIT
ICC MAX 0.01 0.01 0.01 0.01 mAIOH MAX -32 -24 -8 -4 mAIOL MAX 32 24 8 4 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT LVC5V
LVC3.3V
LVC2.5V
LVC1.8V
tPLH 3.2 4.1 4.4 7.9tPHL 3.2 4.1 4.4 7.9UNIT:ns
OUTPUT
Y
MAX or MIN
MAXA
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LVC5V
LVC3.3V
LVC2.5V
LVC1.8V UNIT
ICC MAX 0.01 0.01 0.01 0.01 mAVO MAX 5.5 5.5 5.5 5.5 VIOL MAX 32 24 8 4 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT LVC5V
LVC3.3V
LVC2.5V
LVC1.8V
tPLH 2.9 3.4 3.9 7.2tPHL 2.9 3.4 3.9 7.2UNIT:ns
MAX or MIN
Y MAXA
OUTPUT
47
1A 1Y1
2A 2Y3
3A 3Y6
7
5
2
Logic Diagram
OUTPUTY
INPUTA
HL
HL
FUNCTION TABLE(each buffer/driver)
3G07TRIPLE BUFFER/DRIVER WITH OPEN-DRAIN OUTPUTS
1A 1Y1
2A 2Y3
3A 3Y6
7
5
2
Logic Diagram
OUTPUTY
INPUTA
LHL H
FUNCTION TABLE(each inverter)
3G14TRIPLE SCHMITT-TRIGGER INVERTER
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LVC5V
LVC3.3V
LVC2.5V
LVC1.8V UNIT
ICC MAX 0.01 0.01 0.01 0.01 mAVO MAX 5.5 5.5 5.5 5.5 VIOL MAX 32 24 8 4 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT LVC5V
LVC3.3V
LVC2.5V
LVC1.8V
tPLH 2.9 3.7 4.3 7.8tPHL 2.9 3.7 4.3 7.8UNIT:ns
MAX
OUTPUT MAX or MIN
A Y
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LVC5V
LVC3.3V
LVC2.5V
LVC1.8V UNIT
ICC MAX 0.01 0.01 0.01 0.01 mAIOH MAX -32 -24 -8 -4 mAIOL MAX 32 24 8 4 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT LVC5V
LVC3.3V
LVC2.5V
LVC1.8V
tPLH 4.3 5.4 5.7 9.2tPHL 4.3 5.4 5.7 9.2UNIT:ns
OUTPUT
Y
MAX or MIN
MAXA
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
48
1A 1Y1
2A 2Y3
3A 3Y6
7
5
2
Logic Diagram
OUTPUTY
INPUTA
HL
HL
FUNCTION TABLE
3G17TRIPLE SCHMITT-TRIGGER BUFFER
1A 1Y1
2A 2Y3
3A 3Y6
7
5
2
Logic Diagram
OUTPUTY
INPUTA
LHL
H
FUNCTION TABLE(each gate)
3G34TRIPLE BUFFER GATE
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LVC5V
LVC3.3V
LVC2.5V
LVC1.8V UNIT
ICC MAX 0.01 0.01 0.01 0.01 mAIOH MAX -32 -24 -8 -4 mAIOL MAX 32 24 8 4 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT LVC5V
LVC3.3V
LVC2.5V
LVC1.8V
tPLH TBD TBD TBD TBDtPHL TBD TBD TBD TBDUNIT:ns
MAX or MIN
MAXA
OUTPUT
Y
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LVC5V
LVC3.3V
LVC2.5V
LVC1.8V UNIT
ICC MAX 0.01 0.01 0.01 0.01 mAIOH MAX -32 -24 -8 -4 mAIOL MAX 32 24 8 4 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT LVC5V
LVC3.3V
LVC2.5V
LVC1.8V
tPLH 3.2 4.1 4.4 7.9tPHL 3.2 4.1 4.4 7.9UNIT:ns
MAX
OUTPUT MAX or MIN
A Y
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
FUNCTION
51
GATE (AND/NAND/OR/NOR)
Bipolar CMOS BiCMOS Advanced CMOS
TT
L
LS S
AL
S
AS F HC
HC
T
BC
T
AB
T
LV
T
AL
VT
AC
AC
T
AH
C
AH
CT
LV
LV
C
AL
VC
AV
C
08 × / / // // A A OC 09 × × ×/- OC 15 × × × BUF 1008 ×A A
SCH 7001 /- 6 BUF 808 × B ×/-
BUF 1808 × × 11 × A / -/ ×//- ×//- A
BUF 1011 × 4 2 21 A / ×/ ×/-/- ×/-/- A
2 8003 × 00 A / / // // A A
OC 01 × × × ×/- OC 03 × × B / -/
SCH 24 × OC 26 × BUF 37 × A × OC 38 B
SCH 132 × × / -/ ×/-/- ×/-/- ABUF 1000 ×A A OC 1003 ×A
SCH OC 7003 ×/- OC 39 × BUF 804 A B ×/- BUF 1804 ×A ×
10 A / -/ ×// ×// A A OC 12 × × × BUF 1010 ×
SCH 13 × × ×/-/- -/×/-SCH 18 ×
20 × × A / -/ ×/×/ ×/×/ AOC 22 × × × × BUF 40 × × × × × BUF 140 BUF 1020 ×
3 SCH 618 × 8 1 30 × × A ×/ -/ ×/-/× /-/×
12 1 3S 134 × 13 1 133 × ×/-
32 / / // // A A BUF 1032 × A
SCH 7032 /- BUF 832 A B ×/- BUF 1832 ×A ×
3 3 4075 ×/ -/
02 A / / ×/-/ ×/-/ A ABUF 28 × × × OC 33 × A
36 × ×/- BUF 128 BUF 1002 ×A
SCH 7002 /- BUF 1036 ×A BUF 805 A B ×/- BUF 1805 × ×
3 3 27 × A / -/ ×/-/× ×/-/× A23 × 25
4002 ×/ 5 2 260
Explanatory notes [Input] SCH:Schmitt-Trigger Inputs
Explanatory notes [Output] BUF:Buffered Output OC:Open-Collector Output 3S:3-State Output
Status :Product available in technology indicated *:New product planned in technology indicated
Status ×:Discontinued :Not recommended for new designs
Status HC:SN74HCxx / CD74HCxx
Status HCT:SN74HCxx / CD74HCTxx
Status BCT:SN74BCTxx / SN64BCTxx
Status AC:74AC11xxx (Product available in reduced-noise advanced CMOS:11000 Series) / SN74ACxx / CD74ACxx
Status ACT:74ACT11xxx (Product available in reduced-noise advanced CMOS:11000 Series) / SN74ACTxx / CD74ACTxx
Technology
Output
POS- NOR
24
6
4 2
2
POS- OR2
4
6
POS-NAND
4
4
6
3 3
2
POS-AND
2
3 3
4
Description No. ofInput DeviceCurcuit Input
52
GATE (EX-OR/EX-NOR/INVERTER/NONINVERTER/etc.)
Bipolar CMOS BiCMOS Advanced CMOS
TT
L
LS S
AL
S
AS F HC
HC
T
BC
T
AB
T
LV
T
AL
VT
AC
AC
T
AH
C
AH
CT
LV
LV
C
AL
VC
AV
C
86 × A A / -/ // ×// A AOC 136 × × ×
386 × ×/-
OC 266 /- 810 × × ×/-/- ×/-/-
OC 811 × × 7266 ×/
EX-OR/NOR 2 4 135 ×
04 B / / // // A A OC 05 × A /- -/-/ -/-/ AOC 06 A A
SCH 14 / / ×// ×// A A OC 16
SCH 19 A BUF 1004 A OC 1005
4049 ー/U04 / A A
8 SCH 619 ×
425 × 426 ×
OC 07 A AOC 17
34 × × ×/-/- ×/-/-OC 35 A BUF 1034 A OC 1035
4050 ー/
1 6 63 × 2 6 31
50 × 51 × × × ×/- ×/-/- ×/-/-60 × 53 × 55 ×
4078 ×/- 10 1 54 × ×
64 × × ×/-/- ×/-/-OC 65 × BUF 800 ×/-/- ×/-/-BUF 802 ×/-/- ×/-/-
7006 ×/- 7008 ×/- 7074 ×/- 7075 ×/- 7076 ×/-
Explanatory notes [Input] SCH:Schmitt-Trigger Inputs
Explanatory notes [Output] BUF:Buffered Output OC:Open-Collector Output 3S:3-State Output
Status :Product available in technology indicated *:New product planned in technology indicated
Status ×:Discontinued :Not recommended for new designs
Status HC:SN74HCxx / CD74HCxx
Status HCT:SN74HCxx / CD74HCTxx
Status BCT:SN74BCTxx / SN64BCTxx
Status AC:74AC11xxx (Product available in reduced-noise advanced CMOS:11000 Series) / SN74ACxx / CD74ACxx
Status ACT:74ACT11xxx (Product available in reduced-noise advanced CMOS:11000 Series) / SN74ACTxx / CD74ACTxx
12 3
-
Technology
Input Output Device
4
1
11 1
2
8
6
4
EX-OR 2 4
EX-NOR 2
61
OTHER
Description No. ofInput Curcuit
INVERTING
NON-INVERTING 1
6
4
53
BUFFER/DRIVER(NON-INVERTING)
Bipolar CMOS BiCMOS Advanced CMOS
TT
L
LS S
AL
S
AS F HC
HC
T
BC
T
AB
T
LV
T
AL
VT
AC
AC
T
AH
C
AH
CT
LV
LV
C
AL
VC
AV
C
3S 125 × A / / A/A H A A 3S 126 × A / -/ ×A/A H A A 3S 365 × A / -/ 3S 367 × A / -/ A 3S 241 C A / ×/ /- A H ×//- ×// -
3S 244 C/C1 A / / / A
B/T/
HA/Z
// // AA/
HA/ZA
/H
3S 455 ×/- 3S 465 × 3S 467 × × 3S 541 /1 / / A/- B H -/-/ -/-/ A A3S 656 ×/-/- ×/-/- 3S 747 × OC 757 / OC 760 /- 3S 1241 3S 1244 A
R3S 2241 /- R3S 2244 × /- A AR3S 2541 3S 25241 ×/- 3S 25244 / OC 25757 ×/- OC 25760 ×/- 3S 827 ×/-/- ×/-/- A
R3S 2827 C/- 3S 29827 B/-
11 R3S 5400 A 3S 5402 A
R3S 16903 H3S 16241 A H × H×A
3S 16244 A/ H
B/HA H
A/HA/ZA
A/H
3S 16541 A H HA ×R3S 162241 H
R3S 162244 A/H H A/HA H
R3S 162541 H ×3S 16825 H
R3S 162825
3S 16835 H /H
R3S 162835 /H
3S 16827 H H 3S 162827 A H H
32 3S 32244 /H H /H H
Explanatory notes [Output] 3S:3-State Output R3S:Series Resistor and 3-State Output OC:Open-Collector Output
Status :Product available in technology indicated *:New product planned in technology indicated
Status ×:Discontinued :Not recommended for new designs
Status HC:SN74HCxx / CD74HCxx
Status HCT:SN74HCxx / CD74HCTxx
Status BCT:SN74BCTxx / SN64BCTxx
Status AC:74AC11xxx (Product available in reduced-noise advanced CMOS:11000 Series) / SN74ACxx / CD74ACxx
Status ACT:74ACT11xxx (Product available in reduced-noise advanced CMOS:11000 Series) / SN74ACTxx / CD74ACTxx
Description No. ofOutput Output
Technology
20
Device
18
4
6
8
NON-INVERTING
10
12
16
54
BUFFER/DRIVER(INVERTING、INVERTING AND NON-INVERTING、ADDRESS DRIVERS)
Bipolar CMOS BiCMOS Advanced CMOS
TT
L
LS S
AL
S
AS F HC
HC
T
BC
T
AB
T
LV
T
AL
VT
AC
AC
T
AH
C
AH
CT
LV
LV
C
AL
VC
AV
C
3S 366 × × ×/ 3S 368 × A / -/ 3S 436 × 3S 437 × 3S 231 × ×
3S 240 A/A1 A / / /- A A/H // // A A/
ZA3S 456 ×/- 3S 466 × × 3S 468 × × 3S 540 /1 × / / A/- H -/-/ -/-/ A A3S 655 ×/-/- ×/-/- 3S 746 × OC 756 × /- OC 763 × 3S 1240 ×
R3S 2240 × /- A R3S 2540 × 3S 25240 ×/- OC 25756 ×/- 3S 828 ×/-/- ×/-/- A
R3S 2828 ×/- 3S 29828 ×B/-
11 R3S 5401 12 R3S 5403
3S 16240 A /H H × HA/ZA H
3S 16540 A × HA ×R3S 162240 /H -R3S 162540 ×
20 3S 16828 × ×32 3S 32240
3S 230 × ×
OC 762 ×
3S 16830 H*
R3S 162830 H/HS
3S 16344 H3S 16831 H3S 16832 H
R3S 162344 HR3S 162831 /HR3S 162832 H
Explanatory notes [Output] 3S:3-State Output R3S:Series Resistor and 3-State Output OC:Open-Collector Output
Status :Product available in technology indicated *:New product planned in technology indicated
Status ×:Discontinued :Not recommended for new designs
Status HC:SN74HCxx / CD74HCxx
Status HCT:SN74HCxx / CD74HCTxx
Status BCT:SN74BCTxx / SN64BCTxx
Status AC:74AC11xxx (Product available in reduced-noise advanced CMOS:11000 Series) / SN74ACxx / CD74ACxx
Status ACT:74ACT11xxx (Product available in reduced-noise advanced CMOS:11000 Series) / SN74ACTxx / CD74ACTxx
Description No. ofOutput Output
16
6
8
Device
Technology
ADDRESSDRIVERS
1-2
1-4
INVERTINGANDNON-
INVERTING
8
INVERTING
10
55
BUS TRANSCEIVER(NON-INVERTING)
Bipolar CMOS BiCMOS Advanced CMOS
TT
L
LS S
AL
S
AS F HC
HC
T
BC
T
AB
T
LV
T
AL
VT
AC
AC
T
AH
C
AH
CT
LV
LV
C
AL
VC
AV
C
3S 226 ×
3S 440 × OC 441 × 3S 442 3S 443 × 3S 444 × OC 448 × 3S 449 × 3S 243 A × × -/ -/ 3S 1243
3S 245 A/A1
/ / / B/H
B/ HA/ R
// // AA/
HA/ZA
/H
3S 470 ×/-/- ×/-/- 3S 472 ×/-/- ×/-/- 3S 474 ×/-/- ×/-/- 3S 543 /- A H ×/-/- /-/- AOC 615 ×
OC 621 × A/A1
× ×
3S 623 A × × /- /- /- ×/-/ /-/ 3SOC 639 × A ×
OC 641 A/A1
3S 645 /1
A/A1
/- /-
3S 646 A / / /- /A H ×/-/ ×/-/ A
OC 647 × ×
3S 652 A / / /- /A H ×/-/ /-/ A
3SOC 654 × 3S 657 ×/- A ×/-/- ×/-/- 3S 659 ×/- ×/- 3S 665 ×/- ×/- 3S 852 × ×/-/- ×/-/- 3S 856 × ×/-/- ×/-/- 3S 877 × ×/-/- ×/-/- 3S 899 ×/- 3S 1245 A 3S 1645 A 3S 2245 /- /R H RA3S 2623 × 3S 2645 × 3S 2952 ×/- A H A3S 25245 /- H 3S 25543 ×/- 3S 25621 ×/- 3S 25623 ×/- 3S 25641 ×/- 3S 25646 ×/- 3S 25647 ×/- 3S 25652 ×/- 3S 25654 ×/- 3S 3245 × CA
3S 4245 A/CA
3SOC 833 ×/-/- ×/-/-3SOC 853 ×/-/- ×/-/- 3SOC 29833 × ×/- 3SOC 29853 × ×/-
3S 863 ×/-/- ×/-/- A3S 29863 B/-
3S 16409 H/HR
3S 861 ×/-/- ×/-/- A3S 29861 × ×B/-
Explanatory notes [No. of Output] +P:With Parity Bit
Explanatory notes [Output] 3S:3-State Output R3S:Series Resistor and 3-State Output
Explanatory notes [Output] OC:Open-Collector Output 3SOC:3-State Output / Open-Collector Output
Status :Product available in technology indicated *:New product planned in technology indicated
Status ×:Discontinued :Not recommended for new designs
Status HC:SN74HCxx / CD74HCxx
Status HCT:SN74HCxx / CD74HCTxx
Status BCT:SN74BCTxx / SN64BCTxx
Status AC:74AC11xxx (Product available in reduced-noise advanced CMOS:11000 Series) / SN74ACxx / CD74ACxx
Status ACT:74ACT11xxx (Product available in reduced-noise advanced CMOS:11000 Series) / SN74ACTxx / CD74ACTxx
Output DeviceDescription No. ofOutput
Technology
NON-INVERTING
4
8
8+1P
9
9X4
10
56
BUS TRANSCEIVER (NON-INVERTING)
Bipolar CMOS BiCMOS Advanced CMOS
TT
L
LS S
AL
S
AS F HC
HC
T
BC
T
AB
T
LV
T
AL
VT
AC
AC
T
AH
C
AH
CT
LV
LV
C
AL
VC
AV
C
3S 16268 ×
3S 16269 H/HRA
3S 16270 H3S 16271 H3S 16272 ×3S 162268 H3S 162269 3S 162280 HG
3S 16245 A/H
B/HA H *
A/HA/
HRA/ZA
H/HR
3S 16334 /H 3S 16470 ×
3S 16543 H * × /HA H
3S 16623 × 3S 16646 H × HA H 3S 16652 H * HA ×3S 16952 H HA H
R3S 162245 /H A/H H R
R3S 164245 /H
R3S 162334 /H3S 32316 H 3S 32318 H 3S 16657 3S 16833 × 3S 16853 × 3S 16472 × 3S 16474 × 3S 16500 B H H3S 16501 H H3S 16525 H3S 16600 - H
3S 16601 H - H/HR
3S 16834 3S 16863 H3S 16901 H H
R3S 162500 R3S 162501 R3S 162525 HR3S 162600
R3S 162601 H/HR×
R3S 162834 3S 16282 H
R3S 162282 HG3S 16836 H* *3S 16861
R3S 162836 /H3S 32543 H 3S 32952 ×
3S 32245 H H / HA H
3S 32500 × 3S 32501 H H
Explanatory notes [No. of Output] +P:With Parity Bit
Explanatory notes [Output] 3S:3-State Output R3S:Series Resistor and 3-State Output
Explanatory notes [Output] OC:Open-Collector Output 3SOC:3-State Output / Open-Collector Output
Status :Product available in technology indicated *:New product planned in technology indicated
Status ×:Discontinued :Not recommended for new designs
Status HC:SN74HCxx / CD74HCxx
Status HCT:SN74HCxx / CD74HCTxx
Status BCT:SN74BCTxx / SN64BCTxx
Status AC:74AC11xxx (Product available in reduced-noise advanced CMOS:11000 Series) / SN74ACxx / CD74ACxx
Status ACT:74ACT11xxx (Product available in reduced-noise advanced CMOS:11000 Series) / SN74ACTxx / CD74ACTxx
Output Device
NON-INVERTING
12/24
16/32
Technology
32
36
16
16X3
20
16+2P
18
18/36
18X3
Description No. ofOutput
57
BUS TRANSCEIVER(INVERTING、NON-INVERTING/INVERTING)
Bipolar CMOS BiCMOS Advanced CMOS
TT
L
LS S
AL
S
AS F HC
HC
T
BC
T
AB
T
LV
T
AL
VT
AC
AC
T
AH
C
LV
LV
C
AL
VC
AV
C
3S 242 × × × × ×/- ×/- 3S 446 × 3S 1242 ×
R3S 2242 × 3S 544 × ×/- ×/-/- ×/-/- 3S 471 ×/-/- ×/-/- 3S 473 ×/-/- ×/-/- 3S 475 ×/-/- ×/-/- OC 614 × 3S 620 × A × × ×/- ×/- ×/- ×/-/- ×/-/- OC 622 × × × ×
3SOC 638 × A/A1 A
3S 640 /1
B/B1
/ ×/ /- ×/-/- ×/-/-
OC 642 /1
A/A1
× ×/-
3S 648 A ×/- ×/- ×/- ×/-/- ×/-/- OC 649 × × 3S 651 × A × ×/- ×/- ×/- ×/-/- ×/-/
3SOC 653 × 3S 658 ×/- ×/- 3S 664 ×/- ×/- 3S 1640 × 3S 2620 × 3S 2640 × ×/- 3S 2953 ×/- 3S 25620 ×/- 3S 25622 ×/- 3S 25640 ×/- 3S 25642 /- 3S 25648 ×/- 3S 25649 ×/- 3S 25651 ×/- 3S 25653 ×/-
3SOC 834 ×/-/- ×/-/- 3SOC 854 ×/-/- ×/-/- 3SOC 29834 × ×/- 3SOC 29854 /-
3S 864 ×/-/- ×/-/- 3S 29864 × B/- 3S 862 ×/-/- ×/-/- 3S 29862 × ×B/- 3S 16471 3S 16544 × 3S 16620 × × 3S 16640 × × 3S 16648 × 3S 16651 3S 16862 3S 16953 × 3S 16475 × 3S 16524 H3S 16864 ×
3S 643 × × × ×/- ×/- ×/-/- ×/-/- OC 644 × × × OC 758 × × OC 759 × 3S 7340 ×/-
Explanatory notes [No. of Output] +P:With Parity Bit
Explanatory notes [Output] 3S:3-State Output R3S:Series Resistor and 3-State Output
Explanatory notes [Output] OC:Open-Collector Output 3SOC:3-State Output / Open-Collector Output
Status :Product available in technology indicated *:New product planned in technology indicated
Status ×:Discontinued :Not recommended for new designs
Status HC:SN74HCxx / CD74HCxx
Status HCT:SN74HCxx / CD74HCTxx
Status BCT:SN74BCTxx / SN64BCTxx
Status AC:74AC11xxx (Product available in reduced-noise advanced CMOS:11000 Series) / SN74ACxx / CD74ACxx
Status ACT:74ACT11xxx (Product available in reduced-noise advanced CMOS:11000 Series) / SN74ACTxx / CD74ACTxx
Technology
Description No. ofOutput Output Device
NON-INVERTING/INVERTING
8
INVERTING
4
8
8+1P
9
10
16
18
AH
CT
58
J/K FLIP-FLOP
Bipolar CMOS BiCMOS Advanced CMOS
TT
L
LS S
AL
S
AS F HC
HC
T
BC
T
AB
T
LV
T
AL
VT
AC
AC
T
AH
C
LV
LV
C
AL
VC
AV
C
1 B 2S B 72 × B 2S B 70 × B 2S B 73 × A ×/ -/ B 2S B 109 × A A A / -/ ×/-/ ×/-/ B 2S B 110 × B 2S B 111 ×
4 B 2S Q 376 × B 2S B 76 × × ×/- B 2S B 78 × ×/- B 2S B 107 A ×/ -/ B 2S B 112 A A A / -/ ×/-/ ×/-/ AB 2S B 113 × × × × ×/- B 2S B 114 × × × × ×/-
4 B 2S Q 276 ×
D-TYPE FLIP-FLOP
Bipolar CMOS BiCMOS Advanced CMOST
TL
LS S
AL
S
AS F HC
HC
T
BC
T
AB
T
LV
T
AL
VT
AC
AC
T
AH
C
LV
LV
C
AL
VC
AV
C
2 B 2S B 74 × A A A / / // // A AC 2S B 171 × C 2S B 175 × B / -/ /-/ ×/-/ A
2S B 379 × × ×/- ×/-/- ×/-/- C 2S Q 174 × A / -/ ×/-/ ×/-/ A
2S Q 378 × ×/- ×/-/- ×/-/- C 2S Q 273 × × / / H ×/-/ ×/-/ A
3S Q 374 A / / /- A H ×// // A A H2S Q 377 A / / A ×/-/- ×/-/- 3S Q 478 ×/-/- ×/-/- 3S /Q 534 A × × ×/ ×/ ×/- A ×// ×//- 3S /Q 564 B × ×/ ×/ ×/- ×//- ×//- 3S Q 574 B / / /- A H ×// ×// A A3S Q 575 A × 3S /Q 576 B 3S /Q 577 A × 3S Q 825 A ×/-/- ×/-/- 3S Q 826 × ×/-/- ×/-/-
C 3S Q 874 B ×/-/- ×/-/- P 3S /Q 876 A C 3S Q 878 × × C 3S /Q 879 ×A ×
3S Q 4374 B 3S Q 29825 × × /- 3S Q 29826 × × ×/-
C 3S Q 823 A ×/-/- ×/-/- AC 3S /Q 824 ×A ×/-/- ×/-/- C 3S Q 29823 × × ×/- C 3S /Q 29824 × × ×/-
3S Q 821 A A ×/-/- ×/-/- A3S /Q 822 × ×/-/- ×/-/- 3S Q 1821 × 3S Q 29821 × /- 3S /Q 29822 × × ×/- 3S Q 16820 H3S Q 162820 H
3S Q 16374 A H H A/HA H
3S /Q 16534 × 3S Q 162374 H H
C 3S Q 16823 /H × HC 3S Q 162823 A
3S Q 16721 * H3S Q 16821 H × H3S Q 162721 H3S Q 162821 ×
22 3S Q 16722 3S Q 32374 H H HA H3S Q 322374 H
Explanatory notes [Trigger] POS:Positive edge NEG:Negative Edge
Explanatory notes [PRE ・ CLR] B:Preset and Clear C:Clear Only
Explanatory notes [Output] 2S:Totem pole Output 3S:3-State Output
Explanatory notes [Q・/Q] B:Q・/Q-Output Q:Q-Output /Q:/Q-Output
Status :Product available in technology indicated *:New product planned in technology indicated
Status ×:Discontinued :Not recommended for new designs
Status HC:SN74HCxx / CD74HCxx
Status HCT:SN74HCxx / CD74HCTxx
Status BCT:SN74BCTxx / SN64BCTxx
Status AC:74AC11xxx (Product available in reduced-noise advanced CMOS:11000 Series) / SN74ACxx / CD74ACxx
Status ACT:74ACT11xxx (Product available in reduced-noise advanced CMOS:11000 Series) / SN74ACTxx / CD74ACTxx
Q・/Q
Device
Technology
Technology
Trigger CurcuitPRE・
CLROutput
PRE・
CLROutput
Q・/Q
Device
20
4
6
8
9
10
10X2
POS
Trigger
POS 2
NEG 2
Curcuit
32
16
18
AH
CT
AH
CT
59
LATCH
Bipolar CMOS BiCMOS Advanced CMOS
TT
L
LS S
AL
S
AS F HC
HC
T
BC
T
AB
T
LV
T
AL
VT
AC
AC
T
AH
C
LV
LV
C
AL
VC
AV
C
S-R 4 2S Q 279 × A
8 2S Q 259 × B / -/ ×/-/- ×/-/- 8 2S Q 4724 ×/-
4 2S Q 75 × ×/ ×/ /-/- 4 2S Q 77 ×/- 4 2S Q 375 ×/- 8 2S Q 100 ×
8 3S Q 990 8 3S /Q 991 × 8 3S B Q 666 8 3S C Q 996 8 3S B /Q 667 9 3S C Q 992 9 3S C /Q 993 ×
10 3S Q 994 10 3S /Q 995 ×
8 2S C Q 116 × 8 3S Q 373 A / / /- H ×// // A A H8 3S Q 2373 8 3S /Q 533 A A × ×/ ×/ ×/- A ×//- ×//- 8 3S Q 573 C A A/ / /- A H ×// ×// A A8 3S /Q 563 B × / ×/ ×/- ×// ×//- 8 3S /Q 580 B × 8 3S C Q 873 B ×A ×/-/- ×/-/- 8 3S P Q 880 ×A × 8 3S B Q 845 × × ×/-/- ×/-/- 8 3S B Q 29845 × × ×/- 8 3S B /Q 846 × × ×/-/- ×/-/- 8 3S B /Q 29846 × × ×/- 9 3S B Q 843 × ×/-/- ×/-/- 9 3S B Q 1843 9 3S B Q 29843 × × /- 9 3S B /Q 844 × × ×/-/- ×/-/- 9 3S B /Q 29844 × × ×/-
10 3S Q 841 ×A A ×/-/- ×/-/- A10 3S Q 29841 × × ×/- 10 3S /Q 842 × × ×/-/- ×/-/- 10 3S /Q 29842 × ×/-
12/24 3S Q 16260 H H12/24 3S Q 162260 H H
16 3S Q 16373 A H H A/HA H
16 3S /Q 16533 × 16 3S Q 162373 H ×18 3S B Q 16843 × ×20 3S Q 16841 H20 3S Q 162841 H32 3S Q 32373 H H HA *
Explanatory notes [Type] S-R:S-R Latch AD:Addressable Latch BIS:Bistable Latch
Explanatory notes [Type] R-B:Read-Back Latch D:D-Type Transparent Latch
Explanatory notes [PRE ・ CLR] B:Preset and Clear C:Clear Only
Explanatory notes [Output] 2S:Totem-Pole Output 3S:3-State Output
Explanatory notes [Q・/Q] B:Q・/Q-Output Q:Q-Output /Q:/Q-Output
Status :Product available in technology indicated *:New product planned in technology indicated
Status ×:Discontinued :Not recommended for new designs
Status HC:SN74HCxx / CD74HCxx
Status HCT:SN74HCxx / CD74HCTxx
Status BCT:SN74BCTxx / SN64BCTxx
Status AC:74AC11xxx (Product available in reduced-noise advanced CMOS:11000 Series) / SN74ACxx / CD74ACxx
Status ACT:74ACT11xxx (Product available in reduced-noise advanced CMOS:11000 Series) / SN74ACTxx / CD74ACTxx
PRE・
CLR
Q・
/Q
Technology
Device
D
R/B
Output
AD
BIS
Type Curcuit
AH
CT
60
SHIFT REGISTER
Bipolar CMOS BiCMOS Advanced CMOS
TT
L
LS S
AL
S
AS F HC
HC
T
BC
T
AB
T
LV
T
AL
VT
AC
AC
T
AH
C
LV
LV
C
AL
VC
AV
C
R 2S 178 × C R 2S 179 ×
R 2S 195 × × × × ×/ B 2S 95 × × × B 2S 295 ×C
C R 3S 395 ×A C B 2S 194 × A × ×/ -/ ×/-/- ×/-/-
5 C R 2S 96 × × C R 3S 322 × ×/- C B 2S 198 × C B 3S 299 × × ×/ -/ ×/- ×/-/ ×/-/ C B 3S 323 × × × ×/- ×/-/ ×/-/ C B 2S 199 ×
R 2S 165 × A / -/ AC R 2S 166 × A × / -/ A
S S/P 8 C R 2S 164 × A / -/ -/-/ -/-/ A
S P 10 C 2S 898 ×/-/- ×/-/-
S S 8 R 2S 91 × ×
4 C R 2S 94 × 16 R 3S 674
SHIFT REGISTER WITH LATCH
Bipolar CMOS BiCMOS Advanced CMOS
TT
L
LS S
AL
S
AS F HC
HC
T
BC
T
AB
T
LV
T
AL
VT
AC
AC
T
AH
C
LV
LV
C
AL
VC
AV
C
4 C B 3S 671 × 4 C B 3S 672 × 8 C R 2S 598
8 C R 3S 595 /- A8 C R OC 599 × 8 C R OC 596 8 C R 2S 594 /- A
16 C B 3S 673
S/P S 8 C R 2S 597 -/ -/
Explanatory notes [Input/Output Type] S:Serial P:Parallel S/P:Alternative Serial/ParallelExplanatory notes [CLR] C:With ClearExplanatory notes [Shift] R:Right-Shift B:Alternative Shift Right/LeftExplanatory notes [Output] 2S:Totem-Pole Output 3S:3-State OutputStatus :Product available in technology indicated *:New product planned in technology indicatedStatus ×:Discontinued :Not recommended for new designsStatus HC:SN74HCxx / CD74HCxxStatus HCT:SN74HCxx / CD74HCTxxStatus BCT:SN74BCTxx / SN64BCTxxStatus AC:74AC11xxx (Product available in reduced-noise advanced CMOS:11000 Series) / SN74ACxx / CD74ACxxStatus ACT:74ACT11xxx (Product available in reduced-noise advanced CMOS:11000 Series) / SN74ACTxx / CD74ACTxx
DeviceInputType
OutputType
No. ofBit
Technology
InputType
OutputType
No. ofBit Output
S/P S 8
Technology
S/P S/P
4
8
CLR Shift Device
P S
Output
S/P S/P
CLR Shift
S S/P
AH
CT
AH
CT
61
REGISTER(ETC)
Bipolar CMOS BiCMOS Advanced CMOS
TT
L
LS S
AL
S
AS F HC
HC
T
BC
T
AB
T
LV
T
AL
VT
AC
AC
T
AH
C
LV
LV
C
AL
VC
AV
C
172 × 170 × × 670 -/ -/ 870 × ×/-/- ×/-/- 858 ×/-/- ×/-/- 871 × × 859 ×/-/- ×/-/- 298 × A ×/- 398 × 173 × A ×/ -/ 396 × 818 ×/-/- ×/-/- 819 ×/-/- ×/-/-
29818 × ×/-
Status :Product available in technology indicated *:New product planned in technology indicatedStatus ×:Discontinued :Not recommended for new designsStatus HC:SN74HCxx / CD74HCxxStatus HCT:SN74HCxx / CD74HCTxxStatus BCT:SN74BCTxx / SN64BCTxxStatus AC:74AC11xxx (Product available in reduced-noise advanced CMOS:11000 Series) / SN74ACxx / CD74ACxxStatus ACT:74ACT11xxx (Product available in reduced-noise advanced CMOS:11000 Series) / SN74ACTxx / CD74ACTxx
MONOSTABLE MULTIVIBRATOR
Bipolar CMOS BiCMOS Advanced CMOS
TT
L
LS S
AL
S
AS F HC
HC
T
BC
T
AB
T
LV
T
AL
VT
AC
AC
T
AH
C
AH
CT
LV
LV
C
AL
VC
AV
C
121 122 × 422 ×
123 -/ -/ A A A221 -/ -/ A423 -/ -/
4538 -/ -/
Explanatory notes [CLR] C:With ClearExplanatory notes [Retrigger] R:With RetriggerStatus :Product available in technology indicated *:New product planned in technology indicatedStatus ×:Discontinued :Not recommended for new designsStatus HC:SN74HCxx / CD74HCxxStatus HCT:SN74HCxx / CD74HCTxxStatus BCT:SN74BCTxx / SN64BCTxxStatus AC:74AC11xxx (Product available in reduced-noise advanced CMOS:11000 Series) / SN74ACxx / CD74ACxxStatus ACT:74ACT11xxx (Product available in reduced-noise advanced CMOS:11000 Series) / SN74ACTxx / CD74ACTxx
Device
Device
Descriotion
Curcuit CLR Retrigger
Technology
Technology
REGISTER FILES 8WX2BREGISTER FILES 4WX4BREGISTER FILES 4WX4BREGISTER FILES 16WX5BREGISTER FILES 16WX5BREGISTER FILES 16WX6BREGISTER FILES 32WX4BMUX WITH STRAGEMUX WITH STRAGE4BIT BUS-BUFFER REGISTER8BIT STORAGE REGISTER
8BIT DIAGNOTICCS/PIPELINE REGISTER
1 C RC R
C R
2
C RCC R
AH
CT
62
DECADE/BINARY COUNTER
Bipolar CMOS BiCMOS Advanced CMOS
TT
L
LS S
AL
S
AS F HC
HC
T
BC
T
AB
T
LV
T
AL
VT
AC
AC
T
AH
C
AH
CT
LV
LV
C
AL
VC
AV
C
A 68 × 9 90 ×
290 × × A D 390 × ×/ -/ A A 176 × A A 196 × × × A 9 D 490 × × ×
560 × S S 162 × ×A × ×B × × ×/- ×/-/- ×/-/- A S 160 × ×A ×B × × ×/- ×/-/- ×/-/- A S 690 × S S 692 ×
S 568 × × ×/-/- ×/-/- S 168 × × × × ×/-/- ×/-/- S 668 × A 190 × × × ×A ×/ ×/-/- ×/-/-
A S 696 × S S 698 × A A 192 × × × ×/ ×/-/- ×/-/-
8 A J 4017 ×/
A 69 × 93 × -/ -/
293 × A D 393 × / -/ AA A 177 × A A 197 × × ×
7 A 4024 ×/ -/ 12 A 4040 / -/ A
A 4020 / -/ A 4060 / -/ A 4061 ×/-
561 A S S 163 × A B A / -/ ×/-/ ×/-/ AS S 693 × A S 161 × A B A / -/ ×/-/ ×/-/ AA S 691 ×
D 4518 -/S 669
S S 699 × S 169 B × B A ×/-/- ×/-/- A 191 × A / -/ ×/-/- ×/-/-
A S 697 A A 193 × A ×A / -/ ×/-/- ×/-/- A A 569 A × ×/-/- ×/-/- A S 461 ×/-/- ×/-/- S S 463 ×/-/- ×/-/- A A R 590 A/- ×/-/- ×/-/- A A R 591 × A A R 592 ×/-/- ×/-/- A A R 593 ×/-/- ×/-/- A J 4022 ×/-
4520 -/A J 7022 ×/-
40103 -/ S 469 ×/-/- ×/-/-
579 ×/-/- ×/-/- S S 869 ×/-/- ×/-/- A S 867 A ×/-/- ×/-/-
OTH A 1 12 92 ×
Explanatory notes [DEC・BIN] DEC:Decoder BIN:Binary Counter OHE:OtherExplanatory notes [ASYN・SYN] ASYN:Asynchronous SYN:SynchronousExplanatory notes [Up/Down] Y:Up/DownExplanatory notes [CLR] A:With Asynchronous Clear S:With Synchronous ClearExplanatory notes [LOAD] A:With Asynchronous Clear S:With Synchronous Clear 9:Preset 9Explanatory notes [ETC] D:2-Curcuit R:With Series Register J:Johnson Counter 12:Devide By-Twelve CounterStatus :Product available in technology indicated *:New product planned in technology indicatedStatus ×:Discontinued :Not recommended for new designsStatus HC:SN74HCxx / CD74HCxxStatus HCT:SN74HCxx / CD74HCTxxStatus BCT:SN74BCTxx / SN64BCTxxStatus AC:74AC11xxx (Product available in reduced-noise advanced CMOS:11000 Series) / SN74ACxx / CD74ACxxStatus ACT:74ACT11xxx (Product available in reduced-noise advanced CMOS:11000 Series) / SN74ACTxx / CD74ACTxx
DEC・
BIN
ASYN・
SYN
No. ofBit
UP/DOWNMode
CLR LOAD ETC
A
14
Technology
Device
4
4
Y
Y
DEC
S
Y
BIN
S
4
8
A
4
63
RATE MULTIPLIER/FREQUENCY DIVIDERS
Bipolar CMOS BiCMOS Advanced CMOS
TT
L
LS S
AL
S
AS F HC
HC
T
BC
T
AB
T
LV
T
AL
VT
AC
AC
T
AH
C
LV
LV
C
AL
VC
AV
C
56 × 57 × 97
167 × 292 294
Status :Product available in technology indicated *:New product planned in technology indicatedStatus ×:Discontinued :Not recommended for new designsStatus HC:SN74HCxx / CD74HCxxStatus HCT:SN74HCxx / CD74HCTxxStatus BCT:SN74BCTxx / SN64BCTxxStatus AC:74AC11xxx (Product available in reduced-noise advanced CMOS:11000 Series) / SN74ACxx / CD74ACxxStatus ACT:74ACT11xxx (Product available in reduced-noise advanced CMOS:11000 Series) / SN74ACTxx / CD74ACTxx
DATA SELECTOR/MULTIPLEXER
Bipolar CMOS BiCMOS Advanced CMOS
TT
L
LS S
AL
S
AS F HC
HC
T
BC
T
AB
T
LV
T
AL
VT
AC
AC
T
AH
C
AH
CT
LV
LV
C
AL
VC
AV
C
2S 150 ×/-/- ×/-/- 3S 250 A ×/-/- ×/-/- 3S 850 × 3S 851 × 2S 4067 ×/
2S 151 ×A B / -/ ×/-/ ×/-/ 2S 152 ×/- 3S 251 × × × B / -/ ×/-/ ×/-/× 3S 354 × ×/ -/ 3S 356 × ×/- -/ 3S 4051 -/ -/ A3S 4351 -/ -/OC 355 × OC 357 ×
2S 352 × × × × ×/- ×/-/- ×/-/- 3S 153 × × / -/ ×/-/ ×/-/ 3S 253 A / -/ ×/-/ ×/-/ 3S 353 × × × × ×/- ×/-/- ×/-/- 3S 4052 -/ -/ A3S 4352 -/3S 16460 H ×3S 162460 H
2S 157 × A A / / ×/-/ ×/-/ A A2S 158 × ×A / -/ ×/-/ ×/-/ -2S S 399 3S 257 B A / / /-/ /-/ A3S 258 B × A / -/ ×/-/- ×/-/ - 3S 4053 -/ -/ A3S U 857 × 3S S 604 × × OC S 605 × 3S S 606 × OC S 607 ×
3S AD 16254 ×
Explanatory notes [Output] 2S:Totem pole Output 3S:3-State Output OC:Open-Collector OutputExplanatory notes [ETC] S:Storage RegisterStatus :Product available in technology indicated *:New product planned in technology indicatedStatus ×:Discontinued :Not recommended for new designsStatus HC:SN74HCxx / CD74HCxxStatus HCT:SN74HCxx / CD74HCTxxStatus BCT:SN74BCTxx / SN64BCTxxStatus AC:74AC11xxx (Product available in reduced-noise advanced CMOS:11000 Series) / SN74ACxx / CD74ACxxStatus ACT:74ACT11xxx (Product available in reduced-noise advanced CMOS:11000 Series) / SN74ACTxx / CD74ACTxx
Technology
Technology
DECADE RATE MULTILIER
11116/1
1
1
11
1
1
1111
2222
4
4
4
114
8
16
2/1
16
88
68
11
Device
DeviceOutput Curcuit ETC
PROGRAMABLE FREQUENCYDIVIDER/DIGITAL TIMERS
FREQUENCY DIVIDERSFREQUENCY DIVIDERS6BIT BINARY RATE MULTIPLIER
2
4/1
1
8/1
Descriotion
No. ofInput/output
2
AH
CT
64
DECODER/DEMULTIPLEXER
Bipolar CMOS BiCMOS Advanced CMOS
TT
L
LS S
AL
S
AS F HC
HC
T
BC
T
AB
T
LV
T
AL
VT
AC
AC
T
AH
C
AH
CT
LV
LV
C
AL
VC
AV
C
2S 1 AD 4514 ×/ -/ 2S 1 AD 4515 ×/ -/ 3S 1 154 ×/ -/ ×/-/- ×/-/- OC 1 159
2S 1 BD 42 ×A / -/ 2S 1 BD 43 × 2S 1 BD 44 ×
2S 1 238 ×/ -/ ×/-/ ×/-/ 2S 1 138 A A / / /-/ ×/-/ A A2S 1 AD 237 ×/ -/ 2S 1 AD 137 × A × ×/ ×/ 2S 1 AD 131 × ×
2S 2 139 A A × × / / ×/-/ /-/ A A2S 2 239 ×/- ×/-/- ×/-/- 2S 2 155 × A OC 2 156 ×
Explanatory notes [Output] 2S:Totem pole Output 3S:3-State Output OC:Open-Collector OutputExplanatory notes [ETC] AD:Adress Latch BD:BCD TO DECIMALStatus :Product available in technology indicated *:New product planned in technology indicatedStatus ×:Discontinued :Not recommended for new designsStatus HC:SN74HCxx / CD74HCxxStatus HCT:SN74HCxx / CD74HCTxxStatus BCT:SN74BCTxx / SN64BCTxxStatus AC:74AC11xxx (Product available in reduced-noise advanced CMOS:11000 Series) / SN74ACxx / CD74ACxxStatus ACT:74ACT11xxx (Product available in reduced-noise advanced CMOS:11000 Series) / SN74ACTxx / CD74ACTxx
CODE CONVERTER、 PRIORITY ENCODER/REGISTER
Bipolar CMOS BiCMOS Advanced CMOS
TT
L
LS S
AL
S
AS F HC
HC
T
BC
T
AB
T
LV
T
AL
VT
AC
AC
T
AH
C
LV
LV
C
AL
VC
AV
C
184 × 185 × 147 × × -/ -/ 148 × × /- 348 ×
278 ×
Status :Product available in technology indicated *:New product planned in technology indicatedStatus ×:Discontinued :Not recommended for new designsStatus HC:SN74HCxx / CD74HCxxStatus HCT:SN74HCxx / CD74HCTxxStatus BCT:SN74BCTxx / SN64BCTxxStatus AC:74AC11xxx (Product available in reduced-noise advanced CMOS:11000 Series) / SN74ACxx / CD74ACxxStatus ACT:74ACT11xxx (Product available in reduced-noise advanced CMOS:11000 Series) / SN74ACTxx / CD74ACTxx
Technology
Technology
DeviceCurcuitNo. ofInput/output
Device
3/8
2/4
4/16
4/10
Output ETC
Descriotion
8-3 PRIORITY ENCODER
4BIT CASCADABLE PRIORITYREGISTER
CODE CONVERTERCODE CONVERTER10-4 PRIORITY ENCODER8-3 PRIORITY ENCODER
AH
CT
65
Display Decoder/Driver
Bipolar CMOS BiCMOS Advanced CMOS
TT
L
LS S
AL
S
AS F HC
HC
T
BC
T
AB
T
LV
T
AL
VT
AC
AC
T
AH
C
AH
CT
LV
LV
C
AL
VC
AV
C
45 141 × 145 445 ×
46 × 47 A 48 × × 49 ×
246 × 247 × 347 447 248 × 249 × 142 × 143 × 144 ×
Explanatory notes [Function] D:BCD TO DECIMAL、7:BCD TO 7-SEGMENT、B:COUNTER/LATCH/DECODER/DRIVERExplanatory notes [VOH] Off-Stage Output Voltage(V)Status :Product available in technology indicated *:New product planned in technology indicatedStatus ×:Discontinued :Not recommended for new designsStatus HC:SN74HCxx / CD74HCxxStatus HCT:SN74HCxx / CD74HCTxxStatus BCT:SN74BCTxx / SN64BCTxxStatus AC:74AC11xxx (Product available in reduced-noise advanced CMOS:11000 Series) / SN74ACxx / CD74ACxxStatus ACT:74ACT11xxx (Product available in reduced-noise advanced CMOS:11000 Series) / SN74ACTxx / CD74ACTxx
COMPARATOR
Bipolar CMOS BiCMOS Advanced CMOS
TT
L
LS S
AL
S
AS F HC
HC
T
BC
T
AB
T
LV
T
AL
VT
AC
AC
T
AH
C
AH
CT LV
LV
C
AL
VC
AV
C
4 S Y N Y Y 2S 85 × × ×A/ -/ 6 S N Y N N 2S 29806 × 8 20 Y N N N OC 518 × 8 20 N Y N N 2S 520 × ×/-/- ×/-/- 8 20 N Y N N OC 522 × 8 20 N Y Y N 2S 682 /- 8 20 N Y Y N OC 683 × 8 S Y N N N OC 519 × × 8 S N Y N N 2S 521 ×/-/- ×/-/- 8 S N Y Y N 2S 684 /- 8 S N Y Y N OC 685 × 8 S N Y Y N 2S 686 × 8 S N Y Y N OC 687 × 8 S N Y N N 2S 688 / -/ 8 S N Y N N OC 689 × × 8 S Y N Y Y 2S 860 ×/-/- ×/-/- 8 S N N Y Y 2S 865 ×/-/- ×/-/- 8 LP N N Y Y 2S 885 ×/-/- ×/-/- 8 LPQ Y N Y Y OC 866 ×A 9 - N Y N N 2S 29809 ×
Explanatory notes [Input] S:Standard 20:20-kW Pullup Resistors LP:P-Port Latch LPQ:L,P-port LatchExplanatory notes [P=Q, P=Q, P>Q, P<Q] Y:Yes N:NoExplanatory notes [Output] 2S:Totem Pole Output、OC:Open-Collector OutputStatus :Product available in technology indicated *:New product planned in technology indicatedStatus ×:Discontinued :Not recommended for new designsStatus HC:SN74HCxx / CD74HCxxStatus HCT:SN74HCxx / CD74HCTxxStatus BCT:SN74BCTxx / SN64BCTxxStatus AC:74AC11xxx (Product available in reduced-noise advanced CMOS:11000 Series) / SN74ACxx / CD74ACxxStatus ACT:74ACT11xxx (Product available in reduced-noise advanced CMOS:11000 Series) / SN74ACTxx / CD74ACTxx
BB
7777
D7
15
B
Function
DD
D
Technology
777
60
DeviceNo. ofBit Input P=Q P=Q P>Q P<Q Output
7
5.57
5.577
5.5
15
75.5
Technology
3077
157
30
DeviceVOH (V)
30
66
ADRESS COMPARATOR、FUSE-PROGRAMMABLE IDENTITY COMPARATOR
Bipolar CMOS BiCMOS Advanced CMOS
TT
L
LS S
AL
S
AS F HC
HC
T
BC
T
AB
T
LV
T
AL
VT
AC
AC
T
AH
C
AH
CT
LV
LV
C
AL
VC
AV
C
677 ×A × ×/-/- ×/-/-678 × × ×/-/- ×/-/-679 × 680 × × 526 × 528 × 527 ×
Explanatory notes [Function] A:Adress Comparator F:Fuse-Programmable Identity ComparatorsExplanatory notes [ETC] OE:Output-With Enable L:Output-With LatchStatus :Product available in technology indicated *:New product planned in technology indicatedStatus ×:Discontinued :Not recommended for new designsStatus HC:SN74HCxx / CD74HCxxStatus HCT:SN74HCxx / CD74HCTxxStatus BCT:SN74BCTxx / SN64BCTxxStatus AC:74AC11xxx (Product available in reduced-noise advanced CMOS:11000 Series) / SN74ACxx / CD74ACxxStatus ACT:74ACT11xxx (Product available in reduced-noise advanced CMOS:11000 Series) / SN74ACTxx / CD74ACTxx
PARITY GENERATOR/CHECKER
Bipolar CMOS BiCMOS Advanced CMOS
TT
L
LS S
AL
S
AS F HC
HC
T
BC
T
AB
T
LV
T
AL
VT
AC
AC
T
AH
C
LV
LV
C
AL
VC
AV
C
180 × × 280 B ×/ -/ ×/ー/ ×/-/286 × ×/-/- /-/-
Status :Product available in technology indicated *:New product planned in technology indicatedStatus ×:Discontinued :Not recommended for new designsStatus HC:SN74HCxx / CD74HCxxStatus HCT:SN74HCxx / CD74HCTxxStatus BCT:SN74BCTxx / SN64BCTxxStatus AC:74AC11xxx (Product available in reduced-noise advanced CMOS:11000 Series) / SN74ACxx / CD74ACxxStatus ACT:74ACT11xxx (Product available in reduced-noise advanced CMOS:11000 Series) / SN74ACTxx / CD74ACTxx
VOLTAGE CONTROLLED OSCILLATOR(VCO)
Bipolar CMOS BiCMOS Advanced CMOS
TT
L
LS S
AL
S
AS F HC
HC
T
BC
T
AB
T
LV
T
AL
VT
AC
AC
T
AH
C
LV
LV
C
AL
VC
AV
C
20 Y Y Y 624 20 Y Y Y Y 628 24 Y Y 7046 -/ -/
20 627 × 20 Y Y 629 20 Y 625 × 20 Y Y 626 × 60 Y Y 124 24 Y Y 4046 -/
Status :Product available in technology indicated *:New product planned in technology indicatedStatus ×:Discontinued :Not recommended for new designsStatus HC:SN74HCxx / CD74HCxxStatus HCT:SN74HCxx / CD74HCTxxStatus BCT:SN74BCTxx / SN64BCTxxStatus AC:74AC11xxx (Product available in reduced-noise advanced CMOS:11000 Series) / SN74ACxx / CD74ACxxStatus ACT:74ACT11xxx (Product available in reduced-noise advanced CMOS:11000 Series) / SN74ACTxx / CD74ACTxx
2
1
PLLRextRANGEINPUTENABLECOMP'L
Z OUTFmax(MHz)Curcuit
F 16F
Device
12
99
F 8
8
12-4 OE
OE
A 12-4 L
No. of Bit
Descriotion ETCNo. of Bit
A 16-4 LA 16-4
A
Technology
Technology
Device
Device
Technology
AH
CT
AH
CT
67
ACCUMULATORS, ARITHMETIC LOGIC UNIT(ALU), LOOK-AHEAD CARRY GENERATOR
Bipolar CMOS BiCMOS Advanced CMOS
TT
L
LS S
AL
S
AS F HC
HC
T
BC
T
AB
T
LV
T
AL
VT
AC
AC
T
AH
C
AH
CT
LV
LV
C
AL
VC
AV
C
281 × 681 × 181 × × A ×/-/- ×/-/- 381 × × × 881 ×A ×/-/- ×/-/- 382 × × 264 × 182 × × 282 × 882 ×A ×/-/- ×/-/- 385 ×
Status :Product available in technology indicated *:New product planned in technology indicatedStatus ×:Discontinued :Not recommended for new designsStatus HC:SN74HCxx / CD74HCxxStatus HCT:SN74HCxx / CD74HCTxxStatus BCT:SN74BCTxx / SN64BCTxxStatus AC:74AC11xxx (Product available in reduced-noise advanced CMOS:11000 Series) / SN74ACxx / CD74ACxxStatus ACT:74ACT11xxx (Product available in reduced-noise advanced CMOS:11000 Series) / SN74ACTxx / CD74ACTxx
ADDER
Bipolar CMOS BiCMOS Advanced CMOS
TT
L
LS S
AL
S
AS F HC
HC
T
BC
T
AB
T
LV
T
AL
VT
AC
AC
T
AH
C
AH
CT
LV
LV
C
AL
VC
AV
C
83 × × 283 × -/ -/ -/-/ -/-/ 183 ×
80 × 82 ×
Status :Product available in technology indicated *:New product planned in technology indicatedStatus ×:Discontinued :Not recommended for new designsStatus HC:SN74HCxx / CD74HCxxStatus HCT:SN74HCxx / CD74HCTxxStatus BCT:SN74BCTxx / SN64BCTxxStatus AC:74AC11xxx (Product available in reduced-noise advanced CMOS:11000 Series) / SN74ACxx / CD74ACxxStatus ACT:74ACT11xxx (Product available in reduced-noise advanced CMOS:11000 Series) / SN74ACTxx / CD74ACTxx
MULTIPLIER
Bipolar CMOS BiCMOS Advanced CMOS
TT
L
LS S
AL
S
AS F HC
HC
T
BC
T
AB
T
LV
T
AL
VT
AC
AC
T
AH
C
AH
CT
LV
LV
C
AL
VC
AV
C
261 × 284 × 285 × 384 ×
Status :Product available in technology indicated *:New product planned in technology indicatedStatus ×:Discontinued :Not recommended for new designsStatus HC:SN74HCxx / CD74HCxxStatus HCT:SN74HCxx / CD74HCTxxStatus BCT:SN74BCTxx / SN64BCTxxStatus AC:74AC11xxx (Product available in reduced-noise advanced CMOS:11000 Series) / SN74ACxx / CD74ACxxStatus ACT:74ACT11xxx (Product available in reduced-noise advanced CMOS:11000 Series) / SN74ACTxx / CD74ACTxx
2'S COMPLEMENT MULTIPLIERS
Descriotion
4BIT BINARY FULL ADDER4BIT BINARY FULL ADDERDUAL CARRY SAVE FULL ADDER
4-4 PARALLEL BINARY MULTIPLIERS
LOOK AHEAD CARRY GENERATORSLOOK AHEAD CARRY GENERATORSLOOK AHEAD CARRY GENERATORSQUAD SERIAL ADDER/SUBTRACTOR
Descriotion
4BIT PARALLEL BINARY ACCUMULATORS4BIT PARALLEL BINARY ACCUMULATORS4BIT ALU/FUNCTION GENERATORS
Technology
Technology
Technology
Device
Device
Device
GATED FULL ADDER2BIT BINARY FULL ADDER
2-4 PARALLEL BINARY MULTIPLIERS
Descriotion
4-4 PARALLEL BINARY MULTIPLIERS
4BIT ALU WITH RIPPLE CARRYLOOK AHEAD CARRY GENERATORS
4BIT ALU/FUNCTION GENERATORS4BIT ALU/FUNCTION GENERATORS
68
MEMORY
Bipolar CMOS BiCMOS Advanced CMOS
TT
L
LS S
AL
S
AS F HC
HC
T
BC
T
AB
T
LV
T
AL
VT
AC
AC
T
AH
C
AH
CT
LV
LV
C
AL
VC
AV
C
600 × 601 × 603 × 608 × 612 × 613 × 610 × 611 × 412 ×
2414 /-
Status :Product available in technology indicated *:New product planned in technology indicatedStatus ×:Discontinued :Not recommended for new designsStatus HC:SN74HCxx / CD74HCxxStatus HCT:SN74HCxx / CD74HCTxxStatus BCT:SN74BCTxx / SN64BCTxxStatus AC:74AC11xxx (Product available in reduced-noise advanced CMOS:11000 Series) / SN74ACxx / CD74ACxxStatus ACT:74ACT11xxx (Product available in reduced-noise advanced CMOS:11000 Series) / SN74ACTxx / CD74ACTxx
CLOCK GENERATOR CIRCUIT
Bipolar CMOS BiCMOS Advanced CMOS
TT
L
LS S
AL
S
AS F HC
HC
T
BC
T
AB
T
LV
T
AL
VT
AC
AC
T
AH
C
AH
CT
LV
LV
C
AL
VC
AV
C
265 × 120 × 320 × 321 × 297 -/ -/ -/-/
Status :Product available in technology indicated *:New product planned in technology indicatedStatus ×:Discontinued :Not recommended for new designsStatus HC:SN74HCxx / CD74HCxxStatus HCT:SN74HCxx / CD74HCTxxStatus BCT:SN74BCTxx / SN64BCTxxStatus AC:74AC11xxx (Product available in reduced-noise advanced CMOS:11000 Series) / SN74ACxx / CD74ACxxStatus ACT:74ACT11xxx (Product available in reduced-noise advanced CMOS:11000 Series) / SN74ACTxx / CD74ACTxx
SWITCH , SHIFTER , ERROR DETECTION CORRECTION CIRCUIT , HARD DISK DRIVER
Bipolar CMOS BiCMOS Advanced CMOS
TT
L
LS S
AL
S
AS F HC
HC
T
BC
T
AB
T
LV
T
AL
VT
AC
AC
T
AH
C
AH
CT
LV
LV
C
AL
VC
AV
C
4016 -/ A4066 / -/
ANALOG SWITCHES WITH LEVEL TRANSLATION 4316 -/ -/350 × × 636 × 637 × 616 × 617 630 × 631 × 632 × × 633 × 634 × × 635 ×
1250 ×
Status :Product available in technology indicated *:New product planned in technology indicatedStatus ×:Discontinued :Not recommended for new designsStatus HC:SN74HCxx / CD74HCxxStatus HCT:SN74HCxx / CD74HCTxxStatus BCT:SN74BCTxx / SN64BCTxxStatus AC:74AC11xxx (Product available in reduced-noise advanced CMOS:11000 Series) / SN74ACxx / CD74ACxxStatus ACT:74ACT11xxx (Product available in reduced-noise advanced CMOS:11000 Series) / SN74ACTxx / CD74ACTxx
16BIT PARALLEL ERROR DETECTION CORRECTIONCIRCUIT
32BIT PARALLEL ERROR DETECTION CORRECTIONCIRCUIT
HARD DISK DRIVER
Descriotion
DUAL PULSE SYNCHRONIZERS/DRIVERSCRYSTAL-CONTOROLLED OSCILLATORSCRYSTAL-CONTOROLLED OSCILLATORS
8BIT PARALLEL ERROR DETECTION CORRECTIONCIRCUIT
DIGITAL PHASE-LOCK LOOP
Descriotion
Descriotion
Device
Device
Technology
Technology
Technology
Device
4BIT SHIFTERS
MEMMORY MAPPERS WITH LATCHMEMMORY MAPPERS WITH LATCHMULTI-MODE LATCH3-8 MEMORY DECIDER
MEMORY REFRESH CONTROLLERSMEMORY CYCLE CONTROLLER
QUAD COMPLEMENTARY-OUTPUT LOGIC
QUAD BILATERAL SWITCHES
MEMMORY MAPPERSMEMMORY MAPPERS
MEMORY REFRESH CONTROLLERSMEMORY REFRESH CONTROLLERS
PIN ASSIGNMENTS
71
Pin Assignments
00QUADRUPLE 2-INPUTPOSITIVE-NAND GATESpositive logic:Y = A • B
01QUADRUPLE 2-INPUT POSITIVE-NAND GATESWITH OPEN-COLLECTOR OUTPUTSpositive logic:Y = A • B
02QUADRUPLE 2-INPUTPOSITIVE-NOR GATESpositive logic:Y = A + B
03QUADRUPLE 2-INPUT POSITIVE-NAND GATESWITH OPEN-COLLECTOR OUTPUTSpositive logic:Y = A • B
04HEX INVERTERSpositive logic:Y = A
U04HEX INVERTERSpositive logic:Y = A
05HEX INVERTERSWITH OPEN-COLLECTOR OUTPUTSpositive logic:Y = A
06HEX INVERTER BUFFERS/DRIVERSWITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTSpositive logic:Y = A
See page 139 See page 143
See page 144See page 140
See page 144
See page 145See page 142
See page 141
1 2 3 4 5 6 7
14 13 12 11 10 9 8
1A 1Y 2A 2Y 3A 3Y GND
VCC 6A 6Y 5A 5Y 4A 4Y
1 2 3 4 5 6 7
14 13 12 11 10 9 8
1A 1Y 2A 2Y 3A 3Y GND
VCC 6A 6Y 5A 5Y 4A 4Y
1 2 3 4 5 6 7
14 13 12 11 10 9 8
1A 1Y 2A 2Y 3A 3Y GND
VCC 6A 6Y 5A 5Y 4A 4Y
1 2 3 4 5 6 7
14 13 12 11 10 9 8
1A 1Y 2A 2Y 3A 3Y GND
VCC 6A 6Y 5A 5Y 4A 4Y
1 2 3 4 5 6 7
14 13 12 11 10 9 8
1A 1B 1Y 2A 2B 2Y GND
VCC 4B 4A 4Y 3B 3A 3Y
1 2 3 4 5 6 7
14 13 12 11 10 9 8
1Y 1A 1B 2Y 2A 2B GND
VCC 4Y 4B 4A 3Y 3B 3A
1 2 3 4 5 6 7
14 13 12 11 10 9 8
1Y 1A 1B 2Y 2A 2B GND
VCC 4Y 4B 4A 3Y 3B 3A
1 2 3 4 5 6 7
14 13 12 11 10 9 8
1A 1B 1Y 2A 2B 2Y GND
VCC 4B 4A 4Y 3B 3A 3Y
72
Pin Assignments
07HEX BUFFERS/DRIVERS WITH OPEN-COLLECTORHIGH-VOLTAGE OUTPUTSpositive logic:Y = A
09QUADRUPLE 2-INPUT POSITIVE-AND GATESWITH OPEN-COLLECTOR OUTPUTSpositive logic:Y = A • B
08QUADRUPLE 2-INPUT POSITIVE-AND GATESpositive logic:Y = A • B
10TRIPLE 3-INPUTPOSITIVE-NAND GATESpositive logic:Y = A • B • C
11TRIPLE 3-INPUTPOSITIVE-AND GATESpositive logic:Y = A • B • C
14HEX SCHMITT-TRIGGERINVERTERSpositive logic:Y = A
16HEX INVERTER BUFFERS/DRIVERSWITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTSpositive logic:Y = A
17HEX BUFFERS/DRIVERS WITH OPEN-COLLECTORHIGH-VOLTAGE OUTPUTSpositive logic:Y = A
See page 149See page 145
See page 146 See page 150
See page 147 See page 151
See page 148 See page 151
1 2 3 4 5 6 7
14 13 12 11 10 9 8
1A 1Y 2A 2Y 3A 3Y GND
VCC 6A 6Y 5A 5Y 4A 4Y
1 2 3 4 5 6 7
14 13 12 11 10 9 8
1A 1B 1Y 2A 2B 2Y GND
VCC 4B 4A 4Y 3B 3A 3Y
1 2 3 4 5 6 7
14 13 12 11 10 9 8
1A 1B 1Y 2A 2B 2Y GND
VCC 4B 4A 4Y 3B 3A 3Y
1 2 3 4 5 6 7
14 13 12 11 10 9 8
1A 1B 2A 2B 2C 2Y GND
VCC 1C 1Y 3C 3B 3A 3Y
1 2 3 4 5 6 7
14 13 12 11 10 9 8
1A 1B 2A 2B 2C 2Y GND
VCC 1C 1Y 3C 3B 3A 3Y
1 2 3 4 5 6 7
14 13 12 11 10 9 8
1A 1Y 2A 2Y 3A 3Y GND
VCC 6A 6Y 5A 5Y 4A 4Y
1 2 3 4 5 6 7
14 13 12 11 10 9 8
1A 1Y 2A 2Y 3A 3Y GND
VCC 6A 6Y 5A 5Y 4A 4Y
1 2 3 4 5 6 7
14 13 12 11 10 9 8
1A 1Y 2A 2Y 3A 3Y GND
VCC 6A 6Y 5A 5Y 4A 4Y
73
Pin Assignments
19HEX SCHMITT-TRIGGER INVERTERSpositive logic:Y = A
20DUAL 4-INPUTPOSITIVE-NAND GATESpositive logic:Y = A • B • C • D
21DUAL 4-INPUTPOSITIVE-AND GATESpositive logic:Y = A • B • C • D
25DUAL 4-INPUT POSITIVE-NOR GATESWITH STROBEpositive logic:Y = G (A + B + C + D)
26QUADRUPLE 2-INPUT HIGH-VOLTAGEINTERFACE POSITIVE-NAND GATESpositive logic:Y = AB
27TRIPLE 3-INPUTPOSITIVE-NOR GATESpositive logic:Y = A + B + C
308-INPUT POSITIVE-NAND GATESpositive logic:Y = A • B • C • D • E • F • G • H
31DELAY ELEMENTS
See page 155See page 152
See page 154
See page 154
See page 153 See page 155
See page 156
See page 156
1 2 3 4 5 6 7
14 13 12 11 10 9 8
1A 1Y 2A 2Y 3A 3Y GND
VCC 6A 6Y 5A 5Y 4A 4Y
1 2 3 4 5 6 7
14 13 12 11 10 9 8
1A 1B NC 1C 1D 1Y GND
VCC 2D 2C NC 2B 2A 2Y
1 2 3 4 5 6 7
14 13 12 11 10 9 8
1A 1B STROBE1G
1C 1D 1Y GND
VCC 2D 2CSTROBE
2G 2B 2A 2Y
1 2 3 4 5 6 7
14 13 12 11 10 9 8
1A 1B 1Y 2A 2B 2Y GND
VCC 4B 4A 4Y 3B 3A 3Y
1 2 3 4 5 6 7
14 13 12 11 10 9 8
1A 1B NC 1C 1D 1Y GND
VCC 2D 2C NC 2B 2A 2Y
1 2 3 4 5 6 7
14 13 12 11 10 9 8
1A 1B 2A 2B 2C 2Y GND
VCC 1C 1Y 3C 3B 3A 3Y
1 2 3 4 5 6 7
14 13 12 11 10 9 8
A B C D E F GND
VCC NC H G NC NC Y
1 2 3 4 5 6 7
14 13 12 11 10 9 8
A B C D E F GND
VCC NC H G NC NC Y
NC – No internal connection
NC – No internal connectionNC – No internal connection
NC – No internal connection
74
Pin Assignments
32QUADRUPLE 2-INPUTPOSITIVE OR GATESpositive logic:Y = A + B
33QUADRUPLE 2-INPUT POSITIVE-NOR BUFFERSWITH OPEN-COLLECTOR OUTPUTSpositive logic:Y = A + B
35HEX NONINVERTERSWITH OPEN-COLLECTOR OUTPUTSpositive logic:Y = A
37QUADRUPLE 2-INPUTPOSITIVE-NAND BUFFERSpositive logic:Y = A • B
38QUADRUPLE 2-INPUT POSITIVE-NAND BUFFERSWITH OPEN-COLLECTOR OUTPUTSpositive logic:Y = A • B
424-LINE-TO-10-LINE DECODERS
45BCD-TO-DECIMAL DECODER/DRIVER
1 2 3 4 5 6 7
14 13 12 11 10 9 8
1Y 1A 1B 2Y 2A 2B GND
VCC 4Y 4B 4A 3Y 3B 3A
1 2 3 4 5 6 7
14 13 12 11 10 9 8
1A 1Y 2A 2Y 3A 3Y GND
VCC 6A 6Y 5A 5Y 4A 4Y
1 2 3 4 5 6 7
14 13 12 11 10 9 8
1A 1B 1Y 2A 2B 2Y GND
VCC 4B 4A 4Y 3B 3A 3Y
1 2 3 4 5 6 7
14 13 12 11 10 9 8
1A 1B 1Y 2A 2B 2Y GND
VCC 4B 4A 4Y 3B 3A 3Y
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
VCC A B C D 9 8 7
GND6543210
A B C D
2 3 4 5 6 7 8 910
OUTPUTSINPUTS
OUTPUTS
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
VCC A B C D 9 8 7
GND6543210
A B C D
2 3 4 5 6 7 8 910
OUTPUTSINPUTS
OUTPUTS
BCD-TO-DECIMAL
1 2 3 4 5 6 7
14 13 12 11 10 9 8
1A 1B 1Y 2A 2B 2Y GND
VCC 4B 4A 4Y 3B 3A 3Y
See page 157
See page 159
See page 158
See page 160
See page 158
See page 159 See page 162
75
Pin Assignments
47BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
51AND-OR-INVERT GATES’51, ’S51 DUAL 2-WIDE 2-INPUTpositive logic:Y = AB + CD
644-2-3-2 INPUT AND-OR INVERT GATEpositive logic:Y = ABCD + EF + GHI + JK
73DUAL J-K FLIP-FLOPS WITH CLEAR
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
VCC f g a b c d e
GNDADRBIN-PUT
RBOUT-PUT
LAMPTEST
CB
f g a b
C LTBI/
RBO RBI D AB
OUTPUTS
c d e
INPUTS INPUTS
1 2 3 4 5 6 7
14 13 12 11 10 9 8
1CLR 1D 1CK 1PR 1Q 1Q GND
VCC 2CLR 2D 2CK 2PR 2Q 2Q
CLR
PRD Q
QCK
Q
QD
CK
CLR
PR
1 2 3 4 5 6 7 8
14 13 12 11 10 9
1Q 1D 2D ENABLE3–4
VCC 3D 4D 4Q
1Q 2Q 2QENABLE
1–2 GND 3Q 3Q
1516
4Q
Q
Q
D
G
D
G
Q
Q
Q
G
D
Q
D
G
Q
Q
1 2 3 4 5 6 7
14 13 12 11 10 9 8
1A 2A 2B 2C 2D 2Y GND
VCC 1B 1D 1C 1Y
MAKE NO EXTERNAL CONNECTION
1 2 3 4 5 6 7
14 13 12 11 10 9 8
1Y 2A 2B 2C 2D 2Y GND
VCC 1C 1B 1F 1E 1D 1Y
1 2 3 4 5 6 7
14 13 12 11 10 9 8
A E F G H I GND
VCC D C B K J Y
1 2 3 4 5 6 7
14 13 12 11 10 9 8
1CK 1CLR 1K VCC 2CK 2CLR 2J
1J 1Q 1Q GND 2K 2Q 2Q
Q Q
K CK J
Q
J
CLR
Q
K
CLR
CK
See page 164
See page 167
See page 168
74DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPSWITH PRESET AND CLEAR
754-BIT BISTABLE LATCHES
See page 170
See page 172
AND-OR-INVERT GATES‘LS51 2-WIDE 3-INPUT, 2-WIDE 2-INPUTpositive logic:1Y = (1A • 1B • 1C) + (1D • 1E • 1F)2Y = (2A • 2B) + (2C • 2D)
See page 166
76
Pin Assignments
854-BIT MAGNITUDE COMPARATORS
86QUADRUPLE 2-INPUT EXCLUSIVE-OR GATESpositive logic:Y = A ⊕ B or Y = AB + AB
90DECADE COUNTER
92DIVIDE-BY-TWELVE COUNTERS
934-BIT BINARY COUNTERS
97SYNCHRONOUS 6-BIT BINARY RATE MULTIPLIER
107DUAL J-K FLIP-FLOPS WITH CLEAR
109DUAL J-K POSITIVE-EDGE-TRIGGEREDFLIP-FLOPS WITH PRESET AND CLEAR
NC – No internal connection
NC – No internal connection
NC – No internal connectionSee page 173 See page 177
See page 174 See page 178
See page 180See page 175
See page 182See page 176
A
14 13 12 11 10 9 8
1 2 3 4 5 6 7
R0 (1) R0 (2) Q9 (1)
QA QD QB
BDINPUT
R0 (1) R0 (2) NC VCC Q9 (1) Q9 (2)
NC QA QD GND QB QC
INPUT
BD
A QC
Q9 (2)
A
14 13 12 11 10 9 8
1 2 3 4 5 6 7
R0 (1)
QA QD QC
INPUTB
NC NC NC VCC R0 (1) R0 (2)
NC QA QB GND QC QD
INPUT
B
A QD
R0 (2)
A
14 13 12 11 10 9 8
1 2 3 4 5 6 7
R0 (1) R0 (2)
QA QD QB
INPUTB
R0 (1) R0 (2) NC VCC NC NC
NC QA QD GND QB QC
INPUT
B
AQC
14 13 12 11 10 9 8
1 2 3 4 5 6 71J 1Q 1K
VCC
GND
1CK 2K 2CK 2J
2Q
1CLR 2CLR
1Q 2Q
JCK
KCK
Q
CLR CLR
QQQ
K J
1Q
2QVCC
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 81CLR 1J 1CK 1PR GND
2CLR 2CK 2PR2J 2Q
CK
KQKCLR
J Q
CLR
PRJ
CK
Q
Q
2K
1K 1Q
PR
4B
14 13 12 11 10 9 8
1 2 3 4 5 6 71B 1Y 2A 2B 2Y GND
4A 4Y 3B 3A 3YVCC
1A
VCC
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
A<BIN
A=BIN
A>BIN
A>BOUT
A=BOUT
A<BOUT
A3 B2 A1 B1 A0
B3DATAINPUT
A<B A=B A>B A>B A=B A<B GND
A3 A1 B1 A0
B3
A2 B0B2
A2
B0
DATA INPUTS
CASCADE INPUTS OUTPUTS
VCC
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8B E F A Z Y ENABLE
OUTPUT
GND
D CASCADE INPUT STROBE
B
CLEAR CLOCKC
CK
RATE INPUTENA-BLEUNITY/
RATE INPUTS OUTPUTS
D C CLEAR UNITY/CASCADE
ENA-BLE
INPUT
STROBE
E F A Z YENABLEOUTPUT
77
Pin Assignments
112DUAL J-K NEGATIVE-EDGE-TRIGGEREDFLIP-FLOPS WITH PRESET AND CLEAR
121MONOSTABLE MULTIVIBRATOR
122RETRIGGERABLE MONOSTABLE MULTIVIBRATORSWITH CLEAR
123DUAL RETRIGGERABLE MONOSTABLEMULTIVIBARATORS WITH CLEAR
124DUAL VOLTAGE-CONTROLLED OSCILLATORSWITH ENABLE INPUTS
125QUADRUPLE BUS BUFFER GATESWITH THREE-STATE OUTPUTSpositive logic:Y = A
126QUADRUPLE BUS BUFFER GATESWITH THREE-STATE OUTPUTSpositive logic:Y = A
128SN54128...75-Ω LINE DRIVERSN74128...50-Ω LINE DRIVERpositive logic:Y = A + B
NC – No internal connection
NC – No internal connection
See page 188 See page 192
See page 191See page 187
See page 186 See page 190
See page 189See page 184
2Q1Q
VCC
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 81CK 1K 1J 1PR 1Q GND
2K 2J2CK 2Q2CLR 2PR1CLR
CLRK
CK
J Q
Q
PR
PR Q
Q
J
CK
KCLR
VCC
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 81A 1B 1CLR 2Q 2
Cext2Rext/
CextGND
1Rext/Cext
1Cext 1Q 2CLR 2B 2A2Q
1Q
CLR
Q
Q
Q
Q
CLR
2YOUTPUT GNDVCC
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 82 1 1
RANGE1G
ENABLE
2RANGE
1YOUTPUT
~ VCC
~ GND
FREQUENCYCONTROL
1Cext
RNG
FREQCONT
FREQCONT
RNG
EN
Cext
Cext
EN
Y
Y
2Cext2G
ENABLE
3Y
14 13 12 11 10 9 8
1 2 3 4 5 6 71C 1A 1Y 2C
VCC
GND
4C 4A 4Y 3C 3A
2A 2Y
3Y
14 13 12 11 10 9 8
1 2 3 4 5 6 71C 1A 1Y 2C
VCC
GND
4C 4A 4Y 3C 3A
2A 2Y
NC
14 13 12 11 10 9 8
1 2 3 4 5 6 7NC A1 A2
VCC
GND
NCRext/
Cext Cext Rint
B Q
Q
Q
NC
Q
Q
14 13 12 11 10 9 8
1 2 3 4 5 6 7A1 A2 B1 B2
VCC
GND
Rext/Cext NC Cext NC Rint
CLR Q
Q
Q
CLR
4Y
14 13 12 11 10 9 8
1 2 3 4 5 6 71A 1B 2Y 2A 2B GND
4B 4A 3Y 3B 3AVCC
1Y
78
Pin Assignments
132QUADRUPLE 2-INPUT POSITIVE-NANDSCHMITT TRIGGERSpositive logic:Y = A • B
13313-INPUT POSITIVE-NAND GATESpositive logic:Y = A • B • C • D • E • F • G • H • I • J • K • L • M
136QUAD 2-INPUT EXCLUSIVE-OR GATESWITH OPEN COLLECTOR OUTPUTSpositive logic:Y = A ⊕ B = AB + AB
1373-TO 8-LINE DECODERS/DEMULTIPLEXERSWITH ADDRESS LATCHES
1383-TO-LINE DECODERS/DEMULTIPLEXRS
139DUAL 2-TO-4-LINE DECODERS/DEMULTIPLEXERS
140DUAL 4-INPUT POSITIVE-NAND 50-ΩLINE DRIVERSpositive logic:Y = ABCD
145BCD-TO-DECIMAL DECODERS/DRIVERSFOR LAMPS, RELAYS, MOS
NC – No internal connection
See page 192 See page 196
See page 198See page 193
See page 193 See page 200
See page 201See page 194
VCC
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8A B C G1 Y7 GND
Y0 Y1 Y2 Y3 Y4 Y5 Y6
Y0 Y1 Y2 Y3 Y4 Y5
Y6A
B C G1 Y7
DATA OUTPUTS
SELECT ENABLE OUTPUT
G2A G2B
G2A G2B
1GENABLE
ENABLE2GVCC
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 81A 1B 1Y2 1Y3 GND
2A 2B 2Y0 2Y1 2Y2 2Y3
Y3
1Y0 1Y1
DATA OUTPUTSSELECT
SELECT DATA OUTPUTS
A B Y0 Y1 Y2
A B Y0 Y1 Y2 Y3
G
G
GL G2
VCC
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8A B C G1 Y7 GND
Y0 Y1 Y2 Y3 Y4 Y5 Y6
Y0 Y1 Y2 Y3 Y4 Y5
Y6A
B C GL G2 G1 Y7
DATA OUTPUTS
SELECT ENABLE OUTPUT
2D
14 13 12 11 10 9 8
1 2 3 4 5 6 71B NC 1C 1D 1Y GND
2C NC 2B 2A 2YVCC
1A
VCC
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8A B C D E F G GND
M L K J I H Y
4B
14 13 12 11 10 9 8
1 2 3 4 5 6 71B 1Y 2A 2B 2Y GND
4A 4Y 3B 3A 3YVCC
1A
B
0
AVCC
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 81 2 5 6 GND
C D 9 8 7
3 4
OUTPUTS
OUTPUTS
A B C D
0 1 2 3 4 5 6 7 8 9
BCD-TO-DECIMAL
PARALLEL INPUTS
4B
14 13 12 11 10 9 8
1 2 3 4 5 6 71B 1Y 2A 2B 2Y GND
4A 4Y 3B 3A 3YVCC
1A
79
Pin Assignments
1488-TO-3-LINE OCTAL PRIORITY ENCODERS
1518-TO-1 LINE DATA SELECTORS/MULTIPLEXERS
153DUAL 4-LINE TO 1-LINE DATASELECTORS/MULTIPLEXERS
1544-LINE TO 16-LINE DECODER/DEMULTIPLEXER
See page 210
See page 208
See page 204
See page 212
1
A
24 23 22 21 20 19 18 17 16 15
1 2 3 4 5 6 7 8 9 10
2 3 4 5 6 7 8
B C D 15 14
2 3 4 5 6 7 8 9
B C D 15 14VCC 13
0 11
0
14
11
13
12GND
11
9
13
1
12
12
10
10
A
OUTPUTS
OUTPUTSINPUTS
G2 G1
G2 G1
VCC
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
5 6 7 EI A2 A1
E0 GS 3 2 1 0
A0
4 5 6 7 EI A2 A1 GND
E0 GS 3 2 1 0OUTPUT
A0
4
INPUTS
OUTPUTS
OUTPUTS
INPUTS
VCC
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
D2 D1 D0 Y W S
D4 D5 D6 D7 A B
C
3 2 1 0 Y W STROBE GND
4 5 6 7 A B C
D3
DATA INPUTS
DATA INPUTS DATA SELECT
OUTPUTS
STROBE
1G
VCC
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8B
SELECT
1C3 1C2 1C1 1C0 OUTPUT
1Y
GND
STROBE
2GA
SELECT 2C3 2C2 2C1 2C0
OUTPUT
2Y
DATA INPUTS
DATA INPUTS
2G2C3 2C2 2C1 2C0 2Y
A ABB
AABB
1Y1C01C11C21C31G
14710-TO-4 LINE PRIORITY ENCODER
See page 202
NC – No internal connection
1501-OF-16 DATA SELECTOR
See page 206
6
8
24 23 22 21 20 19 18 17 16 15
1 2 3 4 5 6 7 8 9 10
E5 E4 E3 E2 E1 E0 S
E9 E10 E11 E12 E13 E14 E15
5 4 3 2 1 0 STROBE WOUT-PUT
9 10 11 12 13 14 15VCC A
E7 C
7
14
11
13
12GND
C
W
A
E6
B
B
D
DDATA
SELECT
E8
DATA INPUTS
DATA SELECTDATA INPUTS
VCC
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
5 6 7 8 C B
D 3 2 1 9
A
I4 I5 I6 I7 I8 Y2 Y1 GND
NC Y3 I3 I2 I1 I9 Y0
4
INPUTS
INPUTS
OUTPUTS
80
Pin Assignments
1594-TO-16 LINE DECODER/DEMULTIPLEXER
161163SYNCHRONOUS 4-BIT BINARY COUNTERS
1648-BIT PARALLEL OUTPUT SERIAL SHIFT REGISTERS
1658-BIT SHFT REGISTERS
See page 222 See page 230
See page 224, 226
See page 228
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
VCCCLOCKINHIBIT D C B A
SERIALINPUT
OUTPUTQH
GNDOUTPUTQH
HGFECLOCKSHIFT/LOAD
CK HGFE QH
SHIFT/LOAD
CLOCKINHIBIT
D C B A SERIALIN
QH
PARALLEL INPUTS
PARALLEL INPUTS
14 13 12 11 10 9 8
1 2 3 4 5 6 7
VCC QF QE CLEAR CLOCK
GNDQDQCQBQABA
QGQH
SERIAL INPUTS
OUTPUTS
OUTPUTS
QDQCQBQAB
QF QE CLEARQGQH
A CK
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
VCC
RIPPLECARRYOUTPUT QA QB QC QD
ENABLET
GNDENABLEP
DCBACLOCKCLEAR
CK
OUTPUTS
DATA INPUTS
ENABLEPDCBA
QA QB QC QD ENABLET
LOAD
RIPPLECARRYOUTPUTCLEAR LOAD
20 19 18 17 16 15 14 13
5 6 7 8 9 10 11 12
D G2 G1 15 14 13 12 11
GND10987654
24 23 22 21
1 2 3 4
VCC A B C
210 3
1098765421 3
0 11
D G2 G1 15 14 13 12A B C
INPUTS OUTPUTS
OUTPUTS
155156DECODERS/DEMULTIPLEXERS
157158QUAD 2-TO 1-LINE DATA SELECTORS/MULTIPLEXERS
See page 218, 220
See page 214, 216
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
VCCDATA
2CSTRB
2G
SELECTINPUT
A 2Y3 2Y2 2Y1 2Y0
GND1Y01Y11Y21Y3SELECTINPUT
STRB1G
DATA1C
B B A A
B B A A
OUTPUTS
2Y3 2Y2 2Y1 2Y0
1G 1C
OUTPUTS
1Y01Y11Y21Y3
2G 2C
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
VCC STROBE 4A 4B 4Y 3A 3B 3Y
GND2Y2B2A1Y1B1ASELECT
INPUTS
INPUTS
INPUTS
INPUTS
OUTPUTS OUTPUTS
OUTPUTS OUTPUTS
G 4A 4B 4Y 3A 3B
3Y
2Y2B2A1Y1B1A
S
81
Pin Assignments
1668-BIT SHIFT REGISTERS
1694-BIT UP/DOWN SYNCHRONOUS BINARY COUNTERS
See page 232
See page 234
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
VCCSHIFT/LOAD
PARALLELINPUT
HOUTPUT
QH G E CLEAR
GNDCLOCKCLOCKINHIBIT
DCBASERIALINPUT
SHIFT/LOAD
H QH G F E
B C DCLOCKINHIBIT CKA
SERIALINPUT CLEAR
F
PARALLEL INPUTS
PARALLEL INPUTS
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
VCC
RIPPLECARRYOUTPUT QA QB QC QD
ENABLET LOAD
GNDDCBACKU/D
RIPPLECARRYOUTPUT
QA QB QC QD
A B C DCK
ENABLEP
ENABLET
ENABLEP
UP/DOWN LOAD
OUTPUTS
DATA INPUTS
1704-BY-4-REGISTER FILES
See page 236
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
VCCDATA
D1 WA WB WRITE READ Q1 Q2
GNDQ3Q4RARBD4D3D2
D1 WA WB GW GR Q1
D4 RA Q4 Q3D3
OUTPUTSWRITE SELECT ENABLE
Q2D2
RB
DATA READ SELECT OUTPUTS
1734-BIT D-TYPE REGISTERS
174HEX D-TYPE FLIP-FLOPS
175QUAD D-TYPE FLIP-FLOPS
See page 241
See page 240
See page 238
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
VCC CLEAR 1D 2D 3D 4D G2 G1
GNDCLOCK4Q3Q2Q1QNM
CLEAR 1D 2D 3D 4D DATAENABLE
OUTPUTCONTROL
DATA ENABLEINPUTSDATA INPUTS
OUTPUT CONTROL OUTPUTS
CK4Q3Q2Q1Q
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
VCC 6Q 6D 5D 5Q 4D 4Q CLOCK
GND3Q3D2Q2D1D1QCLEAR
Q DCK
CLEAR
D Q
CLEAR
D Q
CLEARCK CK
CK CKCKQ D D Q D Q
CLEAR CLEAR CLEAR
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
VCC 4Q 4Q 4D 3D 3Q 3Q CLOCK
GND2Q2Q2D1D1Q1QCLEAR
CK DCLRQ Q
Q
DCKCLR
Q Q
D CKCLR
Q
CKCLR
Q Q
D
181ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS
See page 242
20 19 18 17 16 15 14 13
5 6 7 8 9 10 11 12
B2 A3 B3 G Cn+4 P A = B F3
GNDF2F1F0MCnS0S1
INPUTS OUTPUTS
INPUTS
24 23 22 21
1 2 3 4
VCC A1 B1 A2
S3A0B0 S2
OUTPUTS
F2F1F0MCnS0S1S3A0 S2
B2 A3 B3 G Cn+4 P A = BA1 B1 A2
F3B0
82
Pin Assignments
182LOOK-AHEAD CARRY GENERATORS
See page 244
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
VCCDATA
A CLOCKRIPPLECLOCK
MAX/MIN LOAD
DATAC
GNDQDQCDOWN/UP
ENA-BLE
QAQBDATAB
INPUT
DATAD
INPUTS OUTPUTS INPUTS
INPUTSOUTPUTS OUTPUTS
QDQCDN/UPCTENQAQB
A RIPPLECLOCK
MAX/MIN
LOAD C
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
VCC P2 G2 Cn Cn+x Cn+y G
GNDPOUTPUT
P3G3P0G0P1G1
INPUTS OUTPUTS
INPUTS
Cn+z
P2 G2 Cn Cn+x Cn+y G
Cn+z
P3G3P0G0P1 P
G1
193SYNCHRONOUS UP/DOWN DUAL CLOCK COUNTERS
See page 252
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
VCCDATA
A CLEARBO-
RROW CARRY LOADDATA
C
GNDQDQCCOUNTUP
COUNTDOWN
QAQBDATAB
INPUT
DATAD
INPUTS OUTPUTS INPUTS
INPUTSOUTPUTS OUTPUTS
QDQCQAQB
A BO-RROW
CARRY LOAD CCLEAR
COUNTUP
COUNTDOWN
B D
192PRESETTABLE SYNCHRONOUS4-BIT UP/DOWN COUNTERS
See page 250
1944-BIT BIDIRECTIONAL UNIVERSALSHIFT REGISTERS
1954-BIT PARALLEL-ACCESS SHIFT REGISTERS
See page 256
See page 254
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
VCC QA QB QC QD CLOCK S1
GNDSHIFTLEFT
SERIALINPUT
DCBASHIFTRIGHTSERIALINPUT
CLEAR
S0
PARALLEL INPUTS
QA QB QC QD CLOCK S1
S0
DCBA LR
CLEAR
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
VCC QA QB QC QD QD CLOCK
GNDDCBAKJCLEAR
SHIFT/LOAD
SERIAL INPUTS
OUTPUTS
QA QB QC QD QD CK
PARALLEL INPUTS
DCBAKJ
CLEAR SHIFT/LOAD
P1 Q1 Q0 CPD CPU Q2 Q3
VCC P0 MR TCD TCU PL P2
1 2 3 4 5 6 7
16 15 14 13 12 11 10
8
9
GND
P3
190191SYNCHRONOUS UP/DOWN DUAL CLOCK COUNTERS
See page 246, 248
83
Pin Assignments
221DUAL MONOSTABLE MULTIVIBRATORS
See page 258
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
VCC1 Rext/
Cext1
Cext 1Q 2Q 2B
GND2 Rext/Cext
2Cext
2Q1Q1CLR1B1A
2A
Q
QCLR
Q
Q
CLR
2CLR
2373-TO-8 LINE DECODER DEMULTIPLEXERWITH ADDRESS LATCHES
2383-TO-8-LINE DECODERS/DEMULTIPLEXERS
See page 260
See page 262
E1
16 15 14 13
5 6 7 8
910
A0
Y0 Y3 Y4
GNDE3
1 2 3 4A1 E2
12 11
Y1 Y2 Y5 Y6VCC
Y7A2
240OCTAL BUFFERS/LINE DRIVERS/LINE RECEIVERS
241OCTAL BUFFERS/LINE DRIVERS/LINE RECEIVERS
243QUADRUPLE BUS TRANSCEIVERS
See page 264
See page 266
See page 268NC – No internal connection
2G
18 17 16 15 14 13
5 6 7 8 9 10GND2Y11A42Y21A32Y31A22Y4
1 2 3 41G 1A1
12 1120 192A11Y42A21Y32A31Y22A41Y1VCC
2G
18 17 16 15 14 13
5 6 7 8 9 10GND2Y11A42Y21A32Y31A22Y4
1 2 3 41G 1A1
12 1120 192A11Y42A21Y32A31Y22A41Y1VCC
14 13 12 11 10 9 8
1 2 3 4 5 6 7
VCC 1B 2B 3B 4B
GND4A3A2A1ANCGAB
NCGBA
245OCTAL BUS TRANSCEIVERS
See page 272
A1 A2 A3 A4 A5 A6 A7 A8 GND
B1 B2 B3 B4 B5 B6 B7VCC B8G
DIR
ENABLE
18 17 16 15 14 13
5 6 7 8 9 101 2 3 4
12 1120 19
244OCTAL BUFFERS/LINE DRIVERS/LINE RECEIVERS
See page 270
2G
18 17 16 15 14 13
5 6 7 8 9 10GND2Y11A42Y21A32Y31A22Y4
1 2 3 41G 1A1
12 1120 192A11Y42A21Y32A31Y22A41Y1VCC
A0 A1 A3 LE OE1 OE0 Y7
VCC Y0 Y1 Y2 Y3 Y4 Y5
1 2 3 4 5 6 7
16 15 14 13 12 11 10
8
9
GND
Y6
84
Pin Assignments
2598-BIT ADDRESSABLE LATCHES
260DUAL 5-INPUT POSITIVE-NOR GATESpositive logic:Y = A + B + C + D + E
See page 286
See page 288
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
VCC CLEAREN-
ABLEDATA
IN Q7 Q6 Q5
GND
Q2Q1Q0
CB
OUTPUTS
LATCH SEL
Q4
OUTPUTS
A
Q4Q3 Q5 Q6 Q7
CLEAR G DABC
Q2Q1Q0 Q3
14 13 12 11 10 9 8
1 2 3 4 5 6 7
VCC 2E 2D 2C 2B
GND2Y1Y2A1C1B1A
1D1E
247 BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERSWITH RIPPLE BLANKING
2501-OF-16 DATA GENERATOR/MULTIPLEXER
251DATA SELECTORS/MULTIPLEXERS
253DUAL DATA SELECTORS/MULTIPLEXERS
257QUAD DATA SELECTORS/MULTIPLEXERS
258QUAD DATA SELECTORS/MULTIPLEXERS
See page 278
See page 280
See page 274 See page 282
See page 284See page 276
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
VCC f g a b c d
GNDADRBIN-PUT
RBOUT-PUT
LAMPTEST
C
OUTPUTS
INPUTS
e
INPUTS
B
f g a b c d e
B C LTBI/
RBO RBI D A
20 19 18 17 16 15 14 13
5 6 7 8 9 10 11 12
11 12 13 14 15 A B C
GNDDDATA
SELECT
WOUT-PUT
STROBE0123
24 23 22 21
1 2 3 4
VCC 8 9 10
567 4
E11 E12 E13 E14 E15 A BE8 E9 E10
DWGE0E1E2E3E5E6 E4
CE7
DATA INPUTS
DATA INPUTS
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
VCC 4 5 6 7 A B C
GNDSTROBEWY0123
DATA SELECTDATA INPUTS
DATA INPUTS OUTPUTS
D4 D5 D6 D7 A B
SWYD0D1D2
D3 C
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
VCC
OUTPUTCONTROL
2GA
SELECT 2C3 2C2 2C1 2COOUTPUT
2Y
GNDOUTPUT1Y
1C01C11C21C3BSELECT
OUTPUTCONTROL
1G
DATA INPUTS
DATA INPUTS
2C3 2C2 2C1 2CO2G
2Y
B B A A
1Y1C01C11C21C31G B B A A
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
VCC
OUTPUTCONTROL
G 4A ABOUTPUT
4Y 3A 3BOUTPUT
3Y
GND2YOUTPUT
2B2A1YOUTPUT
1B1ASELECT
INPUTS
INPUTS INPUTS
INPUTS
2Y2B2A1Y1B1A
S
G 4A AB 4Y 3A 3B
3Y
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
VCC
OUTPUTCONTROL
G 4A ABOUTPUT
4Y 3A 3BOUTPUT
3Y
GND2YOUTPUT
2B2A1YOUTPUT
1B1ASELECT
INPUTS
INPUTS INPUTS
INPUTS
2Y2B2A1Y1B1A
S
G 4A AB 4Y 3A 3B
3Y
85
Pin Assignments
NC – No internal connection
265QUAD COMPLEMENTARY-OUTPUT ELEMENTSpositive logic:Y = A, W = AY = AB, W = AB
266QUAD 2-INPUT EXCLUSIVE-NOR GATESWITH OPEN-COLLECTOR OUTPUTSpositive logic:Y = A ⊕ B
273OCTAL D-TYPE FLIP-FLOPS
276QUAD J-K FLIP-FLORS
279QUAD S-R LATCHES
2809-BIT ODD/EVEN PARITYGENERATORS/CHECKERS
See page 291
See page 292
See page 289 See page 293
See page 290 See page 294
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
VCC 4A 4W 4Y 3B 3A 3W
GND2Y2W2B2A1Y1W
3Y
1A
1 2 3 4 5 6 7
14 13 12 11 10 9 8
1A 1B 1Y 2Y 2A 2B GND
VCC 4B 4A 4Y 3Y 3B 3A
Q D
CK
CLEAR
D Q
CK
CLEAR
CLEAR CLEAR
Q D D Q
CK CK
8Q
18 17 16 15 14 13
5 6 7 8 9 10GND4Q4D3D3Q2Q2D1D
1 2 3 4CLEAR 1Q
12 1120 19CLOCK5Q5D6D6Q7Q7D8DVCC
Q D
CK
CLEAR
D Q
CK
CLEAR
CLEAR CLEAR
Q D D Q
CK CK
4J
18 17 16 15 14 13
5 6 7 8 9 10GND2J2CK2K2Q1Q1K1CK
1 2 3 4CLEAR 1J
12 1120 19PRESET3J3CK3K3Q4Q4K4CKVCC
CLRK
CKJPRQ
CLRK
CKJPRQ
CLR
CLR
CK
CK
J
Q
J
Q
PR
PR
K
K
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
VCC 4S 4R 4Q 3S1 3R
GND2Q2S2R1Q1S21S11R
3Q3S1
14 13 12 11 10 9 8
1 2 3 4 5 6 7
VCC D C B A
GNDΣ ODDΣ EVENIINPUT
NCHG
F E D C B
H
A
EF
G
INPUTS
INPUTS
OUTPUTS
ΣEVEN
ΣODDI
2834-BIT BINARY FULL ADDERS
See page 296
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
VCC B3 A3 Σ 3 A4 B4 Σ 4
GNDC0B1A1Σ 1A2B2Σ 2
C4
B3 A3 Σ 3 A4 B4 Σ 4
C0B1A1Σ 1A2B2
C4Σ 2
14 13 12 11 10 9 8
1 2 3 4 5 6 7
VCC D C B A
GNDPARITYI/O
PARITYERROR
IINPUT
XMITHG
EF
INPUTS
INPUTS
OUTPUTS
D C BEF
AG
PARITYI/O
PARITYERRORIXMITH
2869-BIT ODD/EVEN PARITY GENERATORS/CHECKERSWITH BUS DRIVER PARITY I/O PORT
See page 298
86
Pin Assignments
321CRYSTAL-CONTROLLED OSCILLATOR
3238-BIT BIDIRECTIONAL SHIFT/STORAGE REGISTERS
See page 314
See page 312
G2G1
F/QF D/QD B/QB CLOCK
SHIFTRIGHT
SR
18 17 16 15 14 13
5 6 7 8 9 10
SHIFTLEFTSL QH´ H/QH
GNDCLEARQA´A/QAC/QCE/QEG/QG
1 2 3 4
VCC S1
S0
12 1120 19
F/QF D/QD B/QB CKSL QH´ H/QHS1
CLEARQA´A/QAC/QCE/QEG/QGG
S0 SR
OUTPUTCONTROLS
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
VCCXTAL
2XTAL
1 F/2 F VCC´ F´
GND2
FF/4FFDFFQGND1
TANK2
F´
TANK1
FF/4FFDFFQTANK2
TANK1
XTAL2
XTAL1
F/2 F´F
F´
292PROGRAMMABLE FREQUENCYDIVIDER/DIGITAL TIMER
2934-BIT BINARY COUNTERS
NC – No internal connection
NC – No internal connection
294PROGRAMMABLE FREQUENCYDIVIDER/DIGITAL TIMER
297DIGITAL PHASE-LOCKED-LOOP FILTERS
298QUAD 2-INPUT MULTIPLEXERS WITH STORAGE
2998-BIT BIDIRECTIONAL UNIVERSALSHIFT/STORAGE REGISTERS
NC – No internal connection
See page 302 See page 310
See page 308See page 300
See page 306
See page 304
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
VCC QA QB QC QD CLOCKWORDSELECT
GNDD1D2C2B1A1A2
DATAINPUT
C1
DATA INPUTS
B2
OUTPUTS
QA QB QC QD CK WS
D1D2C2B1A1A2
B2 C1
G2G1
F/QF D/QD B/QB CLOCK
SHIFTRIGHT
SR
18 17 16 15 14 13
5 6 7 8 9 10
SHIFTLEFTSL QH´ H/QH
GNDCLEARQA´A/QAC/QCE/QEG/QG
1 2 3 4
VCC S1
S0
12 1120 19
F/QF D/QD B/QB CKSL QH´ H/QHS1
CLEARQA´A/QAC/QCE/QEG/QGG
S0 SR
OUTPUTCONTROLS
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
VCC C D φ A2ECPDOUT
EXOROUT φ B
GNDI/DOUT
U/DI/DCLK
KCLK
ENAAB
φ A1
C D φ A2 ECPDOUT
EXOROUT
φ B
φ A1
I/DOUTU/DENAA
I/DCLK
KCLK
B
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
VCC C D TP3 NC CLEAR A
GNDQOUTTP2CLK2CLK1TP1EB
NC
C D TP3 CLR A
QTP2CLK2CLK1TP1E
B
14 13 12 11 10 9 8
1 2 3 4 5 6 7
VCCINPUT
BINPUT
A QA QD
GNDNCQBQCNCNCNC
RO(1)RO(2)
OUTPUTS
OUTPUTS
B A QARO(1)RO(2)
QBQC
QD
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
VCC C D NC NC CLEAR NC
GNDQOUTNCCLK2CLK1TPAB
NC
C D CLR A
QCLK2CLK1TPA
B
87
Pin Assignments
3488-LINE TO 3-LINE PRIORITY ENCODER
365HEX BUS DRIVERS
367HEX BUS DRIVERS
368HEX BUS DRIVERS
373OCTAL D-TYPE LATCHES
See page 316
See page 322
See page 324
See page 324
See page 325
Q D
OE
D Q
OE
Q D D Q
8Q
18 17 16 15 14 13
5 6 7 8 9 10GND4Q4D3D3Q2Q2D1D
1 2 3 4OUTPUT
CONTROL1Q
12 1120 19
ENABLEG5Q5D6D6Q7Q7D8DVCC
Q D
OE
D Q
OE
Q D D Q
OE OE OE OEG G G G
G G G G
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
VCC G2 6A 6Y 5A 5Y 4A 4Y
GND3Y3A2Y2A1Y1AG1
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
VCC G2 6A 6Y 5A 5Y 4A 4Y
GND3Y3A2Y2A1Y1AG1
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
VCC EO GS 3 2 1 0OUTPUT
A0
GNDA1A2EI7654
INPUTSOUTPUTS
INPUTS OUTPUTS
EO GS 3 2 1 0
A1A2EI765
A04
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
VCC G2 6A 6Y 5A 5Y 4A 4Y
GND3Y3A2Y2A1Y1AG1
3543568-INPUT MULTIPLEXERS/REGISTERS 3-STATE
See page 318, 320
S0 S1 S2SELECT
CONTROL
18 17 16 15 14 13
5 6 7 8 9 10
W G3
GNDDATACONTROL/CLOCK
D0D1D2D3D4D5
1 2 3 4
VCC Y
D7 D6
12 1120 19G1G2
S0 S1 S2W G3Y G1G2
DATAC/CD0D1D2D3D4D5D6
D7 SC
366HEX BUS DRIVERSHEX BUFFERS/LINE DRIVERS 3-STATE
See page 323
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
VCC G2 6A 6Y 5A 5Y 4A 4Y
GND3Y3A2Y2A1Y1AG1
88
Pin Assignments
374OCTAL D-TYPE FLIP-FLOPS
3754-BIT BISTABLE LATCHES
378HEX D-TYPE FLIP-FLOPS
390DUAL DECADE COUNTERS
393DUAL 4-BIT BINARY COUNTERS
3954-BIT UNIVERSAL SHIFT REGISTERS
399QUAD 2-INPUT MULTIPLEXER WITH STORAGE
See page 329 See page 334
See page 332
See page 327 See page 331
See page 330See page 326
C2 C1 QC CLOCKD1 D2
GNDQBB1B2A2A1
VCC QD
WORDSELECT
QA
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
C2 C1 QCD1 D2QD
QBB1B2A2A1QA
WS CK
14 13 12 11 10 9
1 2 3 4 5 6 7
VCC 2A2
CLEAR 2 QA 2 QB 2 QC 2 QD
GND1 QD1 QC1 QA1CLEAR
1A
OUTPUTS
OUTPUTS
QACLEAR
A
QB QC
CLEARA
QB QC
8
1 QB
QA QD
QD
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
VCC QA QB QC QD
CASCADEOUTPUT
QD´ CLOCK
GND
LOADSHIFTDCBA
SERIALINPUT
OUTPUTCONTROL
PARALLEL INPUTS
CLEAR
OUTPUTS
QA QB QC QD QD´ CK
SERIALINPUT
OUTPUTCONTROLCLEAR
LOADSHIFT
DCBA
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
VCC 2A2
CLEAROUTPUT
2 QA 2B 2 QB 2 QC 2 QD
GND1 QD1 QC1 QB1B1 QAOUTPUT
1CLEAR
1A
OUTPUTS
OUTPUTS
QACLEAR
A
B QB QC QD
QACLEAR
A
B QB QC QD
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
VCC 6Q 6D 5D 5Q 4D 4Q CLOCK
GND3Q3D2Q2D1D1QENABLEG
Q DCK
G
D Q
G
Q D
GCK CK
CK CKCKQ D D Q Q D
G G G
Q D
G
D Q
G
Q D D Q
8Q
18 17 16 15 14 13
5 6 7 8 9 10GND4Q4D3D3Q2Q2D1D
1 2 3 4ENABLE
G1Q
12 1120 19CLOCK5Q5D6D6Q7Q7D8DVCC
Q D
G
D Q
G
Q D D Q
G G G G
CK CK CK CK
CK CK CK CK
Q D
OE
D Q
OE
Q D D Q
8Q
18 17 16 15 14 13
5 6 7 8 9 10GND4Q4D3D3Q2Q2D1D
1 2 3 4OUTPUT
CONTROL1Q
12 1120 19CLOCK5Q5D6D6Q7Q7D8DVCC
Q D
OE
D Q
OE
Q D D Q
OE OE OE OECK CK CK CK
CK CK CK CK
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
VCC 4D 4Q 4QENABLE
3-4 3Q 3Q 3D
GND2D2Q2QENABLE1-2
1Q1Q1D
Q Q
DG
D G
Q Q QQ
DG D G
377OCTAL D-TYPE FLIP-FLOPS
See page 328
89
Pin Assignments
423RE-TRIGGERABLE MONO-STABLE MULTIVIBRATORpositive logic:Y = A
5188-BIT IDENTITY COMPARATOR
5205218-BIT IDENTITY COMPARATOR
533OCTAL D-TYPE TRANSPARENT LATCHES
534OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
540541OCTAL BUFFERS AND LINE DRIVERS
See page 346
See page 342, 344
See page 340 See page 348, 349
See page 347
See page 335
1 Rext/Cext
GND2 Rext/Cext
2Cext
2Q1Q1CLR
VCC
1A 1B
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
CLR
CLR
1 Cext 1Q 2Q 2CLR 2B 2A P=Q
P0 Q0 P1 Q1 P2 Q2 P3 Q3 GND
Q7 P7 Q6 P6 Q5 P5 Q4VCC P4
G
1 2 3 4 5 6 7 8 9 10
16 15 14 13 12 1120 19 18 17
P0 Q0 P1 Q1 P2 Q2 P3 Q3
Q7 P7 Q6 P6 Q5 P5 Q4
P4
P=Q
G
P=Q
P0 Q0 P1 Q1 P2 Q2 P3 Q3 GND
Q7 P7 Q6 P6 Q5 P5 Q4VCC P4
G
1 2 3 4 5 6 7 8 9 10
16 15 14 13 12 1120 19 18 17
P4G
P0 Q0 P1 Q1 P2 Q2 P3 Q3
Q7 P7 Q6 P6 Q5 P5 Q4P=Q
1Q 2Q 3Q 4Q1D 2D 3D 4D GND
8D 7D 6D 5DVCC C8Q 7Q 6Q 5Q
1 2 3 4 5 6 7 8 9 10
16 15 14 13 12 1120 19 18 17
OC
DC7 Q
DC8
Q DC5
QDC6Q
DC4
Q
OCDC1
OC D OCC2
DC3
Q
OC
OCOC OCOC
DCK
OC
D
OCCK
7Q8Q DCK
DCK
5Q6Q
OC OC
D
4Q
OCDOC D OC
2Q1Q
D
3Q
OCCK CKCK CK
8D 7D 6D 5DVCC CLK8Q 7Q 6Q 5Q
1Q 2Q 3Q 4Q1D 2D 3D 4D GND
1 2 3 4 5 6 7 8 9 10
16 15 14 13 12 1120 19 18 17
OC
G2
A1 A2 A3 A4 A5 A6 A7 A8 GND
Y1 Y2 Y3 Y4 Y5 Y6 Y7VCC Y8
G1
1 2 3 4 5 6 7 8 9 10
16 15 14 13 12 1120 19 18 17
442QUADRUPLE TRIDIRECTIONAL BUS TRANSCEIVERS
See page 336
465OCTAL BUFFERS WITH 3-STATE OUTPUTS
See page 338
G2
A1 Y1 A2 Y2 A3 Y3 A4 Y4 GND
A8 Y8 A7 Y7 A6 Y6 A5VCC Y5
G1
1 2 3 4 5 6 7 8 9 10
16 15 14 13 12 1120 19 18 17
A1 Y1 A2 Y2 A3 Y3 A4 Y4
Y5
A8 Y8 A7 Y7 A6 Y6 A5G2
G1
C2
18 17 16 15 14 13
5 6 7 8 9 10CS
GC A1 A2 S1
GNDB4B3
1 2 3 4B1 B2
12 1120 19S0GB GA A3 A4VCC
C4C3C1
90
Pin Assignments
563OCTAL D-TYPE TRANSPARENT LATCHESWITH INVERTED OUTPUTS
564OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
569SYNCHRONOUS 4-BIT UP/DOWN COUNTERS
573OCTAL D-TYPE TRANSPARENT LATCHES
574OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
575OCTAL D-TYPES EDGE-TRIGGERED FLIP-FLOPS
See page 354 See page 359
See page 360See page 355
See page 356
See page 358
1 2 3 4 5 6 7 8 9 10 11 12
20 19 18 17 16 1524 23 22 21 14 13
OC
NC
D0 D1 D2 D3 D4 D5 D6 D7
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
SCLR NC
CLK
GND
NC
CLK
VCC
SCLR
OC D0 D1 D2 D3 D4 D5 D6 D7
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
1 2 3 4 5 6 7 8 9 10
16 15 14 13 12 1120 19 18 171Q
1D 2D 3D 4D 5D 6D GND
VCC
OC
CLK
CLK
OC 7D 8D
2Q 3Q 4Q 5Q 6Q 7Q 8Q
1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q
1D 2D 3D 4D 5D 6D 7D 8D
OCRCO
CLK DA DB DC DD GND
VCC
U/D
CCO QA QB QC QD ENT SLOAD
ENP ACLR SCLR
1 2 3 4 5 6 7 8 9 10
16 15 14 13 12 1120 19 18 17
DC DD ENP ACLR SCLR
U/D SLOAD
DA DB
OCRCO CCO QA QB QC QD ENT
CLK
1Q
1D 2D 3D 4D 5D 6D GND
VCCENABLE
C
OC 7D 8D
2Q 3Q 4Q 5Q 6Q 7Q 8Q
G
Q OE
D G
Q OE
D G
Q OE
D G
Q OE
D G
Q OE
D G
Q OE
D G
Q OE
D G
Q OE
D
1 2 3 4 5 6 7 8 9 10
16 15 14 13 12 1120 19 18 17
4D
1QVCC CLK2Q 3Q 4Q 5Q 6Q 7Q 8Q
1 2 3 4 5 6 7 8 9 10
16 15 14 13 12 1120 19 18 17
1D 2D 3D 4D 5D 6D GNDOC 7D 8D
CK
Q OE
D CK
Q OE
D CK
Q OE
D CK
Q OE
D CK
Q OE
D CK
Q OE
D CK
Q OE
D CK
Q OE
D
1Q
1D 2D 3D 4D 5D 6D GND
VCCENABLE
C
OC 7D 8D
2Q 3Q 4Q 5Q 6Q 7Q 8Q
1 2 3 4 5 6 7 8 9 10
16 15 14 13 12 1120 19 18 17
OC C
1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q
1D 2D 3D 4D 5D 6D 7D 8D
NC – No internal connection
543OCTAL REGISTERED TRANSCEIVERS
561SYNCHRONOUS 4-BIT COUNTER
See page 352
See page 350
1 2 3 4 5 6 7 8 9 10 11 12
20 19 18 17 16 1524 23 22 21 14 13
OEABLEBA
VCC OEABLEAB
CEAB
CEBA
OEBA A1 A2 A3 A4 A5 A6 A7 A8
B1 B2 B3 B4 B5 B6 B7 B8
LEBA GND
CEABOEBA A1 A2 A3 A4 A5 A6 A7 A8
LEABCEBA B1 B2 B3 B4 B5 B6 B7 B8
RCO
CLK DA DB DC DD ENP GND
CCO QA QB QC QD ENTVCC G SLOAD
ALOAD ACLR SCLR
1 2 3 4 5 6 7 8 9 10
16 15 14 13 12 1120 19 18 17
RCO CCO QA QB QC QD ENTG
DA DB DC DD ENP ACLR SCLR
ALOAD SLOAD
CLK
91
Pin Assignments
576OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
577OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
NC – No internal connection
See page 361
See page 362
1QVCC CLK2Q 3Q 4Q 5Q 6Q 7Q 8Q
1D 2D 3D 4D 5D 6D GNDOC 7D 8D
1 2 3 4 5 6 7 8 9 10
16 15 14 13 12 1120 19 18 17
CK
OE
D
Q
CK
OE
D
Q
CK
OE
D
Q
CK
OE
D
Q
CK
OE
D
Q
CK
OE
D
Q
CK
OE
D
Q
CK
OE
D
Q
1 2 3 4 5 6 7 8 9 10 11 12
20 19 18 17 16 1524 23 22 21 14 13
OC
NC
D0 D1 D2 D3 D4 D5 D6 D7SCLR NC
CLK
GND
NC
CLK
VCC
SCLR
OC D0 D1 D2 D3 D4 D5 D6 D7
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
580OCTAL D-TYPE TRANSPARENT LATCHESWITH INVERTED OUTPUTS
5908-BIT BINARY COUNTER WITH OUTPUT REGISTER
5928-BIT BINARY COUNTER WITH INPUT REGISTER
5938-BIT BINARY COUNTER WITH INPUT REGISTER
See page 368
See page 366
See page 364
See page 363
1QVCCENABLE
C2Q 3Q 4Q 5Q 6Q 7Q 8Q
1D 2D 3D 4D 5D 6D GNDOC 7D 8D
1 2 3 4 5 6 7 8 9 10
16 15 14 13 12 1120 19 18 17
OE
D
Q
G
OE
D
Q
G
OE
D
Q
G
OE
D
Q
G
OE
D
Q
G
OE
D
Q
G
OE
D
Q
G
OE
D
Q
G
VCC
1 2 3 4 5 6 7 8
12 11 10 916 15 14 13RCOCCKENRCK CCKCLOAD CCLRQA
QC QD QE QF QG GND
QB RCO
QB QH
QC QD QE QF QG QH
CCKEN CCLRQA CLOAD RCK CCK
1 2 3 4 5 6 7 8
12 11 10 916 15 14 13RCOCCKENRCK CCKG CCLRQA
QC QD QE QF QG GND
VCC
QB QH
RCK CCKCCKENG CCLRQA
QC QD QE QF QG QH
QB RCO
1 2 3 4 5 6 7 8 9 10
16 15 14 13 12 1120 19 18 17RCOCCKEN CCK CCLRGVCC
CLOAD
G
B/QB C/QC D/QD E/QE F/QF G/QG GND
RCK CCKEN
A/QA H/QH
A/QA
CCLRCCKENG RCK CCKEN CCKRCKENG
RCO
CLOADB/QB C/QC D/QD E/QE F/QF G/QG H/QH
RCKEN
5948-BIT SHIFT REGISTER WITH OUTPUT LACH
5955968-BIT SHIFT REGISTER WITH OUTPUT LATCH
See page 372, 374
See page 370
RCLR QH'RCK SCKSER SCLRQA
QC QD QE QF QG GND
VCC
QB QH'
QB QH
QC QD QE QF QG QH
RCKQA RCLR SCKSER SCLR
1 2 3 4 5 6 7 8
12 11 10 916 15 14 13
1 2 3 4 5 6 7 8
12 11 1016 15 14 13 9QH'RCK SCKSER SCLRGQA
QC QD QE QF QG GND
VCC
QB QH'
QB QH
QC QD QE QF QG QH
RCKQA SCKSER SCLRG
92
Pin Assignments
620621623OCTAL BUS TRANSCEIVERS
624VOLTAGE-CONTROLLED OSCILLATOR
628VOLTAGE-CONTROLLED OSCILLATOR
NC – No internal connection
NC – No internal connection
629VOLTAGE-CONTROLLED OSCILLATOR
See page 380, 381, 382 See page 385
See page 383
See page 384
16 15 14 13 12 11 10
1 2 3 4 5 6 71 1
RANGE1
ENABLE
2ENABLEVCC
9
82 1Y
OUT-PUT
~GND
~VCC
YCext
FREQCONTRNG
YCextRNG
FREQCONT
FREQCONTROL
2RANGE GND
2YOUT-PUT
2Cext
1Cext
EN
EN
1 2 3
20 18
OEAB A1
VCC
19
OEBA
4
17
A2
B1
5
16
A3
B2
6
15
A4 A5 A6 A7 A8
B3
7
14
B4
8
13
B5
9
12
B6
10
11
GND
B7 B8
FREQCONT-ROL
14 13 12 11 10 9 8
1 2 3 4 5 6 7RANGE CX1 CX2 ENABLE Y
OUTPUTGND
ZOUTPUTNC NC NC VCC
EN
~GND
~VCC
RANGE
FREQCONTROL
Cext
Z
Y
FREQCONT-ROL
14 13 12 11 10 9 8
1 2 3 4 5 6 7RANGE CX1 CX2 ENABLE Y
OUTPUTGND
ZOUTPUTNC VCC
EN
~GND
~VCC
RANGE
FREQCONTROL
Cext
Z
Y
Rext
5978-BIT SHIFT REGISTER WITH INPUT LATCH
See page 376
1 2 3 4 5 6 7 8
12 11 1016 15 14 13 9SLOAD QH'RCK SCKSER SCLRA
C D E F G GND
VCC
B QH'
B H
RCK SCK
C D E F G H
A SER SCLRSLOAD
5988-BIT SHIFT REGISTERS
See page 378
SLOAD
SCLRSCKENDS
B/QB C/QC D/QD E/QE F/QF G/QG GND
RCK SCKSER1
A/QA H/QH
SER0
RCK
1 2 3 4 5 6 7 8 9 10
16 15 14 13 12 1120 19 18 17VCC
QH'
SLOADB/QB C/QC D/QD E/QE F/QF G/QG H/QH
QH'G
SCLRSCKENDS SCKSER1SER0 G
A/QA
93
Pin Assignments
641645OCTAL BUS TRANSCEIVERS
646647648OCTAL BUS TRANSCEIVERS AND REGISTERS
651652653654OCTAL BUS TRANSCEIVERS AND REGISTERS
See page 392, 394, 396
See page 389, 391
See page 398, 400, 402, 404
1 2 3 4 5 6 7 8 9 10 11 12
20 19 18 17 16 1524 23 22 21 14 13
SELECTAB
DIREC-TION
A1 A2 A3 A4 A5 A6 A7CLOCKAB
A8 GND
SELECTAB
DIREC-TION A1 A2 A3 A4 A5 A6 A7 A8
CLOCKAB
CLOCKBA B7
SELECTBA
CONT-ROL
G B1 B2 B3 B4 B5 B6 B8
B8
VCC
CLOCKBA
B7SELECTBA
B1 B2 B3 B4 B5 B6CONT-ROL
G
ENABLEGAB
1 2 3 4 5 6 7 8 9 10 11 12
20 19 18 17 16 1524 23 22 21 14 13
SELECTAB
A1 A2 A3 A4 A5 A6 A7CLOCKAB
A8 GND
SELECTAB A1 A2 A3 A4 A5 A6 A7 A8
CLOCKAB
CLOCKBA B7
SELECTBA
ENABLEGBA B1 B2 B3 B4 B5 B6 B8
B8
VCC
CLOCKBA
B7SELECTBA
B1 B2 B3 B4 B5 B6
ENABLEGAB
ENABLEGBA
A1 A2 A3 A4 A5 A6 A7 A8 GND
B1 B2 B3 B4 B5 B6 B7VCC B8
DIR
1 2 3 4 5 6 7 8 9 10
16 15 14 13 12 1120 19 18 17
ENABLEG
638OCTAL BUS TRANSCEIVERS
639OCTAL BUS TRANSCEIVERS
640642OCTAL BUS TRANSCEIVERS
See page 386
See page 387
See page 388, 390
ENABLEG
A1 A2 A3 A4 A5 A6 A7 A8 GND
B1 B2 B3 B4 B5 B6 B7VCC B8
DIR
1 2 3 4 5 6 7 8 9 10
16 15 14 13 12 1120 19 18 17
ENABLEG
A1 A2 A3 A4 A5 A6 A7 A8 GND
B1 B2 B3 B4 B5 B6 B7VCC B8
DIR
1 2 3 4 5 6 7 8 9 10
16 15 14 13 12 1120 19 18 17
A1 A2 A3 A4 A5 A6 A7 A8 GND
B1 B2 B3 B4 B5 B6 B7VCC B8
DIR
1 2 3 4 5 6 7 8 9 10
16 15 14 13 12 1120 19 18 17
ENABLEG
94
Pin Assignments
6704-BY-4 REGISTER FILE
67316-BIT SHIFT REGISTER
67416-BIT SHFT REGISTER
See page 418
See page 414
See page 416
GNDCLOCK
1 2 3 4 5 6 12READ/WRITE
NC MODECONTROL
DATAI/O
24P12
23 22P14
21P13VCC
20 19P11
CHIPSELECT
13
PARALLEL INPUTS
P15
PARALLEL INPUTS
7P0
18P10
8P1
17P9
9P2
16P8P15
10P3
15P7
11P4
14P6 P5
P5
CK DATAI/O
CS
P12P14 P13 P11 P10 P9 P8 P7 P6
MODE P0 P1 P2 P3 P4R/W
GNDSHIFTCLOCK
1 2 3 4 5 6 12READ/WRITE
STORECLR
STORECK
DATAI/O
24Y12
23 22Y14
21Y13VCC
20 19Y11
CHIPSELECT
13
STRAGE REGISTEROUTPUTS
Y15
STORECK
STORAGE REGISTER OUTPUT
7Y0
18Y10
8Y1
17Y9
9Y2
16Y8Y15
10Y3
15Y7
11Y4
14Y6 Y5
Y12Y14 Y13 Y11 Y10 Y9 Y8 Y7 Y6
Y5SHCK R/W
STORECLR
DATAI/O Y0 Y1 Y2 Y3 Y4
CS
GNDD3 Q3
1 2 3 4 5 6 7 8D4 RB RA Q4
16WRITE
15 14WA
13WBVCC
12 11READ
DATAD1
10 9
DATA
D1 GWWA WB GR Q1
D4 RB RA Q4
D2 Q2
Q1 Q2
D2
READ SELECT OUTPUTS
D3 Q3
ENABLEWRITE SELECT OUTPUT
657OCTAL BUS TRANSCEIVERSWITH 8-BIT PARITY GENERATORS/CHECKERS
6666678-BIT D-TYPE TRANSPARENT READ-BACK LATCHES
669SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTER
See page 412
See page 408, 410
See page 406
1 2 3 4 5 6 7 8 9 10 11 12
20 19 18 17 16 1524 23 22 21 14 13
VCC
B8B4 GND GND B5 B6 B7 PARITY
OE
B3B2B1
A1 A2 A3 A4 A5 A6 A7 A8 ERRORODD/EVEN
T/R
A1 A2 A3 A4 A5 A6 A7 A8ODD
/EVEN
T/R
OE
B8B4 B5 B6 B7
PARITY
B3B2B1
ERROR
OE1 CLR
1 2 3 4 5 6 7 8 9 10 11 121D 2D 3D 4D 5D 6D 7D 8D GND
203Q
194Q
185Q
176Q
167Q
158Q
24 23 221Q
212QVCC
14 13COE2 PRE
OERB
OE1 CLR1D 2D 3D 4D 5D 6D 7D 8D
3Q 4Q 5Q 6Q 7Q 8Q1Q 2QOE2 PRE
OERB C
GNDCK ENABLEP
1 2 3 4 5 6 7 8A B C D
16QC
15 14QA
13QBVCC
12 11QD
RIPPLECARRYOUTPUT LOAD
U/D
10 9
DATA INPUTS
RIPPLECARRYOUTPUT
ENABLET
QCQA QB QD ENABLET
CK ENABLEPA B C D
UP/DOWN LOAD
OUTPUTS
NC – No internal connection
95
Pin Assignments
679ADDRESS COMPARATOR
6826848-BIT IDENTITY COMPARATOR
6868-BIT IDENTITY COMPARATOR
NC – No internal connection
See page 426
See page 422, 424
See page 420
P=Q Q7 P7 Q6 P6 Q5 P5 Q4VCC P4
P0 Q0 P1 Q1 P2 Q2 P3 Q3 GNDP>Q
1 2 3 4 5 6
20 19 13
7
18
8
17
9
16
10
15 14 1112
Q0 P1 Q1 P2 Q2 P3 Q3P0
P=Q Q7 P7 Q6 P6 Q5 P5 Q4
P4P>Q
GNDA2
1 2 3 4 5 6A3 A4 A5 A6
P2Y P3VCC
20 19P1
A1
13
7A7
18P0
8A8
17A12
9A9
16A11
10
15A10
14G
A2 A3 A4 A5 A6A1 A7 A8 A9
P2Y P3 P1 P0 A12 A11 A10G
1112
GND
1 2 3 4 5 6 12
24 23 22 21VCC
20 19 13
7NC
18
8
17
9
16
10
15
11
14NCG2 P=Q Q7 P7 Q6 P6 Q5 P5 Q4 P4
P0 Q0 P1 Q1 P2 Q2 P3 Q3P>Q G1
P0 Q0 P1 Q1 P2 Q2 P3 Q3G1
G2 P=Q Q7 P7 Q6 P6 Q5 P5 Q4
P4P>Q
697699SYNCHRONOUS UP/DOWN COUNTERWITH OUTPUT REGISTER, MULTIPLEXEDTHREE-STATE OUTPUT
756OCTAL BUFFER/LINE DRIVER/LINE RECEIVERWITH OPEN-COLLECTOR OUTPUTS
See page 434
See page 430, 432
1 2 3 4 5 6 10
20 19 18 17VCC
16 15 11
7
14
8
13
9
12
1G
2G
1A1
1Y1
2Y4
2A4
1A2
1Y2
2Y3
2A3
1A3
1Y3
2Y2
2A2
1A4
1Y4
2Y1
2A1
GND
P=Q Q7 P7 Q6 P6 Q5 P5 Q4VCC P4
P0 Q0 P1 Q1 P2 Q2 P3 Q3 GND
1 2 3 4 5 6
20 19 13
7
18
8
17
9
16
10
15 14 1112
Q0 P1 Q1 P2 Q2 P3 Q3P0
P=Q Q7 P7 Q6 P6 Q5 P5 Q4
P4
G
G
GND
COUNTERCLOCK
1 2 3 4 5 6 10A B C D
20QC
19 18QA
17QBVCC
16 15QD
R/CSELECT
11
QCQA QB QD
A B C D
U/D R/C
7
14
8
COUNT-ER
CLEAR
13LOAD
9ESIST-
ERCLOCK
12
RIPPLECAPPY
OUTPUT
OUTPUTCONTROL
UP/DOWN
CCK CCLR RCK
RCO LOAD G
3-STATE OUTPUT
DATA INPUTS
ENABLET
ENAP
ENABLEP
ENABLET
6888-BIT IDENTITY COMPARATOR
See page 428
96
Pin Assignments
8258-BIT BUS INTERFACE FLIP-FLOPWITH 3-STATE OUTPUT
See page 442
GND
1 2 3 4 5 6 12
24 23 22 21VCC
20 19 13
7
18
8
17
9
16
10
15
11
14
OC1
CLKOC1
1Q
1D
2Q
2D
3Q
3D
5Q
5D
6Q
6D
7Q
7D
8Q
8D
CLK
1D 2D 3D 5D 6D 7D 8D
1Q 2Q 3Q 5Q 6Q 7Q 8Q
CLR
CLKEN
CLR
CLKEN
OC2
OC2
OC3
OC3 4Q
4D
4D
4Q
757OCTAL BUFFER/LINE DRIVER/LINE RECEIVERWITH OPEN-COLLECTOR OUTPUTS
760OCTAL BUFFER/LINE DRIVER/LINE RECEIVERWITH OPEN-COLLECTOR OUTPUTS
82110-BIT BUS INTERFACE FLIP FLOPSWITH 3-STATE OUTPUT
8239-BIT BUS INTERFACE FLIP-FLOPWITH 3-STATE OUTPUT
See page 440
See page 435
See page 436 See page 439
GND
1 2 3 4 5 6 12
24 23 22 21VCC
20 19 13
7
18
8
17
9
16
10
15
11
14
OC
CLKOC
1Q
1D
2Q
2D
3Q
3D
4Q
4D
5Q
5D
6Q
6D
7Q
7D
8Q
8D
9Q
9D
10Q
10D
CLK
1D 2D 3D 4D 5D 6D 7D 8D 9D 10D
1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q 10Q
GND
1 2 3 4 5 6 12
24 23 22 21VCC
20 19 13
7
18
8
17
9
16
10
15
11
14
OC
CLKOC
1Q
1D
2Q
2D
3Q
3D
4Q
4D
5Q
5D
6Q
6D
7Q
7D
8Q
8D
9Q
9D
CLK
1D 2D 3D 4D 5D 6D 7D 8D 9D
1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q
CLR
CLKEN
CLR
CLKEN
1 2 3 4 5 6 10
20 19 18 17VCC
16 15 11
7
14
8
13
9
12
1G
2G
1A1
1Y1
2Y4
2A4
1A2
1Y2
2Y3
2A3
1A3
1Y3
2Y2
2A2
1A4
1Y4
2Y1
2A1
GND
1 2 3 4 5 6 10
20 19 18 17VCC
16 15 11
7
14
8
13
9
12
1G
2G
1A1
1Y1
2Y4
2A4
1A2
1Y2
2Y3
2A3
1A3
1Y3
2Y2
2A2
1A4
1Y4
2Y1
2A1
GND
804HEX 2-INPUT NAND DRIVERSpositive logic:A = A • B
805HEX 2-INPUT NOR DRIVERSpositive logic:Y = A + B
See page 437
See page 438
808HEX 2-INPUT AND DRIVERSpositive logic:Y = A + B
See page 438
1 2 3 4 5 6 10
20 19 18 17VCC
16 15 11
7
14
8
13
9
12
1A
6B
1B
6A
1Y
6Y
2A
5B
2B
5A
2Y
5Y
3A
4B
3B
4A
3Y
4Y
GND
1 2 3 4 5 6 10
20 19 18 17VCC
16 15 11
7
14
8
13
9
12
1A
6B
1B
6A
1Y
6Y
2A
5B
2B
5A
2Y
5Y
3A
4B
3B
4A
3Y
4Y
GND
1 2 3 4 5 6 10
20 19 18 17VCC
16 15 11
7
14
8
13
9
12
1A
6B
1B
6A
1Y
6Y
2A
5B
2B
5A
2Y
5Y
3A
4B
3B
4A
3Y
4Y
GND
97
Pin Assignments
82710-BIT BUFFER/BUS DRIVERS
832HEX 2-INPUT OR DRIVERSpositive logic:Y=A+B
83310-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
84110-BIT BUS INTERFACE D-TYPE LATCHESWITH 3-STATE OUTPUTS
8439-BIT BUS INTERFACE D-TYPE LATCHESWITH 3-STATE OUTPUTS
8538-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
857HEX 2-TO-1 UNIVERSAL MULTIPLEXERS
See page 454See page 446
See page 445 See page 452
See page 450
See page 444 See page 448
Y3
A3 A4 A5 A6 A7 A8 A9 A10 GND
Y4 Y5 Y6 Y7 Y8 Y9 Y10Y2 OE2
4 5 6 7 8 9 10 11 12
18 17 16 15 14 1321 20Y1
A1
VCC
OE1
1 2
24 23 19
A2
3
22
GND
1 2 3 4 5 6 12
24 23 22 21VCC
20 19 13
7
18
8
17
9
16
10
15
11
14
A2 A3 A4 A5 A6 A7
B1 B2 B3 B4 B5 B6 B7 B8 PARITY OEB CLK
OEA A1 A8 ERR CLR
GND
1 2 3 4 5 6 12
24 23 22 21VCC
20 19 13
7
18
8
17
9
16
10
15
11
14
OC
COC
1Q
1D
2Q
2D
3Q
3D
4Q
4D
5Q
5D
6Q
6D
7Q
7D
8Q
8D
9Q
9D
10Q
10D
C
1D 2D 3D 4D 5D 6D 7D 8D 9D 10D
1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q 10Q
GND
1 2 3 4 5 6 12
24 23 22 21VCC
20 19 13
7
18
8
17
9
16
10
15
11
14
S0
S0
S1
1A
6B
1B
6Y
1Y
5A
2A
5B
2B
5Y
2Y
4A
3A
4B
3B
4Y
3Y OPERZERO
6A
OPER=0
T/C
T/C
S1 6B 6Y 5A 5B 5Y 4A 4B 4Y6A
1A 1B 1Y 2A 2B 2Y 3A 3B 3Y
GND
1 2 3 4 5 6 12
24 23 22 21VCC
20 19 13
7
18
8
17
9
16
10
15
11
14
A2 A3 A4 A5 A6 A7
B1 B2 B3 B4 B5 B6 B7 B8 PARITY OEB LE
OEA A1 A8 ERR CLR
GND
1 2 3 4 5 6 12
24 23 22 21VCC
20 19 13
7
18
8
17
9
16
10
15
11
14
OC
COC
1Q
1D
2Q
2D
3Q
3D
4Q
4D
5Q
5D
6Q
6D
7Q
7D
8Q
8D
9Q
9D
C
1D 2D 3D 4D 5D 6D 7D 8D 9D
1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q
CLR
PRE
CLR
PRE
Y3
A3 A4 A5 A6 A7 A8 A9 A10 GND
Y4 Y5 Y6 Y7 Y8 Y9 Y10Y2 OE2
4 5 6 7 8 9 10 11 12
18 17 16 15 14 1321 20Y1
A1
VCC
OE1
1 2
24 23 19
A2
3
22
82810-BIT BUFFERS/BUS DRIVERS
See page 444
1 2 3 4 5 6 10
20 19 18 17VCC
16 15 11
7
14
8
13
9
12
1A
6B
1B
6A
1Y
6Y
2A
5B
2B
5A
2Y
5Y
3A
4B
3B
4A
3Y
4Y
GND
98
Pin Assignments
86110-BIT TRANSCEIVERSWITH 3-STATE OUTPUTS
8639-BIT BUS TRANSCEIVERWITH 3-STATE OUTPUTS
8678698-BIT SYNCHRONOUS BIDIRECTIONAL COUNTER
870DUAL 16-BY 4-BIT REGISTER FILES
NC – No internal connection
873DUAL 4-BIT D-TYPE LATCHES
874DUAL 4-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOPS
8858-BIT MAGNITUDE COMPARATOR
NC – No internal connection
See page 464See page 456
See page 457 See page 465
See page 458, 460
See page 468See page 462
GND
1 2 3 4 5 6 12
24 23 22 21VCC
20 19 13
7
18
8
17
9
16
10
15
11
14
A2 A3 A4 A5 A6 A7
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 OEAB
OEBA A1 A8 A9 A10
GND
1 2 3 4 5 6 12
24 23 22 21VCC
20 19 13
7
18
8
17
9
16
10
15
11
14
A2 A3 A4 A5 A6 A7
B1 B2 B3 B4 B5 B6 B7 B8 B9 OEAB2 OEAB1
OEBA1 A1 A8 A9 OEBA2
GND
1 2 3 4 5 6 12
24 23 22 21VCC
20 19 13
7
18
8
17
9
16
10
15
11
14
CLR
1Q1 1Q2 1Q3 1Q4 2Q1 2Q2 2Q3 2Q4
1OC
ENABEL1C
1D1
ENABEL2C 2CLR
1CLR 2OC1D2 1D3 1D4 2D1 2D2 2D3 2D4
CLR
D1 D2 D3 D4 D1 D2 D3 D4
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OC OC
C C
GND
1 2 3 4 5 6 12
24 23 22 21VCC
20 19 13
7
18
8
17
9
16
10
15
11
14
CLR
1Q1 1Q2 1Q3 1Q4 2Q1 2Q2 2Q3 2Q4
1OC
1CLK
1D1
2CLK 2CLR
1CLR 2OC1D2 1D3 1D4 2D1 2D2 2D3 2D4
CLR
D1 D2 D3 D4 D1 D2 D3 D4
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OC OC
CLK CLK
GND
1 2 3 4 5 6 12
24 23 22 21VCC
20 19 13
7
18
8
17
9
16
10
15
11
14
P<QIN
P7
P>QIN
P6
Q7
P5
Q6
P4
Q5
P3
Q4
P2
Q3
P1
Q2
P0
Q1
PLE P>QOUT
P>QOUT
L/A
P<QOUT
Q0
L/A
P7 P6 P5 P4 P3 P2 P1 P0PLE P<QOUT
P<QIN P>QIN Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
GND
1 2 3 4 5 6 12
24 23 22 21VCC
20 19 13
7
18
8
17
9
16
10
15
11
14
S0
S0
S1
QA
A
QB
B
QC
C
QD
D
QE
E
QF
F
QG
G
QH
H
CLKENABEL
P RCO
ENABELT
RCO
S1 A B C D E F G HENT
QA QB QC QD QE QF QG QH CLKENP
GND
1 2 3 4 5 6 12
24 23 22 21VCC
20 19 13
7
18
8
17
9
16
10
15
11
14
S0
S0
S1
SERIN
S2
B1
A1
B2
A2
B3
A3
B4
A4
B5
A5
B6
A6
B7
A7
CLK Q8
S1
CLK
Q8
S2
SERIN
B8
A8
DQA1
DQB1
DQA2
DQB2
DQA3
DQB3
DQA4
DQB4
DQA5
DQB5
DQA6
DQB6
DQA7
DQB7
DQA8
DQB8
876DUAL 4-BIT D-TYPE FLIP-FLOPS
See page 466
GND
1 2 3 4 5 6 12
24 23 22 21VCC
20 19 13
7
18
8
17
9
16
10
15
11
14
PRE
1OC
1CLK
1D1
2CLK 2PRE
1PRE 2OC1D2 1D3 1D4 2D1 2D2 2D3 2D4
PRE
D1 D2 D3 D4 D1 D2 D3 D4
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OC OC
CLK CLK
1Q1 1Q2 1Q3 1Q4 2Q1 2Q2 2Q3 2Q4
99
Pin Assignments
9908-BIT D-TYPE TRANSPARENT READ-BACK LATCHES
9968-BIT D-TYPE EDGE-TRIGGERED READ-BACK LATCHES
See page 474
See page 470
1000QUAD 2-INPUT NAND BUFFERS/DRIVERS
1004HEX INVERTING DRIVERS
1005HEX INVERTING BUFFER GATESWITH OPEN-COLLECTOR OUTPUTS
1008QUADRUPLE 2-INPUT POSITIVE-AND BUFFERS/DRIVERS
See page 477
See page 476
See page 476
See page 477
1Q
20 19 18 17 16 15 14 13 12 11
1 2 3 4 5 6 7 8 9 10
1D 2D 3D 4D 5D 6D 7D 8D
2Q 3Q 4Q 5Q 6Q 7Q 8Q
C
1D 2D 3D 4D 5D 6D 7D 8D GND
2Q 3Q 4Q 5Q 6Q 7Q 8QVCC C
1Q
OERB
OERB
6A
14 13 12 11 10 9 8
1 2 3 4 5 6 71Y 2A 2Y 3A 3Y GND
6Y 5A 5Y 4A 4YVCC
1A
6A
14 13 12 11 10 9 8
1 2 3 4 5 6 71Y 2A 2Y 3A 3Y GND
6Y 5A 5Y 4A 4YVCC
1A
4B
14 13 12 11 10 9 8
1 2 3 4 5 6 71B 1Y 2A 2B 2Y GND
4A 4Y 3B 3A 3YVCC
1A1 2 3
20 18
1D 2D
VCC
19
1Q
4
17
3D
2Q
5
16
4D
3Q
6
15
5D 6D 7D 8D
4Q
7
14
5Q
8
13
6Q
9
24
7Q
10
23
RD
8Q OE
11
22
CLK
T/C
12
21
GND
CLR
EN
4B
14 13 12 11 10 9 8
1 2 3 4 5 6 71B 1Y 2A 2B 2Y GND
4A 4Y 3B 3A 3YVCC
1A
9929-BIT D-TYPE TRANSPARENT
See page 471
99410-BIT D-TYPE TRANSPARENT READ-BACK LATCHES
See page 472
1D
1Q
24 23 22 21 20 19 18 17 16 15
1 2 3 4 5 6 7 8 9 10
2D 3D 4D 5D 6D 7D 8D
2Q 3Q 4Q 5Q 6Q 7Q 8Q
2D 3D 4D 5D 6D 7D 8D 9D
2Q 3Q 4Q 5Q 6Q 7Q 8QVCC 9Q
OERB C
OERB
14
11
13
12GND
C
9D
9Q
1D
OEQ
OEQ
CLR
CLR
1Q
1D
1Q
24 23 22 21 20 19 18 17 16 15
1 2 3 4 5 6 7 8 9 10
2D 3D 4D 5D 6D 7D 8D
2Q 3Q 4Q 5Q 6Q 7Q 8Q
2D 3D 4D 5D 6D 7D 8D 9D
2Q 3Q 4Q 5Q 6Q 7Q 8QVCC 9Q
OERB C
OERB
14
11
13
12GND
C
9D
9Q
1D
10Q
10Q
10D
10D
1Q
100
Pin Assignments
1244OCTAL BUFFERS/LINE DRIVERS/LINE RECEIVERS
1245OCTAL BUS TRANSCEIVERS
1640OCTAL BUS TRANSCEIVERS
1645OCTAL BUS TRANSCEIVERS
See page 480
See page 480
See page 481
See page 481
A1
20 19 18 17 16 15 14 13 12 11
1 2 3 4 5 6 7 8 9 10A2 A3 A4 A5 A6 A7 A8 GND
B1 B2 B3 B4 B5 B6 B7VCC B8G
DIR
ENABLE
1A1
20 19 18 17 16 15 14 13 12 11
1 2 3 4 5 6 7 8 9 102Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND
1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4VCC 2A12G
1G
A1
20 19 18 17 16 15 14 13 12 11
1 2 3 4 5 6 7 8 9 10A2 A3 A4 A5 A6 A7 A8 GND
B1 B2 B3 B4 B5 B6 B7VCC B8G
DIR
ENABLE
A1
20 19 18 17 16 15 14 13 12 11
1 2 3 4 5 6 7 8 9 10A2 A3 A4 A5 A6 A7 A8 GND
B1 B2 B3 B4 B5 B6 B7VCC B8G
DIR
ENABLE
1034HEX DRIVERS
1035HEX BUFFERSWITH OPEN-COLLECTOR OUTPUTS
1240OCTAL BUFFERS/LINE DRIVERS/LINE RECEIVERS
See page 478
See page 479
See page 479
6A
14 13 12 11 10 9 8
1 2 3 4 5 6 71Y 2A 2Y 3A 3Y GND
6Y 5A 5Y 4A 4YVCC
1A
1A1
20 19 18 17 16 15 14 13 12 11
1 2 3 4 5 6 7 8 9 102Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND
1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4VCC 2A12G
1G
6A
14 13 12 11 10 9 8
1 2 3 4 5 6 71Y 2A 2Y 3A 3Y GND
6Y 5A 5Y 4A 4YVCC
1A
1032QUAD 2-INPUT OR BUFFERS/DRIVERSpositive logic:Y = A+B
See page 478
4B
14 13 12 11 10 9 8
1 2 3 4 5 6 71B 1Y 2A 2B 2Y GND
4A 4Y 3B 3A 3YVCC
1A
101
Pin Assignments
2240OCTAL BUFFERS AND LINE DRIVERS/MOS DRIVERSWITH 3-STATE OUTPUTS
2241OCTAL BUFFERS AND LINE DRIVERS/MOS DRIVERSWITH 3-STATE OUTPUTS
2244OCTAL BUFFERS AND LINE DRIVERS/MOS DRIVERSWITH 3-STATE OUTPUTS
2245OCTAL TRANSCEIVER AND LINE/MOS DRIVERSWITH 3-STATE OUTPUTS
See page 482
See page 483
See page 484
See page 485
1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND
1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4VCC 2A1
1G
2G
20 19 18 17 16 15 14 13 12 11
1 2 3 4 5 6 7 8 9 10
A1
20 19 18 17 16 15 14 13 12 11
1 2 3 4 5 6 7 8 9 10A2 A3 A4 A5 A6 A7 A8 GND
B1 B2 B3 B4 B5 B6 B7VCC B8G
DIR
ENABLE
1A1
20 19 18 17 16 15 14 13 12 11
1 2 3 4 5 6 7 8 9 102Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND
1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4VCC 2A12G
1G
1A1
20 19 18 17 16 15 14 13 12 11
1 2 3 4 5 6 7 8 9 102Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND
1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4VCC 2A12G
1G
237325-Ω OCTAL TRANSPARENT D-TYPE LATCHWITH 3-STATE OUTPUTS
See page 486
2414MEMORY DECODER WITH ON-CHIP VCC MONITOR
2541NON-INVERTED 3-STATE OUTPUTSOCTAL LINE DRIVERS/MOS DRIVERSWITH 3-STATE OUTPUTS
2827 3-STATE OUTPUTS
2828 3-STATE INVERTING OUTPUTSBUS/MOS MEMORY DRIVERS
See page 490, 491
See page 490
See page 488
A1
Y1
24 23 22 21 20 19 18 17 16 15
1 2 3 4 5 6 7 8 9 10
A2 A3 A4 A5 A6 A7 A8
Y2 Y3 Y4 Y5 Y7 Y8 Y9
A2 A3 A4 A5 A6 A7 A8 A9
Y2 Y3 Y4 Y5 Y6 Y7 Y8VCC Y9
OE1
14
11
13
12GND
A9
Y10
A1
Y10
A10
A10
Y1
OE2
Y6
OE1 OE2
OUTPUTS
Vbat
20 19 18 17 16 15 14 13 12 11
1 2 3 4 5 6 7 8 9 10
1A 2A 1B 2B 2G
1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 2Y2
2Y3
1A 2A 1B 2B 2G GND
1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 2Y2VCC 2Y3
Vbat
VS
VS
SD 1G G
SD 1G G
G2
A1 A2 A3 A4 A5 A6 A7 A8 GND
Y1 Y2 Y3 Y4 Y5 Y6 Y7VCC Y8
G1
1 2 3 4 5 6 7 8 9 10
16 15 14 13 12 1120 19 18 17
2D
18 17 16 15 14 13
5 6 7 8 9 10OE
8Q 7Q 6Q 5Q
GND4Q3Q
1 2 3 41Q 2Q
12 1120 19LE8D 7D 6D 5DVCC
4D3D1D
102
Pin Assignments
2952OCTAL BUS TRANSCEIVERS AND REGISTERS
2953OCTAL BUS TRANSCEIVERS AND REGISTERS
3245OCTAL BUS TRANSCEIVER WITH ADJUSTABLE OUTPUTVOLTAGE AND 3-STATE OUTPUTS
402014-STAGE BINARY COUNTERS
See page 492
See page 502
See page 496
See page 494
B7
A8
24 23 22 21 20 19 18 17 16 15
1 2 3 4 5 6 7 8 9 10
B6 B5 B4 B3 B2 B1
A7 A6 A5 A4 A2 A1
B6 B5 B4 B3 B2 B1 CLKAB
A7 A6 A5 A4 A3 A2 A1VCC
B8
14
11
13
12GND
CLKAB
CLKBA
B7
CLKBA
A8
BA
A3
B8
CEBA
OUTPUTS
OEBA
OEBA
OEBA
CEBA
OEAB CEBA
B7
A8
24 23 22 21 20 19 18 17 16 15
1 2 3 4 5 6 7 8 9 10
B6 B5 B4 B3 B2 B1
A7 A6 A5 A4 A2 A1
B6 B5 B4 B3 B2 B1 CLKAB
A7 A6 A5 A4 A3 A2 A1VCC
B8
14
11
13
12GND
CLKAB
CLKBA
B7
CLKBA
A8
CEBA
A3
B8
CEAB
OUTPUTS
OEBA
OEBA
OEAB
CEBA
OEAB CEAB
1 2 3
24 22
VCCA DIR A1
VCCB NC
23
OE
4
21
A2
B1
5
20
A3
B2
6
19
A4 A5 A6 A7 A8
B3
7
18
B4
8
17
B5
9
16
B6
10
15
GND
B7
11
14
B8
12
13
GND
GND
VCC
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
QM QN QF QE QG QD
QK QJ QH QI CLR CLK
QA
QL QM QN QF QE QG QD GND
QK QJ QH QI CLR CLK QA
QL
OUTPUTS
OUTPUTS
OUTPUT
4002DUAL 4-INPUT POSITIVE-NOR GATESpositive logic:Y = A + B + C + D
See page 497
2Y
14 13 12 11 10 9 8
1 2 3 4 5 6 71A 1B 1C 1D NC GND
2D 2C 2B 2A NCVCC
1Y
4017DECADE COUNTERS/DIVIDERS
See page 500
4016QUAD BILATERAL SWITCH
See page 499
4015DUAL 4-STAGE STATIC SHIFT REGISTER
See page 498
1Q1
16 15 14 13
5 6 7 8
910
2CP
2D 2Q1 2Q2
1MR GND
1 2 3 42Q3 1Q0
12 11
2MR 2Q0 1Q3 1CPVCC
1D1Q2
14 13
5 6 7
8910
1Y
1E 4Z
2E GND
1 2 3 41Z 2Y
12 11
4E 4Y 3Z 3YVCC
3E2Z
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
VCC CLR CLK CLKEN CO Y9 Y4
GNDY3Y7Y6Y2Y0Y1
OUTPUTS
Y8
Y5
OUTPUTS
CLR CLK CO Y9 Y4
Y6Y2Y0Y1 Y3
Y8Y5
Y7
NC – No internal connection
103
Pin Assignments
404012-STAGE BINARY COUNTERS
VCC
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
QF QE QG QD QC QB
QK QJ QH QI CLR CLK
QA
QL QF QE QG QD QC QB GND
QK QJ QH QI CLR CLK QA
QL
OUTPUTS
OUTPUTS
OUTPUT
See page 504
40518-CHANNEL ANALOGMULTIPLEXERS/DEMULTIPLEXERS
4052DUAL 4-CHANNEL ANALOGMULTIPLEXERS/DEMULTIPLEXERS
4053TRIPLE 2-CHANNEL ANALOGMULTIPLEXERS/DEMULTIPLEXERS
See page 509
See page 508
See page 507
1 2 3
16 14
2Y0 2Y2 2-COM
VCC
15
1Y2 1Y1
4
13
2Y3
1-COM
5
12
2Y1
1Y0
6
11
INH
1Y3
7
10
GND
A
8
9
GND
B
1 2 3
16 14
Y4 Y6 COM
VCC
15
Y2 Y1
4
13
Y7
Y0
5
12
Y5
Y3
6
11
INH
A
7
10
GND
B
8
9
GND
C
1 2 3
16 14
2Y1 2Y0 3Y1
VCC
15
2-COM 1-COM
4
13
3-COM
1Y1
5
12
3Y0
1Y0
6
11
INH
A
7
10
GND
B
8
9
GND
C
40247-STAGE BINARY COUNTERS
See page 503NC – No internal connection
VCC
14 13 12 11 10 9 8
1 2 3 4 5 6 7
CLR QG QF QE QD
QA QB QC
CLK CLR QG QF QE QD GND
NC QA QB NC QC NC
CLK
OUTPUTS
OUTPUTS
OUTPUT
4046PHASE-LOCKED-LOOP WITH VCO
See page 505
4049HEX INVERTING BUFFERS
See page 506
4050HEX INVERTING BUFFERS NON-INVERTING
See page 506
VCC
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8PCPOUT PC1OUT COMPIN VCOOUT INH C1A C1B GND
PC3OUT SIGIN PC2OUT R2 R1 DEMOUT VCOIN
VCC 1Y 1A 2Y 2A 3Y 3A
NC 6Y 6A NC 5Y 5A 4Y
1 2 3 4 5 6 7
16 15 14 13 12 11 10
8
9
GND
4A
VCC 1Y 1A 2Y 2A 3Y 3A
NC 6Y 6A NC 5Y 5A 4Y
1 2 3 4 5 6 7
16 15 14 13 12 11 10
8
9
GND
4A
NC – No internal connection
NC – No internal connection
104
Pin Assignments
4060ASYNCHRONOUS 14-STAGE BINARY COUNTERSAND OSCILLATORS
4066QUADRUPLE BILATERAL SWITCHES
4245OCTAL BUS TRANSCEIVER AND 3.3-V TO 5-V SHIFTERWITH 3-STATE OUTPUTS
See page 511
See page 518See page 512
1C
14 13 12 11 10 9 8
1 2 3 4 5 6 71B 2B 2A 2C 3C GND
4C 4A 4B 3B 3AVCC
1A
VCC
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
QM QN QF QE QG QD
QJ QH QI CLR CKI
CKO
QL QM QN QF QE QG QD GND
QJ QH QI CLR CKI CKO
QL
OUTPUTS
CKO
CKO
OUTPUTS
1 2 3
24 22
(5V)VCCA
DIR A1
(3.3V)VCCB
(3.3V)VCCB
23
OE
4
21
A2
B1
5
20
A3
B2
6
19
A4 A5 A6 A7 A8
B3
7
18
B4
8
17
B5
9
16
B6
10
15
GND
B7
11
14
B8
12
13
GND
GND
4059CMOS PROGRAMMABLE DIVIDE-BY-N COUNTER
See page 510
406716-CHANNEL ANALOG MULTIPLEXER/DEMULTIPLEXER
See page 513
4075TRIPLE 3-INPUT OR GATESpositive logic:Y = A + B + C
See page 514
I5
18 17 16 15 14 13
5 6 7 8 9 10COMMOMN
INPUT/OUTPUT
I8 I11 I12 I15
S2 S1 GNDI0I3
1 2 3 4I7 I4
1211
24 23 22 21 20 19E S2 S3I9 I10 I13 I14VCC
I1I2I6
40948-STAGE SHIFT AND STORE BUS REGISTER,THREE-STATE
See page 516
3C
14 13 12 11 10 9 8
1 2 3 4 5 6 72B 1A 1B 1C 1Y GND
3B 3A 3Y 2Y 2CVCC
2A
Q0
16 15 14 13
5 6 7 8
910
STROBE
OE Q6 Q7
GNDQ2
1 2 3 4DATA Q1
12 11
Q4 Q5 QS2 QS1VCC
Q3CP
4316QUAD ANALOG SWITCH WITH LEVEL TRANSLATION
See page 519
CP LE J1 J2 J3 J4 J16
VCC Q J5 J6 J7 J8 J9
1 2 3 4 5 6 7
24 23 22 21 20 19 18
8
17
J15
J10
J14 J13 Kc
J11 J12 Ka
9 10 11
16 15 14
12
13
GND
Kb
VCC VEE
1Y1Z 2Y 2Z 2S 3S E
1S 4S 4Z 4Y 3Y 3Z
1 2 3 4 5 6 7
16 15 14 13 12 11 10
8
9
GND
105
Pin Assignments
4374OCTAL EDGE-TRIGGERED D-TYPE DUAL-RANK FLIP-FLOPWITH 3-STAE OUTPUTS
See page 522
2D
18 17 16 15 14 13
5 6 7 8 9 10OE8Q7Q6Q5QGND4Q3Q
1 2 3 41Q 2Q
12 1120 19CLK8D7D6D5DVCC4D3D1D
4351ANALOG MULTIPLEXERS/DEMULTIPLEXERSWITH LATCH
See page 520
45144-LINE TO 16-LINE DECODERS/DEMULTIPLEXERSWITH LATCHES
See page 524
4352ANALOG MULTIPLEXERS/DEMULTIPLEXERSWITH LATCH
See page 521
45154-LINE TO 16-LINE DECODERS/DEMULTIPLEXERSWITH LATCHES
See page 526
4518DUAL SYNCHRONOUS COUNTERS
See page 528
4511BCD-TO-7 SEGMENT LATCH/DECODER/DRIVERS
See page 523
D0
16b
15c
10 9
6D3D1
1Bt
42D2
5LE
12
f g a
14d
13eVCC
8GND
3LT
7
11
7-SEGMENT OUTPUTS
BCD INPUTS BCD INPUTS
ACOMMON
18 17 16 15 14 13
5 6 7 8 9 10A4
A2 A3 S0 S2
GNDVEEA5
1 2 3 4A6 A7
12 1120 19LEA1 A0 NC S1VCC
E2E1NC
BCOMMON
18 17 16 15 14 13
5 6 7 8 9 10B0
A2 A3 NCA
COMMON
GNDVEEB1
1 2 3 4B2 B3
12 1120 19LEA1 A0 S0 S1VCC
E2E1NC
GNDA
1 2 3 4 5 6 12B Y7 Y6 Y5
24Y10
23 22D
21CVCC
20 19Y11
LE
13
DATA INPUTS
DATA INPUTS
7Y4
18Y8
8Y3
17Y9
9Y2
16Y14G
10Y1
15Y15
11Y0
14Y12 Y13
INPUTS
INPUTS
A B Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
Y10D C Y11 Y8 Y9 Y14G Y15 Y12
Y13LE
GNDA
1 2 3 4 5 6 12B Y7 Y6 Y5
24Y10
23 22D
21CVCC
20 19Y11
LE
13
DATA INPUTS
DATA INPUTS
7Y4
18Y8
8Y3
17Y9
9Y2
16Y14G
10Y1
15Y15
11Y0
14Y12 Y13
INPUTS
INPUTS
A B Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
Y10D C Y11 Y8 Y9 Y14G Y15 Y12
Y13LE
VCC
1E1CP 1Q0 1Q1 1Q2 1Q3
2Q3 2Q2 2Q1 2Q0
1MR
2MR 2E
1 2 3 4 5 6 7
16 15 14 13 12 11 10
8
9
GND
2CP
NC – No internal connection
NC – No internal connection
106
Pin Assignments
4520DUAL SYNCHRONOUS COUNTERS
See page 529
540011-BIT LINE/MEMORY DRIVERSWITH 3-STATE OUTPUTS
See page 534
D1 OE2D9
Y9
D2
Y3 Y4 Y5 Y6 GND GND Y7 Y8
D3 D4 D5 D6 VCC VCC D7 D8
Y1 OE1Y10 Y11
D10 D11
Y2
1 2 3 4 5 6 7 8 9 10 11 12 13 14
20 19 18 17 16 1528 27 26 25 24 23 22 21
4538DUAL RETRIGGERABLEPRECISION MONO STABLE MULTIVIBRATOR
See page 530
4543BCD-TO-7 SEGMENT LATCH/DECODER/DRIVERS
See page 532
540111-BIT LINE/MEMORY DRIVERSWITH 3-STATE OUTPUTS
540212-BIT LINE/MEMORY DRIVERSWITH 3-STATE OUTPUTS
540311-BIT LINE/MEMORY DRIVERSWITH 3-STATE OUTPUTS
See page 534
See page 535
See page 535
D1 OE2D10
Y10
D2
Y3 Y4 Y5 Y6 GND Y7 Y8 Y9
D3 D4 D5 D6 D7 VCC D8 D9
Y1 OE1Y11 Y12
D11 D12
Y2
1 2 3 4 5 6 7 8 9 10 11 12 13 14
20 19 18 17 16 1528 27 26 25 24 23 22 21
D1 OE2D10
Y10
D2
Y3 Y4 Y5 Y6 GND Y7 Y8 Y9
D3 D4 D5 D6 D7 VCC D8 D9
Y1 OE1Y11 Y12
D11 D12
Y2
1 2 3 4 5 6 7 8 9 10 11 12 13 14
20 19 18 17 16 1528 27 26 25 24 23 22 21
D1 OE2D9
Y9
D2
Y3 Y4 Y5 Y6 GND GND Y7 Y8
D3 D4 D5 D6 VCC VCC D7 D8
Y1 OE1Y10 Y11
D10 D11
Y2
1 2 3 4 5 6 7 8 9 10 11 12 13 14
20 19 18 17 16 1528 27 26 25 24 23 22 21
B1
16d
15c
10 9
6PHDL
1D3
42D2
5D0
12
f g e
14b
13aVCC
8GND
3D1
7
11
7-SEGMENT OUTPUTS
BCD INPUTS
VCC
1E1CP 1Q0 1Q1 1Q2 1Q3
2Q3 2Q2 2Q1 2Q0
1MR
2MR 2E
1 2 3 4 5 6 7
16 15 14 13 12 11 10
8
9
GND
2CP
VCC
1CX
2CX
1RXCX
2RXCX
1R 1A 1B 1Q 1Q
1 2 3 4 5 6 7
16 15 14 13 12 11 10
8
9
GND
1R 1A 1B 1Q 1Q
107
Pin Assignments
8003DUAL 2-INPUT POSITIVE-NAND GATES
See page 539
2B
1B 1Y GND
2A 2YVCC
1A
8 7 6 5
1 2 3 4
7046PHASE-LOCKED LOOP WITH VCO AND LOCK DETECTOR
See page 538
7266QUAD 2-INPUT EXCLUSIVE-NOR GATESpositive logic:Y = A ⊕ B
See page 539
16R2
15R1
10
GND
9
6C1ALD
1VCOOUT
42PC1OUT
5INH
12
GLD SIGIN PC2OUT
14DEMOUT
13VCOINVCC
83COMPIN
7
11
C1B
4B
14 13 12 11 10 9 8
1 2 3 4 5 6 71B 1Y 2Y 2A 2B GND
4A 4Y 3Y 3B 3AVCC
1A
7002QUADRUPLE POSITIVE-NOR GATESWITH SCHMITT-TRIGGER INPUTSpositive logic:Y = A + B
7032QUADRUPLE POSITIVE-OR GATESWITH SCHMITT-TRIGGER INPUTSpositive logic:Y = A + B
See page 536
See page 537
4B
14 13 12 11 10 9 8
1 2 3 4 5 6 71B 1Y 2A 2B 2Y GND
4A 4Y 3B 3A 3YVCC
1A
4B
14 13 12 11 10 9 8
1 2 3 4 5 6 71B 1Y 2A 2B 2Y GND
4A 4Y 3B 3A 3YVCC
1A
7001QUADRUPLE POSITIVE-AND GATESWITH SCHMITT-TRIGGER INPUTSpositive logic:Y = A • B
See page 536
4B
14 13 12 11 10 9 8
1 2 3 4 5 6 71B 1Y 2A 2B 2Y GND
4A 4Y 3B 3A 3YVCC
1A
108
Pin Assignments
1624116-BIT BUS BUFFERS/DRIVERSWITH 3-STATE OUTPUTS
1624416-BIT BUS BUFFERS/DRIVERSWITH 3-STATE OUTPUTS
1624516-BIT BUS TRANSCEIVERWITH 3-STATE OUTPUTS
See page 541
See page 544
See page 546
2A1 3A23A12A31A4 2A4VCC 2A2 GND VCC 3OE4A4GND3A3 4A3GND 3A4 4A1 4A21A3GND1A1 1A22OE
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
3Y11Y4 VCC 2Y2 GND 2Y3 3Y22Y41Y3 2Y1 4Y43Y3 3Y4 VCC 4Y1 4Y2 GND 4OE4Y3GND
1 2 3 4
48 47 46 45 44 43 42 41
1Y1 1Y21OE GND
2A1 3A23A12A31A4 2A4VCC 2A2 GND VCC 3OE4A4GND3A3 4A3GND 3A4 4A1 4A21A3GND1A1 1A22OE
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
3Y11Y4 VCC 2Y2 GND 2Y3 3Y22Y41Y3 2Y1 4Y43Y3 3Y4 VCC 4Y1 4Y2 GND 4OE4Y3GND
1 2 3 4
48 47 46 45 44 43 42 41
1Y1 1Y21OE GND
1A5 2A22A11A71A4 1A8VCC 1A6 GND VCC 2OE2A8GND2A3 2A7GND 2A4 2A5 2A61A3GND1A1 1A21OE
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
2B11B4 VCC 1B6 GND 1B7 2B21B81B3 1B5 2B82B3 2B4 VCC 2B5 2B6 GND 2DIR2B7GND
1 2 3 4
48 47 46 45 44 43 42 41
1B1 1B21DIR GND
1624016-BIT BUS BUFFERS/DRIVERSWITH 3-STATE OUTPUTS
See page 540
2A1 3A23A12A31A4 2A4VCC 2A2 GND VCC 3OE4A4GND3A3 4A3GND 3A4 4A1 4A21A3GND1A1 1A22OE
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
3Y11Y4 VCC 2Y2 GND 2Y3 3Y22Y41Y3 2Y1 4Y43Y3 3Y4 VCC 4Y1 4Y2 GND 4OE4Y3GND
1 2 3 4
48 47 46 45 44 43 42 41
1Y1 1Y21OE GND
109
Pin Assignments
1626912-BIT TO 24-BIT REGISTERED BUS TRANSCEIVERWITH 3-STATE OUTPUTS
1627012-BIT TO 24-BIT REGISTERED BUS EXCHANGERWITH 3-STATE OUTPUTS
See page 550
See page 552
2B7 2B122B11GND2B6 2B10VCC 2B8 2B9 GND 1B51B61B71B11 VCC1B12 1B10 1B9 1B82B5GNDCLKENA2 2B4OEB2
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33CLKCLKENA1GND 1B4
32 31 30 29
A12A6 A7 A9 GND A10 VCCA11A5 A8 1B2 GND 1B3 NC SEL1B1
9 10 11 12
56 55 54 53 52 51 50 49
A3 GNDA2 A4
5 6 7 82B1 VCC2B2 A1
1 2 3 4OEB1 2B3OEA GND
2B7 2B122B11GND2B6 2B10VCC 2B8 2B9 GND 1B51B61B71B11 VCC1B12 1B10 1B9 1B82B5GNDCLKENA2 2B4OEB
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33CLKCLKENA1GND 1B4
32 31 30 29
A12A6 A7 A9 GND A10 VCCA11A5 A8 1B2 GND 1B3 CLKEN2B SEL1B1
9 10 11 12
56 55 54 53 52 51 50 49
A3 GNDA2 A4
5 6 7 82B1 VCC2B2 A1
1 2 3 4CLKEN1B 2B3OEA GND
1627112-BIT TO 24-BIT MULTIPLEXED BUS EXCHANGERWITH 3-STATE OUTPUTS
See page 554
OEA
1 2 3 4 5 6 7LE1B GND2B3 2B2 VCC
CLKENA2 GND2B4 2B5 VCC
82B1
2B6
9
48
A1
2B7
10
47
A2
2B8 2B9
11
46
A3
GND
12
45
GND GND
2B10
13
44
A4
2B11
14
43
A5
2B12
15
42
A6
1B12 1B11 1B10
16
41
A8
1B9
17
40
A9 A10 A11 A12
1B8 1B7
18
39
GND
GND
19
38
1B1
1B6
20
37
1B2
1B5
21
36
22
35
VCC
VCC
23
34
1B3
1B4 CLKENA1
24
33 32
A7
GND
31 30
SEL
CLKOEB
LE2B
53
25
52
26
51
27
50
28
49545556 29
1626012-BIT TO 24-BIT MULTIPLEXES D-TYPE LATCHWITH 3-STATE OUTPUTS
See page 548
2B7 2B122B11GND2B6 2B10VCC 2B8 2B9 GND 1B51B61B71B11 VCC1B12 1B10 1B9 1B82B5GNDLEA2B 2B4OE2B
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33OE1BLEA1BGND 1B4
32 31 30 29
A12A6 A7 A9 GND A10 VCCA11A5 A8 1B2 GND 1B3 LE2B SEL1B1
9 10 11 12
56 55 54 53 52 51 50 49
A3 GNDA2 A4
5 6 7 82B1 VCC2B2 A1
1 2 3 4LE1B 2B3OEA GND
NC – No internal connection
110
Pin Assignments
1637316-BIT TRANSPARENT LATCHESWITH 3-STATE OUTPUTS
See page 562
1D5 2D22D11D71D4 1D8VCC 1D6 GND VCC 2LE2D8GND2D3 2D7GND 2D4 2D5 2D61D3GND1D1 1D21LE
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
2Q11Q4 VCC 1Q6 GND 1Q7 2Q21Q81Q3 1Q5 2Q82Q3 2Q4 VCC 2Q5 2Q6 GND 2OE2Q7GND
1 2 3 4
48 47 46 45 44 43 42 41
1Q1 1Q21OE GND
1633416-BIT UNIVERSAL BUS DRIVERWITH 3-STATE OUTPUTS
See page 558
1 2 3 4 5 6 7NCY1 GNDY2 Y3 VCC
CLK A1 GNDA2 A3 VCC
8Y4
A4
9
48
Y5
A5
10
47
Y6
A6
11
46
GND
GND
12
45
Y7
A7
13
44
Y8
A8
14
43
Y9
A9
15
42
Y10
A10
16
41
Y11
A11
17
40
Y12
A12
18
39
GND
GND
19
38
Y13
A13
20
37
Y14
A14
21
36
Y15
A15
22
35
VCC
VCC
23
34
Y16
A16
24
33
LE
2532
GND
GND
2631 2730
OE
2829
163441-BIT TO 4-BIT ADDRESS DRIVERWITH 3-STATE OUTPUTS
See page 560
52 51
102B2 GND
92B1
61B4OE1
1GND
421B1
51B3
4855 54 53 50 4956
81A 2B42B3 3B23B1 3B43B32A 4A3A 4B24B1 4B44B3
31B2
7
47 42 41 3845 44 43 40 3946 37 32 3135 34 33 30 2936
161512 1918171413 20 21 22 23 24 25 26 27 2811VCC GND GNDVCC OE2
7B2 GND7B18B4OE4 GND8B1 8B3 8A 7B47B3 6B26B1 6B46B37A 5A6A 5B25B1 5B45B38B2 VCC GND GNDVCC OE3
1628218-BIT TO 36-BIT REGISTERED BUS EXCHANGERWITH 3-STATE OUTPUTS
See page 556
1 2 3 4 5 6 7GND GND1B92B9 VCC VCCVCCVCC
GNDVCC
82B8
9
72
A1
A17
10
71
A2
A16 A15 A14 A13
11
70
A3
GND
12
69
GND GND
2B101B10
13
68
A4
1B11 2B11
14
67
A5
2B12
15
66
A6
1B12 1B13 2B13 1B14 2B14
16
65
A8
17
64
A91B8 2B7 1B7
18
63
GND GND
GND
19
62
2B6
1B17
20
61
1B6 2B5 1B5 2B4 1B4 2B3 1B3 2B2 1B2 2B1 1B1
2B17 1B18
21
60
22
59
VCC
VCC 1B15 2B15 1B16 2B16 VCC
23
58
2B18
24
57 56
A7
GND VCC A18 VCCGND A11 A10A12 GND
55 5477
25
76
26
75
27
74
28
73787980 53
29
52
30
51
31
50
32
49
33
48
34
47
35
46
36
45
37
44
38
43
OE
39
42
SELCLK
DIR
40
41
NC – No internal connection
111
Pin Assignments
164099-BIT, 4-PORT UNIVERSAL BUS EXCHANGERWITH 3-STATE OUTPUTS
164604-TO-1 MULTIPLEXED/DEMULTIPLEXED TRANSCEIVERSWITH 3-STATE OUTPUTS
See page 568
See page 566
1B4 1B91B8GND1B3 1B7VCC 1B5 1B6 GND 2B82B72B62B2 VCC2B1 2B3 2B4 2B51B2GNDSELEN 1B1CLK
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33SEL3SEL4GND 2B9
32 31 30 29
2A61A9 2A1 2A3 GND 2A4 VCC2A51A8 2A2 2A8 GND 2A9 SEL1 SEL22A7
9 10 11 12
56 55 54 53 52 51 50 49
1A6 GND1A5 1A7
5 6 7 81A3 VCC1A2 1A4
1 2 3 4SEL0 1A1PRE GND
1B3 2B42B3GND1B2 2B2VCC 1B4 2B1 GND 4B44B34B23B2 VCC3B1 3B3 3B4 4B11B1GNDOEB2 SEL0OEB1
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33OEB4OEB3GND SEL1
32 31 30 29
CLKENBACE_SEL0 CE_SEL1 4A GND CLKENAB VCCCLKENB2A 3A LEB4 GND OEA LEAB3 LEAB3LEB3
9 10 11 12
56 55 54 53 52 51 50 49
CLKAB GNDOEB 1A
5 6 7 8LEB2 VCCLEB1 CLKBA
1 2 3 4LEAB2 LEBALEAB1 GND
1647016-BIT REGISTERED TRANSCEIVERSWITH 3-STATE OUTPUTS
See page 570
1B3 1B81B7GND1B2 1B6VCC 1B4 1B5 GND 2B82B72B62B2 VCC2B1 2B3 2B4 2B51B1GND1CLKBA 1CLKENBA1OEBA
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 332OEBA2CLKBAGND 2CLKENBA
32 31 30 29
2A61A8 2A1 2A3 GND 2A4 VCC2A51A7 2A2 2A8 GND 2CLKENAB 2CLKAB 2OEAB2A7
9 10 11 12
56 55 54 53 52 51 50 49
1A5 GND1A4 1A6
5 6 7 81A2 VCC1A1 1A3
1 2 3 41CLKAB 1CLKENAB1OEAB GND
1637416-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPSWITH 3-STATE OUTPUTS
See page 564
1D5 2D22D11D71D4 1D8VCC 1D6 GND VCC 2CLK2D8GND2D3 2D7GND 2D4 2D5 2D61D3GND1D1 1D21CLK
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
2Q11Q4 VCC 1Q6 GND 1Q7 2Q21Q81Q3 1Q5 2Q82Q3 2Q4 VCC 2Q5 2Q6 GND 2OE2Q7GND
1 2 3 4
48 47 46 45 44 43 42 41
1Q1 1Q21OE GND
112
Pin Assignments
1652518-BIT REGISTERED BUS TRANSCEIVERWITH 3-STATE OUTPUTS
See page 578
1 2 3 4 5 6 7GNDA1 VCC
CLKAB GNDB1 B2 VCC
8
B3
9
48
B4
10
47
A2
B5 B6
11
46
A3
GND
12
45
GND GND
B7
13
44
A4
B8
14
43
A5
B9
15
42
A6
B10 B11 B12
16
41
A8
B13
17
40
A9 A10 A11 A12 A13 A14 A15
B14 B15
18
39
GND
GND
19
38
A16
B16
20
37
A17
B17
21
36
22
35
VCC
VCC
23
34
A18
B18 CLK1BA
24
33 32
A7
GND
31 30
SEL CLK2BA
CLKENAB OEAB CLKENABOEBA
53
25
52
26
51
27
50
28
49545556 29
1650118-BIT UNIVERSAL BUS TRANSCEIVERWITH 3-STATE OUTPUTS
1652418-BIT REGISTERED BUS TRANSCEIVERWITH 3-STATE OUTPUTS
See page 574
See page 576
B4 B9B8GNDB3 B7VCC B5 B6 GND B17B16B15B11 VCCB10 B12 B13 B14B2GNDCLKAB B1GND
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33GNDCLKBAGND B18
32 31 30 29
A15A9 A10 A12 GND A13 VCCA14A8 A11 A17 GND A18 OEBA LEBAA16
9 10 11 12
56 55 54 53 52 51 50 49
A6 GNDA5 A7
5 6 7 8A3 VCCA2 A4
1 2 3 4LEAB A1OEAB GND
B4 B9B8GNDB3 B7VCC B5 B6 GND B17B16B15B11 VCCB10 B12 B13 B14B2GNDSEL B1GND
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33GNDCLKGND B18
32 31 30 29
A15A9 A10 A12 GND A13 VCCA14A8 A11 A17 GND A18 OEBA CLKENBAA16
9 10 11 12
56 55 54 53 52 51 50 49
A6 GNDA5 A7
5 6 7 8A3 VCCA2 A4
1 2 3 4OEAB A1GND GND
1650018-BIT UNIVERSAL BUS TRANSCEIVERWITH 3-STATE OUTPUTS
See page 572
B4 B9B8GNDB3 B7VCC B5 B6 GND B17B16B15B11 VCCB10 B12 B13 B14B2GNDCLKAB B1GND
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33GNDCLKBAGND B18
32 31 30 29
A15A9 A10 A12 GND A13 VCCA14A8 A11 A17 GND A18 OEBA LEBAA16
9 10 11 12
56 55 54 53 52 51 50 49
A6 GNDA5 A7
5 6 7 8A3 VCCA2 A4
1 2 3 4LEAB A1OEAB GND
113
Pin Assignments
1654116-BIT BUFFERS/DRIVERSWITH 3-STATE OUTPUTS
1654316-BIT REGISTERED TRANSCEIVERSWITH 3-STATE OUTPUTS
See page 582
See page 581
1B3 1B81B7GND1B2 1B6VCC 1B4 1B5 GND 2B82B72B62B2 VCC2B1 2B3 2B4 2B51B1GND1LEBA 1CEBA1OEBA
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 332OEBA2LEBAGND 2CEBA
32 31 30 29
2A61A8 2A1 2A3 GND 2A4 VCC2A51A7 2A2 2A8 GND 2CEAB 2LEAB 2OEAB2A7
9 10 11 12
56 55 54 53 52 51 50 49
1A5 GND1A4 1A6
5 6 7 81A2 VCC1A1 1A3
1 2 3 41LEAB 1CEAB1OEAB GND
1A5 2A22A11A71A4 1A8VCC 1A6 GND VCC 2OE22A8GND2A3 2A7GND 2A4 2A5 2A61A3GND1A1 1A21OE2
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
2Y11Y4 VCC 1Y6 GND 1Y7 2Y21Y81Y3 1Y5 2Y82Y3 2Y4 VCC 2Y5 2Y6 GND 2OE12Y7GND
1 2 3 4
48 47 46 45 44 43 42 41
1Y1 1Y21OE1 GND
1660018-BIT UNIVERSAL BUS TRANSCEIVERSWITH 3-STATE OUTPUTS
See page 584
B4 B9B8GNDB3 B7VCC B5 B6 GND B17B16B15B11 VCCB10 B12 B13 B14B2GNDCLKAB B1CLKENAB
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33CLKENBACLKBAGND B18
32 31 30 29
A15A9 A10 A12 GND A13 VCCA14A8 A11 A17 GND A18 OEBA LEBAA16
9 10 11 12
56 55 54 53 52 51 50 49
A6 GNDA5 A7
5 6 7 8A3 VCCA2 A4
1 2 3 4LEAB A1OEAB GND
1654016-BIT BUFFERS/DRIVERSWITH 3-STATE OUTPUTS
See page 580
1A5 2A22A11A71A4 1A8VCC 1A6 GND VCC 2OE22A8GND2A3 2A7GND 2A4 2A5 2A61A3GND1A1 1A21OE2
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
2Y11Y4 VCC 1Y6 GND 1Y7 2Y21Y81Y3 1Y5 2Y82Y3 2Y4 VCC 2Y5 2Y6 GND 2OE12Y7GND
1 2 3 4
48 47 46 45 44 43 42 41
1Y1 1Y21OE1 GND
114
Pin Assignments
1664016-BIT BUS TRANSCEIVERWITH 3-STATE OUTPUTS
See page 591
1A5 2A22A11A71A4 1A8VCC 1A6 GND VCC 2OE2A8GND2A3 2A7GND 2A4 2A5 2A61A3GND1A1 1A21OE
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
2B11B4 VCC 1B6 GND 1B7 2B21B81B3 1B5 2B82B3 2B4 VCC 2B5 2B6 GND 2DIR2B7GND
1 2 3 4
48 47 46 45 44 43 42 41
1B1 1B21DIR GND
1662016-BIT BUS TRANSCEIVERSWITH 3-STATE OUTPUTS
1662316-BIT BUS TRANSCEIVERSWITH 3-STATE OUTPUTS
See page 588
See page 590
1A5 2A22A11A71A4 1A8VCC 1A6 GND VCC 2OEBA2A8GND2A3 2A7GND 2A4 2A5 2A61A3GND1A1 1A21OEBA
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
2B11B4 VCC 1B6 GND 1B7 2B21B81B3 1B5 2B82B3 2B4 VCC 2B5 2B6 GND 2OEAB2B7GND
1 2 3 4
48 47 46 45 44 43 42 41
1B1 1B21OEAB GND
1A5 2A22A11A71A4 1A8VCC 1A6 GND VCC 2OEBA2A8GND2A3 2A7GND 2A4 2A5 2A61A3GND1A1 1A21OEBA
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
2B11B4 VCC 1B6 GND 1B7 2B21B81B3 1B5 2B82B3 2B4 VCC 2B5 2B6 GND 2OEAB2B7GND
1 2 3 4
48 47 46 45 44 43 42 41
1B1 1B21OEAB GND
1660118-BIT UNIVERSAL BUS TRANSCEIVERSWITH 3-STATE OUTPUTS
See page 586
B4 B9B8GNDB3 B7VCC B5 B6 GND B17B16B15B11 VCCB10 B12 B13 B14B2GNDCLKAB B1CLKENAB
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33CLKENBACLKBAGND B18
32 31 30 29
A15A9 A10 A12 GND A13 VCCA14A8 A11 A17 GND A18 OEBA LEBAA16
9 10 11 12
56 55 54 53 52 51 50 49
A6 GNDA5 A7
5 6 7 8A3 VCCA2 A4
1 2 3 4LEAB A1OEAB GND
115
Pin Assignments
1665116-BIT BUS TRANSCEIVERS AND REGISTERSWITH 3-STATE OUTPUTS
1665216-BIT BUS TRANSCEIVERS AND REGISTERSWITH 3-STATE OUTPUTS
See page 596
See page 594
1B3 1B81B7GND1B2 1B6VCC 1B4 1B5 GND 2B82B72B62B2 VCC2B1 2B3 2B4 2B51B1GND1CLKBA 1SBA1OEBA
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 332OEBA2CLKBAGND 2SBA
32 31 30 29
2A61A8 2A1 2A3 GND 2A4 VCC2A51A7 2A2 2A8 GND 2SAB 2CLKAB 2OEAB2A7
9 10 11 12
56 55 54 53 52 51 50 49
1A5 GND1A4 1A6
5 6 7 81A2 VCC1A1 1A3
1 2 3 41CLKAB 1SAB1OEAB GND
1B3 1B81B7GND1B2 1B6VCC 1B4 1B5 GND 2B82B72B62B2 VCC2B1 2B3 2B4 2B51B1GND1CLKBA 1SBA1OEBA
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 332OEBA2CLKBAGND 2SBA
32 31 30 29
2A61A8 2A1 2A3 GND 2A4 VCC2A51A7 2A2 2A8 GND 2SAB 2CLKAB 2OEBA2A7
9 10 11 12
56 55 54 53 52 51 50 49
1A5 GND1A4 1A6
5 6 7 81A2 VCC1A1 1A3
1 2 3 41CLKAB 1SAB1OEAB GND
1665716-BIT TRANSCEIVERSWITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS
See page 598
1B3 1B81B7GND1B2 1B6VCC 1B4 1B5 GND 2B82B72B62B2 VCC2B1 2B3 2B4 2B51B1GND1ODD/EVEN 1PARITY1T/R
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 332T/R2ODD/EVENGND 2PARITY
32 31 30 29
2A61A8 2A1 2A3 GND 2A4 VCC2A51A7 2A2 2A8 GND 2ERR NC 2OE2A7
9 10 11 12
56 55 54 53 52 51 50 49
1A5 GND1A4 1A6
5 6 7 81A2 VCC1A1 1A3
1 2 3 4NC 1ERR1OE GND
1664616-BIT BUS TRANSCEIVERS AND REGISTERSWITH 3-STATE OUTPUTS
See page 592
1B3 1B81B7GND1B2 1B6VCC 1B4 1B5 GND 2B82B72B62B2 VCC2B1 2B3 2B4 2B51B1GND1CLKBA 1SBA1OE
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 332OE2CLKBAGND 2SBA
32 31 30 29
2A61A8 2A1 2A3 GND 2A4 VCC2A51A7 2A2 2A8 GND 2SAB 2CLKAB 2DIR2A7
9 10 11 12
56 55 54 53 52 51 50 49
1A5 GND1A4 1A6
5 6 7 81A2 VCC1A1 1A3
1 2 3 41CLKAB 1SAB1DIR GND
NC – No internal connection
116
Pin Assignments
1682120-BIT BUS INTERFACE FLIP-FLOPSWITH 3-STATE OUTPUTS
See page 603
1D5 1D101D9GND1D4 1D8VCC 1D6 1D7 GND 2D82D72D62D2 VCC2D1 2D3 2D4 2D51D3GND1D1 1D21CLK
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 332CLK2D10GND 2D9
32 31 30 29
2Q61Q10 2Q1 2Q3 GND 2Q4 VCC2Q51Q9 2Q2 2Q8 GND 2Q9 2Q10 2OE2Q7
9 10 11 12
56 55 54 53 52 51 50 49
1Q7 GND1Q6 1Q8
5 6 7 81Q4 VCC1Q3 1Q5
1 2 3 41Q1 1Q21OE GND
1682010-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPSWITH DUAL OUTPUTS
See page 602
D3 NCD5GNDNC NCVCC NC D4 GND NCD9NCNC VCCD6 D7 NC D8D2GNDD1 NCCLK
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33NCNCGND D10
32 31 30 29
8Q25Q2 6Q1 7Q1 GND 7Q2 VCC8Q15Q1 6Q2 9Q2 GND 10Q1 10Q2 2OE9Q1
9 10 11 12
56 55 54 53 52 51 50 49
4Q1 GND3Q2 4Q2
5 6 7 82Q2 VCC2Q1 3Q1
1 2 3 41Q1 1Q21OE GND
1672222-BIT FLIP-FLOP WITH 3-STATE OUTPUTS
See page 601
1 2 3 4 5 6 7Q3 Q4Q2Q1 GNDVCC Q5
CLK D2D1 GND D4 VCC
8Q18
D3
9 10
D5
11Q7
D6
12
D7
13Q6
GND
14GND
D12
15
D11
16Q9
D16
17Q15
D13 GND
18Q14 Q17
D8
19Q11
D21
20Q19GND Q22 GND NCQ21
D15
21GND
D17
22Q8 VCC Q20 VCC
VCC D20 VCCD18D9
23Q16
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31
50
32
49 3348 3447 3546 3645 3744 3843 3942 404164
Q10
D10 D14 GND D19 D22
5863 5962
Q13Q12OE
CLKENGND
6061
1672120-BIT FLIP-FLOPWITH 3-STATE OUTPUTS
See page 600
D5 D10D9GNDD4 D8VCC D6 D7 GND D18D17D16D12 VCCD11 D13 D14 D15D3GNDD1 D2CLK
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33CLKEND20GND D19
32 31 30 29
Q16Q10 Q11 Q13 GND Q14 VCCQ15Q9 Q12 Q18 GND Q19 Q20 NCQ17
9 10 11 12
56 55 54 53 52 51 50 49
Q7 GNDQ6 Q8
5 6 7 8Q4 VCCQ3 Q5
1 2 3 4Q1 Q2OE GND
NC – No internal connection
NC – No internal connection
NC – No internal connection
117
Pin Assignments
1682518-BIT BUS BUFFERS/DRIVERSWITH 3-STATE OUTPUTS
1682720-BIT BUS BUFFERS/DRIVERSWITH 3-STATE OUTPUTS
See page 606
See page 605
1A5 1A101A9GND1A4 1A8VCC 1A6 1A7 GND 2A82A72A62A2 VCC2A1 2A3 2A4 2A51A3GND1A1 1A21OE2
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 332OE22A10GNA 2A9
32 31 30 29
2Y61Y10 2Y1 2Y3 GNA 2Y4 VCC2Y51Y9 2Y2 2Y8 GNA 2Y9 2Y10 2OE12Y7
9 10 11 12
56 55 54 53 52 51 50 49
1Y7 GNA1Y6 1Y8
5 6 7 81Y4 VCC1Y3 1Y5
1 2 3 41Y1 1Y21OE1 GNA
1A5 GND1A9GND1A4 1A8VCC 1A6 1A7 GND 2A72A62A52A1 VCCGND 2A2 2A3 2A41A3GND1A1 1A21OE2
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 332OE22A9GNA 2A8
32 31 30 29
2Y5GND GND 2Y2 GNA 2Y3 VCC2Y41Y9 2Y1 2Y7 GNA 2Y8 2Y9 2OE12Y6
9 10 11 12
56 55 54 53 52 51 50 49
1Y7 GNA1Y6 1Y8
5 6 7 81Y4 VCC1Y3 1Y5
1 2 3 41Y1 1Y21OE1 GNA
168311-TO-4 ADDRESS REGISTER/DRIVERWITH 3-STATE OUTPUTS
See page 607
1 2 3 4 5 6 71Y1GND3Y1 NC A3VCC GND
1Y2 GND2Y2 3Y2 VCC
8A6
4Y2
9
80
NC
1Y3
10
79
A1
2Y3
11
78
GND
GND
12
77
NC
3Y3
13
76
A2
4Y3
14
75
2Y1
2Y4
15
74
4Y1
1Y4
16
73
NC
2Y5
17
72
A4
3Y4 4Y4
18
71
GND GND
GND
19
70
CLK
2Y6
20
69
A7 NC GNDA8 NC GNDA9 NC 2Y94Y9 1Y93Y9
1Y5
21
68
SEL
3Y5
22
67
VCC VCC VCC
VCC VCC VCC
23
66
A5
4Y5
24
65 57
25
56
26
55
27
54
28
53
29
52
30
51
31
50
32
49
33
48
34
47
35
46
36
45
37
44
38
43
39
42
40
4164
GND
GND GND GND GND GND
5863 5962
OE2OE1
1Y6 4Y63Y6 2Y71Y7 4Y73Y7 2Y81Y8 4Y83Y8
6061
1682318-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPSWITH DUAL OUTPUTS
See page 604
1D4 1D91D8GND1D3 1D7VCC 1D5 1D6 GND 2D82D72D62D2 VCC2D1 2D3 2D4 2D51D2GND1CLKEN 1D11CLK
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 332CLK2CLKENGND 2D9
32 31 30 29
2Q61Q9 2Q1 2Q3 GND 2Q4 VCC2Q51Q8 2Q2 2Q8 GND 2Q9 2OE 2CLR2Q7
9 10 11 12
56 55 54 53 52 51 50 49
1Q6 GND1Q5 1Q7
5 6 7 81Q3 VCC1Q2 1Q4
1 2 3 41OE 1Q11CLR GND
NC – No internal connection
118
Pin Assignments
168353.3-V ABT 18-BIT UNIVERSAL BUS DRIVERWITH 3-STATE OUTPUTS
See page 613
A4 A9A8GNDA3 A7VCC A5 A6 GND A17A16A15A11 VCCA10 A12 A13 A14A2GNDNC A1GND
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33GNDCLKGND A18
32 31 30 29
Y15Y9 Y10 Y12 GND Y13 VCCY14Y8 Y11 Y17 GND Y18 OE LEY16
9 10 11 12
56 55 54 53 52 51 50 49
Y6 GNDY5 Y7
5 6 7 8Y3 VCCY2 Y4
1 2 3 4NC Y1NC GND
16833DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
1683416-BIT UNIVERSAL BUS DRIVERWITH 3-STATE OUTPUTS
See page 610
See page 612
1 2 3 4 5 6 7Y18Y1 GND Y2 Y3 VCC
NCGND A1 GND A2 A3 VCC
8Y4
A4
9
48
Y5
A5
10
47
Y6
A6
11
46
GND
GND
12
45
Y7
A7
13
44
Y8
A8
14
43
Y9
A9
15
42
Y10
A10
16
41
Y11
A11
17
40
Y12
A12
18
39
GND
GND
19
38
Y13
A13
20
37
Y14
A14
21
36
Y15
A15
22
35
VCC
VCC
23
34
Y16
A16 A17
24
3353 32
GND
GND A18 CLK GND
54 3155 30
OEY17 LE
25
52
26
51
NC
27
50
NC
28
4956 29
1B3 1B81B7GND1B2 1B6VCC 1B4 1B5 GND 2B82B72B62B2 VCC2B1 2B3 2B4 2B51B1GND1CLR 1PARITY1OEA
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 332OEA2CLRGND 2PARITY
32 31 30 29
2A61A8 2A1 2A3 GND 2A4 VCC2A51A7 2A2 2A8 GND 2ERR 2CLK 2OEB2A7
9 10 11 12
56 55 54 53 52 51 50 49
1A5 GND1A4 1A6
5 6 7 81A2 VCC1A1 1A3
1 2 3 41CLK 1ERR1OEB GND
168321-TO-4 ADDRESS REGISTER/DRIVERWITH 3-STATE OUTPUTS
See page 608
1 2 3 4 5 6 71Y1GND3Y1 A3VCC GND
1Y2 GND2Y2 3Y2 VCC
8A6
4Y2
9
1Y3
10A1
2Y3
11GND
GND
12
3Y3
13A2
4Y3
142Y1
2Y4
154Y1
1Y4
16NC
2Y5
17A4
3Y4 4Y4
18GND GND
GND
19CLK
2Y6
20A7GND GND 2Y74Y7 1Y73Y7
1Y5
21SEL
3Y5
22VCC VCC VCC
VCC VCCVCC
23A5
4Y5
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31
50
32
49 3348 3447 3546 3645 3744 3843 3942 404164
GND
GND GND GND GND GND
5863 5962
OE2OE1
1Y6 4Y63Y6
6061
NC – No internal connection
NC – No internal connection
NC – No internal connection
119
Pin Assignments
16853DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
See page 616
1D4 1D91D8GND1D3 1D7VCC 1D5 1D6 GND 2D82D72D62D2 VCC2D1 2D3 2D4 2D51D2GND1PRE 1D11LE
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 332LE2PREGND 2D9
32 31 30 29
2Q61Q9 2Q1 2Q3 GND 2Q4 VCC2Q51Q8 2Q2 2Q8 GND 2Q9 2OE 2CLR2Q7
9 10 11 12
56 55 54 53 52 51 50 49
1Q6 GND1Q5 1Q7
5 6 7 81Q3 VCC1Q2 1Q4
1 2 3 41OE 1Q11CLR GND
1684318-BIT BUS INTERFACE D-TYPE LATCHESWITH 3-STATE OUTPUTS
See page 615
1D4 1D91D8GND1D3 1D7VCC 1D5 1D6 GND 2D82D72D62D2 VCC2D1 2D3 2D4 2D51D2GND1PRE 1D11LE
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 332LE2PREGND 2D9
32 31 30 29
2Q61Q9 2Q1 2Q3 GND 2Q4 VCC2Q51Q8 2Q2 2Q8 GND 2Q9 2OE 2CLR2Q7
9 10 11 12
56 55 54 53 52 51 50 49
1Q6 GND1Q5 1Q7
5 6 7 81Q3 VCC1Q2 1Q4
1 2 3 41OE 1Q11CLR GND
1686120-BIT BUS TRANSCEIVERSWITH 3-STATE OUTPUTS
See page 618
1A5 1A101A9GND1A4 1A8VCC 1A6 1A7 GND 2A82A72A62A2 VCC2A1 2A3 2A4 2A51A3GND1A1 1A21OEBA
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 332OEBA2A10GNA 2A9
32 31 30 29
2B61B10 2B1 2B3 GNA 2B4 VCC2B51B9 2B2 2B8 GNA 2B9 2B10 2OEAB2B7
9 10 11 12
56 55 54 53 52 51 50 49
1B7 GNA1B6 1B8
5 6 7 81B4 VCC1B3 1B5
1 2 3 41B1 1B21OEAB GNA
1684120-BIT BUS INTERFACE D-TYPE LATCHESWITH 3-STATE OUTPUTS
See page 614
1D5 1D101D9GND1D4 1D8VCC 1D6 1D7 GND 2D82D72D62D2 VCC2D1 2D3 2D4 2D51D3GND1D1 1D21LE
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 332LE2D10GND 2D9
32 31 30 29
2Q61Q10 2Q1 2Q3 GND 2Q4 VCC2Q51Q9 2Q2 2Q8 GND 2Q9 2Q10 2OE2Q7
9 10 11 12
56 55 54 53 52 51 50 49
1Q7 GND1Q6 1Q8
5 6 7 81Q4 VCC1Q3 1Q5
1 2 3 41Q1 1Q21OE GND
120
Pin Assignments
1695216-BIT REGISTERED TRANSCEIVERSWITH 3-STATE OUTPUTS
See page 624
1B3 1B81B7GND1B2 1B6VCC 1B4 1B5 GND 2B82B72B62B2 VCC2B1 2B3 2B4 2B51B1GND1CLKBA 1CLKENBA1OEBA
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 332OEBA2CLKBAGND 2CLKENBA
32 31 30 29
2A61A8 2A1 2A3 GND 2A4 VCC2A51A7 2A2 2A8 GND 2CLKENAB 2CLKAB 2OEAB2A7
9 10 11 12
56 55 54 53 52 51 50 49
1A5 GND1A4 1A6
5 6 7 81A2 VCC1A1 1A3
1 2 3 41CLKAB 1CLKENAB1OEAB GND
169033.3-V 12-BIT UNIVERSAL BUS DRIVERWITH PARITY CHECKER AND DUAL 3-STATE OUTPUTS
See page 622
CLKEN
PAROE
1 2 3 4 5 6 79Y21Y1 GND1Y2 2Y1 VCC
CLK 1A GND11A/YERREN 11Y1 VCC
82Y2
11Y2
9
48
3Y1
2A
10
47
3Y2
3A
11
46
GND
GND
12
45
4Y1
4A
13
44
4Y2
12A
14
43
5Y1
12Y1
15
42
5Y2
12Y2
16
41
6Y1
5A
17
40
6Y2
6A
18
39
GND
GND
19
38
7Y1
7A
20
37
7Y2
APAR
21
36
8Y1
8A
22
35
VCC
VCC
23
34
8Y2
YERR 9A MODE
24
3353 32
GND
GND 10A PARI/O
54 3155 30
OE 9Y1 10Y2
25
52
26
51
27
50
10Y1
28
4956 29
1690118-BIT UNIVERSAL BUS TRANSCEIVERWITH PARITY GENERATORS/CHECKERS
See page 620
2ERRA
1B2 GND1B61B4GND 1B51B1 1B3 VCC 2B2 2B6VCC2B41B8 2B51B7 2B1 GND 2B31BPAR1ERRBLEBA CLKBA1CLKENBA
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 412BPARGND2B7 2B8
40 39 38 37
2A4GND 1A7 2A1 2A2 GND 2A52A31A6 1A8 2B6 2A7 2B8 GND 2APARVCC
9 10 11 12
64 63 62 61 60 59 58 57
VCC 1A41A3 1A5
5 6 7 8GND 1A11APAR 1A2
1 2 3 4LEAB CLKAB1CLKENAB 1ERRA
29 30 31 32
2CLKENBAODD/EVEN2ERRB OEBA
36 35 34 33
OEAB SEL 2CLKENAB
1686318-BIT BUS TRANSCEIVERSWITH 3-STATE OUTPUTS
See page 619
1A5 GND1A9GND1A4 1A8VCC 1A6 1A7 GND 2A72A62A52A1 VCCGND 2A2 2A3 2A41A3GND1A1 1A21OEBA
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 332OEBA2A9GNA 2A8
32 31 30 29
2B5GND GND 2B2 GNA 2B3 VCC2B41B9 2B1 2B7 GNA 2B8 2B9 2OEAB2B6
9 10 11 12
56 55 54 53 52 51 50 49
1B7 GNA1B6 1B8
5 6 7 81B4 VCC1B3 1B5
1 2 3 41B1 1B21OEAB GNA
121
Pin Assignments
2984110-BIT BUS INTERFACE D-TYPE LATCHESWITH 3-STATE OUTPUTS
See page 633
9 10 11 12A9 A10A8 GND
5 6 7 8A5 A6A4 A7
1 2 3 4A1 A2OE1 A3
24 23 22 21 20 19 18 17 16 15 14 13Y7 Y10Y5 OE2Y6 Y8 Y9Y4Y3Y1 Y2VCC
2524525-Ω OCTAL BUS TRANSCEIVERSWITH 3-STATE OUTPUTS
298258-BIT BUS-INTERFACE FLIP-FLOPSWITH 3-STATE OUTPUTS
See page 627
See page 630
9 10 11 129D CLR8D GND
5 6 7 85D 6D4D 7D
1 2 3 41D 2DOC 3D
24 23 22 21 20 19 18 17 16 15 14 137Q PRE5Q C6Q 8Q 9Q4Q3Q1Q 2QVCC
9 10 11 129D 10D8D GND
5 6 7 85D 6D4D 7D
1 2 3 41D 2DOE 3D
24 23 22 21 20 19 18 17 16 15 14 137Q 10Q5Q CLK6Q 8Q 9Q4Q3Q1Q 2QVCC
25642 25-Ω OCTAL BUS TRANSCEIVER
See page 628
298272982810-BIT BUFFERS AND BUS DRIVERSWITH 3-STATE OUTPUTS
See page 631, 632
9 10 11 12CLR8D GND
5 6 7 85D 6D4D 7D
1 2 3 41D 2DOE1 OE2 3D
24 23 22 21 20 19 18 17 16 15 14 136Q CLKEN4Q CLK5Q 7Q 8Q3Q2QOE3 1QVCC
16B3
15B4
10A7 GND A8
9A6
6A4A1
1A3
42GND
5GND
VCC
12
B1
19 18B2
17VCC
14B5
13B6
24 23 22 21 20DIR
8GND
3A2
7 11A5
B7 B8 OE
2524425-Ω OCTAL BUS BUFFERS/DRIVERSWITH 3-STATE OUTPUTS
2982110-BIT BUS-INTERFACE FLIP-FLOPSWITH 3-STATE OUTPUTS
See page 626
See page 629
9 10 11 122Y3 GND2Y2 2Y4
5 6 7 81Y4 2Y1GND GND
1 2 3 4GND 1Y21Y1 1Y3
24 23 22 21 20 19 18 17 16 15 14 132A2 2A41A4 2OE2A1 VCC 2A31A3VCC1A1 1A21OE
9 10 11 12A7 GNDA6 A8
5 6 7 8A4 A5GND GND
1 2 3 4GND A2A1 A3
24 23 22 21 20 19 18 17 16 15 14 13B6 B8B4 OEB5 VCC B7B3VCCB1 B2DIR
298439-BIT BUS INTERFACE D-TYPE LATCHESWITH 3-STATE OUTPUTS
See page 634
9 10 11 129D 10D8D GND
5 6 7 85D 6D4D 7D
1 2 3 41D 2DOE 3D
24 23 22 21 20 19 18 17 16 15 14 137Q 10Q5Q LE6Q 8Q 9Q4Q3Q1Q 2QVCC
122
Pin Assignments
3224032-BIT BUFFER/DRIVER
See page 640
terminal assignments
1 2 3 4 5 6
A 1Y2 1Y1 1OE 2OE 1A1 1A2
B 1Y4 1Y3 GND GND 1A3 1A4
C 2Y2 2Y1 1VCC 1VCC 2A1 2A2
D 2Y2 2Y3 GND GND 2A3 2A4
E 3Y2 3Y1 GND GND 3A1 3A2
F 3Y4 3Y3 1VCC 1VCC 3A3 3A4G 4Y2 4Y1 GND GND 4A1 4A2
H 4Y3 4Y4 4OE 3OE 4A4 4A3
J 5Y2 5Y1 5OE 6OE 5A1 5A2
K 5Y4 5Y3 GND GND 5A3 5A4
L 6Y2 6Y1 2VCC 2VCC 6A1 6A2M 6Y4 6Y3 GND GND 6A3 6A4
N 7Y2 7Y1 GND GND 7A1 7A2
P 7Y4 7Y3 2VCC 2VCC 7A3 7A4R 8Y2 8Y1 GND GND 8A1 8A2T 8Y3 8Y4 8OE 7OE 8A4 8A3
GKE PACKAGE(TOP VIEW)
1 2 3 4 5 6
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
298548-BIT TO 9-BIT PARITY BUS TRANSCEIVER
See page 636
1 2 3
24 22
OEA CLRA1
VCC PARITY
23
OEB
4
21
A2
B1
5
20
A3
B2
6
19
A4 A5 A6 A7 A8
B3
7
18
B4
8
17
B5
9
16
B6
10
15
ERR
B7
11
14
B8
12
13
GND
LE
298649-BIT BUS TRANSCEIVERSWITH 3-STATE OUTPUTS
See page 639
9 10 11 12A9 OEAB2A8 GND
5 6 7 8A5 A6A4 A7
1 2 3 4A1 A2OEAB1 A3
24 23 22 21 20 19 18 17 16 15 14 13B7 OEAB2B5 OEAB1B6 B8 B9B4B3B1 B2VCC
298639-BIT BUS TRANSCEIVERSWITH 3-STATE OUTPUTS
See page 638
9 10 11 12A9 OEAB2A8 GND
5 6 7 8A5 A6A4 A7
1 2 3 4A1 A2OEAB1 A3
24 23 22 21 20 19 18 17 16 15 14 13B7 OEAB2B5 OEAB1B6 B8 B9B4B3B1 B2VCC
123
Pin Assignments
1
A
GKE PACKAGE(TOP VIEW)
B C D E F G H J K L M N P R T
2
3
4
5
6
6 1A2
5 1A1
4 2OE
3 1OE
2 1Y1
1 1Y2
A
1A4
1A3
GND
GND
1Y3
1Y4
B
2A2
2A1
VCC
VCC
3OE
4OE
6OE
5DIR
7OE
8DIR
GND
GND
VCC
VCC
2Y1
2Y2
2A4
2A3
GND
GND
GND
GND
GND
GND
VCC
VCC
GND
GND
GND
GND
VCC
VCC
GND
GND
2Y3
2Y4
3A2
3A1
3Y1
3Y2
3A4
3A3
3Y3
3Y4
4A2
4A1
4Y1
4Y2
4A3
4A4
4Y4
4Y3
5A2
5A1
5Y1
5Y2
5A4
5A3
5Y3
5Y4
6A2
6A1
6Y1
6Y2
6A4
6A3
6Y3
6Y4
7A2
7A1
7Y1
7Y2
7A4
7A3
7Y3
7Y4
8A2
8A1
8Y1
8Y2
8A3
8A4
8Y4
8Y3
C D E F G H J K L M N P R T
3224436-BIT BUFFER/DRIVERWITH 3-STATE OUTPUTS
See page 642
124
Pin Assignments
1
A
GKE PACKAGE(TOP VIEW)
B C D E F G H J K L M N P R T
2
3
4
5
6
6 1A2
5 1A1
4 1OE
3 1DIR
2 1B1
1 1B2
A
1A4
1A3
GND
GND
1B3
1B4
B
1A6
1A5
VCC
VCC
2OE
2DIR
3OE
3DIR
4OE
4DIR
GND
GND
VCC
VCC
1B5
1B6
1A8
1A7
GND
GND
GND
GND
GND
GND
VCC
VCC
GND
GND
GND
GND
VCC
VCC
GND
GND
1B7
1B8
2A2
2A1
2B1
2B2
2A4
2A3
2B3
2B4
2A6
2A5
2B5
2B6
2A7
2A8
2B8
2B7
3A2
3A1
3B1
3B2
3A4
3A3
3B3
3B4
3A6
3A5
3B5
3B6
3A8
3A7
3B7
3B8
4A2
4A1
4B1
4B2
4A4
4A3
4B3
4B4
4A6
4A5
4B5
4B6
4A7
4A8
4B8
4B7
C D E F G H J K L M N P R T
38 39 40 41 42 43 44 45 46 47 48 49 504B53OE 3DIR 4B9 4B8 4B7 GND4B6VCC GND 4B3 4B24B4
34 35 36 37GND 4DIR4A9 4OE
30 31 32 334A6 4A74A5 4A8
26 27 28 294A3 4A44A2 GND
63
64
65
66
67
68
69
70
71
72
73
74
75
2A3
2B9
2B8
2A6
GND
2A5
2B2
2A4
VCC
2A7
2A1
1B9
GND
59
60
61
62
3B3
3B2
3B4
3B1
55
56
57
58
3B6
3B5
3B7
GND
51
52
53
54
3B9
GND
4B1
3B8
13
14
15
16
17
18
19
20
21
22
23
24
25
3A7
3A1
3A2
3A4
GND
3A5
3A8
3A6
VCC
3A3
3A9
4A1
GND
9
10
11
12
2A7
2A8
2A6
2A9
5
6
7
8
2A4
2A5
2A3
GND
1
2
3
4
2A1
GND
1A9
2A2
888990919293949596979899100
1B52OE 2DIR 1B1 1B2 1B3 GND1B4VCC GND 1B7 1B81B6
84858687
GND 1DIR1A1 1OE
80818283
1A4 1A31A5 1A2
76777879
1A7 1A61A8 GND
3224536-BIT BUS TRANSCEIVERWITH 3-STATE OUTPUTS
3224536-BIT BUS TRANSCEIVERWITH 3-STATE OUTPUTS
See page 644
See page 644
125
Pin Assignments
51
50
38 39 40
41
42
43
44
45
46
47
48
49
B15
B9 B10
B12
B13
GND
B16
B14
B8
B11
B18
GND
B17
34 35 36 37B6 B7B5 GND
30 31 32 33GND B3VCC B4
26 27 28 29CLKB B1LEB B2
C12C17 VCC C16 C15 C14 GNDC13GND C10 C9C11
59
60 C8
LEC
C7
CLKC
55
56
57
58
C5
GND
C4
C6
52
53
54
C1
C2
VCC
C3
13
14
15
16
17
18
19
20
21 22 23 24 25A18
A12
A13
GND
A15
A16
CLKA
A17
A11
A14
OEB SELBLEA
9
10
11
12
VCC
GND
A9
A10
5
6
7
8
A6
A7
A5
A8
1
2
3
4
A3
A4
A2
GND
A1 SELA OEC SELCOEA C18
80 7879 63646566676869707172737475 61627677
51
50
38 39 40
41
42
43
44
45
46
47
48
49
B13
B7 B8
B10
B11
GND
B14
B12
B6
B9
B16
GND
B15
34 35 36 37B4 B5B3 GND
30 31 32 33GND B1VCC B2
26 27 28 29CLKB CLKENBLEB NC
C12NC VCC C16 C15 C14 GNDC13GND C10 C9C11
59
60 C8
LEC
C7
CLKC
55
56
57
58
C5
GND
C4
C6
52
53
54
C1
C2
VCC
C3
13
14
15
16
17
18
19
20
21 22 23 24 25CLKENA
A12
A13
GND
A15
A16
CLKA
NC
A11
A14
OEB SELBLEA
9
10
11
12
VCC
GND
A9
A10
5
6
7
8
A6
A7
A5
A8
1
2
3
4
A3
A4
A2
GND
A1 SELA OEC SELCOEA CLKENC
80 7879 63646566676869707172737475 61627677
3231616-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS
3231818-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS
See page 646
See page 648
NC – No internal connection
126
Pin Assignments
3237332-BIT TRANSPARENT D-TYPE LATCHWITH 3-STATE OUTPUTS
3237432-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPWITH 3-STATE OUTPUTS
See page 652
See page 650
1
A
GKE PACKAGE(TOP VIEW)
B C D E F G H J K L M N P R T
2
3
4
5
6
6 1D2
5 1D1
4 1LE
3 1OE
2 1Q1
1 1Q2
A
1D4
1D3
GND
GND
1Q3
1Q4
B
1D6
1D5
VCC
VCC
2LE
2OE
3LE
3OE
4LE
4OE
GND
GND
VCC
VCC
1Q5
1Q6
1D8
1D7
GND
GND
GND
GND
GND
GND
VCC
VCC
GND
GND
GND
GND
VCC
VCC
GND
GND
1Q7
1Q8
2D2
2D1
2Q1
2Q2
2D4
2D3
2Q3
2Q4
2D6
2D5
2Q5
2Q6
2D7
2D8
2Q8
2Q7
3D2
3D1
3Q1
3Q2
3D4
3D3
3Q3
3Q4
3D6
3D5
3Q5
3Q6
3D8
3D7
3Q7
3Q8
4D2
4D1
4Q1
4Q2
4D4
4D3
4Q3
4Q4
4D6
4D5
4Q5
4Q6
4D7
4D8
4Q8
4Q7
C D E F G H J K L M N P R T
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
2 3 4 5 6
1OE
2OE
3OE
4OE
A
1 2 3 4
1CLK
2CLK
3CLK
4CLK
5 6
1Q2 1Q1 1D1 1D2
GND GND1Q4 1Q3 1D3 1D4
VCC VCC1Q6 1Q5 1D5 1D6
GND GND
GND GND
VCC VCC
GND GND
GND GND
VCC VCC
GND GND
GND GND
VCC VCC
GND GND
1Q8 1Q7 1D7 1D8
2Q2 2Q1 2D1 2D2
2Q4 2Q3 2D3 2D4
2Q6 2Q5 2D5 2D6
2Q8 2Q7 2D7 2D8
3Q2 3Q1 3D1 3D2
3Q4 3Q3 3D3 3D4
3Q6 3Q5 3D5 3D6
3Q8 3Q7
4Q2 4Q1
4Q4 4Q3
4Q6 4Q5
4Q84Q7
3D7 3D8
4D1 4D2
4D3 4D4
4D5 4D6
4D74D8
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
GKE PACKAGE(TOP VIEW)
terminal assignments
127
Pin Assignments
38 39 40 41 42 43 44 45 46 47 48 49 501B141CLKAB 1LEAB 1B18 1B17 1B16 GND1B15VCC 1OEAB 1B12 1B111B13
34 35 36 371OEBA 1LEBA1A18 1CLKBA
30 31 32 331A15 1A161A14 1A17
26 27 28 291A12 1A131A11 GND
63
64
65
66
67
68
69
70
71
72
73
74
75
2A7
2B1
2B2
2A4
GND
2A5
2B8
2A6
VCC
2A3
2A9
2B10
GND
59
60
61
62
1B3
1B2
1B4
1B1
55
56
57
58
1B6
1B5
1B7
GND
51
52
53
54
1B9
GND
1B10
1B8
13
14
15
16
17
18
19
20
21
22
23
24
25
1A7
1A1
1A2
1A4
GND
1A5
1A8
1A6
VCC
1A3
1A9
1A10
GND
9
10
11
12
2A3
2A2
2A4
2A1
5
6
7
8
2A6
2A5
2A7
GND
1
2
3
4
2A9
GND
2A10
2A8
888990919293949596979899100
2B142CLKAB 2LEAB 2B18 2B17 2B16 GND2B15VCC 2OEAB 2B12 2B112B13
84858687
2OEBA 2LEBA2A18 2CLKBA
80818283
2A15 2A162A14 2A17
76777879
2A12 2A132A11 GND
2CEBA
38 39 40 41 42 43 44 45 46 47 48 49 502B15VCC 2LEAB 2CEAB 2B18 2B17 GND2B162LEBA 2OEAB 2B13 2B12 2B112B14
34 35 36 372A18 2OEBA
30 31 32 332A15 2A162A14 2A17
26 27 28 292A12 2A132A11 GND
63
64
65
66
67
68
69
70
72
71
73
74
75
1B12
1B18
1B17
1B15
GND
1B14
1B11
1B13
VCC
1B16
1B10
1B9
GND
59
60
61
62
2B3
2B2
2B4
2B1
55
56
57
58
2B6
2B5
2B7
GND
51
52
53
54
2B9
GND
2B10
2B8
13
14
15
16
17
18
19
20
21
22
23
24
25
2A7
2A1
2A2
2A4
GND
2A5
2A8
2A6
VCC
2A3
2A9
2A10
GND
9
10
11
12
1A16
1A17
1A15
1A18
5
6
7
8
1A13
1A14
1A12
GND
1
2
3
4
1A10
GND
1A9
1A11
888990919293949596979899100
1B51LEAB 1OEAB 1B1 1B1 1B3 GND1B4VCC 1CEAB 1B7 1B81B6
84858687
1CEBA 1OEBA1A1 1LEBA
80818283
1A4 1A31A5 1A2
76777879
1A7 1A61A8 GND
3250136-BIT UNIVERSAL BUS TRANSCEIVERSWITH 3-STATE OUTPUTS
3254336-BIT REGISTERED BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
See page 656
See page 654
128
Pin Assignments
1622403.3-V ABT 16-BIT BUFFERS/DRIVERSWITH 3-STATE OUTPUTS
1622413.3-V ABT 16-BIT BUFFERS/DRIVERSWITH 3-STATE OUTPUTS
16224416-BIT BUFFERS/DRIVERSWITH 3-STATE OUTPUTS
See page 661
See page 660
See page 659
2A1 3A23A12A31A4 2A4VCC 2A2 GND VCC 3OE4A4GND3A3 4A3GND 3A4 4A1 4A21A3GND1A1 1A22OE
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
3Y11Y4 VCC 2Y2 GND 2Y3 3Y22Y41Y3 2Y1 4Y43Y3 3Y4 VCC 4Y1 4Y2 GND 4OE4Y3GND
1 2 3 4
48 47 46 45 44 43 42 41
1Y1 1Y21OE GND
1OE
1 2 3 4 5 6 71Y1 GND1Y2 1Y3 VCC
2OE 1A1 GND1A2 1A3 VCC
81Y4
1A4
9
48
2Y1
2A1
10
47
2Y2
2A2
11
46
GND
GND
12
45
2Y3
2A3
13
44
2Y4
2A4
14
43
3Y1
3A1
15
42
3Y2
3A2
16
41
3Y3
3A3
17
40
3Y4
3A4
18
39
GND
GND
19
38
4Y1
4A1
20
37
4Y2
4A2
21
36
22
35
VCC
VCC
23
34
4Y3
4A3 4A4
24
33 32
GND
GND 3OE
31 30
4OE4Y4
2526272829
1OE
1 2 3 4 5 6 71Y1 GND1Y2 1Y3 VCC
2OE 1A1 GND1A2 1A3 VCC
81Y4
1A4
9
48
2Y1
2A1
10
47
2Y2
2A2
11
46
GND
GND
12
45
2Y3
2A3
13
44
2Y4
2A4
14
43
3Y1
3A1
15
42
3Y2
3A2
16
41
3Y3
3A3
17
40
3Y4
3A4
18
39
GND
GND
19
38
4Y1
4A1
20
37
4Y2
4A2
21
36
22
35
VCC
VCC
23
34
4Y3
4A3 4A4
24
33 32
GND
GND 3OE
31 30
4OE4Y4
2526272829
401038-STAGE SYNCHRONOUS DOWN COUNTERS
See page 658
VCC
CP
PE(SYNC)
MR
TC
TE P0 P1 P2 P3
1 2 3 4 5 6 7
16 15 14 13 12 11 10
8
9
GND
P7 P6 P5 P4 PL
129
Pin Assignments
16226012-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCHWITH 3-STATE OUTPUTS
16226812-BIT TO 24-BIT REGISTERED BUS EXCHANGERWITH 3-STATE OUTPUTS
See page 664
See page 666
2B7 2B122B11GND2B6 2B10VCC 2B8 2B9 GND 1B51B61B71B11 VCC1B12 1B10 1B9 1B82B5GNDCLKENA2 2B4OEB
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33CLKCLKENA1GND 1B4
32 31 30 29
A12A6 A7 A9 GND A10 VCCA11A5 A8 1B2 GND 1B3 CLKEN2B SEL1B1
9 10 11 12
56 55 54 53 52 51 50 49
A3 GNDA2 A4
5 6 7 82B1 VCC2B2 A1
1 2 3 4CLKEN1B 2B3OEA GND
OEA
1 2 3 4 5 6 7LE1B GND2B3 2B2 VCC
LEA2B GND2B4 2B5 VCC
82B1
2B6
9
48
A1
2B7
10
47
A2
2B8 2B9
11
46
A3
GND
12
45
GND GND
2B10
13
44
A4
2B11
14
43
A5
2B12
15
42
A6
1B12 1B11 1B10
16
41
A8
1B9
17
40
A9 A10 A11 A12
1B8 1B7
18
39
GND
GND
19
38
1B1
1B6
20
37
1B2
1B5
21
36
22
35
VCC
VCC
23
34
1B3
1B4 LEA1B
24
33 32
A7
GND
31 30
SEL
OE1BOE2B
LE2B
53
25
52
26
51
27
50
28
49545556 29
16224516-BIT TRANSCEIVERWITH 3-STATE OUTPUTS
See page 662
1A5 2A22A11A71A4 1A8VCC 1A6 GND VCC 2OE2A8GND2A3 2A7GND 2A4 2A5 2A61A3GND1A1 1A21OE
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
2B11B4 VCC 1B6 GND 1B7 2B21B81B3 1B5 2B82B3 2B4 VCC 2B5 2B6 GND 2DIR2B7GND
1 2 3 4
48 47 46 45 44 43 42 41
1B1 1B21DIR GND
16228016-BIT TO 32-BIT REGISTERED BUS EXCHANGERWITH BYTE MASKS AND 3-STATE OUTPUTS
See page 668
1 2 3 4 5 6 7GND GND1B72B7 VCC VCCVCCVCC
GNDVCC
82B6
9
72
C1
A15
10
71
C2
A14 A13 A12 A11
11
70
A1
GND
12
69
GND GND
2B81B8
13
68
A2
1B9 2B9
14
67
A3
2B10
15
66
A4
1B10 1B11 2B11 1B12 2B12
16
65
A6
17
64
A71B6 2B5 1B5
18
63
GND GND
GND
19
62
2B4
1B15
20
61
1B4 2B3 1B3 2B2 1B2 2B1 1B1 2D2 1D2 2D1 1D1
2B15 1B16
21
60
22
59
VCC
VCC 1B13 2B13 1B14 2B14 VCC
23
58
2B16
24
57 56
A5
GND VCC A16 VCCGND A9 A8A10 GND
55 5477
25
76
26
75
27
74
28
73787980 53
29
52
30
51
31
50
32
49
33
48
34
47
35
46
36
45
37
44
38
43
OE
39
42
SELCLK
DIR
40
41
130
Pin Assignments
1623441-BIT TO 4-BIT ADDRESS DRIVERWITH 3-STATE OUTPUTS
1623733.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHESWITH 3-STATE OUTPUTS
See page 676
See page 674
1D5 2D22D11D71D4 1D8VCC 1D6 GND VCC 2LE2D8GND2D3 2D7GND 2D4 2D5 2D61D3GND1D1 1D21LE
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
2Q11Q4 VCC 1Q6 GND 1Q7 2Q21Q81Q3 1Q5 2Q82Q3 2Q4 VCC 2Q5 2Q6 GND 2OE2Q7GND
1 2 3 4
48 47 46 45 44 43 42 41
1Q1 1Q21OE GND
OE1
1 2 3 4 5 6 71B1 GND1B2 1B3 VCC
8B1 GND8B2 8B3 VCC
81B4
8B4
9
48
1A
8A
10
47
2B1
7B1 7B2
11
46
2B2
GND
12
45
GND GND
7B3
13
44
2B3
7B4
14
43
3B4
7A
15
42
2A
6A 6B1 6B2
16
41
3B1
6B3
17
40
3B2 3B3 3B4 4A
6B4 5A
18
39
GND
GND
19
38
4B1
5B1
20
37
4B2
5B2
21
36
22
35
VCC
VCC
23
34
4B3
5B3 5B4
24
33 32
3A
GND
31 30
OE2
OE3OE4
4B4
53
25
52
26
51
27
50
28
49545556 29
16233416-BIT UNIVERSAL BUS DRIVERWITH 3-STATE OUTPUTS
See page 672
1 2 3 4 5 6 7NCY1 GNDY2 Y3 VCC
CLK A1 GNDA2 A3 VCC
8Y4
A4
9
48
Y5
A5
10
47
Y6
A6
11
46
GND
GND
12
45
Y7
A7
13
44
Y8
A8
14
43
Y9
A9
15
42
Y10
A10
16
41
Y11
A11
17
40
Y12
A12
18
39
GND
GND
19
38
Y13
A13
20
37
Y14
A14
21
36
Y15
A15
22
35
VCC
VCC
23
34
Y16
A16
24
33
LE
2532
GND
GND
2631 2730
OE
2829
16228218-BIT TO 36-BIT REGISTERED BUS EXCHANGERWITH 3-STATE OUTPUTS
See page 670
52 51
10VCC 2B6
91B7
6GNDVCC
1GND
422B9
52B8
4855 54 53 50 4980
82B7 2B51B6 2B31B4 VCC1B31B5 2B22B4 1B12B1 A1 A2 A3VCC VCC
31B9
7
47 42 41
38
45 44 43
4039
4662 61 5865 64 63 60 59 57 5672 71 6875 74 73 70 69 67 667879 77 76
373231 3534333029 36161512 1918171413 20 21 22 23 24 25 26 27 28111B8 GND GND GND A4 A5 A6 A7 A8 A9 CLKGND1B2 SEL
VCC 1B132B12GNDVCC GND 1B10 1B11 1B12 1B142B13 1B162B15 VCC2B162B14 1B171B15 2B181B18 A18 A17 A16VCC VCC2B10 2B11 GND GND GND A15 A14 A13 A12 A11 A10 OEGND2B17 DIR
NC – No internal connection
131
Pin Assignments
1623743.3-V ABT 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPSWITH 3-STATE OUTPUTS
1624604-TO-1 MULTIPLEXED/DEMULTIPLEXED REGISTERED TRANSCEIVERSWITH 3-STATE OUTPUTS
See page 678
See page 677
1D5 2D22D11D71D4 1D8VCC 1D6 GND VCC 2CLK2D8GND2D3 2D7GND 2D4 2D5 2D61D3GND1D1 1D21CLK
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
2Q11Q4 VCC 1Q6 GND 1Q7 2Q21Q81Q3 1Q5 2Q82Q3 2Q4 VCC 2Q5 2Q6 GND 2OE2Q7GND
1 2 3 4
48 47 46 45 44 43 42 41
1Q1 1Q21OE GND
1B3 2B42B3GND1B2 2B2VCC 1B4 2B1 GND 4B44B34B23B2 VCC3B1 3B3 3B4 4B11B1GNDOEB2 SEL0OEB1
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33OEB4OEB3GND SEL1
32 31 30 29
CLKENBACE_SEL0 CE_SEL1 4A GND CLKENAB VCCCLKENB2A 3A LEB4 GND OEA LEAB3 LEAB3LEB3
9 10 11 12
56 55 54 53 52 51 50 49
CLKAB GNDOEB 1A
5 6 7 8LEB2 VCCLEB1 CLKBA
1 2 3 4LEAB2 LEBALEAB1 GND
B4 B9B8GNDB3 B7VCC B5 B6 GND B17B16B15B11 VCCB10 B12 B13 B14B2GNDCLKAB B1GND
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33GNDCLKBAGND B18
32 31 30 29
A15A9 A10 A12 GND A13 VCCA14A8 A11 A17 GND A18 OEBA LEBAA16
9 10 11 12
56 55 54 53 52 51 50 49
A6 GNDA5 A7
5 6 7 8A3 VCCA2 A4
1 2 3 4LEAB A1OEAB GND
16250018-BIT UNIVERSAL BUS TRANSCEIVERWITH 3-STATE OUTPUTS
See page 680
1 2 3 4 5 6 7A18A1 GND A2 A3 VCC
CLKABGND B1 GND B2 B3 VCC
8A4
B4
9
48
A5
B5
10
47
A6
B6
11
46
GND
GND
12
45
A7
B7
13
44
A8
B8
14
43
A9
B9
15
42
A10
B10
16
41
A11
B11
17
40
A12
B12
18
39
GND
GND
19
38
A13
B13
20
37
A14
B14
21
36
A15
B15
22
35
VCC
VCC
23
34
A16
B16 B17
24
3353 32
GND
GND B18 CLKBA GND
54 3155 30
OEBAA17 LEBA
25
52
26
51
LEAB
27
50
OEAB
28
4956 29
16250118-BIT UNIVERSAL BUS TRANSCEIVERSWITH 3-STATE OUTPUTS
See page 682
132
Pin Assignments
16260118-BIT UNIVERSAL BUS TRANSCEIVERWITH 3-STATE OUTPUTS
1627213.3-V 20-BIT FLIP-FLOPWITH 3-STATE OUTPUTS
See page 690
See page 688
B4 B9B8GNDB3 B7VCC B5 B6 GND B17B16B15B11 VCCB10 B12 B13 B14B2GNDCLKAB B1CLKENAB
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33CLKENBACLKBAGND B18
32 31 30 29
A15A9 A10 A12 GND A13 VCCA14A8 A11 A17 GND A18 OEBA LEBAA16
9 10 11 12
56 55 54 53 52 51 50 49
A6 GNDA5 A7
5 6 7 8A3 VCCA2 A4
1 2 3 4LEAB A1OEAB GND
D5 D10D9GNDD4 D8VCC D6 D7 GND D18D17D16D12 VCCD11 D13 D14 D15D3GNDD1 D2CLK
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33CLKEND20GND D19
32 31 30 29
Q16Q10 Q11 Q13 GND Q14 VCCQ15Q9 Q12 Q18 GND Q19 Q20 NCQ17
9 10 11 12
56 55 54 53 52 51 50 49
Q7 GNDQ6 Q8
5 6 7 8Q4 VCCQ3 Q5
1 2 3 4Q1 Q2OE GND
B4 B9B8GNDB3 B7VCC B5 B6 GND B17B16B15B11 VCCB10 B12 B13 B14B2GNDCLKAB B1SEL
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33CLK2BACLK1BAGND B18
32 31 30 29
A15A9 A10 A12 GND A13 VCCA14A8 A11 A17 GND A18 OEBA CLKENBAA16
9 10 11 12
56 55 54 53 52 51 50 49
A6 GNDA5 A7
5 6 7 8A3 VCCA2 A4
1 2 3 4OEAB A1CLKENAB GND
1 2 3 4 5 6 71Y1 GND1Y2 1Y3 VCC
1A1 GND1A2 1A3 VCC
81Y4
1A4
9
48
1Y5
1A5
10
47
1Y6
1A6
11
46
GND
GND
12
45
1Y7
1A7
13
44
1Y8
1A8
14
43
2Y1
2A1
15
42
2Y2
2A2
16
41
2Y3
2A3
17
40
2Y4
2A4
18
39
GND
GND
19
38
2Y5
2A5
20
37
2Y6
2A6
21
36
2Y7
2A7
22
35
VCC
VCC
23
34
2Y8
2A8
24
33 2532
GND
GND
2631 2730
1OE1
1OE2
2OE1
2OE2
2829
16252516-BIT REGISTERED BUS TRANSCEIVERWITH 3-STATE OUTPUTS
1625413.3-V ABT 16-BIT BUFFERS/DRIVERSWITH 3-STATE OUTPUTS
See page 684
See page 686
NC – No internal connection
133
Pin Assignments
1628203.3-V 10-BIT FLIP-FLOP WITH DUAL OUTPUTSAND 3-STATE OUTPUTS
16282318-BIT BUS-INTERFACE FLIP-FLOPSWITH 3-STATE OUTPUTS
See page 692
See page 691
D3 NCD5GNDNC NCVCC NC D4 GND NCD9NCNC VCCD6 D7 NC D8D2GNDD1 NCCLK
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33NCNCGND D10
32 31 30 29
8Q25Q2 6Q1 7Q1 GND 7Q2 VCC8Q15Q1 6Q2 9Q2 GND 10Q1 10Q2 2OE9Q1
9 10 11 12
56 55 54 53 52 51 50 49
4Q1 GND3Q2 4Q2
5 6 7 82Q2 VCC2Q1 3Q1
1 2 3 41Q1 1Q21OE GND
1OE1CLR
1 2 3 4 5 6 72Q91Q1 GND 1Q2 1Q3 VCC
1CLKEN1CLK 1D1 GND 1D2 1D3 VCC
81Q4
1D4
9
48
1Q5
1D5
10
47
1Q6
1D6
11
46
GND
GND
12
45
1Q7
1D7
13
44
1Q8
1D8
14
43
1Q9
1D9
15
42
2Q1
2D1
16
41
2Q2
2D2
17
40
2Q3
2D3
18
39
GND
GND
19
38
2Q4
2D4
20
37
2Q5
2D5
21
36
2Q6
2D6
22
35
VCC
VCC
23
34
2Q7
2D7 2D8
24
3353 32
GND
GND 2D9 2CLKEN 2CLK
54 3155 30
2OE 2CLR2Q8
25
52
26
51
27
50
28
4956 29
16282518-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
See page 693
1A5 GND1A9GND1A4 1A8VCC 1A6 1A7 GND 2A72A62A52A1 VCCGND 2A2 2A3 2A41A3GND1A1 1A21OE2
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 332OE22A9GND 2A8
32 31 30 29
2Y5GND GND 2Y2 GND 2Y3 VCC2Y41Y9 2Y1 2Y7 GND 2Y8 2Y9 2OE12Y6
9 10 11 12
56 55 54 53 52 51 50 49
1Y7 GND1Y6 1Y8
5 6 7 81Y4 VCC1Y3 1Y5
1 2 3 41Y1 1Y21OE1 GND
16282720-BIT BUS BUFFERS/DRIVERSWITH 3-STATE OUTPUTS
See page 694
1A5 1A101A9GND1A4 1A8VCC 1A6 1A7 GND 2A82A72A62A2 VCC2A1 2A3 2A4 2A51A3GND1A1 1A21OE2
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 332OE22A10GNA 2A9
32 31 30 29
2Y61Y10 2Y1 2Y3 GNA 2Y4 VCC2Y51Y9 2Y2 2Y8 GNA 2Y9 2Y10 2OE12Y7
9 10 11 12
56 55 54 53 52 51 50 49
1Y7 GNA1Y6 1Y8
5 6 7 81Y4 VCC1Y3 1Y5
1 2 3 41Y1 1Y21OE1 GNA
NC – No internal connection
134
Pin Assignments
16283416283518-BIT UNIVERSAL BUS DRIVERWITH 3-STATE OUTPUTS
See page 698, 699
1 2 3 4 5 6 7Y18Y1 GND Y2 Y3 VCC
NCGND A1 GND A2 A3 VCC
8Y4
A4
9
48
Y5
A5
10
47
Y6
A6
11
46
GND
GND
12
45
Y7
A7
13
44
Y8
A8
14
43
Y9
A9
15
42
Y10
A10
16
41
Y11
A11
17
40
Y12
A12
18
39
GND
GND
19
38
Y13
A13
20
37
Y14
A14
21
36
Y15
A15
22
35
VCC
VCC
23
34
Y16
A16 A17
24
3353 32
GND
GND A18 CLK GND
54 3155 30
OEY17 LE
25
52
26
51
NC
27
50
NC
28
4956 29
1628301-BIT to 2-BIT ADDRESS DRIVERWITH 3-STATE OUTPUTS
1628311-BIT TO 4-BIT ADDRESS REGISTER/DRIVERWITH 3-STATE OUTPUTS
1628321-BIT TO 4-BIT ADDRESS REGISTER/DRIVERWITH 3-STATE OUTPUTS
See page 697
See page 696
See page 695
1 2 3 4 5 6 71Y1GND1Y2 A5 A6VCC GND
1Y3 GND2Y3 1Y4 VCC
8A12
2Y4
9
80
A1
1Y5
10
79
A2
2Y5
11
78
GND
GND
12
77
A3
1Y6
13
76
A4
2Y6
14
75
2Y1
2Y7
15
74
2Y2
1Y7
16
73
A7
2Y9
17
72
A8
1Y8 2Y8
18
71
GND GND
GND
19
70
A9
2Y11
20
69
A13 A14 GNDA15 A16 GNDA17 A18 2Y172Y18 1Y171Y18
1Y9
21
68
A10
1Y10
22
67
VCC VCC VCC
VCC VCC VCC
23
66
A11
2Y10
24
65 57
25
56
26
55
27
54
28
53
29
52
30
51
31
50
32
49
33
48
34
47
35
46
36
45
37
44
38
43
39
42
40
4164
GND
GND GND GND GND GND
5863 5962
OE2OE1
1Y11 2Y121Y12 2Y131Y13 2Y141Y14 2Y151Y15 2Y161Y16
6061
1 2 3 4 5 6 71Y1GND3Y1 NC A3VCC GND
1Y2 GND2Y2 3Y2 VCC
8A6
4Y2
9
80
NC
1Y3
10
79
A1
2Y3
11
78
GND
GND
12
77
NC
3Y3
13
76
A2
4Y3
14
75
2Y1
2Y4
15
74
4Y1
1Y4
16
73
NC
2Y5
17
72
A4
3Y4 4Y4
18
71
GND GND
GND
19
70
CLK
2Y6
20
69
A7 NC GNDA8 NC GNDA9 NC 2Y94Y9 1Y93Y9
1Y5
21
68
SEL
3Y5
22
67
VCC VCC VCC
VCC VCC VCC
23
66
A5
4Y5
24
65 57
25
56
26
55
27
54
28
53
29
52
30
51
31
50
32
49
33
48
34
47
35
46
36
45
37
44
38
43
39
42
40
4164
GND
GND GND GND GND GND
5863 5962
OE2OE1
1Y6 4Y63Y6 2Y71Y7 4Y73Y7 2Y81Y8 4Y83Y8
6061
1 2 3 4 5 6 71Y1GND3Y1 A3VCC GND
1Y2 GND2Y2 3Y2 VCC
8A6
4Y2
9
1Y3
10A1
2Y3
11GND
GND
12
3Y3
13A2
4Y3
142Y1
2Y4
154Y1
1Y4
16NC
2Y5
17A4
3Y4 4Y4
18GND GND
GND
19CLK
2Y6
20A7GND GND 2Y74Y7 1Y73Y7
1Y5
21SEL
3Y5
22VCC VCC VCC
VCC VCCVCC
23A5
4Y5
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31
50
32
49 3348 3447 3546 3645 3744 3843 3942 404164
GND
GND GND GND GND GND
5863 5962
OE2OE1
1Y6 4Y63Y6
6061
NC – No internal connection
NC – No internal connection
135
Pin Assignments
16283620-BIT UNIVERSAL BUS DRIVERWITH 3-STATE OUTPUTS
16284120-BIT BUS-INTERFACE D-TYPE LATCHWITH 3-STATE OUTPUTS
16424516-BIT TRANSCEIVER AND 3.3-V TO 5-V SHIFTERWITH 3-STATE OUTPUTS
See page 700
See page 701
See page 702
1A5 2A22A11A71A4 1A8(3.3V)VCCA 1A6 GND (3.3V)VCCA 2OE2A8GND2A3 2A7GND 2A4 2A5 2A61A3GND1A1 1A21OE
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
2B11B4 (5V)VCCB 1B6 GND 1B7 2B21B81B3 1B5 2B82B3 2B4 (5V)VCCB 2B5 2B6 GND 2DIR2B7GND
1 2 3 4
48 47 46 45 44 43 42 41
1B1 1B21DIR GND
1 2 3 4 5 6 7Y18Y1 GNDY2 Y3 VCC
CLK A1 GNDA2 A3 VCC
8Y4
A4
9
48
Y5
A5
10
47
Y6
A6
11
46
GND
GND
12
45
Y7
A7
13
44
Y8
A8
14
43
Y9
A9
15
42
Y10
A10
16
41
Y11
A11
17
40
Y12
A12
18
39
GND
GND
19
38
Y13
A13
20
37
Y14
A14
21
36
Y15
A15
22
35
VCC
VCC
23
34
Y16
A16 A17 A18
24
3353 32
GND
GND A19 A20
54 3155 30
OE Y17 Y20
LE
25
52
26
51
NC
27
50
Y19
28
4956 29
1 2 3 4 5 6 72Q81Q1 GND1Q2 1Q3 VCC
1LE 1D1 GND1D2 1D3 VCC
81Q4
1D4
9
48
1Q5
1D5
10
47
1Q6
1D6
11
46
GND
GND
12
45
1Q7
1D7
13
44
1Q8
1D8
14
43
1Q9
1D9
15
42
1Q10
1D10
16
41
2Q1
2D1
17
40
2Q2
2D2
18
39
GND
GND
19
38
2Q3
2D3
20
37
2Q4
2D4
21
36
2Q5
2D5
22
35
VCC
VCC
23
34
2Q6
2D6 2D7 2D8
24
3353 32
GND
GND 2D9 2D10
54 3155 30
1OE 2OE2Q7 2Q10
2LE
25
52
26
51
27
50
2Q9
28
4956 29
NC – No internal connection
136
Pin Assignments
3223743.3-V ABT 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPWITH 3-STATE OUTPUTS
See page 703
terminal assignments
1 2 3 4 5 6
A 1Q2 1Q1 1OE 1CLK 1D1 1D2
B 1Q4 1Q3 GND GND 1D3 1D4
C 1Q6 1Q5 VCC VCC 1D5 1D6
D 1Q8 1Q7 GND GND 1D7 1D8
E 2Q2 2Q1 GND GND 2D1 2D2
F 2Q4 2Q3 VCC VCC 2D3 2D4
G 2Q6 2Q6 GND GND 2D5 2D6
H 2Q7 2Q8 2OE 2CLK 2D8 2D7
J 3Q2 3Q1 3OE 3CLK 3D1 3D2
K 3Q4 3Q3 GND GND 3D3 3D4
L 3Q6 3Q5 VCC VCC 3D5 3D6
M 3Q8 3Q7 GND GND 3D7 3D8
N 4Q2 4Q1 GND GND 4D1 4D2
P 4Q4 4Q3 VCC VCC 4D3 4D4
R 4Q6 4Q5 GND GND 4D5 4D6
T 4Q7 4Q8 4OE 4CLK 4D8 4D7
NC – No internal connection
GKE PACKAGE(TOP VIEW)
J
H
G
F
E
D
C
B
A
21 3 4 65
P
N
M
L
K
T
R
FUNCTION
AND
ELECTRICAL
CHARACTERISTICS
139
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
00QUADRUPLE 2-INPUTPOSITIVE-NAND GATES
Y = A•B 74AC11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series) 74ACT11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series)
A
BY
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS S ALS AS F SN74HC
CD74HC
SN74HCT
CD74HCT
AC11
SN74AC
CD74AC
ACT11 UNIT
ICC MAX 22 4.4 36 3 17.4 10.2 0.02 0.04 0.02 0.04 0.04 0.02 0.08 0.04 mAIOH MAX -0.4 -0.4 -1 -0.4 -2 -1 -4 -4 -4 -4 -24 -24 -24 -24 mAIOL MAX 16 8 20 8 20 20 4 4 4 4 24 24 24 24 mA
PARAMETER MAX or MIN SN74ACT
CD74ACT AHC AHCT LV
3VLV5V
LVC3V
ALVC3V UNIT
ICC MAX 0.02 0.08 0.02 0.02 - 0.02 0.01 0.01 mAIOH MAX -24 -24 -8 -8 -6 -12 -24 -24 mAIOL MAX 24 24 8 8 6 12 24 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN TTL LS S ALS AS F SN74HC
CD74HC
SN74HCT
CD74HCT
AC11
SN74AC
CD74AC
ACT11
tPLH A or B Y MAX 22 15 4.5 11 4.5 6 23 27 25 30 7.4 8.5 7.3 12.3tPHL A or B Y MAX 15 15 5 8 4 5.3 23 27 25 30 6.8 7 7.3 8.8
PARAMETER INPUT OUTPUT MAX or MIN SN74ACT
CD74ACT AHC AHCT LV
3VLV5V
LVC3V
ALVC3V
tPLH A or B Y MAX 9.5 10.8 8.5 9 13 8.5 4.3 3tPHL A or B Y MAX 8 13.2 8.5 9 13 8.5 4.3 3UNIT:ns
140
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
01QUADRUPLE 2-INPUTPOSITIVE-NAND GATESWITH OPEN-COLLECTOROUTPUTS
Y = A•B
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS ALS HC UNIT
ICC MAX 22 4.4 3 0.02 mAVOH MAX 5.5 5.5 5.5 VCC VIOL MAX 16 8 8 4 mA
4A
4B4Y
3A
3B3Y
2A
2B2Y
1Y1B
1A
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN TTL LS ALS HC
tPLH A or B Y MAX 55 32 54 31tPHL A or B Y MAX 15 28 28 25UNIT:ns
141
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
02QUADRUPLE 2-INPUTPOSITIVE-NOR GATES
Y = A + B 74AC11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series) 74ACT11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series)
A
BY
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS S ALS AS F SN74HC
CD74HC
SN74HCT
CD74HCT
AC11
CD74AC
ACT11 UNIT
ICC MAX 27 5.4 45 4 20.1 13 0.02 0.04 0.02 0.04 0.04 0.08 0.04 mAIOH MAX -0.4 -0.4 -1 -0.4 -2 -1 -4 -4 -4 -4 -24 -24 -24 mAIOL MAX 16 8 20 8 20 20 4 4 4 4 24 24 24 mA
PARAMETER MAX or MIN CD74ACT AHC AHCT LV
3VLV5V
LVC3V UNIT
ICC MAX 0.08 0.02 0.02 - 0.02 0.01 mAIOH MAX -24 -8 -8 -6 -12 -24 mAIOL MAX 24 8 8 6 12 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN TTL LS S ALS AS F SN74HC
CD74HC
SN74HCT
CD74HCT
AC11
CD74AC
ACT11
tPLH A or B Y MAX 22 15 5.5 12 4.5 6.5 23 27 25 32 6.9 11.5 10.6tPHL A or B Y MAX 15 15 5.5 10 4.5 5.3 23 27 25 32 6.4 11.5 8.7
PARAMETER INPUT OUTPUT MAX or MIN CD74ACT AHC AHCT LV
3VLV5V
LVC3V
tPLH A or B Y MAX 12.2 8.5 8.5 13 8.5 4.4tPHL A or B Y MAX 12.2 8.5 8.5 13 8.5 4.4UNIT: ns
142
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
03QUADRUPLE 2-INPUTPOSITIVE-NAND GATESWITH OPEN-COLLECTOROUTPUTS
Y = A•B
A
BY
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS S ALS SN74HC
CD74HC
CD74HCT UNIT
ICC MAX 22 4.4 36 4 0.02 0.04 0.04 mAVOH MAX 5.5 8 5.5 8 0.05 VCC VCC VIOL MAX 16 0.1 20 0.1 4 4 4 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN TTL LS S ALS SN74HC
CD74HC
CD74HCT
tPLH A or B Y MAX 45 32 7.5 50 31 30 36tPHL A or B Y MAX 15 28 7 13 25 30 36UNIT: ns
143
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
04HEXINVERTERS
Y = A 74AC11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series) 74ACT11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series)
YA
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS S ALS AS F SN74HC
CD74HC
SN74HCT
CD74HCT
AC11
SN74AC
CD74AC
ACT11 UNIT
ICC MAX 33 6.6 54 4.2 26.3 15.3 0.02 0.04 0.02 0.04 0.04 0.02 0.08 0.04 mAIOH MAX -0.4 -0.4 -1 -0.4 -2 -1 -4 -4 -4 -4 -24 -24 -24 -24 mAIOL MAX 16 8 20 8 20 20 4 4 4 4 24 24 24 24 mA
PARAMETER MAX or MIN SN74ACT
CD74ACT AHC AHCT LV
3VLV5V
LVC3V
ALVC3V UNIT
ICC MAX 0.02 0.08 0.02 0.02 - 0.02 0.01 0.01 mAIOH MAX -24 -24 -8 -8 -6 -12 -24 -24 mAIOL MAX 24 24 8 8 6 12 24 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN TTL LS S ALS AS F SN74HC
CD74HC
SN74HCT
CD74HCT
AC11
SN74AC
CD74AC
ACT11
tPLH A or B Y MAX 22 15 4.5 11 5 6 24 26 25 29 7.1 7.5 6.5 9.7tPHL A or B Y MAX 15 15 5 8 4 5.3 24 26 25 29 6 7 6.5 9.6
PARAMETER INPUT OUTPUT MAX or MIN SN74ACT
CD74ACT AHC AHCT LV
3VLV5V
LVC3V
ALVC3V
tPLH A or B Y MAX 9 9.3 8.5 8.5 12 8.5 4.5 2.8tPHL A or B Y MAX 8.5 9.3 8.5 8.5 12 8.5 4.5 2.8UNIT: ns
05HEX INVERTERSWITH OPEN-COLLECTOROUTPUTS
Y = A
YA
144
Logic Diagram
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
U04HEXINVERTERS
Y = A Unbuffered Output
YA
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN SN74HC
CD74HC AHC LV
3VLV5V
LVC3V UNIT
ICC MAX 0.02 0.04 0.02 - 0.02 0.01 mAIOH MAX -4 -4 -8 -6 -12 -24 mAIOL MAX 4 4 8 6 12 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN SN74HC
CD74HC AHC LV
3VLV5V
LVC3V
tPLH A or B Y MAX 20 21 8 13 8 3.8tPHL A or B Y MAX 20 21 8 13 8 3.8UNIT: ns
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS S ALS SN74HC
CD74AC
CD74ACT AHC LV
3VLV5V UNIT
ICC MAX 33 6.6 54 4.2 0.02 0.08 0.08 0.02 - 0.02 mAIOH MAX - - - - - -24 -24 - - - mAVOH MAX 5.5 5.5 5.5 5.5 5.5 5.5 5.5 Vcc 5.5 5.5 VIOL MAX 16 8 20 8 4 24 24 8 6 12 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN TTL LS S ALS SN74HC
CD74AC
CD74ACT AHC LV
3VLV5V
tPLH A or B Y MAX 55 32 7.5 54 29 - - - 12 8.5tPHL A or B Y MAX 15 28 7 14 21 - - - 12 8.5tPLZ A Y MAX - - - - - 8.2 9.3 8.5 - -tPZL A Y MAX - - - - - 6.5 10.8 8.5 - -UNIT: ns
06HEX INVERTER BUFFERS/DRIVERSWITH OPEN-COLLECTORHIGH-VOLTAGE OUTPUTS
Y = A
A Y
145 145
Logic Diagram
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS LV3V
LV5V
LVC3V UNIT
ICC MAX 51 60 - 0.02 0.01 mAIOH MAX 0.25 0.25 - 0.0025 - mAVOH MAX 30 30 5.5 5.5 5.5 VIOL MAX 40 40 8 16 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN TTL LS LV3V
LV5V
LVC3V
tPLH A or B Y MAX 15 15 12 8.5 3.7tPHL A or B Y MAX 23 20 12 8.5 3.7UNIT: ns
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS LV3V
LV5V
LVC3V UNIT
ICC MAX 41 45 - 0.02 0.01 mAIOH MAX 0.25 0.25 - 0.0025 - mAVOH MAX 30 30 5.5 5.5 5.5 VIOL MAX 40 40 8 16 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN TTL LS LV3V
LV5V
LVC3V
tPLH A or B Y MAX 15 10 12 8.5 2.9tPHL A or B Y MAX 26 30 12 8.5 2.9UNIT: ns
07HEX BUFFERS/DRIVERSWITH OPEN-COLLECTORHIGH-VOLTAGE OUTPUTS
Y = A
A Y
146
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
A
BY
08QUADRUPLE 2-INPUTPOSITIVE-AND GATES
Y = A•B 74AC11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series) 74ACT11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series)
146
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS S ALS AS F SN74HC
CD74HC
SN74HCT
CD74HCT
AC11
SN74AC
CD74AC
ACT11 UNIT
ICC MAX 33 8.8 57 4 24 12.9 0.02 0.04 0.02 0.04 0.04 0.02 0.08 0.04 mAIOH MAX -0.8 -0.4 -1 -0.4 -2 -1 -4 -4 -4 -4 -24 -24 -24 -24 mAIOL MAX 16 8 20 8 20 20 4 4 4 4 24 24 24 24 mA
PARAMETER MAX or MIN SN74ACT
CD74ACT AHC AHCT LV
3VLV5V LVC ALVC UNIT
ICC MAX 0.02 0.08 0.02 0.02 - 0.02 0.01 0.01 mAIOH MAX -24 -24 -8 -8 -6 -12 -24 -24 mAIOL MAX 24 24 8 8 6 12 24 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN TTL LS S ALS AS F SN74HC
CD74HC
SN74HCT
CD74HCT
AC11
SN74AC
CD74AC
ACT11
tPLH A or B Y MAX 27 15 7 14 5.5 6.6 25 27 30 38 6.9 8.5 8.7 9tPHL A or B Y MAX 19 20 7.5 10 5.5 6.3 25 27 30 38 6.5 7.5 8.7 8.2
PARAMETER INPUT OUTPUT MAX or MIN SN74ACT
CD74ACT AHC AHCT LV
3VLV5V LVC ALVC
tPLH A or B Y MAX 10 12.9 9 9 14 9 4.1 2.9tPHL A or B Y MAX 10 12.9 9 9 14 9 4.1 2.9UNIT: ns
147
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS S ALS F SN74HC UNIT
ICC MAX 33 8.8 57 4.2 26.3 15.3 mAIOH MAX - 0.1 0.25 0.1 - - mAVOH MAX 5.5 5.5 5.5 5.5 5.5 VCC mAIOL MAX 16 8 20 8 20 4 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN TTL LS S ALS F SN74HC
tPLH A or B Y MAX 32 35 10 54 9.6 31tPHL A or B Y MAX 24 35 10 15 4.8 25UNIT: ns
09QUADRUPLE 2-INPUTPOSITIVE-AND GATESWITH OPEN-COLLECTOROUTPUTS
Y = A•B
11A
21B
1Y3
42A
52B
2Y6
93A
103B
3Y8
124A
134B
4Y11
148
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
10TRIPLE 3-INPUTPOSITIVE-NAND GATES
Y = A•B•C 74AC11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series) 74ACT11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series)
A
CYB
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS S ALS AS F SN74HC
CD74HC
SN74HCT
CD74HCT
AC11
SN74AC
CD74AC
ACT11 UNIT
ICC MAX 16.5 3.3 27 2.2 13 7.7 0.02 0.04 0.02 0.04 0.04 0.02 0.08 0.04 mAIOH MAX -0.4 -0.4 -1 -0.4 -2 -1 -4 -4 -4 -4 -24 -24 -24 -24 mAIOL MAX 16 8 20 8 20 20 4 4 4 4 24 24 24 24 mA
PARAMETER MAX or MIN SN74ACT
CD74ACT
LV3V
LV5V
LVC3V ALVC UNIT
ICC MAX 0.04 0.08 - 0.02 0.01 0.01 mAIOH MAX -24 -24 -6 -12 -24 -24 mAIOL MAX 24 24 6 12 24 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN TTL LS S ALS AS F SN74HC
CD74HC
SN74HCT
CD74HCT
AC11
SN74AC
CD74AC
ACT11
tPLH A, B or C Y MAX 22 15 4.5 11 4.5 6 24 30 19 36 6.7 8 12.2 8.9tPHL A, B or C Y MAX 15 15 5 10 4.5 5.3 24 30 19 36 7 6.5 12.2 8.2
PARAMETER INPUT OUTPUT MAX or MIN SN74ACT
CD74ACT
LV3V
LV5V
LVC3V ALVC
tPLH A, B or C Y MAX 10 - 13.5 9 4.9 3tPHL A, B or C Y MAX 9.5 13.5 13.5 9 4.9 3UNIT: ns
149
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
11TRIPLE 3-INPUTPOSITIVE-AND GATES
Y = A•B•C 74AC11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series) 74ACT11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series)
A
CYB
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LS S ALS AS F SN74HC
CD74HC
SN74HCT
CD74HCT
AC11
SN74AC
ACT11
SN74ACT
LV3V
LV5V UNIT
ICC MAX 6.6 42 3 18 9.7 0.02 0.04 0.02 0.04 0.04 0.02 0.04 0.02 - 0.02 mAIOH MAX -0.4 -1 -0.4 -2 -1 -4 -4 -4 -4 -24 -24 -24 -24 -6 -12 mAIOL MAX 8 20 8 20 20 4 4 4 4 24 24 24 24 6 12 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN LS S ALS AS F SN74HC
CD74HC
SN74HCT
CD74HCT
AC11
SN74AC
ACT11
SN74ACT
tPLH A, B or C Y MAX 15 7 13 6 6.6 25 30 21 42 6.5 8.5 9.6 10.5tPHL A, B or C Y MAX 20 7.5 10 5.5 6.5 25 30 21 42 6.9 7.5 8.7 10.5
PARAMETER INPUT OUTPUT MAX or MIN LV3V
LV5V
tPLH A, B or C Y MAX 14 9tPHL A, B or C Y MAX 14 9UNIT: ns
150
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
14HEX SCHMITT-TRIGGERINVERTERS
Y = A 74AC11xxx: Product Available in Reduced-Noise
Advanced CMOS (Series) 74ACT11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series)
YA
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS SN74HC
CD74HC
SN74HCT
CD74HCT
SN74AC
CD74AC
SN74ACT
CD74ACT AHC AHCT UNIT
ICC MAX 60 21 0.02 0.04 0.02 0.04 0.02 0.08 0.02 0.08 0.02 0.02 mAIOH MAX -0.8 -0.4 -4 -4 -4 -4 -24 -24 -24 -24 -8 -8 mAIOL MAX 16 8 4 4 4 4 24 24 24 24 8 8 mA
PARAMETER MAX or MIN LV3V
LV5V
LVC3V
ALVC3V UNIT
ICC MAX - 0.02 0.01 0.01 mAIOH MAX -6 -12 -24 -24 mAIOL MAX 6 12 24 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN TTL LS SN74HC
CD74HC
SN74HCT
CD74HCT
SN74AC
CD74AC
SN74ACT
CD74ACT
tPLH A or B Y MAX 22 22 31 41 40 57 11 10.5 12.5 14.5tPHL A or B Y MAX 22 22 31 41 40 57 9.5 10.5 11 9.5
PARAMETER INPUT OUTPUT MAX or MIN AHC AHCT LV3V
LV5V
LVC3V
ALVC3V
tPLH A or B Y MAX 12 9 18.5 12 6.4 3.4tPHL A or B Y MAX 12 9 18.5 12 6.4 3.4UNIT: ns
151
Logic Diagram
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
16HEX INVERTERBUFFERS/DRIVERSWITH OPEN-COLLECTORHIGH-VOLTAGE OUTPUTS
Y = A
17HEX BUFFERS/DRIVERSWITH OPEN-COLLECTORHIGH-VOLTAGE OUTPUTS
Y = A
1A
2A
3A
4A
5A
6A
1Y
2Y
3Y
4Y
5Y
6Y
1
3
5
9
11
13
2
4
6
8
10
12
A Y
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL UNIT
ICC MAX 51 mAVOH MAX 15 VIOL MAX 40 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN TTL
tPLH A Y MAX 15tPHL A Y MAX 23UNIT: ns
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL UNIT
ICC MAX 41 6.6VOH MAX 15 VIOL MAX 40 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN TTL
tPLH A Y MAX 15tPHL A Y MAX 26UNIT: ns
152
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
19HEX SCHMITT-TRIGGERINVERTERS
Y = A P-N-P Input Reduce System Loading
(IIL = -0.05mA MAX) Excellent Noise Immunity with Typical
Hysteresis of 0.8V
1A
2A
3A
4A
5A
6A
1Y
2Y
3Y
4Y
5Y
6Y
1
3
5
9
11
13
2
4
6
8
10
12
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LS UNIT
ICC MAX 30 mAIOH MAX -0.4 mAIOL MAX 8 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN LS
tPLH A or B Y MAX 20tPHL A or B Y MAX 30UNIT: ns
153
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
20DUAL 4-INPUTPOSITIVE-NANDGATES
Y = A•B•C•D 74AC11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series) 74ACT11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series)
1A1Y1B
1C1D
2A2Y2B
2C2D
1245
9101213
6
8
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS S ALS AS F SN74HC
CD74HC
CD74HCT
AC11
CD74AC
ACT11
CD74ACT
LV3V
LV5V UNIT
ICC MAX 11 2.2 18 1.5 8.7 5.1 0.02 0.04 0.04 0.04 0.08 0.04 0.08 - 0.02 mAIOH MAX -0.4 -0.4 -1 -0.4 -2 -1 -4 -4 -4 -24 -24 -24 -24 -6 -12 mAIOL MAX 16 8 20 8 20 20 4 4 4 24 24 24 24 6 12 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN TTL LS S ALS AS F SN74HC
CD74HC
CD74HCT
AC11
CD74AC
ACT11
CD74ACT
tPLH A, B, C or D Y MAX 22 15 4.5 11 5 6 28 30 42 6.7 12.2 9.1 13.5tPHL A, B, C or D Y MAX 15 15 5 10 4.5 5.3 28 30 42 7.3 12.2 9.2 13.5
PARAMETER INPUT OUTPUT MAX or MIN LV3V
LV5V
tPLH A, B, C or D Y MAX 11.5 8tPHL A, B, C or D Y MAX 11.5 8UNIT: ns
154
Logic Diagram
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
21DUAL 4-INPUTPOSITIVE-ANDGATES
Y = A•B•C•D 74AC11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series) 74ACT11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series)
25DUAL 4-INPUTPOSITIVE-NOR GATESWITH STROBE
Y = G (A + B + C + D)
1A1Y1B
1C1D
2A2Y2B
2C2D
1245
9101213
6
8
A
OUTPUTY
GATE 1 OFSN5423/SN7423
ONLY
B
C
D
GX X
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LS ALS AS F SN74HC
CD74HC
CD74HCT
AC11
ACT11
LV3V
LV5V UNIT
ICC MAX 4.4 2.3 12 7.3 0.02 0.04 0.04 0.04 0.04 - 0.02 mAIOH MAX -0.4 -0.4 -2 -1 -4 -4 -4 -24 -24 -6 -12 mAIOL MAX 8 8 20 20 4 4 4 24 24 6 12 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN LS ALS AS F SN74HC
CD74HC
CD74HCT
AC11
ACT11
LV3V
LV5V
tPLH A, B, C or D Y MAX 15 15 6 5.3 28 33 41 8.8 9.8 12 6tPHL A, B, C or D Y MAX 20 10 6 5.5 28 33 41 6.9 8.9 12 8UNIT: ns
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL UNIT
ICC MAX 19 mAIOH MAX -0.8 mAIOL MAX 16 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN TTL
tPLH A or B Y MAX 22tPHL A or B Y MAX 15UNIT: ns
155
Logic Diagram
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
26QUADRUPLE 2-INPUTHIGH-VOLTAGE INTERFACEPOSITIVE-NAND GATES
Y = AB
27TRIPLE 3-INPUTPOSITIVE-NOR GATES
Y = A + B + C 74AC11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series) 74ACT11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series)
1Y3
11A
21B
2Y6
42A
52B
3Y8
93A
103B
4Y11
124A
134B
A
CYB
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS UNIT
ICC MAX 22 4.4 mAVOH MAX 15 15 VIOL MAX 16 8 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN TTL LS
tPLH A or B Y MAX 24 32tPHL A or B Y MAX 17 28UNIT: ns
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS ALS AS F SN74HC
CD74HC
CD74HCT
AC11
ACT11
LV3V
LV5V UNIT
ICC MAX 26 6.8 4 17.1 12 0.02 0.04 0.04 0.04 0.04 - 0.02 mAIOH MAX -0.8 -0.4 -0.4 -2 -1 -4 -4 -4 -24 -24 -6 -12 mAIOL MAX 16 8 8 20 20 4 4 4 24 24 6 12 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN TTL LS ALS AS F SN74HC
CD74HC
CD74HCT
AC11
ACT11
LV3V
LV5V
tPLH A, B or C Y MAX 15 15 15 5.5 5.5 23 29 35 7.7 10.1 14 9tPHL A, B or C Y MAX 11 15 9 4.5 4.5 23 29 35 8.1 9.4 14 9UNIT: ns
156
Logic Diagram
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
31DELAY ELEMENTS
Delay Elements for Generating Delay Line Inverting and Non-inverting Elements Buffer NAND Elements Rated at IOL of 12/24mA P-N-P Inputs Reduce Fan-In (IIL = -0.2mA MAX) Worst Case MIN/MAX Delays Guaranteed Across
Temperature and VCC Range
308-INPUTPOSITIVE-NANDGATES
Y = A•B•C•D•E•F•G•H 74AC11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series) 74ACT11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series)
Y8
1A
2B
3C
4D
5E
6F
11G
12H
Y1A1
Y2A2
A5
A6
A3
B3Y3
A4
B4Y4
Y5
Y6
(2)(1)
(4)(3)
(13)
(15)
(5)
(6)(7)
(10)
(11)(9)
(12)
(14)
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS S ALS AS F SN74HC
CD74HC
CD74HCT
AC11
ACT11 UNIT
ICC MAX 6 1.1 10 0.9 4.9 4 0.02 0.04 0.04 0.04 0.04 mAIOH MAX -0.4 -0.4 -1 -0.4 -2 -1 -4 -4 -4 -24 -24 mAIOL MAX 16 8 20 8 20 20 4 4 4 24 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN TTL LS S ALS AS F SN74HC
CD74HC
CD74HCT
AC11
ACT11
tPLH A thru H Y MAX 22 15 6 10 5 5.5 33 39 42 7.2 8.5tPHL A thru H Y MAX 15 20 7 12 4.5 5 33 39 42 7.4 8.7UNIT: ns
RECOMMENDED RECOMMENDED OPERATING CONDITIONS
MAX or MIN LS UNIT
ICC MAX 20 mAY3, Y4 outputs MAX -1.2 mAAll other outputs MAX -0.4 mAY3, Y4 outputs MAX 24 mAAll other outputs MAX 8 mA
IOH
PARAMETER
IOL
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN LS
tPLH 65tPHL 45tPLH 80tPHL 95tPLH A3, B3 15tPHL A4, Y4 15UNIT: ns
MAX
MAX
A1, A6
A2, A5
Y1, Y6
Y2, Y5
Y3, Y4
MAX
157
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
32QUADRUPLE 2-INPUTPOSITIVE-OR GATES
Y = A + B
A
BY
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS S ALS AS F SN74HC
CD74HC
SN74HCT
CD74HCT
AC11
SN74AC
CD74AC
ACT11 UNIT
ICC MAX 38 9.8 68 4.9 26.6 15.5 0.02 0.04 0.02 0.04 0.04 0.02 0.08 0.04 mAIOH MAX -0.8 -0.4 -1 -0.4 -2 -1 -4 -4 -4 -4 -24 -24 -24 -24 mAIOL MAX 16 8 20 8 20 20 4 4 4 4 24 24 24 24 mA
PARAMETER MAX or MIN SN74ACT
CD74ACT AHC AHCT LV
3VLV5V
LVC3V ALVC UNIT
ICC MAX 0.02 0.08 0.02 0.02 0.02 0.02 0.01 0.01 mAIOH MAX -24 -24 -8 -8 -6 -12 -24 -24 mAIOL MAX 24 24 8 8 6 12 24 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN TTL LS S ALS AS F SN74HC
CD74HC
SN74HCT
CD74HCT
AC11
SN74AC
tPLH A or B Y MAX 15 22 7 14 5.8 6.6 25 27 30 36 6.7 8.5tPHL A or B Y MAX 22 22 7 12 5.8 - 25 27 30 36 5.9 7.5
PARAMETER INPUT OUTPUT MAX or MIN CD74AC
ACT11
SN74ACT
CD74ACT AHC AHCT LV
3VLV5V
LVC3V
ALVC3V
tPLH A or B Y MAX 9.5 9 10 12.1 8.5 9 13 8.5 3.8 2.8tPHL A or B Y MAX 9.5 8 10 12.1 8.5 9 13 8.5 3.8 2.8UNIT: ns
158
Logic Diagram
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
33QUADRUPLE 2-INPUTPOSITIVE-NOR BUFFERSWITH OPEN-COLLECTOROUTPUTS
Y = A + B
35HEX NONINVERTERSWITH OPEN-COLLECTOROUTPUTS
Y = A
1A
1B1Y
2A
2B2Y
3A
3B3Y
4A
4B4Y
11A 1Y
2
32A 2Y
4
53A 3Y
6
94A 4Y
8
115A 5Y
10
136A 6Y
12
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS ALS UNIT
ICC MAX 16.5 13.8 9 mAVOH MAX 5.5 5.5 5.5 VIOL MAX 48 24 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN TTL LS ALS
tPLH A or B Y MAX 15 32 33tPHL A or B Y MAX 18 28 12UNIT: ns
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALS UNIT
ICC MAX 63 mAVOH MAX 5.5 VIOL MAX 8 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALS
tPLH A Y MAX 50tPHL A Y MAX 14UNIT: ns
159
Logic Diagram
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
37QUADRUPLE 2-INPUTPOSITIVE-NAND BUFFERS
Y = A•B
38QUADRUPLE 2-INPUTPOSITIVE-NAND BUFFERSWITH OPEN-COLLECTOR OUTPUTS
Y = A•B
1Y3
11A
21B
2Y6
42A
52B
3Y8
93A
103B
4Y11
124A
134B
1Y3
11A
21B
2Y6
42A
52B
3Y8
93A
103B
4Y11
124A
134B
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS S ALS F UNIT
ICC MAX 54 12 80 7.8 33 mAIOH MAX -1.2 -1.2 -3 -2.6 -15 mAIOL MAX 48 24 60 24 64 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN TTL LS S ALS F
tPLH A or B Y MAX 22 24 6.5 8 6.5tPHL A or B Y MAX 15 24 6.5 7 5UNIT: ns
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS S ALS F UNIT
ICC MAX 54 12 80 7.8 30 mAVOH MAX 5.5 5.5 5.5 5.5 4.5 VIOL MAX 48 24 60 24 64 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN TTL LS S ALS F
tPLH A or B Y MAX 22 32 10 33 13tPHL A or B Y MAX 18 28 10 12 5.5UNIT: ns
160
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
424-LINE TO 10-LINE DECODERS
All Outputs Are High for Invalid Input Conditions Also for Applications as
3-Line to 8-Line Decoders4-Line to 16-Line Decoders
Full Decoding of Valid Input Logic Ensures That All Inputs Remain Off for All Invalid Input Conditions
0
1
2
3
4
5
6
7
8
9
A
B
C
D
15
14
13
12
1
2
3
4
5
6
7
9
10
11
161PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS SN74HC
CD74HC
CD74HCT UNIT
ICC MAX 56 13 0.08 0.16 0.16 mAIOH MAX -0.8 -0.4 -4 -4 -4 mAIOL MAX 16 8 4 4 4 mA
SWITCHING CHARACTERISTICS
PARAMETER INTPUT OUTPUT MAX or MIN TTL LS SN74HC
CD74HC
CD74HCT
tPLH 2Level Logic 0-9 25 25 38 45 53
tPHL 2Level Logic 0-9 25 25 38 45 53
tPLH 3Level Logic 0-9 30 30 38 45 53
tPHL 3Level Logic 0-9 30 30 38 45 53UNIT: ns
MAX
MAX
A, B, C or D
A, B, C or D
No.INPUTS
D
FUNCTION TABLE
C B A0
0 1 2 3 4 5 6 7 8 9
OUTPUTS
L
H
1234
56789
LLLL L
L L
L
H
L
HH
H HLH
H
H
HH L
H
L
H
H
LH
HH
HH
HH
HH
HHH
HL
HHH
HH
HH
HH
HH
HHH
LH
HHH
HH
HH
HH
HH
HHH
HH
LHH
HH
HH
HH
HH
HHH
HH
HLH
HH
HH
HH
HH
HHH
HH
HHL
HH
HH
HH
HL
HHH
HH
HHH
HH
HH
HH
LH
HHH
HH
HHH
HH
HH
HH
HH
LHH
HH
HHH
HH
HH
HH
HH
HLH
HH
HHH
HH
HH
HH
HH
HHL
HH
HHH
H H
L
LL
H
LLL
LL
LH
LLL
LL
LL H
LH
H
H
HH
HH
HH
H
H
L
H
INV
ALI
D
162: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
45BCD-TO-DECIMAL DECODER/DRIVER
80-mA Sink-Current Capability All Outputs Are Off for Invalid BCD Input Conditions
Logic Diagram
0
1
2
3
4
5
6
7
8
9
A
B
C
D
15
14
13
12
1
2
3
4
5
6
7
9
10
11
163PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL UNIT
ICC MAX 70 mAVO (on) MAX 0.9 VIOL MAX 80 mA
SWITCHING CHARACTERISTICS
PARAMETER MAX or MIN TTL
tPLH 25tPHL 25UNIT: ns
MAX
No.INPUTS
D
FUNCTION TABLE
C B A0
0 1 2 3 4 5 6 7 8 9
OUTPUTS
L
H
1234
56789
LLLL L
L L
L
H
L
HH
H HLH
H
H
HH L
H
L
H
H
LH
HH
HH
HH
HH
HHH
HL
HHH
HH
HH
HH
HH
HHH
LH
HHH
HH
HH
HH
HH
HHH
HH
LHH
HH
HH
HH
HH
HHH
HH
HLH
HH
HH
HH
HH
HHH
HH
HHL
HH
HH
HH
HL
HHH
HH
HHH
HH
HH
HH
LH
HHH
HH
HHH
HH
HH
HH
HH
LHH
HH
HHH
HH
HH
HH
HH
HLH
HH
HHH
HH
HH
HH
HH
HHL
HH
HHH
H H
L
LL
H
LLL
LL
LH
LLL
LL
LL H
LH
H
H
HH
HH
HH
H
H
L
H
INV
ALI
D
164: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
Logic Diagram
47BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS
Open-Collector Outputs Lamp-Test Provision Leading/Trailing Zero Suppression
INPUTA
INPUTB
INPUTC
INPUTD
BI/RBOBLANKINGINPUT OR
RIPPLE-BLANKINGOUTPUT
LTLAMP-TEST
INPUTRBI
RIPPLE-BLANKINGINPUT
(7)
(13)
(12)
(11)
(10)
(9)
(15)
(14)
OUTPUTa
OUTPUTb
OUTPUTc
OUTPUTd
OUTPUTe
OUTPUTf
OUTPUTg
(1)
(2)
(6)
(4)
(3)
(5)
165PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS UNIT
ICC MAX 103 13 mAIOH MAX -0.2 -0.05 mAIOL MAX 8 3.2 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN TTL LS
toff A A to g MAX 100 100ton A A to g MAX 100 100toff RBI A to g MAX 100 100ton RBI A to g MAX 100 100UNIT: ns
No.INPUTS
D
FUNCTION TABLE
C B A0
BI/RBOOUTPUTS
L123
4567
89
LLL
L
LL
HH
L
HH
HH
HH
1011
12131415
BIRBILT
LT
HH
H
H
HH
HH
HH
H
HHHH
H
XH
RBI
XH L
LLL
H
HH
HH
LLHH
LL
HH
HH
LHLH
L
L
H
H
H
H
HH
HH
HH
HH
LLH
aONOFFONON
OFF
OFFON
ONON
ON
OFFOFF
OFFON
OFFOFF
OFFOFFON
HH
HH
HH
HH
XX
XXXX
XXXX
XXXX
XLXL
XLX
XLX
XLX
XLX
HHH
HH
H
H
LL
L
L
LLLL
LL
L
L
bON
ONON
ON
ONON
OFF
ON
OFFOFF
OFFOFFON
cON
OFFON
ON
ONON
ON
OFF
OFF
OFF
OFFOFFON
dONOFFONON
OFF
OFF
ON
ON
OFF
OFFON
OFF
OFFOFFON
eONOFFON
ON
ON
OFF
OFF
ONOFF
OFFOFFON
fONOFF
OFF
ONON
ON
OFFOFF
ONOFF
OFFOFFON
g
OFFONON
OFF
ONON
ON
ONOFF
OFFOFFON
ON
ONOFFOFF
OFF
ON
ON
ON
OFF ON
OFFOFF
ON
ONON
ON
OFF
OFFOFFOFF
OFFOFFONOFF
ONON
ONON
OFF
ONON
ON ONON ON
OFF
166
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
51AND-OR INVERT GATES
'51, 'S51: Y = AB + CD 'F51, 'LS51: 1Y = (1A•1B•1C) + (1D•1E•1F) 'HC51: 2Y = (2A•2B) + (2C•2D)
1A1B1C
1Y
1D1E1F
2A
2B
1Y
2C
2D
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS S F SN74HC UNIT
ICC MAX 14 2.8 22 7.5 0.08 mAIOH MAX -0.4 -0.4 -1 -1 -4 mAIOL MAX 16 8 20 20 4 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN TTL LS S F SN74HC
tPLH Any Y MAX 22 20 5.5 6.5 35tPHL Any Y MAX 15 20 5.5 4.5 35UNIT: ns
167
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN S F UNIT
ICC MAX 16 4.7 mAIOH MAX -1 -1 mAIOL MAX 20 20 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN S F
tPLH Any Y MAX 5.5 7tPHL Any Y MAX 5.5 5.5UNIT: ns
644-2-3-2 INPUT AND-ORINVERT GATE
Y = ABCD + EF + GHI + JK
D
AB
F
E
C
I
G
Y
H
K
J
168
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
CLK
J
CLR
Q
K
Q
J
K
CL
CL R
12 (9)Q
13 (8)Q
14 (7)
CD74HC/HCT73
'LS73
3(10)
J
K
1 (5)CP
2 (6)R
73DUAL J-K FLIP-FLOPS WITH CLEAR
169PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
INPUTS
J
FUNCTION TABLE (SN74)
K Q
OUTPUTS
XLHLHH
LHHH
↓
↓↓↓
CLOCKX X
LLHH
LQ0HL
H
LH
TOGGLE
CLEAR Q
QO
XH H X Q0 Q0
TRUTH TABLE (CD74)
INPUTS OUTPUTS
R CP J K Q Q
L X X X L H
H ↓ L L No Change
H ↓ H
H ↓ L
L
H
H
L
L
H
H ↓ H H Toggle
H H X X No Change
NOTE:H = High Level (Steady State)L = Low Level (Steady State)X = Irrelevant↓ = High-to-Low Transition
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS SN74HC
CD74HC
CD74HCT UNIT
ICC MAX 20 6 0.04 0.08 0.08 mAIOH MAX 16 8 4 4 4 mAIOL MAX -0.4 -0.4 -4 -4 -4 mA
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN TTL LS SN74HC
CD74HC
CD74HCT
MIN 15 30 25 20 20
tw CLOCK"L" 20 - 20 - -
CLOCK"H" 47 20 20 - -
CP Pulse Wide - - - 24 24
CLEAR "L" 25 20 20 24 27tsu CLK 0 20 25 - -
J,K to CP - - - 24 24
th CLK 0 0 0 - -
J,K to CP - - - 3 3tPLH 25 20 39 44 51tPHL - 20 39 44 51tPLH - 20 39 44 51tPHL 40 20 39 44 51tPLH 25 20 32 - -tPHL 40 20 32 - -tPLH - - - 48 57tPHL - - - 48 57tPLH - - - 48 54tPHL - - - 48 54
UNIT fmax : MHz, other : ns
CP Q MAX
CP Q MAX
CLEAR Q MAX
CLOCK Q or Q MAX
MIN
CLEAR Q MAX
PARAMETER
fmax
MIN
MIN
170
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
74DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPSWITH PRESET AND CLEAR
74AC11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series) 74ACT11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)
TG
C
C
TG
C
TG
C
C
C
C
TG
C
C
PRE
CLK
D
CLR
Q
Q
C
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
171
PRESET
INPUTS
D
FUNCTION TABLE
Q
OUTPUTS
XXXHLH
HLLH
↓↓
CLOCK
X HLH*H
L
H*L
CLEAR Q
H
XH Q0 Q0
H
LHLH
H
XX
LL H
† This configuration is unstable; that is, it does not persist when PRE or CLR returns to its inactive (high) level.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS S ALS AS F SN74HC
CD74HC
SN74HCT
CD74HCT
AC11
SN74AC
CD74AC
ACT11 UNIT
ICC MAX 15 8 25 4 16 16 0.04 0.08 0.04 0.08 0.04 0.02 0.08 0.04 mAIOH MAX -0.4 -0.4 -1 -0.4 -2 -1 -4 -4 -4 -4 -24 -24 -24 -24 mAIOL MAX 16 8 20 8 20 20 4 4 4 4 24 24 24 24 mA
PARAMETER MAX or MIN SN74ACT
CD74ACT AHC AHCT LV
3VLV5V
LVC3V UNIT
ICC MAX 0.02 0.08 0.02 0.02 - 0.02 0.01 mAIOH MAX -24 -24 -8 -8 -6 -12 -24 mAIOL MAX 24 24 8 8 6 12 24 mA
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN TTL LS S ALS AS F SN74HC
CD74HC
SN74HCT
CD74HCT
AC11
MIN 15 25 75 34 105 100 25 20 24 16 125tw CLOCK"H" MIN 30 25 6 14.5 4 4 20 24 23 27 4
CLOCK"L" MIN 37 - 7.3 14.5 5.5 5 20 24 23 27 4
RESET or CLEAR "L" MIN 30 25 7 15 4 4 25 24 20 24 4tsu D MIN 20 20 3 15 4.5 3 25 18 15 18 3.5
PRE, CLR INACTIVE MIN 20 - - 10 2 2 6 - 0 5 1MIN 5 5 2 0 0 1 0 3 0 3 0
tPLH Q 25 25 6 13 7.5 7.1 58 60 44 60 7.1tPHL Q 40 40 13.5 15 10.5 10.5 58 60 44 60 9tPLH Q 25 25 6 13 7.5 7.1 58 60 44 60 7.1tPHL Q 40 40 13.5 15 10.5 10.5 58 60 44 60 9tPLH 25 25 9 16 8 7.8 44 53 35 53 8.2tPHL 40 40 9 18 9 9.2 44 53 35 53 7.5
INPUT OUTPUT MAX or MIN SN74AC
CD74AC
ACT11
SN74ACT
CD74ACT AHC AHCT LV
3VLV5V
LVC3V
MIN 125 110 85 125 85 75 65 45 75 100tw CLOCK"H" MIN 5 4.5 5 6 5.7 5 5 7 5 3.3
CLOCK"L" MIN 5 4.5 5 6 5.7 5 5 7 5 3.3
RESET or CLEAR "L" MIN 5 4 5 6 5 5 5 7 5 3.3tsu D MIN 3 3.5 4.5 3.5 4 5 5 7 5 3
PRE, CLR INACTIVE MIN 0 - 2 0 - 3 3.5 5 3 2MIN 0.5 0 0 1 9.5 0.5 0 0.5 0.5 0
tPLH Q 10 10.5 9.6 11.5 11.5 11 13 18 11 5.4tPHL Q 10.5 11.5 12.5 12.5 12.5 11 13 18 11 5.4tPLH Q 10 10.5 9.6 11.5 11.5 11 13 18 11 5.4tPHL Q 10.5 11.5 12.5 12.5 12.5 11 13 18 11 5.4tPLH 10.5 10 9.4 14 9.5 10.5 10 17.5 10.5 5.2tPHL 10.5 10 8.8 12 9.5 10.5 10 17.5 10.5 5.2UNIT fmax : MHz, other : ns
MAX
MAX
MAX
PARAMETER
fmax
th
Q or Q
RESET
CLEAR
CLOCK
PARAMETER
fmax
th
RESET MAX
CLEAR MAX
CLOCK Q or Q MAX
172
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
CD74HC/HCT75
SN74LS75
D0
3 (7)
2 (6)LATCH 0
QD
LE LE
16 (10)
1 (11)
Q0
Q0
E
13 (4)
LATCH 1
QD
LE LE
D1
14 (8)
Q1
15 (9)Q1
5
12GND
VCC
DATA Q
QTOOTHERLATCH
ENABLEC
754-BIT BISTABLE LATCHES
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS SN74HC
CD74HC
CD74HCT UNIT
ICC MAX 53 12 0.04 0.08 0.08 mAIOH MAX -0.4 -0.4 -4 -4 -4 mAIOL MAX 16 8 4 4 4 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN TTL LS SN74HC
CD74HC
CD74HCT
tw 20 20 20 24 24tsu 20 20 25 18 18th MIN 5 5 5 3 3tPLH 30 27 30 33 42tPHL 25 17 30 33 42tPLH 40 20 30 39 42tPHL 15 15 30 39 42tPLH 30 27 33 39 42tPHL 15 25 33 39 42tPLH 30 30 33 39 45tPHL 15 15 33 39 45UNIT: ns
MAX
MIN
MAX
MAX
MAX
QD
G
G
D Q
Q
Q
INPUTS
FUNCTION TABLE
Q
OUTPUTS
LH L
QH
Q0 Q0
DLHX
H
L
C
H
173PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
Logic Diagram
854-BIT MAGNITUDE COMPARATORS
A = B(3)
A > B(4)
A < B(2)
A2(13)
B2(14)
A1(12)
B1(11)
A0(10)
B0(9)
A = B(6)
A < B(7)
A > B(5)
A3(15)
B3(1)
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS S SN74HC
CD74HC
CD74HCT UNIT
ICC MAX 88 20 115 0.08 0.16 0.16 mAIOH MAX -0.4 -0.4 -1 -4 -4 -4 mAIOL MAX 16 8 20 4 4 4 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT Nunber ofGate Levels MAX or MIN TTL LS S SN74
HCCD74
HCCD74HCT
A B, A B 3 MAX 26 36 16 58 59 56
A B 4 MAX 35 45 18 50 53 60
A B, A B 3 MAX 30 30 16.5 58 59 56
A B 4 MAX 30 45 16.5 50 53 60tPLH A B, A B A B 1 11 22 7.5 44 42 45tPHL A B, A B A B 1 17 17 8.5 44 42 45tPLH A B A B 2 20 20 10.5 37 - -tPHL A B A B 2 17 26 7.5 37 - -tPLH A B, A B A B 1 11 22 7.5 44 42 47tPHL A B, A B A B 1 17 17 8.5 44 42 47UNIT: ns
MAX
MAX
MAX
tPLH
tPHL
Any A or Bdata input
Any A or Bdata input
FUNCTION TABLE
OUTPUTS
LH
A>BA>BX
A<B A<BA=B A=B
COMPARINGINPUTS
A2, B2 A0, B0XX
X
A3, B3A3>B3
CASCADINGINPUTS
A2>B2A2<B2A2=B2
X X L
A1, B1X
A3<B3A3=B3A3=B3A3=B3A3=B3A3=B3A3=B3A3=B3A3=B3A3=B3A3=B3A3=B3
A2=B2A2=B2A2=B2A2=B2A2=B2A2=B2A2=B2A2=B2
LXX X X LXLHXX X X LXLXX X X LXLHXX X X LLXX X X LLHX X X LLX X X LLHH L L LLL H LLH H LLHL LHX X H L
A1>B1
A0>B0A1<B1
A0<B0A1=B1
A0=B0A1=B1
A0=B0A1=B1
A0=B0A1=B1
A0=B0A1=B1
A0=B0A1=B1A1=B1
LLL
L
LH
H
H
H
H
H
174
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
= 1
Exclusive OR
1A1Y
1B
(1)(3)
(2)
2A2Y
2B
(4)(6)
(5)
3A3Y
3B
(9)(8)
(10)
4A4Y
4B
(12)(11)
(13)
An exclusive-OR gate has many applications,some of which can be represented betterby alternative logic symbols.
86QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
Y = A ⊕ B or Y = AB + AB 74AC11xxx : Product Available in Reduced-Noise Advanced CMOS (11000 Series) 74ACT11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS S ALS AS F SN74HC
CD74HC
CD74HCT
AC11
SN74AC
CD74AC
ACT11 UNIT
ICC MAX 50 10 75 5.9 38 28 0.02 0.04 0.04 0.04 0.02 0.08 0.04 mAIOH MAX 16 8 20 8 20 20 4 4 4 24 24 24 24 mAIOL MAX -0.8 -0.4 -1 -0.4 -2 -1 -4 -4 -4 -24 -24 -24 -24 mA
PARAMETER MAX or MIN SN74ACT
CD74ACT AHC AHCT LV
3VLV5V
LVC3V UNIT
ICC MAX 0.04 0.08 0.02 0.02 - 0.02 0.01 mAIOH MAX 24 24 8 8 6 12 24 mAIOL MAX -24 -24 -8 -8 -6 -12 -24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN TTL LS S ALS AS F SN74HC
CD74HC
CD74HCT
AC11
SN74AC
CD74AC
ACT11
tPLH Y MAX 23 23 10.5 17 7.5 6.5 25 36 48 7.6 9 10.8 9.6tPHL Y MAX 17 17 10 12 6.5 6.5 25 36 48 6.8 9.5 10.8 9tPLH Y MAX 30 30 10.5 17 6.5 8 25 36 48 7.6 9 10.8 9.6tPHL Y MAX 22 22 10 10 7 7.5 25 36 48 6.8 9.5 10.8 9
PARAMETER INPUT OUTPUT MAX or MIN SN74ACT
CD74ACT AHC AHCT LV
3VLV5V
LVC3V
tPLH Input Low Y MAX 10 14.6 10 10 16.5 10 4.6tPHL Input Low Y MAX 10.5 14.6 10 10 16.5 10 4.6tPLH Input High Y MAX 10 14.6 10 10 16.5 10 4.6tPHL Input High Y MAX 10.5 14.6 10 10 16.5 10 4.6UNIT: ns
A or B
A or B
A or B
A or B
175
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
90DECADE COUNTER
J (8)Q
CK
QC
K
J (12)Q
CK
QA
K
S (11)Q
Q
CK
QD
R0(1)(2)
R
J (9)Q
CK
QB
K
R0(2)(3)
R9(1)(6)
R9(2)
CKA
CKB
(7)
(14)
(1)
QB
BCD COUNT SEQUENCE
OUTPUTS
LL
QCQD
4
0123
Count
5
HH
67
QA
89
FUNCTION TABLE
LLLLLL
LLLL
LL
HH
HH
LLHHLLHHLL
L
HL
HL
HL
HL
H
QC
BI-QUINARY
OUTPUTS
LL
QDQA
4
0123
Count
5
HH
67
QB
89
LLL
LLLL
L
H
LLHHL
LHHL
L
HL
HL
HL
HL
H
HH
H
LLL L L
QB
RESET/COUNTFUNCTION TABLE
OUTPUTS
LL
QCQD QA
H
LL
Count
LLL
LLH
R9(1)
RESET INPUTS
HH
R0(2)R0(1) R9(2)
XXLLX
L
CountCountCount
H
HX
XX
L
LXL
XL
XL
HXLH
XL
XL
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS UNIT
ICC MAX 39 15 mAIOH MAX -0.8 -0.4 mAIOL MAX 16 8 mA
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN TTL LS
A QA 32 32B QB 16 16
A 15 15B 30 30
RESET 15 30
tPLH 16 16tPHL 18 18tPLH 48 48tPHL 50 50tPLH 16 16tPHL 21 21tPLH 32 32tPHL 35 35tPLH 32 32tPHL 35 35tPHL Set to 0 Any MAX 40 40tPLH QA, QD 30 30tPHL QB, QC 40 40UNIT fmax : MHz, other : ns
tsu MIN 25 25RESETINACTIVE
PARAMETER
fmax
tw
MAX
A
A
B
B
Set to 9
QC
QD
MIN
QC
MIN
MAX
MAX
QA
MAX
B QB MAX
MAX
176
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
92DIVIDE-BY-12 COUNTERS
QA(12)
QB(11)
QC(9)
QD(8)
J QCK
K
J QCK
K
J Q
Q
CK
K
J QCK
K
R0(1)(6)(7)R0(2)
CKA
CKB(1)
(14)
QB
FUNCTION TABLE
OUTPUTS
LL
QCQD
4
0123
COUNT
5
HH
67
QA
89
LLLL
LLLL
LL
HH
LLHHLLLL
L
HL
HL
HL
HL
H
QB
OUTPUTS
L
QCQD QALCOUNT
L L
RESET INPUTS
HL
R0(2)R0(1)
X COUNT
H
LX
HH
1011
LL
LL
LH
HH
HH
HH
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS UNIT
ICC MAX 39 15 mAIOH MAX -0.8 -0.4 mAIOL MAX 16 8 mA
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN TTL LS
A QA 32 32B QB 16 16
A 15 15B 30 30
RESET 15 30
tPLH 16 16tPHL 18 18tPLH 48 48tPHL 50 50tPLH 16 16tPHL 21 21tPLH 16 16tPHL 21 21tPLH 32 32tPHL 35 35tPHL Set to 0 Any MAX 40 40UNIT fmax : MHz, other : ns
B
A
MAX
MIN
MIN
MIN
MAX
MAXQD
QB
QC
A
B
B
PARAMETER
fmax
tw
tsu RESETINACTIVE 25 25
QD
QA MAX
MAX
177
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
934-BIT BINARY COUNTERS QA
(12) [13]
(9) [9]
(8) [10]
(11) [12]
QB
QC
QD
J QCK
K
J QCK
K
J QCK
K
J QCK
KR0(1)
(2)(3)
[1][2]R0(2)
CKA
CKB(1)
(14)
[8]
[14]
QB
FUNCTION TABLE
OUTPUTS
LL
QCQD
4
0123
COUNT
5
HH
67
QA
89
LLLL
LLLLHH
LLHH
L
HL
HL
HL
HL
H
QB
OUTPUTS
L
QCQD QALCOUNT
L L
RESET INPUTS
HL
R0(2)R0(1)
X COUNT
H
LX
HH
1011
LL
LH
H12 HH13 HH14 HH15 H
LL
HH
LL
LLHHLLHHLLHH
LHLH
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS CD74HC
CD74HCT UNIT
ICC MAX 39 15 0.16 0.16 mAIOH MAX -0.8 -0.4 -4 -4 mAIOL MAX 16 8 4 4 mA
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN TTL LS CD74HC
CD74HCT
A QA 32 32 20 20B QB 16 16 20 20
A 15 15 24 24B 30 30 24 24
RESET 15 30 24 24- -- -
tPLH 16 16 38 51tPHL 18 18 38 51tPLH 70 70 - 87tPHL 70 70 - 87tPLH 16 16 41 51tPHL 21 21 41 51tPLH 32 32 56 69tPHL 35 35 56 69tPLH 51 51 74 87tPHL 51 51 74 87tPHL Set to 0 ANY MAX 40 40 - -UNIT fmax : MHz, other : ns
B
QA
QD
QC
QD
A
A
B
QBB
MAX
MAX
MAX
MAX
MAX
MIN 25
PARAMETER
fmax
tw
tsu
MIN
MIN
25RESETINACTIVE
178: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
Logic Diagram
97SYNCHRONOUS 6-BIT BINARY RATE MULTIPLIER
Perform Fixed-Rate or Variable-Rate Frequency Division Typical Maximum Clock Frequency: 32MHz
G
CLEAR
T
QF
QF
G
CLEAR
T
QE
QE
G
CLEAR
T
QD
QD
G
CLEAR
T
QC
QC
G
CLEAR
T
QB
QB
G
CLEAR
T
QA
QA
ENABLEOUTPUT
RATEINPUT B0
(7)
(4)RATEINPUT B1
(1)RATEINPUT B2
RATEINPUT B3
UNITY/CASCADEINPUT
Z OUTPUT
Y OUTPUT
RATEINPUT B4
ENABLEINPUT
CLEAR
CLOCK
STROBE
RATEINPUT B5
(14)
(12)
(5)
(6)
(15)(2)(3)
(13)
(11)
(9)
(10)
179PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
OUTPUTS
HL
FCLEAR Y
FUNCTION TABLE
LLL
LLL
XLLL
HH
HH
L
24
63
H
L1
1632
40LL
L
LL 8L
HL
STROBE
LLL
LLL
LL
L
XL
ENABLE
LLL
LLL
LL
L
NUMBER OFCLOCK PULSES
X64
UNITY/CASCADE
HH
64 H64 H64 H64 H64 H64 H64 H
64 L64 H
BINARY RATE
E
XLLL
HL
H
LL
D
XLLL
HH
H
L
L
C
XLLL
HL
H
LL
B
XLL
HL
H
L
LL
A
XL
L
HL
H
L
LL
L L L L LH
HH
HH
INPUTS
Z
H
24
63
63
H1
1632
40
8
ENABLE
H11111111
11
LOGI LEVEL ORNUMBER OF PULSES
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL UNIT
ICC MAX 120 mAIOH MAX 16 mAIOL MAX -0.4 mA
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN TTL
A QA MIN 25tw CLK MIN 20
CLR MIN 15tsu Positive MIN 25
Negative MIN 0th Positive MIN 0
Negative MIN 20tPLH MAX 20tPHL MAX 21tPLH MAX 18tPHL MAX 23tPLH MAX 39tPHL MAX 30tPLH MAX 18tPHL MAX 26tPLH MAX 10tPHL MAX 14tPLH MAX 14tPHL MAX 10tPLH MAX 30tPHL MAX 33tPLH MAX 30tPHL MAX 33tPLH Y MAX 36tPHL Z MAX 23tPLH MAX 23tPHL MAX 23
UNIT fmax : MHz other : ns
CLR
RATE Y
Y
STRB Y
CLK ENABLE
UNITY/CAS
CLK Z
RATE Z
STRB Z
CLK Y
PARAMETER
fmax
ENABLE ENABLE
180
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
CLK
J
CLR
Q
K
K
Q
J
CLR
Q
CLK
Q
107DUAL J-K FLIP-FLOPS WITH CLEAR
181PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS SN74HC
CD74HC
CD74HCT UNIT
ICC MAX 20 6 0.04 0.08 0.08 mAIOH MAX -0.4 -0.4 -4 -4 -4 mAIOL MAX 16 8 4 4 4 mA
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN TTL LS SN74HC
CD74HC
CD74HC
MIN 15 30 25 20 19tw CLK H MIN 20 20 20 - -
CLK L MIN 47 - 20 - -
CP MIN - - - 24 27
CLR L (or R) MIN 25 25 20 25 36tsu J, K MIN 0 20 25 30 30
CLR INACTIVE MIN 0 25 25 - -MIN 0 0 0 3 5
Q MAX 25 20 39 47 57
Q MAX 40 20 39 47 57
Q MAX 25 20 32 - -
Q MAX 40 20 32 - -MAX - - - 51 65MAX - - - 51 65MAX - - - 51 60MAX - - - 51 60
UNIT fmax : MHz, other : ns
CP QtPHL
tPLHCP Q
tPHL
tPLH
tPHLCLR (or R)
tPLHCLK
tPHL
PARAMETER
thtPLH
fmax
INPUTS
J
FUNCTION TABLES'107
K Q
OUTPUTS
XLHLHH
LHHH
CLOCKX X
LLHH
LQOHL
H
LH
TOGGLE
CLEAR Q
QO
INPUTS
J
'LS107A,'HC107
K Q
OUTPUTS
XLHLHH
LHHH
↓
↓↓↓
CLOCKX X
LLHH
LQOHL
H
LH
TOGGLE
CLEAR Q
QO
XH X QO QOH
182
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
C
C
C
C
K
J
PRE
CLK
TG
CLR
C
C
TG
C
C
TG
C
C
Q
TGQ
109DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR
183PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
PRESET
INPUTS
J
FUNCTION TABLE
Q
OUTPUTS
XXXLHH
HLLH
CLOCKX H
LH†
L
H†
CLEAR Q
H
LH QO QO
H
LHLH
H
XX
HHXH QO QO
HH L
TOGGLE
H L
XXXL
HX
LH
K
L H↑↑
↑↑
† The output levels in this configuration are not guaranteed to meet the minimum levels for VOH. Furthermore, this configuration is nonstable; that is, it will not persist when either PRE or CLR returns to its inactive (high) level.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS ALS AS F SN74HC
CD74HC
CD74HCT
CD74AC
CD74ACT UNIT
ICC MAX 15 8 4 17 17 0.04 0.08 0.08 0.08 0.08 mAIOH MAX -0.8 -0.4 -0.4 -2 -1 -4 -4 -4 -24 -24 mAIOL MAX 16 4 8 20 20 4 4 4 24 24 mA
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN TTL LS ALS AS F SN74HC
CD74HC
CD74HCT
CD74AC
CD74ACT
MIN 25 25 34 105 90 25 25 19 100 100tw CLK H MIN 20 25 14.5 4 4 20 - - - -
CLK L MIN 20 - 14.5 5.5 5 20 - - - -
CP MIN - - - - - - 24 27 5 5
PRE L MIN 20 25 15 4 4 25 - - - -
CLR L MIN 20 25 15 4 4 25 - - - -
R MIN - - - - - - 24 36 4.5 5.5tsu J, K MIN 10 25 15 5.5 3 25 - - - -
PRE, CLR MIN 10 - 10 2 2 6 - - - -
J, K to CP MIN - - - - - - 30 30 5.5 5.5MIN 6 5 0 0 1 0 3 5 0 1
Q MAX 15 25 13 8 8 58 - - - -
Q MAX 35 40 15 10.5 10.5 58 - - - -
Q MAX 15 25 13 8 8 58 - - - -
Q MAX 25 40 15 10.5 10.5 58 - - - -MAX 16 25 16 9 8 44 - - - -MAX 28 40 18 9 9.2 44 - - - -MAX - - - - - - 51 65 10.3 10.3MAX - - - - - - 51 65 10.3 10.3MAX - - - - - - 51 60 10.3 10.3MAX - - - - - - 51 60 10.3 10.3MAX - - - - - - 47 57 12.2 12.2MAX - - - - - - 47 57 12.2 12.2
UNIT fmax : MHz, other : ns
tPLHR Q,Q
tPHL
tPLHCP Q
tPHL
tPLHCP Q
tPHL
tPLHCLK Q,Q
tPHL
PREtPHL
tPLHCLR
tPHL
fmax
PARAMETER
thtPLH
184
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
PRE
CLK
J
CLR
Q
Q
C
C
C
C
K
TGTG
TG TG
C
C
C
C
C
C
112DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET AND CLEAR
185PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
INPUTS
A2
FUNCTION TABLE
A1XH
Q
OUTPUTS
LL† H†
QH
B
L† H†L† H†
LX
CLEARLXXXHH
HHH↑↑
H
LL
XX
HH
XX
XHXXXX
H
LL
↓↓ ↓
↓
XL
B2X XX X
XX
H HH HH HH HH
HH
H H
H
↑
↑↑
↑
LL
See explanation of function table on page† These lines of the functional tables assume that the indicated steady-state conditions at the A and B inputs have been set up long enough to complete any pulse started before the set up.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LS S ALS F SN74HC
CD74HC
CD74HCT
CD74AC
CD74ACT
LVC3V UNIT
ICC MAX 6 25 4.5 19 0.04 0.08 0.08 0.08 0.08 0.01 mAIOH MAX -0.4 -1 -0.4 -1 -4 -4 -4 -24 -24 -24 mAIOL MAX 8 20 8 20 4 4 4 24 24 24 mA
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN LS S ALS F SN74HC
CD74HC
CD74HCT
LVC3V
MIN 30 80 30 100 20 20 20 150tw PRE, CLR MIN 25 8 10 5 25 24 27 -
CLK H MIN 20 6 16.5 5 25 - - 3.3
CLK L MIN - 6.5 16.5 5 25 - - 3.3
CP MIN - - - - - 24 24 -tsu DATA MIN 20 7 22 5 25 24 24 2.3
PRE INACTIVE MIN 25 - 20 5 25 - - 2.4
CLR INACTIVE MIN 20 - 20 5 25 - - 2.4MIN 0 0 0 0 0 0 3 0.7MAX 20 7 15 7.5 41 - - 4.8MAX 20 7 18 7.5 41 - - 4.8MAX 20 7 15 7.5 31 - - 5.9MAX 20 7 19 7.5 31 - - 5.9MAX - - - - - 53 53 -MAX - - - - - 53 53 -MAX - - - - - 47 48 -MAX - - - - - 47 48 -MAX - - - - - 54 56 -MAX - - - - - 54 56 -
UNIT fmax : MHz, other : ns
tPLHR Q or Q
tPHL
tPLHS Q or Q
tPHL
tPLHCP Q or Q
tPHL
tPLHCLK Q or Q
tPHL
PARAMETER
fmax
Q or Q
thtPLH
tPHLPRE or CLR
186
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
121MONOSTABLE MULTIVIBRATOR
Internal Timing Resistors (2kΩ) Programmable Output Pulse Width with
Rext/Cext: 40ns to 28s
A1
A2
B
(3)
(10)
(4)
(5)
(1)
(6)
(11)
Cext
Rint = 2 kΩ NOM
C
Q
(9)Rint
Rext / Cext
NOTES: 1. An external capacitor may be connected between Cext (positive) and Rext /Cext.2. To use the internal timing resistor, connect Rint to VCC. For improved pulse width
accuracy and repestability, connect an external resistor between Rext /Cext and VCC with Rint open-circuited.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL UNIT
ICC MAX 40 mAIOH MAX -0.4 mAIOL MAX 16 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN TTL
tw (IN) MIN 50tPLH A 70tPHL B 80tPLH A 55tPHL B 65UNIT: NS
Q MAX
Q MAX
INPUTS
A2
FUNCTION TABLE
XLX
A1LXXH
Q
OUTPUTS
LL† H†
QH
BHH
L† H†L† H†
H
LX
XL
HHH↑↑
LX
H
H
↓↓ ↓
↓
See explanation of function table on page† These lines of the functional tables assume that the indicated steady-state conditions at the A and B inputs have been set up long enough to complete any pulse started before the set up.
187
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
122RETRIGGERABLE MONOSTABLEMULTIVIBRATORS WITH CLEAR
Retriggerable for Very Long Output Pulse, Up to100% Duty Cycle
Internal Timing Resistors (5kΩ)
B1(3)
A2(2)
Q(6)
Q
R
(8)
Rext /Cext(13)
A1(1)
B2(4)
CLR(5)
Cext(11)
RintRint (9)
Rint is nominally 10 kW for '122 and 'LS122
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS UNIT
ICC MAX 66 11 mAIOH MAX -0.8 -0.4 mAIOL MAX 16 8 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN TTL LS
tw MIN 40 40A 33 33B 28 44A 40 45B 36 56
tPLH Q 27 27tPHL Q 40 45UNIT: NS
MAX
MAX
MAX
tPLH
tPHL
CLEAR
Q
Q
INPUTS
A2
FUNCTION TABLE
A1XH
Q
OUTPUTS
LL† H†
QH
B
L† H†L† H†
LX
CLEARLXXXHH
HHH↑↑
H
LL
XX
HH
XX
XHXXXX
H
LL
↓↓ ↓
↓
XL
B2X XX X
XX
H HH HH HH HH
HH
H H
H
↑
↑↑
↑
LL
See explanation of function table on page† These lines of the functional tables assume that the indicated steady-state conditions at the A and B inputs have been set up long enough to complete any pulse started before the set up.
188
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
123DUAL RETRIGGERABLE MONOSTABLEMULTIVIBARATORS WITH CLEAR
Retriggerable for Very Long Output Pulse, Up to100% Duty Cycle
CLR
Cext
Rext/Cext
R
B
A
Q
Q
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS CD74HC
CD74HCT AHC AHCT LV
3VLV5V UNIT
ICC MAX 66 20 0.16 0.16 0.65 0.975 0.28 0.65 mAIOH MAX -0.8 -0.4 -4 -4 -8 -8 -6 -12 mAIOL MAX 16 8 4 4 8 8 6 12 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN TTL LS CD74HC
CD74HCT AHC AHCT LV
3VLV5V
tw MIN 40 40 30 30 5 5 5 5
A (A) 33 33 90 - 16 12 27.5 16B 28 44 90 - 16 12 27.5 16
A (A) 40 45 96 - 16 12 27.5 16B 36 56 96 - 16 12 27.5 16
tPLH Q 27 27 65 - 13 14 22 13tPHL Q 40 45 65 - 13 14 22 13UNIT: NS
MAX
tPLH
tPHL
MAX
MAX
Q
Q
CLEAR(R)
INPUTS
FUNCTION TABLE
A (A)XH
Q
OUTPUTS
LL† H†
QH
B
L† H†
L
CLEARLXXHH
LX
XX
HH
L
↑↓
↑
See explanation of function table on page† These lines of the functional tables assume that the indicated steady-state conditions at the A and B inputs have been set up long enough to complete any pulse started before the set up.
189PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
Block Diagram
124DUAL VOLTAGE-CONTROLLED OSCILLATORS WITH ENABLE INPUTS
Frequency Spectrum: 1Hz to 60MHz Typical fmax: 85MHz Typical Power Dissipation: 525mW
FREQCONT
RNG
Cext
Cext
(2)1 FREQUENCY CONTROL
1 RANGE
1 Cext
1 Cext
1G ENABLE
(3)
Y
EN
(4)
(5)
(6)
(7)1Y
FREQCONT
RNG
Cext
Cext
(1)2 FREQUENCY CONTROL
2 RANGE
2 Cext
2 Cext
2G ENABLE
(14)
Y
EN
(12)
(13)
(11)
(10)2Y
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN S UNIT
ICC MAX 150 mAIOH MAX -1 mAIOL MAX 20 mA
SWITCHING CHARACTERISTICS
PARAMETER MAX or MIN S
fo MIN 60UNIT: NS
190
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
125QUADRUPLE BUS BUFFER GATES WITH THREE-STATE OUTPUTS
Y = A
2A 2Y
2OE
1A 1Y
1OE1
2
4
5
3
64A 4Y
4OE
3A 3Y
3OE10
9
13
12
8
11
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS F SN74HC
CD74HC
SN74HCT
CD74HCT
SN74BCT
SN64BCT ABT UNIT
ICC MAX 54 20 40 0.08 0.16 0.08 0.16 49 49 30 mAIOH MAX -5.2 -2.6 -15 -6 -6 -6 -6 -15 -15 -32 mAIOL MAX 16 24 64 6 6 6 6 64 64 64 mA
PARAMETER MAX or MIN LVTH3V AHC AHCT LV
3VLV5V
LVC3V ALVC UNIT
ICC MAX 7 0.04 0.02 0.02 0.02 0.01 0.01 mAIOH MAX -32 -8 -8 -8 -16 -24 -24 mAIOL MAX 64 8 8 8 16 24 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN TTL LS F SN74HC
CD74HC
SN74HCT
CD74HCT
SN74BCT
SN64BCT ABT
tPLH MAX 13 15 6.5 30 30 33 38 5.7 6 4.9tPHL MAX 18 18 8 30 30 33 38 7.7 8 4.9tPZH MAX 17 20 8.5 30 38 35 38 10.3 11.1 5.9tPZL MAX 25 25 9 30 38 35 38 11.7 12.8 6.8tPHZ MAX 8 20 6 30 38 33 42 8.9 9.4 6.2tPLZ MAX 12 20 6 30 38 33 42 8.6 9.9 6.2
PARAMETER INPUT OUTPUT MAX or MIN LVTH3V AHC AHCT LV
3VLV5V
LVC3V ALVC
tPLH MAX 3.5 8.5 8.5 13 8.5 4.8 2.8tPHL MAX 3.9 8.5 8.5 13 8.5 4.8 2.8tPZH MAX 4 8 8 13 8 5.4 3.5tPZL MAX 4 8 8 13 8 5.4 3.5tPHZ MAX 4.5 10 10 15 10 4.6 4tPLZ MAX 4.5 10 10 15 10 4.6 4UNIT: NS
A Y
G Y
A Y
G Y
191
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
126QUADRUPLE BUS BUFFER GATES WITH THREE-STATE OUTPUTS
Y = A
11OE
21A 1Y
3
42OE
52A 2Y
6
103OE
93A 3Y
8
134OE
124A 4Y
11
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS F SN74HC
CD74HC
CD74HCT
SN74BCT
SN64BCT ABT LVTH
3V UNIT
ICC MAX 62 22 48 0.08 0.16 0.16 51 51 30 7 mAIOH MAX -5.2 -2.6 -15 -6 -6 -6 -15 -15 -32 -32 mAIOL MAX 16 24 64 6 6 6 64 64 64 64 mA
PARAMETER MAX or MIN AHC AHCT LV3V
LV5V
LVC3V ALVC UNIT
ICC MAX 0.04 0.02 0.02 0.02 0.01 0.01 mAIOH MAX -8 -8 -8 -16 -24 -24 mAIOL MAX 8 8 8 16 24 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN TTL LS F SN74HC
CD74HC
CD74HCT
SN74BCT
SN64BCT ABT LVTH
3V
tPLH MAX 13 15 7 30 30 36 6.3 6.3 6.3 3.8tPHL MAX 18 18 8.5 30 30 36 7.4 7.4 5.7 3.9tPZH MAX 18 25 8.5 30 38 38 7.9 7.9 6.5 5.4tPZL MAX 25 35 8.5 30 38 38 10.5 10.5 6.5 5.2tPHZ MAX 16 25 7.5 30 38 42 10 10 6.8 3.8tPLZ MAX 18 25 8 30 38 42 12.3 12.3 6.7 5.5
PARAMETER INPUT OUTPUT MAX or MIN AHC AHCT LV5V
LV3V
LVC3V ALVC
tPLH MAX 8.5 8.5 8.5 13 4.7 3.1tPHL MAX 8.5 8.5 8.5 13 4.7 3.1tPZH MAX 8 8 8 13 5.7 3.3tPZL MAX 8 8 8 13 5.7 3.3tPHZ MAX 10 10 10 15 6 3.7tPLZ MAX 10 10 10 15 6 3.7UNIT: ns
A Y
G Y
A
G
Y
Y
192
Logic Diagram
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
12850-Ω LINE DRIVERS
Y = A + B
132QUADRUPLE 2-INPUT POSITIVE-NANDSCHMITT TRIGGERS
Y = A•B
YB
A
A
B
Y
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL UNIT
ICC MAX 57 mAIOH MAX -42.4 mAIOL MAX 48 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN TTL
tPLH A, B Y MAX 9tPHL A, B Y MAX 12UNIT: ns
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS S SN74HC
CD74HC
CD74HCT AHC AHCT LV
3VLV5V UNIT
ICC MAX 40 14 68 0.02 0.04 0.04 0.02 0.02 0.02 0.02 mAIOH MAX -0.8 -0.4 -1 -4 -4 -4 -8 -8 -6 -12 mAIOL MAX 16 8 20 4 4 4 8 8 6 12 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN TTL LS S SN74HC
CD74HC
CD74HCT AHC AHCT LV
3VLV5V
tPLH A, B Y MAX 22 22 10.5 31 38 50 11 10 17.5 11tPHL A, B Y MAX 22 22 13 31 38 50 11 8 17.5 11UNIT: ns
193
Logic Diagram
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
13313-INPUT POSITIVE-NAND GATES
Y = A•B•C•D•E•F•G•H•I•J•K•L•M
136QUAD EXCLUSIVE-ORGATES WITH OPEN-COLLECTOR OUTPUTS
Y = A ⊕ B = AB + AB
Y9
1A
2B
3C
4D
5E
13K
14L
15M
6F
7G
10H
11I
12J
1Y1B
1A
2Y2B
2A
3Y3B
3A
4Y4B
4A
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS ALS AS UNIT
ICC MAX 50 10 5.9 31 mAVOH MAX 5.5 5.5 5.5 5.5 VIOL MAX 16 8 8 20 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN TTL LS ALS AS
tPLH A or B Y (Other Output = L) MAX 18 30 50 12.5tPHL A or B Y (Other Output = L) MAX 50 30 15 7.1tPLH A or B Y (Other Output = L) MAX 22 30 50 11.4tPHL A or B Y (Other Output = L) MAX 55 30 15 10.7UNIT: ns
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN S ALS SN74HC UNIT
ICC MAX 10 0.34 0.02 mAIOH MAX -1 -0.4 -4 mAIOL MAX 20 8 4 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN S ALS SN74HC
tPLH A to M Y MAX 6 11 38tPHL A to M Y MAX 7 25 38UNIT: ns
FUNCTION TABLE
INPUTS
LL
BALH
OUTPUTY
HHH
HLH
L
L
194
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
G1
G2
LE
C
B
A
6
5
4
3
2
1
OutputEnables
LatchEnable
SelectInputs
DataOutputs
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
10
11
12
13
14
7
9
15
1373-TO-8 LINE DECODERS/DEMULTIPLEXERS WITH ADDRESS LATCHES
Incorporates Two Output Enables To Simplify Cascading
195PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
INPUTS
FUNCTION TABLE
G1 Y0
OUTPUTS
HL
B
LHH
LX X
X
HH
L
ENABLE SELECT
G2
HHHHHH
H
LLLLLLL
L
XH
L
HH
LL
X
CXXLL
HH
X
XX
HL
HL
X
LL
A
HL
HL
HH
H
HHHHHHH
Y1
H
L
H
HHHHHH
Y2
H
L
H
H
HHHHH
Y3
H
L
H
HH
HHHH
Y4
H
L
H
HHH
HHH
Y5
H
L
H
HHHH
HH
Y6
H
L
H
HHHHH
H
Y7
H
L
H
HHHHHH
H H H H H H HXX
H
LLLLLLLL
LE
Depends upon the address previously appliedwhile LE was at a logic low.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LS ALS AS SN74HC
CD74HC
SN74HCT
CD74HCT UNIT
ICC MAX 18 11 24 0.08 0.16 0.08 0.16 mAIOH MAX -0.4 -0.4 -2 -4 -4 -4 -4 mAIOL MAX 8 8 20 4 4 4 4 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN LS ALS AS SN74HC
CD74HC
SN74HCT
CD74HCT
tPLH MAX 24 20 12.5 48 54 48 57tPHL MAX 38 20 12.5 48 54 48 57tPLH MAX 21 12 8 36 44 36 56tPHL MAX 27 15 8.5 36 44 36 56tPLH MAX 21 17 10 36 44 36 53tPHL MAX 27 15 9 36 44 36 53tPLH MAX 27 22 13.5 48 57 52 66tPHL MAX 38 20 14 48 57 52 66UNIT:ns
Y (CD74: Y)
Y (CD74: Y)
Y (CD74: Y)
Y (CD74: Y)LE (CD74: LE)
G1
G2
A, B, C
196
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1383-TO-8 LINE DECODERS/DEMULTIPLEXRS
3 Enable Inputs to Simplify Cascading and /or Data Reception 74AC11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series) 74ACT11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)
G2B
G2A
G1
C
B
A
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
DataOutputs
SelectInputs
EnableInputs
1
2
3
6
4
5
15
14
13
12
11
10
9
7
197PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
INPUTS
FUNCTION TABLE
G1 Y0
OUTPUTS
HL
B
LHH
LX X
X
HH
L
ENABLE SELECT
G2*
HHHHHH
LLLLLLL
XH
L
HH
LL
CXXLL
HH
XX
HL
HL
LL
A
HL
HL
HH
H
HHHHHHH
Y1
H
L
H
HHHHHH
Y2
H
L
H
H
HHHHH
Y3
H
L
H
HH
HHHH
Y4
H
L
H
HHH
HHH
Y5
H
L
H
HHHH
HH
Y6
H
L
H
HHHHH
H
Y7
H
L
H
HHHHHH
H H H H H H H
G2* = G2A•G2B
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LS S ALS AS F SN74HC
CD74HC
SN74HCT
CD74HCT
AC11 UNIT
ICC MAX 10 74 10 20 20 0.08 0.16 0.08 0.16 0.04 mAIOH MAX -0.4 -1 -0.4 -2 -1 -4 -4 -4 -4 -24 mAIOL MAX 8 20 8 20 20 4 4 4 4 24 mA
PARAMETER MAX or MIN CD74AC
ACT11
CD74ACT AHC AHCT LV
3VLV5V
LVC3V UNIT
ICC MAX 0.16 0.04 0.16 0.04 0.04 0.02 0.02 0.01 mAIOH MAX -24 -24 -24 -8 -8 -6 -12 -24 mAIOL MAX 24 24 24 8 8 6 12 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN LS S ALS AS F SN74HC
CD74HC
SN74HCT
CD74HCT
AC11
tPLH MAX 27 12 22 10 8.5 45 45 45 53 8.1tPHL MAX 39 12 18 9.5 9 45 45 45 53 8.8tPLH MAX 26 11 17 7.5 8 39 53 42 53 8.3tPHL MAX 38 11 17 8.5 7.5 39 53 42 53 8.3tPLH MAX 26 11 17 10 9 39 53 42 53 7.5tPHL MAX 38 11 17 10 8.5 39 53 42 53 7.7
PARAMETER INPUT OUTPUT MAX or MIN CD74AC
ACT11
CD74ACT AHC AHCT LV
3VLV5V
LVC3V
tPLH MAX 11 9.8 12 11.5 13 18 11.5 6.7tPHL MAX 11 9.7 12 11.5 13 18 11.5 6.7tPLH MAX 10 8.9 10.5 11.5 12 18 11.5 6.5tPHL MAX 10 8.9 10.5 11.5 12 18 11.5 6.5tPLH MAX 11 9.3 11 11.5 11.5 18.5 11.5 5.8tPHL MAX 11 9.8 11 11.5 11.5 18.5 11.5 5.8UNIT: ns
G2 Y (CD74:Y )
G1 Y (CD74:Y )
G1 Y (CD74:Y )
A, B, C Y (CD74:Y )
Y (CD74:Y )
Y (CD74:Y )
A, B, C
G2
198
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
139DUAL 2-TO-4-LINE DECODERS/DEMULTIPLEXERS
Incorporate Two Enable Inputs to Simplify Cascading and /or Data Reception 74ACT11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)
1G
1Y0
1Y1
1Y2
1Y3
2Y0
2Y1
2Y2
2Y3
1A
1B
2G
2A
2B
1
2
3
15
14
13
4
5
6
7
12
11
10
9
199PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
INPUTS
FUNCTION TABLE
Y0
OUTPUTS
HLL
ENABLE SELECT
G
LL
H X
H
A
L
H
HH
Y1
H
L
H
H
Y2
H
L
H
H
Y3
H HL L L
H
H
HH
HH
B
LX
H
L
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LS S ALS SN74HC
CD74HC
SN74HCT
CD74HCT
CD74AC
ACT11
CD74ACT UNIT
ICC MAX 11 90 13 0.08 0.08 0.08 0.16 0.16 0.08 0.16 mAIOH MAX -0.4 -1 -0.4 -4 -4 -4 -4 -24 -24 -24 mAIOL MAX 8 20 8 4 4 4 4 24 24 24 mA
PARAMETER MAX or MIN AHC AHCT LV3V
LV5V
LVC3V
UNIT
ICC MAX 0.04 0.02 - 0.02 0.01 mAIOH MAX -8 -8 -6 -12 -24 mAIOL MAX 8 8 6 12 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN LS S ALS SN74HC
CD74HC
SN74HCT
CD74HCT
CD74AC
ACT11
CD74ACT
tPLH A or B Y (CD74: Y) MAX 29 12 14 44 44 43 51 10.5 8.5 11.5tPHL A or B Y (CD74: Y) MAX 38 12 14 44 44 43 51 10.5 8.5 11.5tPLH G Y (CD74: Y) MAX 24 8 14 44 41 43 51 10.5 7.9 12tPHL G Y (CD74: Y) MAX 32 10 15 44 41 43 51 10.5 7.5 12
PARAMETER INPUT OUTPUT MAX or MIN AHC AHCT LV3V
LV5V
LVC3V
tPLH A or B Y (CD74: Y) MAX 10.5 10.5 16.5 10.5 6.2tPHL A or B Y (CD74: Y) MAX 10.5 10.5 16.5 10.5 6.2tPLH G Y (CD74: Y) MAX 9.5 9.5 14.5 9.5 4.7tPHL G Y (CD74: Y) MAX 9.5 9.5 14.5 9.5 4.7UNIT: ns
200: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
Logic Diagram
1D1C1B 1Y
1A
2D2C2B 2Y
2A
140DUAL 4-INPUT POSITIVE-NAND50-Ω LINE DRIVERS
Y = ABCD
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN S UNIT
ICC MAX 44 mAIOH MAX -40 mAIOL MAX 60 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN S
tPLH MAX 6.5tPHL MAX 6.5UNIT: ns
A, B, C, D Y
201PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
Logic Diagram
145BCD-TO-DECIMAL DECODERS/DRIVERS FOR LAMPS, RELAYS, MOS
Sink-Current Capability: 80mA Low Power Dissipation (SN74LS): 35mW (typ)
INPUT D(12)
OUTPUT 0(1)
OUTPUT 1(2)
OUTPUT 2(3)
OUTPUT 3(4)
OUTPUT 4(5)
OUTPUT 5(6)
OUTPUT 6(7)
OUTPUT 7(9)
OUTPUT 8(10)
OUTPUT 9(11)
INPUT B(14)
INPUT C(13)
INPUT A(15)
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS UNIT
ICC MAX 70 13 mAVo (OFF) MAX 15 15 mA
SWITCHING CHARACTERISTICS
PARAMETER MAX or MIN TTL LS
tPLH MAX 50 50tPHL MAX 50 50UNIT: ns
No.INPUTS
D
FUNCTION TABLE
C B A0
0 1 2 3 4 5 6 7 8 9
OUTPUTS
L
H
1234
56789
LLLL
LL
L
LLLL
L
L
LHH
H
H
L
LL
HH
LL
HH
LH
L
HLL
HH
H
LH
HH
HH
HH
LL
HH
HH
HH
LL
HH
HL
LH
HL
HH
HH
HH
HH
HHH
HL
HHH
HH
HH
HH
HH
HHH
LH
HHH
HH
HH
HH
HH
HHH
HH
LHH
HH
HH
HH
HH
HHH
HH
HLH
HH
HH
HH
HH
HHH
HH
HHL
HH
HH
HH
HL
HHH
HH
HHH
HH
HH
HH
LH
HHH
HH
HHH
HH
HH
HH
HH
LHH
HH
HHH
HH
HH
HH
HH
HLH
HH
HHH
HH
HH
HH
HH
HHL
HH
HHH
INV
ALI
D
202
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
2(12)
1(11)
3(13)
4(1)
5(2)
6(3)
7(4)
8(5)
9(10)
B(7)
C(6)
D(14)
A(9)
14710-TO-4 LINE PRIORITY ENCODER
203PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
INPUTS
D C B A1 2 3 4 5 6 7 8 9
OUTPUTS
HLL
LLLLL
L
LHH
H
H
L
HH
HH
LH
H LL
HH
H
LH
L
H
H
H
L HH
H
L HHH
H
L HL
HHH
H
LH
HH
H
HH
L
H
H
H
HH
L
H
H
HH
H
HH
LH
HHH
H
H
H HH
HH H H
HHHH
HXXXXXXXX
XXXXXXX
XXXXXX
XXXXX
XXXX
XXX
XX
XH
H H LH
FUNCTION TABLE
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS SN74HC
CD74HC
CD74HCT UNIT
ICC MAX 70 20 0.08 0.16 0.16 mAIOH MAX -0.8 -0.4 -4 -4 -4 mAIOL MAX 16 8 4 4 4 mA
SWITCHING CHARACTERISTICS
PARAMETER MAX or MIN TTL LS SN74HC
CD74HC
CD74HCT
tPLH MAX 19 33 48 48 53tPHL MAX 19 23 48 48 53UNIT:ns
204
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1488-TO 3-LINE OCTAL PRIORITY ENCODERS
11
A09
1
A17
A26
GS14
EO15
122
133
14
25
5EI
47
36
100
205PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
INPUTS
A2
FUNCTION TABLE
A1 A0 GS1 2 3 4 5 6 7EI 0
OUTPUTS
LLLLL
LHH
H
L
HH
LH
H LL
HH
H
LH
L
H
H
H
L HH
H
L HHH
H
L HL
HHH
H
LH
HH
H
HH
L
H
H
H
LH
H
H
H
HH
X
XXXXXX
X
XXXXX
X
XXXX
X
XXX
X
XX
X
X
X
H H LH
EO
LH
H
H
H
H
X
X X X X X X X L
HH
H
H
HH
HLLLLLLLL HH H
H
LLLL
HH
LLLL
H
H
H
H
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS SN74HC UNIT
ICC MAX 60 20 0.08 mAIOL MAX 16 8 4 mAIOH MAX -0.8 -0.4 -4 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT WAVEFORM MAX or MIN TTL LS SN74HC
tPLH 15 18 45tPHL 14 25 45tPLH 19 36 45tPHL 19 29 45tPLH 10 18 38tPHL 25 40 38tPLH 30 55 48tPHL 25 21 48tPLH 15 25 49tPHL 15 25 49tPLH 12 17 36tPHL 15 36 36tPLH 15 21 41tPHL 30 35 41UNIT: ns
MAX
MAX
E1 GS In-phase output MAX
E1 A0, A1 or A2 In-phase output
E1
MAX
0 to 7 GS In-phase output MAX
0 to 7 EO Out-of-phaseoutput
EO In-phase output
MAX
1 to 7 A0, A1 or A2 Out-of-phaseoutput MAX
In-phase outputA0, A1 or A21 to 7
206
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
E2(6)
E3(5)
E4(4)
E5(3)
E6(2)
E7DATA
INPUTS
(1)
E8(23)
E9(22)
E10(21)
E11(20)
E12(19)
E13(18)
E14(17)
OUTPUTS(10)
E0(8)
STROBE(ENABLE)
(9)
E15(16)
A(15)
BDATASELECT
(BINARY)
(14)
C(13)
D(11)
E1(7)
DD
CC
BB
AA
1501-OF-16 DATA SELECTOR
207PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
INPUTSOUTPUT
L
SELECT STROBE
G
LL
HX
H
A
LE1
E4
H
E3
W
E2
LL
HH
B
LX
H
L
H
C
LX
H
L
H
D
LX
H
L
E5E6E7E8E9E10E11E12E13E14E15
E0
LH
LL
LL
HH
LH
LL
LH
LL
HH
LH
HH
HH
LH
HH
HH
LH
LLLL
H
L
H
L
H
L
H
L
H
L
H
L
LLLLLLLLLLLL
FUNCTION TABLE
NOTES:H = High Level, L = Low Level, X = irrelevantE0, E1 ... E15 = the complement of the level of the
respective E inputD0, D1 ... D7 = the level of the D respective input
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL UNIT
ICC MAX 48 mAIOH MAX -0.8 mAIOL MAX 16 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN TTL
tPLH 35tPHL 33tPLH 24tPHL 30tPLH 14tPHL 20UNIT:ns
A, B, C or D W MAX
W MAX
E0 thru E15 orE0 thru D7 W MAX
Strobe G
208
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
7
4
3
2
1
15
14
13
12
11
10
9
5
6
G
D0
D1
D2
D3
D4
D5
D6
D7
A
B
C
Y
W
DataInputs
DataSelect
(binary)
1518-TO-1 LINE DATA SELECTORS/MULTIPLEXERS
209PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
INPUTS
FUNCTION TABLE
OUTPUTS
L
SELECT
G
LL
HX
H
A
LD1
D4
L
D3
Y
D2
LL
HH
B
LX
H
L
H
C
LX
H
L
D5D6D7
D0
LH
LL
HH
LH
H
L
H
LLLLL
HW
D0D1D2D3D4D5D6D7
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS S ALS AS F SN74HC
CD74HC
CD74HCT
CD74AC
CD74ACT UNIT
ICC MAX 48 10 70 12 30 21 0.08 0.16 0.16 0.16 0.16 mAIOH MAX -0.8 -0.4 -1 -2.6 -15 -1 -6 -4 -4 -24 -24 mAIOL MAX 16 8 20 24 48 24 6 4 4 24 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN TTL LS S ALS AS F SN74HC
CD74HC
CD74HCT
tPLH 38 43 18 18 14.5 12 63 56 62tPHL 38 30 18 24 15 9 63 56 62tPLH 26 23 15 24 12 9.5 63 62 65tPHL 30 32 13.5 23 12 7.5 63 62 65tPLH 20 32 16.5 10 10.5 7.5 49 51 57tPHL 27 26 18 15 11 7.5 49 51 57tPLH 14 21 13 15 6.5 7 49 56 54tPHL 14 20 12 15 4.5 5 49 56 54tPLH 33 42 12 18 14 10.5 32 42 44tPHL 33 32 12 19 11 7.5 32 42 44tPLH 21 24 7 19 6 7 32 44 54tPHL 23 30 7 23 10 6 32 44 54
PARAMETER INPUT OUTPUT MAX or MIN CD74AC
CD74ACT
tPLH 18.2 20.2tPHL 18.2 20.2tPLH 19.6 21.6tPHL 19.6 21.6tPLH 13.5 15.5tPHL 13.5 15.5tPLH 14.9 16.9tPHL 14.9 16.9tPLH 12.2 12.1tPHL 12.2 12.1tPLH 13.5 13.5tPHL 13.5 13.5UNIT: ns
A, B or C Y MAX
A, B or C W (CD74: Y) MAX
D0 to D7 Y MAX
D0 to D7 W (CD74: Y) MAX
G Y MAX
G W (CD74: Y) MAX
A, B or C Y MAX
A, B or C W (CD74: Y) MAX
D0 to D7 Y MAX
D0 to D7 W (CD74: Y) MAX
G Y MAX
G W (CD74: Y) MAX
210
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
153DUAL 4-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS
Data 2
Select
Data 1
2G
2C3
2C2
2C1
2C0
A
B
1C3
1C2
1C1
1C0
1G
1Y
1
6
5
4
3
2
14
10
11
12
13
15
7
2Y9
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
211
DATA INPUTS
FUNCTION TABLEOUTPUTS
L
SELECT INPUTS
G
LL
HXA
H
Y
LL
HH
B
LX
H
L
C1X
H
C0X
L
H
L
HH
LLLL
STROBE
HL
X
LX
HL
C2 C3
LL
H
H
X
X
X
XXX
LX
L
X
X
X
X
X
X
X
X
X
X
X
X
XX
XXX
H
LL
HL
HL
HL
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS S ALS AS F SN74HC
CD74HC
CD74HCT
CD74AC
CD74ACT UNIT
ICC MAX 60 10 70 14 33 20 0.08 0.16 0.16 0.16 0.16 mAIOH MAX -0.8 -0.4 -1 -2.6 -15 -1 -6 -4 -4 -24 -24 mAIOL MAX 16 8 20 24 48 20 6 4 4 24 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN TTL LS S ALS AS F SN74HC
CD74HC
CD74HCT
CD74AC
CD74ACT
tPLH MAX 18 15 9 10 7 8 35 44 51 13.3 18tPHL MAX 23 26 9 15 8 7.5 35 44 51 13.3 18tPLH MAX 34 29 18 21 12.5 12 38 48 51 20 22tPHL MAX 34 38 18 21 11 10.5 38 48 51 20 22tPLH MAX 30 24 15 18 11.5 10.5 24 36 41 11.8 12.6tPHL MAX 23 32 13.5 18 9 8 24 36 41 11.8 12.6UNIT: ns
DATA
SELECT
STROBE
Y
Y
Y
212: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1544-LINE TO 16-LINE DECODER/DEMULTIPLEXER
Logic Diagram
0(1)
A B C D
D
D
G
A
B
C
1(2)
2(3)
3(4)
(18)(19)
(23)4
(5)
5(6)
7(8)
8(9)
9(10)
10(11)
11(13)
12(14)
13(15)
14(16)
15(17)
6
OUTPUTS
(7)
A
A
B
B
G1G2
A
(22)B
A
A
B
B
C
C
D
G
D
D(20)D
C
C(21)C
INPUTS
213PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL ALS SN74HC
CD74HC
CD74HCT UNIT
ICC MAX 56 23 0.08 0.16 0.16 mAIOH MAX -0.8 24 -4 -4 -4 mAIOL MAX 16 -0.4 4 4 4 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN TTL ALS SN74HC
CD74HC
CD74HCT
tPLH 36 12 45 53 53tPHL 33 12 45 53 53tPLH 30 12 45 53 51tPHL 27 12 45 53 51UNIT: ns
G1 to G2
0 to 15(CD74: Y0 to Y15)
0 to 15(CD74: Y0 to Y15)
MAX
MAX
A, B, C, D
INPUTS
D
FUNCTION TABLE
C B A 0 1 2 3 4 5 6 7 8
OUTPUTS
LL
L
LLLL
L
LHH
H
H
L
HH
LH
H
LL
HH
H
LH
HH H H H H H H H
HHHHH
H
HH
LL
HH
G1 G2LL
HLH
HLLLLH
HH
HXXX
XXX
XXX
XXX
LLL
L LL LL LL LL LL LL LL LL LL LL LL LL LL
H
LLLLL
LL
L
LH
LL
HH
LHLH
HH
HL
HL
HL
HL
HL
HL
HL
HL
HH H H H H H H
HH
HH
HH
HH
HH H H H H H
HH
HH
HH
HH
HH H H H H
HH
HH
HH
HH
HH H H H
HH
HH
HH
HH
HH H H
HH
HH
HH
HH
HH H
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
H
HH
HH
HH
HH
H
9H
LH
H
H
H
H
H
H
H
H
H
H
H
H
H
HHH
10H
HH
H
L
H
H
H
H
H
H
H
H
H
H
H
HHH
11H
HH
H
H
H
L
H
H
H
H
H
H
H
H
H
HHH
12H
HH
H
H
H
H
H
L
H
H
H
H
H
H
H
HHH
13H
HH
H
H
H
H
H
H
H
L
H
H
H
H
H
HHH
14H
HH
H
H
H
H
H
H
H
H
H
L
H
H
H
HHH
15H
HH
H
H
H
H
H
H
H
H
H
H
H
L
H
HHH
HH
HH
HH
HH
HH
HH
HH
H
HH
HH
HH
HH
HH
H
HH
HH
HH
HH
HH
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS214
155DECODERS/DEMULTIPLEXERS
Individual Strobes Simplify Cascading for Decoding or Demultiplexing Lager Words Outputs: Totem Pole
Logic Diagram
(7) OUTPUT1Y0
(2)STROBE1G
(3)SELECTB
DATA1C
(6) OUTPUT1Y1
(5) OUTPUT1Y2
(4) OUTPUT1Y3
(9) OUTPUT2Y0
(10)OUTPUT2Y1
(11)OUTPUT2Y2
(12)OUTPUT2Y3
(15)
(14)
DATA2C
(13)SELECTA
STROBE2G
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
215
LLL
HX
HL
H
LX
H
L HL
HL
L
HL
HL
HHL
HL
XX X
HH
HH
H
H
H
HH HH H
HH
HH
HH
X
LLL
HXL
H
LX
H
L HL
HL
L
HL
HL
HH
L
HL
XX X
HH
HH
H
HH HH H
HH
HH
HH
X
LLL
LLL
HX
H
L
H
LX
H
L HL
HL
L
HL
HL
H
H
L HL
HH
HH
H
H
H
HH HH H
HH
HH
HH
X
HL
HL
LLH
H
H
HH
H
HH H
H H
HHH
LLL
H
L
H
L HL
HL
LLLL
HHHH
H H H H
HHHH
H H H H
HHHH
H H H HH H H H
DATA
OUTPUTS
SELECT
1GA 1CB 1Y11Y0
STROBE
1Y2 1Y3
INPUTS
FUNCTION TABLES
DATA
OUTPUTS
SELECT
2GA 2CB 2Y12Y0
STROBE
2Y2 2Y3
INPUTS
OUTPUTS
SELECT
G‡AC† B 2Y12Y0
STROBEor DATA
2Y2 2Y3
INPUTS
1Y11Y0 1Y2 1Y3
(0) (1) (2) (3) (4) (5) (6) (7)
2-LINE TO 4-LINE DECODER OR1-LINE TO 4-LINE DEMULTIPLEXER
2-LINE TO 4-LINE DECODER OR1-LINE TO 4-LINE DEMULTIPLEXER
3-LINE TO 8-LINE DECODER OR1-LINE TO 8-LINE DEMULTIPLEXER
† C = inputs 1C and 2C connected together‡ G = inputs 1G and 2G connected together
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS ALS UNIT
ICC MAX 40 10 13 mAIOH MAX -0.8 -0.4 -0.4 mAIOL MAX 16 8 8 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN TTL LS ALS
tPLH A or B 32 26 14tPHL A or B 32 30 12tPLH 1C 24 27 12tPHL 1C 30 27 14UNIT: ns
Y
Y
MAX
MAX
216: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
156DECODERS/DEMULTIPLEXERS
Individual Strobes Simplify Cascading for Decoding or Demultiplexing Lager Words Outputs: Open-Collector
Logic Diagram
2
1
3
13
15
14
7
6
5
4
9
10
11
12
1Y0
1Y1
1Y2
1Y3
2Y0
2Y1
2Y2
2Y3Strobe 2G
Strobe 1G
Data 1C
Data 2C
A
B
Select
217PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
DATA
OUTPUTS
L
SELECT
1G
LL
HXA
H
1C
L
H
B
LX
H
L
1Y1
H
1Y0
L
STROBE
HL
L
HL
1Y2 1Y3
HL
HHL
INPUTS
HL
XX X
HH
HH
H
H
H
HH HH H
HH
HH
HH
X
FUNCTION TABLES
DATA
OUTPUTS
L
SELECT
2G
LL
HXA 2C
L
H
B
LX
H
L
2Y1
H
2Y0
L
STROBE
HL
L
HL
2Y2 2Y3
HL
HH
L
INPUTS
HL
XX X
HH
HH
H
HH HH H
HH
HH
HH
X
LLL
OUTPUTS
L
SELECT
G‡
LL
HXA
H
C†
L
H
B
LX
H
L
2Y1
H
2Y0
L
STROBEor DATA
HL
L
HL
2Y2 2Y3
HL
H
H
L
INPUTS
HL
HH
HH
H
H
H
HH HH H
HH
HH
HH
X1Y1
H
1Y0
L
HL
LL
1Y2 1Y3
H
H
H
HH
H
HH H
H H
HHH
(0) (1) (2) (3) (4) (5) (6) (7)
LLL
H
L
H
L HL
HL
LLLL
HHHH
H H H H
HHHH
H H H H
HHHH
H H H HH H H H
2-LINE TO 4-LINE DECODER OR1-LINE TO 4-LINE DEMULTIPLEXER
2-LINE TO 4-LINE DECODER OR1-LINE TO 4-LINE DEMULTIPLEXER
3-LINE TO 8-LINE DECODER OR1-LINE TO 8-LINE DEMULTIPLEXER
† C = inputs 1C and 2C connected together‡ G = inputs 1G and 2G connected together
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS ALS UNIT
ICC MAX 40 10 9 mAIOL MAX 16 8 8 mAVOH MAX 5.5 5.5 5.5 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN TTL LS ALS
tPLH 23 40 38tPHL 30 51 22tPLH A or B 34 46 55tPHL A or B 34 51 25tPLH 1C 27 48 50tPHL 1C 33 48 23UNIT: ns
2C1G or 2G
Y MAX
Y MAX
Y MAX
218
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
157QUAD 2-TO-1 LINE DATA SELECTORS/MULTIPLEXERS
7
4
3
2
1
15
14
13
12
11
10
9
5
6
G
D0
D1
D2
D3
D4
D5
D6
D7
A
B
C
Y
W
DataInputs
DataSelect
(binary)
219PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS S ALS AS F SN74HC
CD74HC
SN74HCT
CD74HCT UNIT
ICC MAX 48 16 78 11 28 23 0.08 0.16 0.08 0.16 mAIOH MAX -0.8 -0.4 -1 -0.4 -2 -1 -6 -4 -6 -4 mAIOL MAX 16 8 20 8 20 20 6 4 6 4 mA
PARAMETER MAX or MIN CD74AC
CD74ACT AHC AHCT LV
3VLV5V
LVC3V UNIT
ICC MAX 0.16 0.16 0.04 0.02 - 0.0.2 0.01 mAIOH MAX -24 -24 -8 -8 -6 -12 -24 mAIOL MAX 24 24 8 8 6 12 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN TTL LS S ALS AS F SN74HC
CD74HC
SN74HCT
CD74HCT
tPLH 14 14 7.5 14 6 6.5 32 38 35 38tPHL 14 14 6.5 12 5.5 7 32 38 35 38tPLH 20 20 12.5 20 10.5 11 29 41 33 41tPHL 21 21 12 13 7.5 7 29 41 33 41tPLH 23 23 15 24 11 11 31 44 40 44tPHL 27 27 15 17 10 8 31 44 40 44
PARAMETER INPUT OUTPUT MAX or MIN CD74AC
CD74ACT AHC AHCT LV
3VLV5V
LVC3V
tPLH 8.5 9.5 9.5 9.8 15 9.5 5.2tPHL 8.5 9.5 9.5 9.8 15 9.5 5.2tPLH 13.5 13.5 12 12 19.5 12 6.5tPHL 13.5 13.5 12 12 19.5 12 6.5tPLH 14.5 14.5 11.5 12 19 11.5 6.8tPHL 14.5 14.5 11.5 12 19 11.5 6.8UNIT: ns
DATA Y MAX
STROBE Y MAX
MAX
DATA Y MAX
MAX
Y MAXSELECT
Y
STROBE Y
SELECT
OUTPUT
L
SELECT
LL
H XB
L
H
AX
LHL
STROBE
HL
H
INPUTS
HH
X
FUNCTION TABLE
LL
XX
X
X
L
L
220
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
158QUAD 2-TO-1 LINE DATA SLECTORS/MULTIPLEXERS
Buffered Inputs and Outputs
2
3
5
6
11
10
14
13
15
1G
A/B
4B
4A
3B
3A
2B
2A
1B
1A
4
7
9
12
1Y
2Y
3Y
4Y
221PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
OUTPUT
L
SELECT
LL
H XB
L
H
AX
L HL
STROBE
HL
H
INPUTS
H
HX
FUNCTION TABLE
LL
XX
X
X
L
H
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LS S ALS AS F SN74HC
CD74HC
CD74HCT UNIT
ICC MAX 11 81 10 22.5 15 0.08 0.16 0.16 mAIOH MAX -0.4 -1 -0.4 -2 -1 -6 -4 -4 mAIOL MAX 8 20 8 20 20 6 4 4 mA
PARAMETER MAX or MIN CD74AC
CD74ACT AHC AHCT UNIT
ICC MAX 0.16 0.16 0.04 0.02 mAIOH MAX -24 -24 -8 -8 mAIOL MAX 24 24 8 8 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN LS S ALS AS F SN74HC
CD74HC
CD74HCT
tPLH 12 6 15 5 7 32 42 42tPHL 15 6 8 4.5 4.5 32 42 42tPLH 17 11.5 18 6.5 7 29 48 48tPHL 24 12 18 10 6.5 29 48 48tPLH 20 12 18 9.5 9.5 31 45 45tPHL 24 12 18 10.5 7 31 45 45
PARAMETER INPUT OUTPUT MAX or MIN CD74AC
CD74ACT AHC AHCT
tPLH 8 9.2 9.5 9.8tPHL 8 9.2 9.5 9.8tPLH 11.9 12.4 12 12tPHL 11.9 12.4 12 12tPLH 12.9 13.5 11.5 12tPHL 12.9 13.5 11.5 12UNIT: ns
DATA
Y
Y MAX
SELECT Y MAX
Y MAX
SELECT
STROBE
DATA Y
MAX
MAX
STROBE Y MAX
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS222
1594-TO-16 LINE DECODER/DEMULTIPLEXER
Logic Diagram
0(1)
A B C D
D
D
G
A
B
C
1(2)
2(3)
3(4)
(18)(19)
(23)4
(5)
5(6)
7(8)
8(9)
9(10)
10(11)
11(13)
12(14)
13(15)
14(16)
15(17)
6
OUTPUTS
(7)
A
A
B
B
G1G2
A
(22)B
A
A
B
B
C
C
D
G
D
D(20)D
C
C(21)C
INPUTS
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
223
INPUTS
D
FUNCTION TABLE
C B A 0 2 3 4 5 6 7 8 9
OUTPUTS
LL
L
LLLL
L
LHH
H
H
L
HH
LH
H
LL
HH
H
LH
HH H H H H H H H
HHHHH
HH
LL
HH
G1 G2LL
HLH
HLLLLH
HH
HXXX
XXX
XXX
XXX
LLL
L LL LL LL LL LL LL LL LL LL LL LL LL LL
H
LLLLL
LL
L
LH
LL
HH
LHLH
HH
HL
HL
HL
HL
HL
HL
HL
HL
HH H H H H H H
HH
HH
HH
HH
HH H H H H H
HH
HH
HH
HH
HH H H H H
HH
HH
HH
HH
HH H H H
HH
HH
HH
HH
HH H H
HH
HH
HH
HH
HH H
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
H
HH
HH
HH
HH
H
HH
HH
HH
HH
HH
HH
HH
H
HH
HH
HH
HH
HH
H
HH
HH
HH
HH
HH
L1
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
HHH
10H
HL
HH
H
H
H
H
H
H
H
H
H
H
HHH
11H
H
L
H
H
HH
H
H
H
H
H
H
H
H
HHH
12H
H
L
H
H
H
H
HH
H
H
H
H
H
H
HHH
13H
H
L
H
H
H
H
H
H
HH
H
H
H
H
HHH
14H
H
L
H
H
H
H
H
H
H
H
HH
H
H
HHH
15H
H
L
H
H
H
H
H
H
H
H
H
H
HH
HHH
H H H H H H H
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL UNIT
ICC MAX 56 mAIOL MAX 16 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN TTL
tPLH 36tPHL 36tPLH 25tPHL 36UNIT: ns
MAX
MAX
INPUT
STROBE
ANY
ANY
224
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
161SYNCHRONOUS 4-BIT BINARY COUNTERS
Asynchronous Clear Function Carry Output for n-Bit Cascading
1
9
10
7
3
15
14
CLR
LOAD
ENT
ENP
CLK
A
RCO
QA
† For simplicity, routing of complementary signals LD and CK is not shown on this overall logic diagram. The uses of these signals are shownon the logic diagram of the D/T flip-flops.
M1G2
G43D4R
1, 2T/1C3
4
13
B
QB
M1G2
G43D4R
1, 2T/1C3
5
12
C
QC
M1G2
G43D4R
1, 2T/1C3
6
11
D
QD
M1G2
G43D4R
1, 2T/1C3
2
LD†
CK†
CK
R
LD
225PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS ALS AS F SN74HC
CD74HC
CD74HCT
CD74AC
CD74ACT
LV3V
LV5V UNIT
ICC MAX 101 32 21 53 55 0.08 0.16 0.16 0.08 0.08 - 0.02 mAIOH MAX -0.8 -0.4 -0.4 -2 -1 4 -4 -4 -24 -24 -6 -12 mAIOL MAX 16 8 8 20 20 -4 4 4 24 24 -6 12 mA
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN TTL LS ALS AS F SN74HC
CD74HC
CD74HCT
MIN 25 25 40 75 90 25 20 20tw CLOCK 25 25 - - 7 20 24 24
CLEAR 20 20 15 8 5 20 30 30tsu INPUT A, B, C, D 20 20 15 8 5 38 18 15
ENABLE, P, T 20 20 15 8 11.5 43 15 20LOAD 25 20 15 8 11.5 34 18 18
CLEAR INACTIVE 20 25 10 8 - 31 20 -MIN 0 3 0 0 2 0 3 5
35 35 20 16.5 15 54 56 6335 35 20 12.5 15 54 56 6325 24 15 7 9.5 51 56 5929 27 20 13 11 51 56 5916 14 13 9 8.5 49 36 4816 14 13 8.5 8.5 49 36 48
ANY Q MAX 38 28 24 13 13 53 63 75RIPPLE CARRY MAX - - 23 12.5 11.5 55 63 75
INPUT OUTPUT MAX or MIN CD74AC
CD74ACT
LV3V
LV5V
MIN 103 91 50 85tw CLOCK 4.8 5.4 5 5
CLEAR 4.4 5.3 5 5tsu INPUT A, B, C, D 4.4 4.4 6.5 4.5
ENABLE, P, T - - 9 6LOAD 5.3 5.3 9.5 6
CLEAR INACTIVE - - 2.5 1.5MIN 0 0 1 1
15.2 15.2 23.5 1415.2 15.2 23.5 1415 15 18.5 11.515 15 18.5 11.59.4 9.8 18 11.59.4 9.8 18 11.5
ANY Q MAX 15 15 19.5 12.5RIPPLE CARRY MAX 15 15 19 12
UNIT fmax : MHz, other : ns
CLEAR
CLEAR
MIN
MIN
MAX
RIPPLE CARRY
MAX
MAX
CLOCK
MAX
tPLHCLOCK RIPPLE CARRY
tPHL
PARAMETER
fmax
RIPPLE CARRY
tPLH
tPHL
tPHL
tPLHENABLE T
ANY Q
th
PARAMETER
th
fmax
tPHL
MIN
MIN
tPLHCLOCK
tPHL
tPLHCLOCK ANY Q MAX
tPHL
tPHL
RIPPLE CARRY MAXtPHL
tPLHENABLE T
226
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1
9
10
7
3
15
14
CLR
LOAD
ENT
ENP
CLK
A
RCO
QA
† For simplicity, routing of complementary signals LD and CK is not shown on this overall logic diagram. The uses of these signals are shownon the logic diagram of the D/T flip-flops.
M1G2
G43D4R
1, 2T/1C3
4
13
B
QB
M1G2
G43D4R
1, 2T/1C3
5
12
C
QC
M1G2
G43D4R
1, 2T/1C3
6
11
D
QD
M1G2
G43D4R
1, 2T/1C3
2
LD†
CK†
CK
R
LD
163SYNCHRONOUS 4-BIT BINARY COUNTERS
Synchronous Clear Function Carry Output for n-Bit Cascading
227PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS S ALS AS F SN74HC
CD74HC
CD74HCT
CD74AC
CD74ACT
LV3V
LV5V UNIT
ICC MAX 101 32 160 21 53 55 0.08 0.16 0.16 0.08 0.08 - 0.02 mAIOH MAX -0.8 -0.4 -1 -0.4 -2 -1 4 -4 -4 -24 -24 -6 -12 mAIOL MAX 16 8 20 8 20 20 -4 4 4 24 24 -6 12 mA
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN TTL LS S ALS AS F SN74HC
MIN 25 25 40 40 75 90 25tw CLOCK 25 25 10 - - 7 20
CLEAR 20 20 10 12.5 6.7 - -tsu INPUT A, B, C, D 20 20 4 15 8 5 38
ENABLE, P, T 20 20 12 15 8 11.5 43
LOAD 25 20 14 15 8 11.5 34
CLEAR 20 20 14 15 12 - 40MIN 0 3 3 0 0 2 0
35 35 25 20 16.5 15 5435 35 25 20 12.5 15 5425 24 15 15 7 9.5 5129 27 15 20 13 11 5116 14 15 13 9 8.5 4916 14 15 13 8.5 8.5 49
INPUT OUTPUT MAX or MIN CD74HC
CD74HCT
CD74AC
CD74ACT
LV3V
LV5V
MIN 20 20 103 91 50 85tw CLOCK 24 24 4.8 5.4 5 5
CLEAR - - - - - -tsu INPUT A, B, C, D 18 15 4.4 4.4 6.5 4.5
ENABLE, P, T 15 20 4.4 5.3 9 6
LOAD 18 18 5.3 6.6 9.5 6
CLEAR 20 20 5.3 6.6 4 3.5MIN 3 5 0 0 1 1
56 63 15.2 15.2 23.5 1456 63 15.2 15.2 23.5 1456 59 15 15 18.5 11.556 59 15 15 18.5 11.536 48 9.4 9.8 18 11.536 48 9.4 9.8 18 11.5
UNIT fmax : MHz, other : ns
MIN
MIN
thtPLH
CLOCK RIPPLE CARRY MAXtPHL
tPHL
tPLH
tPHL
tPLH
PARAMETER
fmax
th
PARAMETER
fmax
CLOCK
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
ENABLE T
ANY Q
RIPPLE CARRY
CLOCK RIPPLE CARRY
ANY QCLOCK
ENABLE T RIPPLE CARRY
MAX
MAX
MIN
MIN
MAX
MAX
MAX
228
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
C1
1D
R
C1
1D
R
QA QB
C1
1D
R
C1
1D
R
QC QD
C1
1D
R
C1
1D
R
QE QF
C1
1D
R
C1
1D
R
QG QH
3 4 5 6 10 11 12 13
8
1
2
9
CLK
A
B
CLR
1648-BIT PARALLEL OUT SERIAL SHIFT REGISTERS
AND-Gated (Enable/Disable) Serial Inputs Fully Buffered Clock and Serial Inputs
229PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS ALS SN74HC
CD74HC
CD74HCT
CD74AC
CD74ACT
LV3V
LV5V UNIT
ICC MAX 54 27 24 0.08 0.16 0.16 0.16 0.16 - 0.02 mAIOH MAX -0.4 -0.4 -0.4 -4 -4 -4 -24 -24 -6 -12 mAIOL MAX 8 8 8 4 4 4 24 24 6 12 mA
INPUTS
A
FUNCTION TABLE
B QA
OUTPUTS
X
HL
H
LHHH
↑
↑↑
CLOCKX X
L
H
LQA0HL
CLEAR
X X
XX
L
L
QBLQB0
QHLQH0
QAn QGnQAn QGnQAn QGn
. . .
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN TTL LS ALS SN74HC
CD74HC
CD74HCT
CD74AC
CD74ACT
MIN 25 25 50 25 20 18 75 70tw CLR "L" MIN 20 20 16 25 18 27 4.5 4.5
CLK "H" MIN 20 20 10 20 24 27 6.7 7.1CLK "L" MIN 20 20 10 20 24 27 6.7 7.1
tsu DATA MIN 15 15 6 25 18 18 2.5 2.5
CLEAR INACTIVE MIN 20 20 8 25 18 18 2.5 2.5MIN 5 5 2 5 4 4 2.5 3
CLEAR Q MAX 42 36 20 51 42 57 13.9 15.830 27 16 44 51 54 12.5 14.937 32 17 44 51 54 12.5 14.9
INPUT OUTPUT MAX or MIN LV3V
LV5V
MIN 45 75tw CLR "L" MIN 5 5
CLK "H" MIN 5 5CLK "L" MIN 5 5
tsu DATA MIN 6 4.5
CLEAR INACTIVE MIN 2.5 2.5MIN 0 1
CLEAR Q MAX 18.5 12.518.5 12.518.5 12.5
UNIT fmax : MHz, other : ns
tPLHCLOCK Q MAX
tPHL
PARAMETER
fmax
thtPHL
tPLH
tPHL
fmax
thtPHL
PARAMETER
CLOCK Q MAX
230
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
S
1DR
C1S
1DR
C1S
1DR
C1S
1DR
C1S
1DR
C1S
1DR
C1S
1DR
C1S
1DR
C1
1
15
2
10
SH/LD
CLK INH
CLK
SER
9
7QHQH
11 12 13 14 3 4 5 6
A B C D E F G H
1658-BIT SHIFT REGISTERS
Complementary Outputs: Serial (QH, QH) Direct Overriding Load (Data) Inputs Parallel-to-Serial Data Conversion
231PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS ALS SN74HC
CD74HC
CD74HCT
LV3V
LV5V UNIT
ICC MAX 63 30 24 0.08 0.16 0.16 - 0.02 mAIOH MAX -0.8 -0.4 -0.4 -4 -4 -4 -6 -12 mAIOL MAX 16 8 8 4 4 4 6 12 mA
INPUTS
CLOCK
FUNCTION TABLE
SERIALOUTPUT
X
H
LHHH
CLOCKINHIBIT
X X
LHX
X X
Lh
QH0QGnQGn
QH
aQA0
HL
QA
bQB0
QB
XLL
L
H
XXX
QAn
QH0QA0 QB0
QAn
PARALLELSHIFT/LOAD A...H
a...h
INTERNALOUTPUTS
↑↑
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN TTL LS ALS SN74HC
CD74HC
CD74HCT
LV3V
LV5V
MIN 20 25 45 25 20 18 50 85tw MIN 25 15 11 20 24 27 7 4
MIN 25 25 11 20 24 27 7 4MIN 15 25 - - - - - -MIN 15 17 12 20 24 30 9 6
tsu CLK INH 30 30 11 25 24 30 5 3.5DATA 10 10 10 25 24 30 8.5 5SER 20 20 10 10 24 30 6 4
SH/ LD "H" 45 45 10 20 - - 6 4MIN 0 0 4 5 11 11 0.5 1
24 25 13 38 50 60 21.5 13.531 25 14 38 50 60 21.5 13.531 35 20 38 53 60 22 13.540 35 22 38 53 60 22 13.517 25 13 38 45 53 20 12.536 30 16 38 45 53 20 12.527 30 15 38 45 53 20 12.527 25 16 38 45 53 20 12.5
UNIT fmax : MHz, other : ns
tPLHH QH MAX
tPHL
HighLow
MIN
th
MAX
MAX
QH or QH
QH or QH
tPHL
tPLH
QH MAXH
tPHL
tPLH
CLOCK
SH/ LD
PARAMETER
tPHL
tPLH
fmax
CLOCKHighLow
SH/ LD "L"
232
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1DC1
15
9
76
13
SH/LD
CLR
CLK
CLK INH
QH
2 3 4 5 10 11 12 14
SER
A B C D E F G H
R
1DC1
R
1DC1
R
1DC1
R
1DC1
R
1DC1
R
1DC1
R
1DC1
R
1
1668-BIT SHIFT REGISTERS
Synchronous Load Direct Overriding Clear Parallel-to-Serial Conversion
233PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS ALS F SN74HC
CD74HC
CD74HCT
LV3V
LV5V UNIT
ICC MAX 127 32 24 60 0.08 0.16 0.16 - 0.02 mAIOH MAX -0.8 -0.4 -0.4 -1 -4 -4 -4 -6 -12 mAIOL MAX 16 8 8 20 4 4 4 6 12 mA
INPUTS
CLOCK
FUNCTION TABLE
SERIALOUTPUT
X
H
LHHH
CLOCKINHIBIT
X X
LH
X
X
L
A...H
a...h hQH0
QGnQGn
QH
aQA0
HL
QA
bQB0
QB
INTERNALOUTPUTS
XL
HXXX
QAn
QH0QA0 QB0
QAn
PARALLELSHIFT/LOAD
H
H
X
X
X
↑↑
↑
↑
X L LLLX
H
LLL
CLEAR
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN TTL LS ALS F SN74HC
CD74HC
CD74HCT
LV3V
LV5V
MIN 25 25 45 110 25 20 16 50 85tw CLOCK 20 20 10 3.5 20 24 30 7 4
CLEAR 20 25 9 4 25 30 53 7 5tsu Mode Control 30 30 16 4 36 44 45 6 4
DATA 20 20 7 3 20 24 24 6 4.5MIN 0 0 3 0 0 1 0 0 1
CLEAR QH MAX 35 30 14 9.5 30 48 60 18.5 1230 25 13 14 38 48 60 21.5 13.526 20 12 9 38 48 60 21.5 13.5
UNIT fmax : MHz, other : ns
MIN
MIN
MAXCLOCK QH
fmax
PARAMETER
tPLH
tPHL
tPHL
th
234
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
C1
1D142
3
7
10
1
9
15
C1
1D13
4
C1
1D12
5
C1
1D11
6
LOAD
U/D
ENT
ENP
CLK
A
B
C
D
QA
QB
QC
QD
RCO
1694-BIT UP/DOWN SYNCHRONOUS ONOUS BINARY COUNTERS
Fully Synchronous Operation for Counting and Programming Internal Carry Look-Ahead Circuitry for Fast Counting Carry Output for n-Bit Cascading
235PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
MAX or MIN LS S ALS AS F UNIT
ICC MAX 45 160 25 63 52 mA
RCO MAX -0.4 -1 -0.4 -2 -1 mAQ MAX -1.2 -1 -0.4 -2 -1 mA
RCO MAX 8 20 8 20 20 mAQ MAX 24 20 8 20 20 mA
PARAMETER
IOH
IOL
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN LS S ALS AS F
MIN 20 40 40 75 9040 21 20 16.5 1725 28 20 13 12.525 15 15 13 9.525 15 20 7 1325 12 13 9 720 25 16 9 935 15 19 12 12.525 22 19 13 12
UNIT fmax : MHz, other : ns
PARAMETER
fmaxtPLH
tPHLRCO
ANY QtPLH
tPHL
RCO
RCO
tPLH
tPHL
tPLH
tPHL
MAX
MAX
MAX
MAX
ENT
U/D
CLK
CLK
236
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
D
G
QD
(9)Q2
OUTPUTS
(1)D2
G
QD
G
QD
G
QD
G
Q
D
G
QD
(7)Q3
(2)D3
G
QD
G
QD
G
QD
G
Q
D
G
QD
(6)Q4
(3)D4
G
QD
G
QD
G
QD
G
(12)
GW
Q
D
G
QD
(10)Q1
(15)D1
G
QD
G
QD
G
QD
WORD 0 WORD 1 WORD 2 WORD 3
G
Q
(13)
WB
WRITE INPUT
(14)
WA
DATAINPUTS
(11)
GR
(5)
RA
READ INPUT
(4)
RB
1704-BY-4 REGISTER FILES
Separate Read/Write Addressing Permits Simultaneous Reading and Writing Fast Access Times: Typically 20ns Expandable to 1024 Words of 4 Bits
237PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS UNIT
ICC MAX 150 40 mAVOH MAX 5.5 5.5 VIOL MAX 16 8 mA
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN TTL LS
MINMIN 25 25
tsu D 10 10W 15 15
th D 15 15W 5 5
15 3030 3035 4040 4040 4545 4030 4545 35
UNIT fmax : MHz, other : ns
tPLH
DATA
PARAMETER
tPLH
tPHL
fmaxtw
tPLH
tPHL
tPLH
tPHL
MIN
MIN
MAX
MAX
tPHLMAX
MAX
Q
Q
Q
Q
READENABLE
READSELECT
WRITEENABLE
WRITE INPUTS
0
WRITE FUNCTION TABLE
1 2
OUTPUTS
Q = DL
HH
WA
X
QO
LH
WB GW
X
LL
HL
H LL
L
3
QO QOQ = D QO QO
Q = D QOQ = D
QOQO
QOQO
QOQO
QO
QOQOQO
READ INPUTS
Q1
READ FUNCTION TABLE
Q2 Q3
OUTPUTS
W0B1L
HH
RA
XLH
RB GR
X
LL
HL
H LL
L
Q4
H H H H
W1B1W2B1W3B1
W0B2W1B2W2B2W3B2
W0B3W1B3W2B3W3B3
W0B4W1B4W2B4W3B4
238
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
M
N
1D
CLR
CLK
2D
3D
4D
OutputControl
DataEnable
G1
G2
1
2
14
9
10
13
7
12
11
15
3
4
5
6
1Q
2Q
3Q
4Q
1734-BIT D-TYPE REGISTERS
3-State Outputs Interface Directly Fully Independent Clock Virtually
239PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS SN74HC
CD74HC
CD74HCT UNIT
ICC MAX 72 24 0.08 0.16 0.16 mAIOH MAX -5.2 -2.6 -6 -6 -6 mAIOL MAX 16 24 6 6 6 mA
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN TTL LS SN74HC
CD74HC
CD74HCT
MIN 25 25 25 20 13MIN 20 25 20 24 28
tsu DATA ENABLE 17 35 25 18 18DATA 10 17 25 18 27
CLR INACTIVE MIN 10 10 23 - -th DATA ENABLE 2 0 0 0 0
DATA 10 3 0 3 0CLEAR Q MAX 27 35 38 53 66
43 25 38 60 6031 30 38 60 6030 23 38 45 4530 27 38 45 4514 20 38 45 -20 17 38 45 -
UNIT fmax : MHz, other : ns
tPZL
tPHZ
tPLZ
PARAMETER
fmaxtw
tPZH
MIN
MIN
MAXtPLH
tPHL
tPHL
MAX
MAX
CLOCK Q
ENABLE Q
DISABLE Q
G1
INPUTS
D
FUNCTION TABLE
QOUTPUT
X
HL
HL
CLOCK
X L
QO
HL
LH
CLEAR
L
X
L
X
XQOQOX
L XL XLL
↑↑↑↑
DATAG2
HL
X
L
X
ENABLE
X
DATA
240
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1D
C1
R
To Five Other Channels
1
9
3
2
CLR
CLK
1D
1Q
174HEX D-TYPE FLIP-FLOPS
Buffered Clock and Direct Clear Inputs Fully Buffered Outputs for Maximum Isolation
from External Disturbances
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS S ALS AS F SN74HC
CD74HC
CD74HCT UNIT
ICC MAX 65 26 144 19 45 55 0.08 0.16 0.16 mAIOH MAX -0.8 -0.4 -1 -0.4 -2 -1 -4 -4 -4 mAIOL MAX 16 8 20 8 20 20 4 4 4 mA
PARAMETER MAX or MIN CD74AC
CD74ACT AHC AHCT LV
3VLV5V UNIT
ICC MAX 0.16 0.16 0.04 0.04 - 0.02 mAIOH MAX -24 -24 -8 -8 -6 -12 mAIOL MAX 24 24 8 8 6 12 mA
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN TTL LS S ALS AS F SN74HC
CD74HC
CD74HCT
CD74AC
MIN 25 30 75 50 100 80 25 20 17 95tw CLR LOW MIN 20 20 10 10 5 5 20 24 38 4
CLK HIGH 20 20 7 10 4 4 20 24 30 5.2CLK LOW 20 20 7 10 6 6 20 24 30 5.2
tsu DATA INPUT MIN 20 20 5 10 4 4.5 25 18 24 2
CLR INACTIVE MIN 25 25 5 6 6 5 25 - - -MIN 5 5 3 0 1 1 0 5 5 3
25 - - 18 - - 40 45 66 14.535 35 22 23 14 15 40 45 66 14.530 30 12 15 8 9 40 50 60 13.535 30 17 17 10 11 40 50 60 13.5
INPUT OUTPUT MAX or MIN CD74ACT AHC AHCT LV
3VLV5V
MIN 80 80 65 50 80tw CLR LOW MIN 4 5 5 5 5
CLK HIGH 6.2 5 5 5 5CLK LOW 6.2 5 5 5 5
tsu DATA INPUT MIN 2 4.5 5 6 4.5
CLR INACTIVE MIN - 2.5 3.5 3 2.5MIN 2.5 0.5 0 0 0.5
15.5 - - 17 1115.5 11 13 17 1114 10.5 10 16.5 10.514 10.5 10 16.5 10.5
UNIT fmax : MHz, other : ns
tPHL
th
PARAMETER
fmax
tPLH
tPHL
tPLH
MAX
MAX
MIN
CLR
CLK ANY Q
ANY Q
PARAMETER
fmax
MIN
thtPLH
CLR ANY Q MAXtPHL
tPLHCLK ANY Q MAX
tPHL
INPUTSD
FUNCTION TABLE
QOUTPUT
XHL
LHHL
CLOCKX L
QO
HL
CLEAR
L X
↑↑
241
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
1Q
9
1
C1
1D
CLR
CLK
1D
R 1Q
To Three Other Channels
4 2
3
INPUTSD
FUNCTION TABLE
QOUTPUTS
XHL
LHH
↑↑
H
CLOCKX L
QO
HL
HLH
CLEAR Q
QOL X
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS S ALS AS F SN74HC
CD74HC
CD74HCT
AC11
CD74AC
CD74ACT
LV3V
LV5V UNIT
ICC MAX 45 18 96 14 34 34 0.04 0.16 0.16 0.08 0.16 0.16 - 0.02 mAIOH MAX -0.8 -0.4 -1 -0.4 -2 -1 -4 -4 -4 -24 -24 -24 -6 -12 mAIOL MAX 16 8 20 8 20 20 4 4 4 24 24 24 6 12 mA
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN TTL LS S ALS AS F SN74HC
CD74HC
CD74HCT
MIN 25 30 75 50 100 100 25 20 16tw CLR LOW 20 20 10 10 5 5 20 24 30
CLK HIGH 20 20 7 10 4 4 20 24 30
CLK LOW 20 20 7 10 5 5 20 24 30tsu DATA INPUT 20 20 5 10 3 3 25 24 30
CLR INACTIVE 25 25 5 6 6 5 25 - -MIN 5 5 3 0 1 1 0 5 5
25 30 15 18 9 9 38 53 5335 30 22 23 13 13 38 53 5330 25 12 15 7.5 7.5 38 53 5035 25 17 17 10 9.5 38 53 50
INPUT OUTPUT MAX or MIN AC11
CD74AC
CD74ACT
LV3V
LV5V
MIN 125 100 114 45 75tw CLR LOW 4 4 4 5 5
CLK HIGH 4 5 5 5 5
CLK LOW 4 5 5 5 5tsu DATA INPUT 5.5 2 2 5 4
CLR INACTIVE 5.5 - - 5 5MIN 0.5 2 2 1 1
6.8 12.2 13 15.5 9.59.3 12.2 13 15.5 9.56.9 12.2 11.5 17 10.59..3 12.2 11.5 17 10.5
UNIT fmax : MHz, other : ns
tPHL
tPLH
tPHL
MIN
MAX
MAXANY Q or Q
PARAMETER
fmax
thtPLH
MIN
CLR
CLK
ANY Q or Q
PARAMETER
fmax
MIN
MIN
thtPLH
CLR ANY Q or QtPHL
MAX
MAXtPLH
CLK ANY Q or QtPHL
175QUAD D-TYPE FLIP-FLOPS
Complementary Outputs (Q, Q) Buffered Clock and Direct Clear Inputs Asynchronous Clear Function
242
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
Cn
A0
A1
A2
A3
B0
B1
B2
B3
P
G
Cn + 4
F0
F1
F2
F3
S3
S2
S1
S0
M
3
4
5
6
18
19
20
21
22
23
1
2
8
7
A = B
17
16
15
13
11
14
10
9
181ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS
Full Look-Ahead for High-Speed Operations on Long Words Input Clamping Diodes Minimize Transmission-Line Effects
243PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
FUNCTION TABLE (ACTIVE LOW)
M = L; ARITHMETIC OPERATIONSSELECTION
ACTIVE-LOW DATA
LLLL
LLL
F = A + BF = 1F = A + B
Cn = L(no carry)
Cn = H(with carry)
F = ABF = A
M = HLOGIC
FUNCTIONS3 S2
LL
S1
L
HLHL
L
LLHH
HHLL F = BH
L F = A ⊕ BLL F = A + BHH F = ABLH F = A ⊕ BHHHHHH
H
HHLL
HHLL
L H F = BF = A + BF = 0F = ABF = ABF = A
F = AB MINUS 1F = MINUS 1(2's COMP)F = A PLUS (A + B)
F = AB MINUS 1F = A MINUS 1
F = AB PLUS (A + B)F = A MINUS B MINUS 1F = A + BF = A PLUS (A + B)F = A PLUS BF = AB PLUS (A + B)F = (A + B)F = A PLUS A*F = AB PLUS AF = AB PLUS AF = A
F = ABF = 0F = A PLUS (A + B) PLUS 1
F = ABF = A
F = AB PLUS (A + B) PLUS 1F = A MINUS BF = (A + B) PLUS 1F = A PLUS (A + B) PLUS 1F = A PLUS B PLUS 1F = AB PLUS (A + B) PLUS 1F = (A + B) PLUS 1F = A PLUS A PLUS 1F = AB PLUS A PLUS 1F = AB PLUS A PLUS 1F = A PLUS 1
LHLHL
LHHH
HLLH
H H H
S0
FUNCTION TABLE (ACTIVE HIGH)
M = L; ARITHMETIC OPERATIONSSELECTION
ACTIVE-HIGH DATA
L
L
L
L
L
L
L
F = AB
F = 0
F = AB
Cn = H(no carry)
Cn = L(with carry)
F = A + B
F = A
M = HLOGIC
FUNCTIONS3 S2
L
L
S1
L
H
L
H
LL
L
L
HH
H
H
LL F = BH
L F = A ⊕ BL
L F = ABH
H F = A + BL
H F = A ⊕ BH
H
H
H
HH
H
H
H
L
L
H
H
L
L
L H F = B
F = AB
F = 1
F = A + B
F = A + B
F = A
F = A + B
F = MINUS 1(2's COMPL)
F = A PLUS AB
F = A + B
F = A
F = (A + B) PLUS AB
F = A MINUS B MINUS 1
F = AB MINUS 1
F = A PLUS AB
F = A PLUS B
F = (A + B) PLUS AB
F = AB MINUS 1
F = A PLUS A*
F = (A + B) PLUS A
F = (A + B) PLUS A
F = A MINUS 1
F = (A + B) PLUS 1
F = 0
F = A PLUS AB PLUS 1
F = (A + B) PLUS 1
F = A PLUS 1
F = (A + B) PLUS AB PLUS 1
F = A MINUS B
F = AB
F = A PLUS AB PLUS 1
F = A PLUS B PLUS 1
F = (A + B) PLUS AB PLUS 1
F = AB
F = A PLUS A PLUS 1
F = (A + B) PLUS A PLUS 1
F = (A + B) PLUS A PLUS 1
F = A
L
H
L
H
L
L
H
H
H
H
L
L
H
H H H
S0
RECOMMENDED OPERATING CONDITIONS
MAX or MIN TTL LS S AS UNIT
MAX 150 37 220 200 mA
IOH -0.8 -0.4 -1 -2 mA
- - - -3 mA
IOL 16 8 20 20 mA
16 8 20 48 mA
MAXG
All outputs exceptG MAXG
PARAMETER
ICC
All outputs exceptA = B
SWITCHING CHARACTERISTICS
PARAMETER MAX or MIN TTL LS S AS
tPLH 18 27 10.5 9tPHL 19 20 10.5 9tPLH 43 38 18.5 12tPHL 41 38 18.5 12tPLH 19 26 12 9tPHL 18 20 12 9tPLH 42 32 16.5 9.5tPHL 32 20 16.5 8UNIT: ns
MAX
Ai , Bi Fi MAX
MAX
A, B Cn 4 MAX
Cn F
INPUT OUTPUT
Cn Cn 4
244
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
Cn+zor
Cn+z
Cn+yor
Cn+y
Cn+xor
Cn+x
(9)
(15)P2 or X2
(14)G2 or Y2
(10)
(6)
(7)
P3 or X3
P or X
G or Y
(5)G3 or Y3
(11)
(2)P1 or X1
(1)G1 or Y1
(12)(4)
P0 or X0(3)
G0 or Y0(13)
Cn or Cn
182LOOK-AHEAD CARRY GENERATORS
245PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
INPUTSG1
G OUTPUTS
P3 P0OUTPUT
XXLX
LXXX
LXX
G2X X
XXL
XXXL
L
L
HL
G3 G
L
P2XLLL
P1XXLL
INPUTS
Cn+y OUTPUTS
G1 G0 P1 P0 Cn Cn+yOUTPUT
XLL
LXX
XLX
XXL
XXH
HHH
L
INPUTSG0
Cn+z OUTPUTS
P2 P1OUTPUT
XXLL
LXXX
G1XXXL
XXXH
H
HHL
G2 P0 Cn Cn+z
HXLXX
XXLX
XLLL
P OUTPUTS
OUTPUT
L
H
INPUTS
LL LP0P2P3 P1
LP
INPUTS
Cn+x OUTPUTS
CnOUTPUT
XH H
Cn+xH
L
G0LX
XP0
L
All other combinations
All othercombinations
All othercombinations All other combinations
All othercombinations
FUNCTION TABLE
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL S AS UNIT
ICC MAX 72 109 36 mAIOH MAX -0.8 -1 -2 mAIOL MAX 16 20 20 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN TTL S AS
tPLH 10 10 10tPHL 10.5 10.5 9.5tPLH 7 7 10.5tPHL 7 7 6tPLH 7.5 7.5 12tPHL 10.5 10.5 8tPLH 6.5 6.5 7.5tPHL 10 10 6UNIT: ns
MAX
MAX
P or G
P
G
P
Cn Cn + X, Cn + Yor Cn + Z MAX
P or G MAXCn + X, Cn + Yor Cn + Z
246
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
Q26
B
C
DEFGHI
J
KL
MNO
P
10P2
Q37
9P3
RC13
TC12
Q Q
PPL
FF2
T
CL
QP
PL
FF3
T
CL
Q
B
PL
Q0
11
3
U/D5
CP14
15
PPL
FF0
T
CL
Q
P0
Q12
CE
C
DEFGHI
J
KL
MNO
P4
1
PPL
FF1
T
CL
Q
P1
Q Q
190SYNCHRONOUS UP/DOWN DECADE COUNTER
247PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS ALS SN74HC
CD74HC UNIT
ICC MAX 105 35 22 0.08 0.16 mAIOH MAX -0.8 -0.4 -0.4 -4 -4 mAIOL MAX 16 8 8 4 4 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN TTL LS ALS SN74HC
CD74HC
fmax MIN 20 20 25 17 25tw 25 25 20 30 20
35 35 20 30 25tsu MIN 20 20 20 38 15th MIN 0 5 5 5 2tPLH 33 33 30 66 49tPHL 50 50 30 66 49tPLH 22 32 21 60 44tPHL 50 40 21 60 44tPLH 20 20 20 30 31tPHL 24 24 20 30 31tPLH 24 24 18 48 43tPHL 36 36 18 48 43tPLH 42 42 31 63 53tPHL 52 52 31 63 53tPLH 45 45 37 57 38tPHL 45 45 28 57 38tPLH 33 33 25 48 41tPHL 33 33 25 48 41
UNIT fmax : MHz other : ns
MAX
MIN
MAX
MAX
MAX
MAX
MAX
MAX
CLK (CP)
LOAD (PL)
Q
DATA Q
Data , high or lowData hold time
LOAD(PL)
CLK(CP)
D/U(U/D)
RCO(RC)
RCO(RC)
MAX/ MIN(TC)
D/U(U/D)
CLK(CP) Q
CLK(CP)
MAX/MIN(TC)
248
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
SC1
1DR
7
9
SC1
1DR
6
10
SC1
1DR
2
1
SC1
1DR
315
11
14
5
4
12
13
QA
QB
QC
QD
RCO
CTEN
D/U
LOAD
MAX/MIN
CLK
A
B
C
D
191SYNCHRONOUS UP/DOWN COUNTERS
Count Enable Control Input Ripple Clock Output for Cascading Asynchronously Presentable with Load Control
249PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS ALS SN74HC
CD74HC
CD74HCT UNIT
ICC MAX 105 35 22 0.08 0.16 0.16 mAIOH MAX -0.8 -0.4 -0.4 -4 -4 -4 mAIOL MAX 16 8 8 4 4 4 mA
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN TTL LS ALS SN74HC
CD74HC
CD74HCT
MIN 20 20 30 17 25 25tw CLK 25 25 16.5 30 20 20
LOAD 35 35 20 30 25 25tsu DATA MIN 20 20 20 38 15 15th DATA MIN 0 5 5 5 2 2
33 33 30 66 49 5050 50 30 66 49 5022 32 21 60 44 4850 40 21 60 44 4820 20 20 30 31 3424 24 20 30 31 3424 24 18 48 43 4436 36 18 48 43 4442 42 31 63 53 5352 52 31 63 53 5345 45 37 57 38 3845 45 28 57 38 3833 33 25 48 41 4833 33 25 48 41 48
UNIT fmax : MHz, other : ns
CLK
CLK
RIPPLECLK
QA, QBQC, QD
QA, QBQC, QD
QA, QBQC, QD
LOAD
DATAA, B, C, D
MAX or MIN
MAX
CLK
D/U
MAX
MIN
MAX
MAX
MAX
MAX
MAX
tPHL
tPLH
tPHL
tPLH
PARAMETER
tPLH
tPHL
tPLH
fmax
tPHL
tPLH
MAX or MIN
tPHL
tPLH
tPHLD/U
RIPPLECLK
tPLH
tPHL
250
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
(2)
(4)
OUTPUT QB
DOWN
(5)UP
(14)CLR
(1)DATAINPUT B
(10)DATAINPUT C
(15)DATAINPUT A
(6)OUTPUT QC
(3)OUTPUT QA
(12)CO
T
S
R
T
S
R
T
S
R
T
S
R
(11)LOAD
(13)BO
(9)DATAINPUT D
(7)OUTPUT QD
192PRESETTABLE SYNCHRONOUS 4-BITUP/DOWN COUNTERS
251PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
FUNCTION TABLE
CLOCK UP RESET FANCTIONCLOCKDOWN
PARALLELLOAD
LX
↑
H
X
X
X
LH
L
H
↑
L
X
H
H
Load Preset inputs
Reset
Count Up
Count Down
NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don't Care, ↑ = Transition from Low to High Level
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN CD74HC UNIT
ICC MAX 0.16 mAIOH MAX -4 mAIOL MAX 4 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN CD74HC
352430
tsu MIN 240
24tPLH 38tPHL 38tPLH 38tPHL 38tPLH 65tPHL 65tPLH 65tPHL 65tPLH 66tPHL 66tPHL MR Qn MAX 60UNIT:ns
TCD
QnPL MAX
CPD
CPD
Qn
Qn
MAX
MAX
MAX
MAX
th
Pn to PLPn to PL
CPD to CPU, CPD to CPUMIN
CPU
CPD
TCU
MINtwCPU, CPD
PLMR
252
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
SC1
1DR
7
9
11
4
5
14
12
13
QD
BO
LOAD
CO
CLR
D
SC1
1DR
6
10
QC
C
SC1
1DR
2
1
QB
B
SC1
1DR
315
QAA
UP
DOWN
S
R
193SYNCHRONOUS UP/DOWN DUAL CLOCKCOUNTERS
Parallel Asynchronous Load for Modulo-N Count Lengths Asynchronous Clear
253PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS ALS F SN74HC
CD74HC
CD74HCT UNIT
ICC MAX 102 34 22 54 0.08 0.16 0.16 mAIOH MAX -0.4 -0.4 -0.4 -1 -4 -4 -4 mAIOL MAX 16 8 8 20 4 4 4 mA
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN TTL LS ALS F SN74HC
CD74HC
CD74HCT
fmax MIN 25 25 30 85 17 17 15tw MIN 20 20 20 4 30 30 35tsu DATA MIN 20 20 20 3.5 28 24 22th DATA MIN 0 5 5 2.5 5 0 0tPLH 26 26 16 9 41 38 41tPHL 24 24 18 9 41 38 41tPLH 24 24 16 9 41 38 41tPHL 24 24 18 9 41 38 41tPLH 38 38 19 9 63 65 60tPHL 47 47 17 13 63 65 60tPLH 40 40 30 11 65 66 69tPHL 40 40 28 13 65 66 69tPHL CLR ANY Q MAX 35 35 17 12 60 60 65UNIT fmax : MHz, other : ns
CO MAX
BO MAX
ANY Q MAX
ANY Q MAX
DOWN
UP orDOWN
LOAD
PARAMETER
UP
254
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
C1
1S
TwoIdenticalChannels
NotShown†
9
2
11
7
S0
S1
SR SER SL SER
QA QD
1CLR
10
1R
CLK
R
C1
1S
1R
R
A3
D6
15 12
Parallel Inputs
Parallel Outputs
† I/O ports not shown: QB (14) and QC (13)
1944-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTERS
Direct Overriding Clear Parallel-to-Serial, Serial-to-Parallel Conversions Left or Right Shifts
255PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS S AS SN74HC
CD74HC
CD74HCT UNIT
ICC MAX 63 23 135 53 0.1 0.16 0.16 mAIOH MAX -0.8 -0.4 -1 -2 -4 -4 -4 mAIOL MAX 16 8 20 20 4 4 4 mA
LEFT
FUNCTION TABLEOUTPUTSINPUTS
XX
MODE SERIAL PARALLEL
H
LHHH
CLEAR
HH
RIGHT
HLLH
XL
X
XXXXXHL
↑↑↑↑↑
X
HL
XX
XX
AX
XX
aX
XX
BX
XX
bX
XX
CX
XX
cX
XX
DX
XX
dX
XX
QC
L
HQCn
dQD0
QCn
L
QA
L
QBn
L
aQA0
H
QBn
QB
L
QCn
QAn
bQB0
QAn
QCn
L
QDn
QBn
cQC0
QBn
QDnH
CLOCK QD
H X X X X X X QD0QA0 QB0 QC0L
XS1 S0
XHHHLLL
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN TTL LS S AS SN74HC
CD74HC
CD74HCT
MIN 25 25 70 80 25 20 18tw CLR 20 20 12 4.5 20 24 24
CLK "H" 20 20 7 4 20 24 24CLK "H" 20 20 7 7 20 24 24
tsu Mode Control 30 30 11 9.5 25 24 30DATA MIN 20 20 5 4 25 21 21
CLR INACTIVE 25 25 9 6 - - -MIN 0 0 3 0.5 0 0 0
CLEAR ANY MAX 30 30 18.5 12 38 42 6022 22 12 7 36 53 5626 26 16.5 7 36 53 56
UNIT fmax : MHz, other : ns
MIN
MAXCLOCK ANY
PARAMETER
fmax
thtPHL
tPLH
tPHL
256
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
J K A
SH/LD
2 3 4
B
5
CLK
CLR
C
6
D
7
9
10
1
C1
1RR
1S
QA
15
C1
1RR
1S
QB
14
C1
1RR
1S
QC
13
C1
1RR
1S
QD
12
QD
11
Serial Inputs Parallel Inputs
Parallel Outputs
1954-BIT PARALLEL-ACCESS SHIFT REGISTERS
Direct Overriding Clear Parallel-to-Serial, Serial-to-Parallel Conversions
257PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS S AS SN74HC
CD74HC UNIT
ICC MAX 63 21 109 57 0.1 0.16 mAIOH MAX -0.8 -0.4 -1 -2 -4 -4 mAIOL MAX 16 8 20 20 4 4 mA
J
FUNCTION TABLEOUTPUTSINPUTS
XL
SHIFT/LOAD
SERIAL PARALLEL
H
LHHH
CLEAR
HH
K
HHHH
X
L
XXXLLHH
↑
↑↑↑↑
X
HL
XX
HL
AX
XX
aX
XX
BX
XX
bX
XX
CX
XX
cX
XX
DX
XX
dX
XX
QC
H
QCnQCn
dQD0
QCnQCn
QA
L
QA0L
aQA0
HQAn
QB
L
QA0QAn
bQB0
QAnQAn
L
QBnQBn
cQC0
QBnQBnH
CLOCK QD
L
QCnQCn
dQD0
QCnQCn
QD
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN TTL LS S AS SN74HC
CD74HC
fmax MIN 30 30 70 70 25 20tw CLOCK 16 16 7 4 20 24
CLEAR 12 12 12 7.2 20 24tsu Shift / Load 25 25 11 8 25 30
Serial & Pararel Data MIN 20 15 5 3.5 25 30Clear Inactive Data 25 25 9 6 25 30
MAX 10 20 6 - - -MIN 0 0 3 1 0 -
CLEAR MAX 30 30 18.5 11.5 38 4522 22 12 8.5 36 5326 26 16.5 10.5 36 53
UNIT fmax : MHz, other : ns
MIN
CLOCKQA, QD
MAX
PARAMETER
TRELEASE
tPHL
tPLH
tPHL
th
258
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
CLR
Cext
Rext/Cext
R
B
A
Q
Q
221DUAL MONOSTABLE MULTIVIBRATORS
Overriding Clear Terminates Outputs Pulse
259PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
FUNCTION TABLE
QBOUTPUTSINPUTS
LX
ACLEAR Q
XHH
X
X
L
L
HLL†L†
X
L
↑↓
↑
X
HH
HH†H†
See explanation of function table on page† These lines of the functional tables assume that the indicated steady-state conditions at the A and B inputs have been set up long enough to complete any pulse started before the set up.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS CD74HC
CD74HCT
LV3V
LV5V UNIT
ICC MAX 80 27 0.16 0.16 0.28 0.65 mAIOH MAX -0.8 -0.4 -4 -4 -6 -12 mAIOL MAX 16 8 4 4 6 12 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN TTL LS CD74HC
CD74HCT
LV3V
LV5V
A (HC, LV: A) 70 70 63 63 27.5 16B 55 55 63 63 27.5 16
A (HC, LV: A) 80 80 51 51 27.5 16B 65 65 51 51 27.5 16
tPHL Q 27 55 48 57 22 13tPLH Q 40 65 54 56 22 13
UNIT: ns
Clear MAX
tPLH
tPHL
MAX
MAXQ
Q
260
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
Y0(15)
Y1(14)
Y2(13)
Y3(12)
Y4(11)
Y5(10)
Y6(9)
Y7(7)
G2(5)
G1(6)
C(3)
GL(4)
TG
TG
B(2)
TG
TG
A(1)
TG
TG
2373-TO-8 LINE DECODER DEMULTIPLEXER WITH ADDRESS LATCHES
261PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
FUNCTION TABLEINPUTS
OE0 Y0
OUTPUTS
LH
A1
LHH
LX X
X
HH
L
OE1
HHHHHHH
LLLLLLLL
XH
L
HH
LL
X
A2XXLL
HH
X
XX
HL
HL
X
LL
A0
HL
HL
HH
L
LLLLLLL
Y1
L
H
L
LLLLLL
Y2
L
H
L
L
LLLLL
Y3
L
H
L
LL
LLLL
Y4
L
H
L
LLL
LLL
Y5
L
H
L
LLLL
LL
Y6
L
H
L
LLLLL
L
Y7
L
H
L
LLLLLL
L L L L L L LXX
H
LLLLLLLL
LE
Depends upon the address previously applied while LE was at a logic low.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN SN74HC
CD74HC
CD74HCT UNIT
ICC MAX 0.08 0.16 0.16 mAIOH MAX -4 -4 -4 mAIOL MAX 4 4 4 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN SN74HC
CD74HC
CD74HCT
tw MIN 20 15 15tsu MIN 19 15 15th MIN 5 9 5tPLH 48 48 57tPHL 48 48 57tPLH 44 44 60tPHL 44 44 60UNIT:ns
Y
MAX
MAXOE
An
An to LE
Y
LE Pulse WidthAn to LE
262
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
E3(6)
(5)
(4)
(1)
(2)
(3)
E2
E1
A0
A1
A2
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
(15)
(14)
(13)
(12)
(11)
(10)
(9)
(7)
2383-TO-8-LINE DECODERS/DEMULTIPLEXERS
263PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
FUNCTION TABLEINPUTS
E3
ENABLE
E2 E1 A2
ADDRESS
A1 A0
OUTPUTS
Y1 Y2 Y3 Y4 Y5 Y6X X HL X XX H XH L LH L LH L LH L LH L LH L LH L LH
Note: H = High Voltage Level, L = Low Volltage Level, X = Don’t Care
L L
X X X
L L LL L
L
X X XX X X
L
L
HH
HH
HH
HH
H
L
L
HH
H
LHHH
H
HH
HLH
L L L L L L L LL L L L L L L LL
LLLLLLL
LLLLLL
LLLLL
LLLL
LLL
LL L
L L L L L L LLLL L L L L L L
L L L L L LL L L L L
L L L LL L L
L LL
Y7Y0
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN CD74HC
CD74HCT
CD74AC
CD74ACT UNIT
ICC MAX 0.16 0.16 0.16 0.16 mAIOH MAX -4 -4 -24 -24 mAIOL MAX 4 4 24 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN CD74HC
CD74HCT
CD74AC
CD74ACT
tPLH 45 53 15 15tPHL 45 53 15 15tPLH - - 11.9 11.9tPHL - - 11.9 11.9tPLH - - 16.6 16.6tPHL - - 16.6 16.6UNIT:ns
E1, E2
E3
MAXYAddress
MAX
MAX
Y
Y
264
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1
2 181Y1
1OE
1A1
4 161Y21A2
6 141Y31A3
8 121Y41A4
19
11 92Y1
2OE
2A1
13 72Y22A2
15 52Y32A3
17 32Y42A4
240OCTAL BUFFERS/LINE DRIVERS/LINE RECEIVERS
3-State Outputs Drive Bus Lines or Buffer Memory Address Registers PNP Inputs Reduce DC Loading 74AC11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series) 74ACT11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)
265PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LS S ALS ALSA-1 AS F SN74
HCCD74
HCSN74HCT
CD74HCT
SN74BCT ABT LVT
3V UNIT
ICCH MAX 27 135 11 11 17 29 0.08 0.16 0.08 0.16 31 0.25 0.19 mAICCL MAX 44 150 23 23 75 75 0.08 0.16 0.08 0.16 71 30 5 mAICCZ MAX 50 150 25 25 38 63 0.08 0.16 0.08 0.16 9 0.25 0.19 mAIOH MAX -15 -15 -15 -15 -15 -15 -6 -6 -6 -6 -15 -32 -32 mAIOL MAX 24 64 24 48 64 64 6 6 6 6 64 64 64 mA
PARAMETER MAX or MIN LVTH3V
AC11
SN74AC
CD74AC
ACT11
SN74ACT
CD74ACT AHC AHCT LV
3VLV5V
LVC3V
LVCZ3V UNIT
ICCH MAX 0.19 0.08 0.04 0.16 0.08 0.04 0.16 0.04 0.04 - 0.02 0.01 0.1 mAICCL MAX 5 0.08 0.04 0.16 0.08 0.04 0.16 0.04 0.04 - 0.02 0.01 0.1 mAICCZ MAX 0.19 0.08 0.04 0.16 0.08 0.04 0.16 0.04 0.04 - 0.02 0.01 0.1 mAIOH MAX -32 -24 -24 -24 -24 -24 -24 -8 -8 -8 -16 -24 -24 mAIOL MAX 64 24 24 24 24 24 24 8 8 8 16 24 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN LS S ALS ALSA-1 AS F SN74
HCCD74
HCSN74HCT
CD74HCT
SN74BCT ABT LVT
3V
tPLH 14 7 9 9 6.5 8 25 30 32 33 5.6 4.8 3.8tPHL 18 7 9 9 6.5 5.7 25 30 32 33 4 4.8 4tPZH 23 10 13 13 6.4 6.1 38 - 44 - 8.8 5.2 4.6tPZL 30 15 18 18 9 10 38 - 44 - 10.5 6.2 4.4tPHZ 25 9 10 10 5 6.3 38 - 44 - 8.1 6.4 4.4tPLZ 20 15 12 12 9.5 9.5 38 - 44 - 9.5 5.8 4.3
PARAMETER INPUT OUTPUT MAX or MIN LVTH3V
AC11
SN74AC
CD74AC
ACT11
SN74ACT
CD74ACT AHC AHCT LV
3VLV5V
LVC3V
LVCZ3V
tPLH 3.8 8.4 7 7.2 10.6 9.5 8.6 8.5 9.5 12.5 8.5 6.5 6.5tPHL 4 7.2 6.5 7.2 8.7 8.5 8.6 8.5 9.5 12.5 8.5 6.5 6.5tPZH 4.6 9.2 8 12 12.5 9.5 13.4 10.5 13 16 10.5 8 8tPZL 4.4 8.7 8.5 12 12.3 10.5 13.4 10.5 13 16 10.5 8 8tPHZ 4.4 6.6 9.5 12 10 10.5 13.4 10.5 13 17 15.5 7 7tPLZ 4.3 7.7 9.5 12 10.8 10.5 13.4 10.5 13 17 15.5 7 7UNIT: ns
G Y MAX
MAX
MAX
MAX
MAX
Y MAX
Y
Y
Y
G
G
A
A Y
G
266
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1
2 181Y1
1OE
1A1
4 161Y21A2
6 141Y31A3
8 121Y41A4
19
11 92Y1
2OE
2A1
13 72Y22A2
15 52Y32A3
17 32Y42A4
241OCTAL BUFFERS/LINE DRIVERS/LINE RECEIVERS
3-State Outputs Drive Bus Lines or Buffer Memory Address Registers PNP Inputs Reduce DC Loading
267PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LS S ALS AS F SN74HC
CD74HC
CD74HCT
SN74BCT ABT LVTH
3VSN74
AC UNIT
ICCH MAX 27 160 18 35 60 0.08 0.16 0.16 43 0.25 0.19 0.04 mAICCL MAX 46 180 26 90 90 0.08 0.16 0.16 85 30 5 0.04 mAICCZ MAX 54 180 30 56 90 0.08 0.16 0.16 10 0.25 0.19 0.04 mAIOH MAX -15 -15 -15 -15 -15 -6 -6 -6 -15 -32 -32 -24 mAIOL MAX 24 64 24 64 64 6 6 6 64 64 64 24 mA
PARAMETER MAX or MIN SN74ACT
CD74ACT UNIT
ICCH MAX 0.04 0.16 mAICCL MAX 0.04 0.16 mAICCZ MAX 0.04 0.16 mAIOH MAX -24 -24 mAIOL MAX 24 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN LS S ALS AS F SN74HC
CD74HC
CD74HCT
SN74BCT ABT LVTH
3VSN74
AC
tPLH 18 9 11 6.2 6.2 29 33 38 4.9 4.6 3.5 7.5tPHL 18 9 10 6.2 6.5 29 33 38 5.9 4.6 3.4 7.5tPZH 23 12 21 9 6.7 38 - - 8.7 6.8 4.5 9.5tPZL 30 15 21 7.5 8 38 - - 9.4 6.8 4.4 9.5tPHZ 25 9 10 6 7 38 - - 8.1 7.1 4.5 10.5tPLZ 20 15 15 9 7 38 - - 9.9 5.9 4.7 10.5tPZH 23 12 21 10.5 6.7 38 - - 8.7 6.8 4.5 9.5tPZL 30 15 21 8.5 8 38 - - 9.4 6.8 4.4 9.5tPHZ 25 9 10 7 7 38 - - 8.1 7.1 4.5 10.5tPLZ 20 15 15 12 7 38 - - 9.9 5.9 4.7 10.5
PARAMETER INPUT OUTPUT MAX or MIN SN74ACT
CD74ACT
tPLH 9.5 9.6tPHL 8.5 9.6tPZH 9.5 13.4tPZL 10.5 13.4tPHZ 10.5 13.4tPLZ 10.5 13.4tPZH 9.5 13.4tPZL 10.5 13.4tPHZ 10.5 13.4tPLZ 10.5 13.4UNIT: ns
2G Y MAX
2G Y MAX
1G Y MAX
1G Y MAX
A Y MAX
2G
2G
Y MAX
Y MAX
1G
1G Y MAX
Y MAX
MAXYA
268
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
B4
B3
B2
B1
OEBA
8
9
10
11
13
A4
A3
A2
A1
OEAB
6
5
4
3
1
243QUADRUPLE BUS TRANSCEIVERS
Two-Way Asynchronous Communication Between Data Buses PNP Inputs Reduce DC Loading
269PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
GBA
FUNCTION TABLE
INPUTS
GAB
L
HL H
OPERATION
B to AA to B
IsolationLatch A and B (A = B)
H HL
L
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LS ALS AS SN74HC
CD74HC
CD74HCT UNIT
ICCH MAX 38 25 44 0.08 0.16 0.16 mAICCL MAX 50 30 74 0.08 0.16 0.16 mAICCZ MAX 54 32 56 0.08 0.16 0.16 mAIOH MAX -15 -15 - - -6 -6 mAIOL MAX 24 24 64 6 6 6 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN LS ALS AS SN74HC
CD74HC
CD74HCT
tPLH A or B A or B MAX 18 11 7.5 25 27 33tPHL A or B A or B MAX 18 11 6.5 25 27 33tPZH 23 20 9 38 45 51tPZL 30 20 7.5 38 45 51tPHZ 25 14 6.5 38 45 53tPLZ 20 22 9 38 45 53tPZH 23 20 10.5 38 45 51tPZL 30 20 8.5 38 45 51tPHZ 25 14 7 38 45 53tPLZ 20 22 11 38 45 53UNIT: ns
MAX
MAXB
BGAB
GAB
GAB
GAB
A
A
MAX
MAX
270
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1
2 181Y1
1OE
1A1
4 161Y21A2
6 141Y31A3
8 121Y41A4
19
11 92Y1
2OE
2A1
13 72Y22A2
15 52Y32A3
17 32Y42A4
244OCTAL BUFFERS/LINE DRIVERS/LINE RECEIVERS
3-State Outputs Drive Bus Lines or Buffer Memory Address Registers PNP Inputs Reduce DC Loading 74AC11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series) 74ACT11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)
271PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LS S ALS ALSC-1 AS F SN74
HCCD74
HCSN74HCT
CD74HCT
SN74BCT
SN64BCT ABT LVT
3VLVTH
3V LVTT LVTZ3V UNIT
ICCH MAX 27 160 17 17 34 60 0.08 0.16 0.08 0.16 40 40 0.25 0.19 0.19 0.19 0.225 mAICCL MAX 46 180 24 24 90 90 0.08 0.16 0.08 0.16 80 80 30 5 5 12 15 mAICCZ MAX 54 180 27 27 54 90 0.08 0.16 0.08 0.16 10 10 0.25 0.19 0.19 0.19 0.225 mAIOH MAX -15 -15 -15 -15 -15 -15 -6 -6 -6 -6 -15 -15 -32 -32 -32 -32 -32 mAIOL MAX 24 64 24 48 64 64 6 6 6 6 64 64 64 64 64 64 64 mA
PARAMETER MAX or MIN AC11
SN74AC
CD74AC
ACT11
SN74ACT
CD74ACT AHC AHCT LV
3VLV5V
LVC3V
LVCH3V
LVCZ3V
ALVC3V
ALVCH3V UNIT
ICCH MAX 0.08 0.04 0.16 0.08 0.04 0.16 0.04 0.04 - 0.02 0.01 0.01 0.1 0.01 0.01 mAICCL MAX 0.08 0.04 0.16 0.08 0.04 0.16 0.04 0.04 - 0.02 0.01 0.01 0.1 0.01 0.01 mAICCZ MAX 0.08 0.04 0.16 0.08 0.04 0.16 0.04 0.04 - 0.02 0.01 0.01 0.1 0.01 0.01 mAIOH MAX -24 -24 -24 -24 -24 -24 -8 -8 -8 -16 -24 -24 -24 -24 -24 mAIOL MAX 24 24 24 24 24 24 8 8 8 16 24 24 24 24 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN LS S ALS ALSC-1 AS F SN74
HCCD74
HCSN74HCT
CD74HCT
SN74BCT
SN64BCT ABT
tPLH 18 9 10 10 6.2 6.2 29 33 35 38 5 5.3 4.6tPHL 18 9 10 10 6.2 6.5 29 33 35 38 5.5 6 4.6tPZH 23 12 20 20 9 6.7 38 - 44 - 8.7 9 5.1tPZL 30 15 20 20 7.5 8 38 - 44 - 8.9 9.4 6.1tPHZ 25 9 10 10 6 7 38 - 44 - 7.7 8 6.6tPLZ 20 15 13 13 9 7 38 - 44 - 8.9 9.8 5.7
PARAMETER INPUT OUTPUT MAX or MIN LVT3V
LVTH3V LVTT LVTZ
3VAC11
SN74AC
CD74AC
ACT11
SN74ACT
CD74ACT AHC AHCT LV
3V
tPLH 3.5 3.5 4.1 4.1 7.3 7.5 8.2 9.9 10 9.6 8.5 9.5 13.5tPHL 3.3 3.3 4.1 4.1 6.9 7.5 8.2 9.2 10 9.6 8.5 9.5 13.5tPZH 4.5 4.5 5.2 5.2 8.5 8 12 12.5 9.5 13.4 10.5 13 16tPZL 4.4 4.4 5.2 5.2 8.5 8.5 12 11.4 10.5 13.4 10.5 13 16tPHZ 4.4 4.4 5.6 5.6 7.3 9.5 12 10.4 10.5 13.4 10.5 13 18tPLZ 4.4 4.4 5.1 5.1 8.2 9.5 12 11.2 10.5 13.4 10.5 13 18
PARAMETER INPUT OUTPUT MAX or MIN LV5V
LVC3V
LVCH3V
LVCZ3V
ALVC3V
ALVCH3V
tPLH 8.5 5.9 5.9 5.9 2.8 2.8tPHL 8.5 5.9 5.9 5.9 2.8 2.8tPZH 10.5 7.6 7.6 7.6 4.5 4.5tPZL 10.5 7.6 7.6 7.6 4.5 4.5tPHZ 15.5 6.5 5.8 6.5 4.2 4.2tPLZ 15.5 6.5 5.8 6.5 4.2 4.2UNIT: ns
G Y MAX
G Y MAX
G Y MAX
A Y MAX
A Y MAX
G Y MAX
A
G
G
MAX
Y MAX
Y MAX
Y
272
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
DIR
OE
A1
B1
To Seven Other Channels
1
2
19
18
245OCTAL BUS TRANSCEIVERS
3-State Outputs Drive Bus Lines Directly PNP Inputs Reduce DC Loading on Bus Lines 74AC11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series) 74ACT11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series)
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LS ALS ALSC-1 AS F SN74
HCCD74
HCSN74HCT
CD74HCT
SN74BCT
SN64BCT ABT ABTH LVT
3VLVTH
3VLVTR
3V UNIT
ICCH MAX 70 45 45 97 90 0.08 0.16 0.08 0.16 57 57 0.25 0.25 0.19 0.19 0.19 mAICCL MAX 90 55 55 143 120 0.08 0.16 0.08 0.16 90 90 30 30 5 5 12 mAICCZ MAX 95 58 58 123 110 0.08 0.16 0.08 0.16 15 15 0.25 0.25 0.19 0.19 0.19 mAIOH (A port) MAX -15 -15 -15 -15 -3 -6 -4 -6 -4 -3 -3 -32 -32 -32 -32 -12 mAIOH (B port) MAX -15 -15 -15 -15 -15 6 -4 -6 -4 -15 -15 -32 -32 -32 -32 -32 mAIOL (A port) MAX 24 24 48 64 24 -6 4 6 4 24 24 64 64 64 64 32 mAIOL (B port) MAX 24 24 48 64 64 6 4 6 4 64 64 64 64 64 64 32 mA
PARAMETER MAX or MIN AC11
SN74AC
CD74AC
ACT11
SN74ACT
CD74ACT AHC AHCT LV
3VLV5V
LVC3V
LVCH3V
LVCZ3V
ALVC3V
ALVCH3V UNIT
ICCH MAX 0.08 0.04 0.16 0.08 0.04 0.16 0.04 0.04 - 0.02 0.01 0.01 0.1 0.01 0.01 mAICCL MAX 0.08 0.04 0.16 0.08 0.04 0.16 0.04 0.04 - 0.02 0.01 0.01 0.1 0.01 0.01 mAICCZ MAX 0.08 0.04 0.16 0.08 0.04 0.16 0.04 0.04 - 0.02 0.01 0.01 0.1 0.01 0.01 mAIOH (A port) MAX -24 -24 -24 -24 -24 -24 -8 -8 -8 -16 -24 -24 -24 -24 -24 mAIOH (B port) MAX -24 -24 -24 -24 -24 -24 -8 -8 -8 -16 -24 -24 -24 -24 -24 mAIOL (A port) MAX 24 24 24 24 24 24 8 8 8 16 24 24 24 24 24 mAIOL (B port) MAX 24 24 24 24 24 24 8 8 8 16 24 24 24 24 24 mA
FUNCTION TABLE
OPERATION
LLH
ENABLEG
LHX
B data to A busA data to B busIsolation
DIRECTIONCONTROL
DIR
273PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN LS ALS ALSC-1 AS F SN74
HCCD74
HCSN74HCT
CD74HCT
SN74BCT
SN64BCT ABT ABTH
tPLH 12 10 10 7.5 7 26 33 28 39 7 7 3.6 3.6tPHL 12 10 10 7 7 26 33 28 39 7 7 3.9 3.9tPZH 40 20 20 9 8 58 45 58 48 10.9 10.9 5.6 5.6tPZL 40 20 20 8.5 9 58 45 58 48 11.6 11.6 6.2 6.2tPHZ 28 10 10 5.5 7.5 50 45 50 45 9.3 9.3 5.9 5.9tPLZ 25 15 15 9.5 7.5 50 45 50 45 9.1 9.1 4.5 4.5
PARAMETER INPUT OUTPUT MAX or MIN LVT3V
LVTH3V
AC11
SN74AC
CD74AC
ACT11
SN74ACT
CD74ACT AHC AHCT LV
3VLV5V
LVC3V
tPLH 3.5 3.5 9.5 7 8.5 10 8 10 8.5 9.5 13.5 8.5 6.3tPHL 3.5 3.5 6.9 7 8.5 9.1 9 10 8.5 9.5 13.5 8.5 6.3tPZH 5.5 5.5 11.4 9 14 13.2 11 14 12 16 19 12 8.5tPZL 5.5 5.5 9.5 9.5 14 12.9 12 14 12 16 19 12 8.5tPHZ 5.9 5.9 9.5 10 14 12.9 11 14.4 11 16.5 22 16 7.5tPLZ 5 5 10.4 10 14 13.9 11 14.4 11 16.5 22 16 7.5
PARAMETER INPUT OUTPUT MAX or MIN LVCH3V
LVCZ3V
ALVC3V
ALVCH3V
tPLH 6.3 6.3 3.4 3.4tPHL 6.3 6.3 3.4 3.4tPZH 8.5 8.5 5.5 5.5tPZL 8.5 8.5 5.5 5.5tPHZ 7.5 7.5 5.5 5.5tPLZ 7.5 7.5 5.5 5.5
PARAMETER INPUT OUTPUT MAX or MIN LVTR3V
A B 4.2B A 4.4A B 4.6B A 4.1
B 5.5A 6B 6.6A 6.4B 6.1A 5.8B 5.2A 5.2
UNIT: ns
G A, B MAX
G A, B MAX
G A, B MAX
A, B B, A MAX
A, B B, A MAX
G A, B MAX
G A, B MAX
MAX
MAX
A, B
G
B, A
A, B
tPLH
G
G MAX
MAX
MAXtPHL
tPZH
tPZL
tPHZ
tPLZ G
MAX
MAXG
MAX
274
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
OUTPUTd
(10)
OUTPUTc
(11)
INPUTA
(7)
OUTPUTb
(12)
OUTPUTa
(13)
OUTPUTf
(15)
OUTPUTe
(9)
OUTPUTg
(14)
INPUTB
(1)
INPUTC
(2)
(4)
(5)
INPUTD
(8)
LAMP TESTINPUT
(3)
BI/RBOBLANKINGINPUT OR
RIPPLE-BLANKINGOUTPUT
RBIRIPPLE-BLANKING
INPUT
247BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS WITH RIPPLE BLANKING
Open-Collector Outputs Drive Indicators Directly Lamp-Test Provision Leading/Trailing Zero Suppression
275PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
DECIMALOR
FUNCTION
INPUTS
D
FUNCTION TABLE
C B A0
BI/RBOOUTPUTS
L123
4567
89
LLL
L
LL
HH
L
HH
HH
HH
1011
12131415
BIRBILT
LT
HH
H
H
HH
HH
HH
H
HHHH
H
XH
RBI
XH L
LLL
H
HH
HH
LLHH
LL
HH
HH
LHLH
L
L
H
H
H
H
HH
HH
HH
HH
LLH
aONOFFONON
OFF
ONON
ONON
ON
OFFOFF
OFFON
OFFOFF
OFFOFFON
HH
HH
HH
HH
XX
XXXX
XXXX
XXXX
XLXL
XLX
XLX
XLX
XLX
HHH
HH
H
H
LL
L
L
LLLL
LL
L
L
bON
ONON
ON
ONON
OFF
ON
OFFOFF
OFFOFFON
cON
OFFON
ON
ONON
ON
OFF
OFF
OFF
OFFOFFON
dONOFFONON
OFF
OFF
ON
ON
ON
OFFON
OFF
OFFOFFON
eONOFFON
ON
ON
OFF
OFF
ONOFF
OFFOFFON
fONOFF
OFF
ONON
ON
OFFOFF
ONOFF
OFFOFFON
g
OFFONON
OFF
ONON
ON
ONOFF
OFFOFFON
ON
ONOFFOFF
OFF
ON
ON
ON
OFF ON
OFFOFF
ON
ONON
ON
OFF
OFFOFFOFF
OFFOFFONOFF
ONON
ONON
OFF
ONON
ON ONON ON
OFF
RECOMMENDED OPERATING CONDITIONS
MAX or MIN TTL LS UNIT
MAX 103 13 mAVO (off) MAX 15 15 VIO (on) MAX 40 24 mAIOH MAX -0.2 -0.05 mAIOL MAX 8 3.2 mA
PARAMETER
ICC
a thru g
BI/RBO
SWITCHING CHARACTERISTICS
MAX or MIN TTL LS
toff 100 100ton 100 100toff 100 100ton 100 100UNIT: ns
MIN
MIN
PARAMETER
INPUT A
INPUT RBI
276
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
E7
E8
E0
E1
E2
E3
E4
E5
E6
E9
E10
E11
E12
E13
E14
E15
A
B
C
D
OE
W
DataInputs
DataSelects
8
7
6
5
4
3
2
1
23
22
21
20
19
18
17
16
15
14
13
11
10
A
B
C
D
A
B
C
D
2501-OF-16 DATA SELECTOR/MULTIPLEXER
4-Line to 1-Line Multiplexers That Can Select 1-of-16 Data Inputs Applications:
Boolean Function GeneratorParallel-to-Serial ConverterData Source Selector
Buffered 3-State Bus Driver Inputs Permit Multiplexing From n Lines to One Line 3-State Outputs
277PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN AS UNIT
ICC MAX 50 mAIOH MAX -15 mAIOL MAX 48 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN AS
tPLH 8tPHL 7tPLH 13tPHL 10.5tPZH 7tPZL 9tPHZ 6tPLZ 6.5UNIT: ns
W
MAX
G
G
MAX
MAX
MAX
SELECT W
W
W
DATA
C
FUNCTION TABLE
LH
BA
L
LLLL
G
L
L
LL
D
L
LHLH
LLHH
HH
LL
LLLLHHHH
L
LL
LH
LL
LL
L
EiE0
E3E4
E7E8
E1E2
E5E6
WE0
E3E4
E7E8
E1E2
E5E6L
HL
INPUTS OUTPUT
LL
L
L
LLL
HLH
L
LL
HH
LLLHH
HH
HH
HH
H
E9E10
E13E14
E11E12
E9E10
E13E14
E11E12L
HH
XLH
H H HXX
E15X
E15Z
HX
278
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
7
4
3
2
1
15
14
13
12
11
10
9
5
6
OE
D0
D1
D2
D3
D4
D5
D6
D7
A
B
C
Y
W
DataInputs
DataSelect
(binary)
251DATA SELECTORS/MULTIPLEXERS
3-State Version of '151 3-State Outputs Interface Directly with System Bus Perform Parallel-to-Serial Conversion Complementary Outputs Provide True and Inverted Data
279PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
FUNCTION TABLE
OUTPUTS
WG
STROBESELECTINPUTS
XL
BCY
LLLHH
X
L
HL
H
L
LZ
D0D1
D3D2
D5H H
AX
H
HL
L
H
L
L D6
D4
H H H
H
L
LL
L
L
L
LL D7
ZD0D1
D3D2
D5D6
D4
D7
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS S ALS F SN74HC
CD74HC
CD74HCT
SN74AC
CD74AC UNIT
ICC MAX 62 12 85 14 24 0.08 0.16 0.16 0.16 0.16 mAIOH MAX -5.2 -2.6 -6.5 -2.6 -3 -6 -4 -4 -24 -24 mAIOL MAX 16 8 20 24 24 6 4 4 24 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN TTL LS S ALS F SN74HC
CD74HC
CD74HCT
SN74AC
CD74AC
tPLH 45 45 18 18 9.5 51 74 63 18.2 18.2tPHL 45 45 19.5 24 7.5 51 74 63 18.2 18.2tPLH 33 33 15 24 12.5 51 74 63 19.6 19.6tPHL 33 33 13.5 23 9 51 74 63 19.6 19.6tPLH 28 28 12 10 7 49 53 53 13.5 13.5tPHL 28 28 12 15 5 49 53 53 13.5 13.5tPLH 15 15 7 15 8 49 53 53 14.9 14.9tPHL 15 15 7 15 8 49 53 53 14.9 14.9tPZH 27 45 19.5 15 7 36 42 45 13.5 13.5tPZL 40 40 21 15 6.5 36 42 45 13.5 13.5tPZH 27 27 19.5 15 6 36 42 45 13.5 13.5tPZL 40 40 21 15 4.5 36 42 45 13.5 13.5tPHZ 8 45 8.5 10 8.5 49 42 45 13.5 13.5tPLZ 23 25 14 10 8 49 42 45 13.5 13.5tPHZ 8 55 8.5 10 5.5 49 42 45 13.5 13.5tPLZ 23 25 14 10 4.5 49 42 45 13.5 13.5UNIT: ns
A, B, C
MAXYA, B, C
G
ANY D
ANY D
G
G
G MAX
MAX
Y
W (CD74: Y)
Y
W (CD74: Y)
Y
W (CD74: Y)
MAX
MAX
MAX
MAX
MAXW (CD74: Y)
280
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
Data 2
Select
Data 1
2OE
2C3
2C2
2C1
2C0
A
B
1C3
1C2
1C1
1C0
1OE
1Y
1
6
5
4
3
2
14
10
11
12
13
15
7
2Y9
253DUAL DATA SELECTORS/MULTIPLEXERS
3-State Version of '153 Perform Parallel-to-Serial Conversion
281PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LS ALS AS F SN74HC
CD74HC
CD74HCT
CD74AC
CD74ACT UNIT
ICC MAX 14 14 33 23 0.08 0.16 0.16 0.16 0.16 mAIOH MAX -2.6 -2.6 -15 -3 -6 -6 -4 -24 -24 mAIOL MAX 8 24 48 24 6 6 4 24 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN LS ALS AS F SN74HC
CD74HC
CD74HCT
CD74AC
CD74ACT
tPLH 25 10 7.5 8 35 53 57 13.3 18tPHL 20 14 8 7 35 53 57 13.3 18tPLH 45 21 13.5 13 38 53 60 20 22tPHL 32 21 11.5 10 38 53 60 20 22tPZH 28 14 12.5 9 25 33 45 11.5 12.6tPZL 23 16 11.5 9 25 33 45 11.5 12.6tPHZ 41 10 6 6 38 45 45 11.5 12.6tPLZ 27 14 7 7 38 45 45 11.5 12.6UNIT: ns
DATA
SELECT
G
G
Y MAX
Y MAX
Y MAX
Y MAX
C2
FUNCTION TABLE
OUTPUTOUTPUT
CONTROLSELECTINPUTS
XL
C1C0
L
XLLL
B
H
X
HHH
H
XLLH
A
LLHH
HXXX
XXXL
XX
HX
XXXXXLHX
X
C3
X
XX
LH
XX
XX
Y
Z
LH
LH
LH
LH
G
H
LL
LL
LL
LLX
XX
DATA INPUTS
282
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
4Y
3Y
2Y
1Y
A/B
OE
4B
4A
3B
3A
2B
2A
1B
1A4
2
3
75
6
911
10
1214
13
1
15
257QUAD DATA SELECTORS/MULTIPLEXERS
3-State Outputs Interface Directly with System Bus Provides Bus Interface from Multiple Sources in High-Performance Systems
283PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LS S ALS AS F SN74HC
CD74HC
SN74HCT
CD74HCT
AC11
CD74AC
ACT11
CD74ACT
LVC3V UNIT
ICC MAX 19 87 14 31.9 23 0.08 0.16 0.08 0.16 0.08 0.16 0.08 0.16 0.01 mAIOH MAX -2.6 -6.5 -2.6 -15 -3 -6 -6 -6 -6 -24 -24 -24 -24 -24 mAIOL MAX 24 20 24 48 24 6 6 6 6 24 24 24 24 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN LS S ALS AS F SN74HC
CD74HC
SN74HCT
CD74HCT
AC11
CD74AC
ACT11
CD74ACT
LVC3V
tPLH 13 7.5 10 5.5 7 25 45 38 50 6.4 9.3 6.9 10.7 4.6tPHL 15 6.5 12 6 6.5 25 45 38 50 7.2 9.3 8.7 10.7 4.6tPLH 21 15 18 11 15 25 53 38 57 7.2 13.4 8.2 15.4 6.4tPHL 24 15 22 10 9.5 25 53 38 57 7.9 13.4 9.4 15.4 6.4tPZH 30 19.5 16 7.5 8.5 38 45 38 45 6.5 14.7 7.3 16.1 5.6tPZL 30 21 18 9.5 8.5 38 45 38 45 8.6 14.7 9.6 16.1 5.6tPHZ 30 8.5 10 6.5 7 38 45 38 45 7.6 14.7 8.4 16.1 4.3tPLZ 25 14 15 7 7 38 45 38 45 7.6 14.7 8.5 16.1 4.3UNIT: ns
ANYSELECT
MAXANYDATA
MAX
G
G
MAX
MAX
Y
Y
FUNCTION TABLE
OUTPUT
XL
A
HL
ZLH
HLLLL H
LHH
XX
XX
B Y
XLH
LX
SELECT
INPUTSOUTPUT
CONTROL
284
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
4Y
3Y
2Y
1Y
A/B
OE
4B
4A
3B
3A
2B
2A
1B
1A 42
3
75
6
911
10
1214
13
1
15
258QUAD DATA SELECTORS/MULTIPLEXERS
3-State Outputs Interface Directly with System Bus Provides Bus Interface from Multiple Sources in High-Performance Systems
285PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LS S ALS AS F SN74HC
CD74HC
CD74HCT
CD74ACT UNIT
ICC MAX 16 87 13 25.2 23 0.08 0.16 0.16 0.16 mAIOH MAX -2.6 -6.5 -2.6 -15 -3 -6 -6 -6 -24 mAIOL MAX 8 20 24 48 24 6 6 6 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN LS S ALS AS F SN74HC
CD74HC
CD74HCT
CD74ACT
tPLH 12 6 8 5 6 25 24 34 10.7tPHL 17 6 7 4 5.5 25 24 34 10.7tPLH 21 12 25 9.5 9.5 29 35 43 15.4tPHL 24 12 20 10 11 29 35 43 15.4tPZH 30 19.5 18 8 8.5 38 35 35 16.1tPZL 30 21 18 10 8.5 38 35 35 16.1tPHZ 30 8.5 10 6 7 38 38 38 16.1tPLZ 25 14 18 6.5 7 38 38 38 16.1UNIT: ns
G Y MAX
G Y MAX
DATA Y MAX
SELECT Y MAX
FUNCTION TABLE
OUTPUT
XL
A
HH
ZHL
SELECT
INPUTS
HL
OUTPUTCONTROL
LLL L
LHH
XX
XX
B
XLH
LX
286
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
14
13
1
2
3
15
12
11
10
9
7
6
5
4G
D
S0
S1
S2
CLR
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
2598-BIT ADDRESSABLE LATCHES
8-Bit Parallel-Out Storage Register Performs Serial-to-Parallel Conversion with Storage Asynchronous Parallel Clear Active-High Decoder Enable/Disable Input Simplifies Expansion Expandable for n-Bit Applications Four Distinct Functional Modes
287PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
INPUTS
HH
GCLEAR
L
L
LL H
HD
DL
Qi0Qi0
LL
Qi0
FUNCTION TABLELATCH SELECTION
C B A
L L LL L HL H LL H HH L LH L HH H LH H H
01234567
SELECTINPUTS LATCH
ADDRESSED FUNCTION
Addressable latchMemory8-line demultiplexerClear
OUTPUT OFADDRESSED
LATCH
EACHOTHER
OUTPUT
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS ALS SN74HC
CD74HC
CD74HCT UNIT
ICC MAX 90 36 22 0.08 0.16 0.16 mAIOH MAX 16 8 8 4 4 4 mAIOL MAX -0.8 -0.4 -0.4 -4 -4 -4 mA
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN TTL LS ALS SN74HC
CD74HC
CD74HCT
tw G 15 17 15 20 21 27
CLR 15 10 10 20 21 27tsu DATA 15 20 15 19 24 26
ADDRESS 5 17 15 19 24 26th DATA 0 0 0 5 0 0
ADDRESS 20 0 0 5 0 0tPLH CLEAR Any Q MAX 25 18 12 38 47 59tPHL 24 30 19 33 56 59tPLH 20 20 12 33 56 59tPHL 28 27 22 50 56 61tPLH 28 20 12 50 56 61tPHL 20 24 20 43 51 57tPHL 20 24 13 43 51 57UNIT: ns
MIN
MIN
MIN
MAX
MAX
MAX
Any Q
Any Q
Any Q
DATA
ADDRESS
ENABLE
PARAMETER
288
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
AB
YCDE
260DUAL 5-INPUT POSITIVE-NOR GATES
Y = A + B + C + D + E
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN S F
tPLH 5.5 6.5tPHL 6 4.5UNIT: ns
A, B, C, D, E Y MAX
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN S F UNIT
ICC MAX 45 9.5 mAIOH MAX -1 -1 mAIOL MAX 20 20 mA
289
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
265QUAD COMPLEMENTARY-OUTPUT ELEMENTS
Y = A, W = A Y = AB, W = AB
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN TTL
tPLH A or B MAX 18
tPHL Y A or B Y MAX 18
tPLH A or B MAX 18
tPHL Y A or B Y MAX 18
UNIT: ns
tPLH-tPHL Y
tPHL-tPLH Y
3
3
A or B
A or B
MAX
MAX
withrespect Y
withrespect Y
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL UNIT
ICC MAX 34 mAIOH MAX -0.8 mAIOL MAX 16 mA
AY
W
A
B
Y
W
ELEMENTS 1 and 4 ELEMENTS 2 and 3
290
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
266QUAD 2-INPUTEXCLUSIVE-NOR GATES WITHOPEN-COLLECTOR OUTPUTS
Y = A ⊕ B
A
BY
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LS HC UNIT
ICC MAX 13 0.02 mAVOH MAX 5.5 Vcc VIOL MAX 8 4 mA
INPUTS
FUNCTION TABLE
OUTPUT
L
YH
ALLH
L
L LHH H
B
H
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN LS SN74HC
tPLHA or B
Other InputLow
Y MAX 30 31
tPHLA or B
Other InputLow
Y MAX 30 25
tPLHA or B
Other InputHigh
Y MAX 30 31
tPHLA or B
Other InputHigh
Y MAX 30 25
UNIT: ns
291
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
273OCTAL D-TYPE FLIP-FLOPS
Contain Eight Flip-Flops with Single-Rail Outputs Buffered Clock and Direct-Clear Inputs
CLK
1D
1Q
2D
2Q
3D
3Q
4D
4Q
5D
5Q
6D
6Q
7D
7Q
8D
8Q
CLR
1D
R
C1
1D
R
C1
1D
R
C1
1D
R
C1
1D
R
C1
1D
R
C1
1D
R
C1
1D
R
C1
3 4 7 8 13 14 17 18
2 5 6 9 12 15 16 19
11
1
CLOCK
FUNCTION TABLE
INPUTS
CLEAR D
L
HH
X
X
OUTPUTQ
HL
LQ0
H↑↑
L
HX
L
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS ALS SN74HC
CD74HC
SN74HCT
CD74HCT ABT LVTH
3VCD74
ACCD74ACT AHC AHCT LV
3VLV5V UNIT
ICC MAX 94 27 29 0.08 0.16 0.08 0.16 30 5 0.16 0.16 0.04 0.04 - 0.02 mAIOH MAX -0.8 -0.4 -2.6 -4 -4 -4 -4 -32 -32 -24 -24 -8 -8 -6 -12 mAIOL MAX 16 8 24 4 4 4 4 64 64 24 24 8 8 6 12 mA
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN TTL LS ALS SN74HC
CD74HC
SN74HCT
CD74HCT ABT LVTH
3VCD74
ACCD74ACT AHC
MIN 30 30 35 21 20 16 16 150 150 100 85 70MIN 16.5 20 14 20 24 25 30 3.3 3.3 5 6 5
tsu DATA INPUT MIN 20 20 10 25 18 25 18 2.5 2.3 2 2 4.5CLR INACVIVE MIN 25 25 15 25 - 25 - 2 2.3 - - 2
MIN 5 5 0 0 3 0 3 1.2 0 2 2 1
CLEAR ANY Q MAX 27 27 18 40 45 42 48 7.4 4.9 13.5 13.5 1227 27 12 40 45 42 45 6.5 4.8 13.5 13.5 12.527 27 15 40 45 42 45 7.3 4.3 13.5 13.5 12.5
INPUT OUTPUT MAX or MIN AHCT LV3V
LV5V
MIN 45 45 70MIN 6.5 6.5 5
tsu DATA INPUT MIN 5 6.5 4.5CLR INACVIVE MIN 2.5 2.5 2
MIN 0 2 1
CLEAR ANY Q MAX 12.6 19.5 129.8 19.5 12.511 19.5 12.5
UNIT fmax : MHz, other : ns
tPLH
tPHLANY Q MAXCLOCK
CLOCK ANY Q MAX
fmax
t
PARAMETER
tPHL
th
PARAMETER
fmax
t
thtPHL
tPLH
tPHL
292
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
CLR
CLEAR
Q
J CK
1Q
1J 1CLK 1K
K
PR
(5)
(1)
(2) (3) (4)
CLRQ
J CK
2Q
2J 2CLK 2K
K
PR
(6)
(9) (8) (7)
CLRQ
J CK
3Q
3J 3CLK 3K
K
PR
(15)
(12) (13) (14)
CLRQ
J CK
4Q
4J 4CLK 4K
K
PR
(16)
(19) (18) (17)
PRESET
(11)
276QUAD J-K FLIP-FLORS
Separate Negative-Edge-Triggered Clocks Fully Buffered Outputs
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL UNIT
ICC MAX 81 mAIOH MAX -0.8 mAIOL MAX 16 mA
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN TTL
MIN 35tw CLOCK high 13.5
CLOCK low 15tsu J, K 3
CLR, PR 10MIN 10
PRESET Q MAX 25
CLEAR Q MAX 303030
UNIT fmax : MHz, other : ns
MIN
PARAMETER
MIN
MAXQCLOCtPLH
tPHL
fmax
thtPLH
tPHL
FUNCTION TABLE
KCLOCKINPUTS OUTPUTCOMMON INPUTS
LH
CLEARPRESET J
LHHHH
H
L
HH
H
H
LXXX
HL
HL
↓↓
↓↓
H H
X
XX
H X
QHLH†
HQ0
TOGGLEL
Q0
XXX
HH
LL
X
† The output levels in this configuration are not guaranteed to meet the minimum levels for VOH. Furthermore, this configuration is nonstable; that is, it will not persist when either PRE or CLR returns to its inactive (high) level.
293
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
R
QS1S2
(latches 1 and 3)
R
QS
(latches 2 and 4)
279QUAD S-R LATCHES
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN TTL LS
t MIN 20 20tPLH 22 22tPHL Q 15 21tPHL R MAX 27 27UNIT: ns
S MAX
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS UNIT
ICC MAX 30 7 mAIOH MAX -0.8 -0.4 mAIOL MAX 16 8 mA
294
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
A
B
C
D
E
F
G
H
I
8
9
10
11
12
13
1
2
4
5
6
Σ EVEN
Σ ODD
2809-BIT ODD/EVEN PARITY GENERATORS/CHECKERS
Generate Either Odd or Even Parity for Nine Data Lines Cascadable for n-Bit Parity
295PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN LS S ALS AS F SN74HC
CD74HC
CD74HCT
CD74AC
CD74ACT
tPLH 50 21 20 12 10 52 60 63 20 21.6tPHL 45 18 20 11 11 52 60 63 20 21.6tPLH 35 21 20 12 10 52 60 68 21 21.6tPHL 50 18 22 11.5 11 52 60 68 21 21.6UNIT: ns
DATA SEVEN MAX
DATA SODD MAX
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LS S ALS AS F SN74HC
CD74HC
CD74HCT
CD74AC
CD74ACT UNIT
ICC MAX 27 105 16 35 35 0.08 0.16 0.16 0.16 0.16 mAIOH MAX -0.4 -1 -2.6 -2 -1 -4 -4 -4 -24 -24 mAIOL MAX 8 20 24 20 20 4 4 4 24 24 mA
Σ EVEN
OUTPUTS
Σ ODD
L HH L
NO. OF INPUTSA–I
THAT ARE HIGH
FUNCTION TABLE
0, 2, 4, 6, 81, 3, 5, 7, 9
296
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
11
12
B4
A4
15
14
B3
A3
2
3
B2
A2
6
5
B1
A1
C07
Σ1
Σ2
Σ3
Σ4
C49
10
13
1
4
2834-BIT BINARY FULL ADDERS
Full-Carry Look-Ahead Across the Four Bits
297PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
WHEN C2 = L
WHEN C0 = L
WHEN C2 = H
WHEN C0 = H
A3 B4
FUNCTION TABLE
Σ3 Σ4L LHLHLHLHLH
LLLL
LL
HH
L
HH
HH
HH
LHLHLH
B3
HL
HL
HL
LL
HHL
LLHH
H
A4
LL L
HHLLH
LH
LH
LLLHH
H
H
L
L
H
LL
HL
HH
HH
Σ3HLLHH
LH
LH
L
HL
HL
HL
LL
C4
LL
LL
HL
LLHHHHLLLLHHHH
HL
H
LLH
H
H
LH
L
L
Σ4L
HH
L
LH
L
L
HH
C4
A1 B2 Σ1 Σ2B1 A2 Σ1C2 Σ2 C2
L
LL
H
HL
H
H
H
H
H
HLL
H
L
H
L
L H
HH
INPUTS
OUTPUTS
RECOMMENDED OPERATING CONDITIONS
MAX or MIN TTL LS S F CD74HC
CD74HCT
CD74AC
CD74ACT UNIT
MAX 110 39 160 55 0.16 0.16 0.16 0.16 mAAny output except C4 MAX -0.8 -0.4 -1 -1 -4 -4 -24 -24
C4 MAX -0.4 -0.4 -0.5 -1 -4 -4 -24 -24Any output except C4 MAX 16 8 20 20 4 4 24 24
C4 MAX 8 8 10 20 4 4 24 24
mA
PARAMETER
ICC
IOL
IOH
mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN TTL LS S F CD74HC
CD74HCT
CD74AC
CD74ACT
tPLH MAX 21 24 18 10.5 69 47 17.6 17.6tPHL MAX 21 24 18 10.5 69 47 17.6 17.6tPLH MAX 24 24 18 10.5 63 69 18.2 18.2tPHL MAX 24 24 18 10.5 63 69 18.2 18.2tPLH MAX 14 17 11 8.5 59 80 17.6 17.6tPHL MAX 16 22 11 8 59 80 17.6 17.6tPLH MAX 14 17 12 8.5 59 72 17.6 17.6tPHL MAX 16 17 12 8 59 72 17.6 17.6UNIT: ns
C4
S
Si
C0
Ai or Bi
C0
Ai or Bi
298
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
PARITYERROR
5
8
9
10
11
12
13
1
2
4
6
3
A
B
C
D
E
F
G
H
I
PARITY I/O
XMIT
2869-BIT PARITY GENERATOR/CHECKER WITH BUS DRIVER PARITY I/O PORT
Generate Either Odd or Even Parity for Nine Data Lines Cascadable for n-Bit Parity Direct Bus Connection for Parity Generation or Checking by Using the Parity I/O Port 74AC11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series) 74ACT11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)
299PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
FUNCTION TABLE
PARITYERROR
PARITYI/O
H
L
hl
h
H
H
HL
XMITNUMBER OF INPUTS
(A–I) THATARE HIGH
0, 2, 4, 6, 8
1, 3, 5, 7, 9
1, 3, 5, 7, 9
0, 2, 4, 6, 8
l
l
l
hh
hh H
L
h = high input level l = low input levelH = high output level L = low output level
RECOMMENDED OPERATING CONDITIONS
MAX or MIN AS AC11
ACT11 UNIT
ICC MAX 50 0.08 0.08 mAParity error MAX -2 -24 -24 mAParity I/O MAX -15 -24 -24 mA
Parity error MAX 20 24 24 mAParity I/O MAX 48 24 24 mA
PARAMETER
IOH
IOL
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN AS AC11
ACT11
tPLH 15 9 10.4tPHL 14 107 12tPLH 16.5 10 11.3tPHL 16.5 12 12.9tPLH 9 6.2 7.7tPHL 9 7.9 9.1tPZH 13 5.3 7.3tPZL 16 8.9 11.4tPHZ 11.5 6.5 8.5tPLZ 10 6.3 7.8UNIT: ns
MAXA to I Parity I/O
MAX
MAX
Parity I/O Parity error MAX
XMIT Parity I/O
A to I Parity error
300
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
TP2(6)
M2
2D R R
2T
22
A
B 2
(10)
(1)
C 4(15)
D 8(14)
E 16(2)
20
18
16
T
TP1(3)
M2
2D R R
2T0
X/Y
28
26
24
CLK1(4)
CLR(11)
CLK2(5)
T
R
T
R
T
R
T
TP3(13)
M2
2D R R
2T
14
12
10
8
T
M2
2D R
2T
Q(7)
M2
2D R
2T
6
4
2
T
R
T
M2
2D R
2T
M3
3DS
3T
292PROGRAMMABLE FREQUENCY DIVIDER/DIGITAL TIMER
Digitally Programmable from 22 to 231
Easily Expandable Applications:
Frequency DivisionDigital Timing
301PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LS UNIT
ICC MAX 75 mAIOH (Q only) MAX -1.2 VIOL (Q only) MAX 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN LS
fmax CLK MIN 30tPLH CLK Q MAX 90tPHL CLK Q MAX 120tPHL CLR Q MAX 65UNIT fmax : Hz, other : ns
Q OUTPUT MODE
LH
CLK 1 CLK 2CLEAR
H
X
LH H
X
X
LCleared to L
CountInhibit
H X H Inhibit
Count
FUNCTION TABLE
≠≠
302
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
J(4)
Q
CK
QC
K
J(9)
Q
CK
QA
K
J(8)
Q
CK
QD
R0(1)(12)
K
J(5)
Q
CKQB
K
R0(2)(13)
INPUT A
INPUT B
(10)
(1)
2934-BIT BINARY COUNTERS
303PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
QB
COUNT SEQUENCEOUTPUTS
LL
QCQD
4
0123
COUNT
5
HH
67
QA
89
RESET/COUNT FUNCTION TABLE
LLLLLL
LLLL
LL
HH
HH
LLHHLLHHLL
L
HL
HL
HL
HL
HH10 L H LH11 L H HH12 H L LH13 H L HH14 H H LH15 H H H
QBOUTPUTS
LQCQD QAL
COUNTL L
RESET INPUTS
HL
R0(2)R0(1)
X COUNT
H
LX
NOTE: Output QA is connected to input B.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS UNIT
ICC MAX 39 15 mAIOH MAX -0.8 -0.4 mAIOL MAX 16 8 mA
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN TTL LS
A QA MIN 32 32B QB MIN 16 16
tw A 15 15B 30 30
Reset 15 15tsu MIN 25 25
16 1618 1870 7070 7016 1621 2132 3235 3551 5151 51
UNIT fmax : Hz, other : ns
B
A, B MIN
A
A QA MAX
QC
QD
QB MAX
MAX
MAX
MAXQB
B
B
PARAMETER
fmax
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
304: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
Logic Diagram
Q(7)
M2
2D R
2T
7
A
B
1(2)
(1)
C
2
(15)
D
4
(14)8
6
5
4
3
2
TP(3)
0
X/Y
CLK1(4)
CLR(11)
CLK2(5)
R
T
R
T
M3
3D S
3T
M2
2D R
2T
14
13
12
11
10
9
8
1
294PROGRAMMABLE FREQUENCY DIVIDER/DIGITAL TIMER
Digitally Programmable from 22 to 215
Easily Expandable Applications
Frequency DivisionDigital Timing
305PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
A
FUNCTION TABLEFREQUENCY DIVISION
PROGRAMMING INPUTS
LL
BCD
L
LLLL
L
L
LL
BINARY
H
LLHH
LLHH
HH
LL
LHLHLHLH
Inhibit
23
24
27
28
Inhibit22
25
26
L
DECIMALInhibit
816
128256
Inhibit4
3264
DECIMALInhibit
512512
4
Inhibit512
512512
BINARYInhibit
29
29
Disabled Low22
Inhibit29
29
29HH
LLH 29L 512 823HLH 210H 1024 1624LLH 211H 2048 3225HHH 212L 4096 6426LHH 213L 8192 12827HHH 214H 16384 25628LHH 215H 32768 51229H
Q TP
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LS UNIT
ICC MAX 50 mAIOH MAX -1.2 VIOL MAX 24 mA
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN LS
CLK MIN 30CLK 1 or 2 MIN 16
CLR MIN 3590
120
CLR Q MAX 65
UNIT fmax : Hz, other : ns
MAXCLK 1 or 2 Q
PARAMETER
tPLH
tPHL
tPLH
fmax
tw
306
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
D 8(14)
C 4
K COUNTER
TO MODE CONTROLS 12-2 (11-STAGES NOT SHOWN)
X/Y
(15)B 2
(1)A 1
(2)
ENCTR(3)
I/D CLK(5)
φB(10)
φA2(13)
φA1(9) EXCLUSIVE-OR PHASE DETECTOR
I/D CIRCUIT
EDGE CONTROLLED PHASE DETECTOR
S
R
XORPDOUT
(11)
I/D OUT(7)
D/U(6)
KCLK(4)
ECPDOUT
(12)
21D
21D
C21
C21
S
R
21J
21K
C21
M1
1D1T
DECREMENT
INCREMENT
T
R R
21D
21D
C2121D
C21
C21C21
21D
21D21D
C21
C21
M1
1D1T T
R R
T
R
T
R
POWER-UP RESET
I = 1
T
R
T
R
M13
13D13T
R
M13
13D13T
R
M14
14D14T
R
M14
14D14T
R
20DC20
20DC20
1
14 13 120 11 10 9 8 7 6 5 4 3 2 1
297DIGITAL PHASE-LOCKED-LOOP FILTERS
307PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
K COUNTER FUNCTION TABLE(DIGITAL CONTROL) EXCLUSIVE OR PHASE DETECTOR
L22
LL LHLL L
24LLL H25HLL H26LHL L27HHL L28LHL H29HHL H210LLH L211HLH L212LLH H213HLH H214LHH L215HHH L216LHH H217HHH H
ACD B
Inhibited
A1 B
FUNCTION TABLES
XORPD OUT
HLL
LH
L
L HLH H
H
EDGE-CONTROLLED PHASE DETECTOR
A2 B ECPD OUT
H
φ φ
φ φ
↑
↑
↓
↓ L
No change
No change
MODULO(K)
H or L
H or L
H or L
H or L
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LS CD74HC
CD74HCT
CD74ACT UNIT
ICC MAX 120 0.16 0.16 0.08 mAIOH (I/D OUT) MAX -1 -6 -4 -24 mAIOH (XOR, ECPD) MAX -0.4 -6 -4 -24 mAIOL (I/D OUT) MAX 24 6 4 24 mAIOL (XOR, ECPD) MAX 8 6 4 24 mA
SWITCHING CHARACTERISTICS
OUTPUT MAX or MIN LS CD74HC
CD74HCT
CD74ACT
I/D OUT 32 20 20 45I/D OUT 16 13 13 35
tw K CLK 16 24 24 8I/D CLK 33 38 38 9
tsu D/U 30 30 30 17ENCLR 31 30 30 16
th D/U 0 0 0 7ENCLR 0 0 0 6
25 53 53 2435 53 53 24
other input low 15 45 45 22other input high 25 45 45 22other input low 25 45 45 22other input high 25 45 45 22
ECPD OUT 30 60 60 30ECPD OUT 30 60 60 30
UNIT fmax : MHz, other : ns
INPUT
fmaxK CLK
MINI/D CLK
PARAMETER
MIN
MIN
MIN
tPLHI/D CLK I/D OUT MAX
tPHL
X or OUTMAX
tPHL A1 or B X or OUT
tPLH A1 or B
tPLH BMAX
tPHL A2
308
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
QD
QC
QB
QA
D2
D1
C2
C1
B2
A2
A1
CLK
B1
WS1S
C1
1S
C1
1S
C1
1S
C1
3
2
10
4
1
9
5
7
6
11
15
14
13
12
1R
1R
1R
1R
298QUAD 2-INPUT MULTIPLEXERS WITH STORAGE
Outputs Storage Register
309PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
INPUTS
FUNCTION TABLE
OUTPUTS
D2
QD
D1
QB
B1B2
QB0
C1
QC0 QD0
QA
A1A2
QA0
CLOCK
H
SELECTWORD
LH
↓↓
X
QC
C2
† a1, a2, etc. = the level of steady-state input at A1, A2, etc.QA0, QB0, etc. = the level of QA, QB, etc. enteredon the most recent O transition of CLK
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS AS SN74HC UNIT
ICC MAX 65 21 36 0.08 mAIOL MAX 16 8 20 4 mAIOH MAX -0.8 -0.4 -2 -4 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN TTL LS AS SN74HC
t MIN 20 20 8 27Data 15 15 4.5 21
Word Select 25 25 13 21Data 5 5 3.5 0
Word Select 0 0 1 0tPLH 27 27 9 31tPHL 32 32 11 31UNIT: ns
tsu
th
GA to GDCLK
MIN
MIN
MAX
310
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
C1
1D
C1
1D
SixIdenticalChannels
NotShown†
19
11
12
8
2
3
18
17
S0
S1
SR(shift right
serial input)
CLK
QA′
OE1
OE2
SL(shift leftserial input)
QH′
7 1 6
A/QA H/QH
9CLR
1
R R
† I/O ports not shown: B/QB (13), C/QC (6), D/QD (14), E/QE (5), F/QF (15), and G/QG (4).
2998-BIT BIDIRECTIONAL UNIVERSAL SHIFT/STORAGE REGISTERS
Multiplexed I/O Ports Provide Improved Bit Density Four Modes of Operation:
Hold (Store)Shift RightShift LeftLoad Data
Operate with Outputs Enabled or at High Impedance 3-State Outputs Drive Bus Lines Directly Can Be Cascaded for n-Bit Word Lengths
311PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
INPUTS I/O PORTS OUTPUTSMODE
CLR S1 S0 OE1 † OE2 † CLK SL SR A/Q A B/Q B C/Q C D/Q D E/Q E F/Q F G/Q G H/Q H Q A' Q H'
ClearLLL
XLH
LXH
LLX
LLX
XXX
XXX
XXX
LLX
LLX
LLX
LLX
LLX
LLX
LLX
LLX
LLL
LLL
Hold HH
LX
LX
LL
LL
XL
XX
XX
Q A0Q A0
Q B0Q B0
Q C0Q C0
Q D0Q D0
Q E0Q E0
Q F0Q F0
Q G0Q G0
Q H0Q H0
Q A0Q A0
Q H0Q H0
ShiftRight
HH
LL
HH
LL
LL
↑↑
XX
HL
HL
Q AnQ An
Q BnQ Bn
Q CnQ Cn
Q DnQ Dn
Q EnQ En
Q FnQ Fn
Q GnQ Gn
HL
Q GnQ Gn
ShiftLeft
HH
HH
LL
LL
LL
↑↑
HL
XX
Q BnQ Bn
Q CnQ Cn
Q DnQ Dn
Q EnQ En
Q FnQ Fn
Q GnQ Gn
Q HnQ Hn
HL
Q BnQ Bn
HL
Load H H H X X ↑ X X a b c d e f g h a h
FUNCTION TABLE
NOTE: a...h =the level of the steady-state input at inputs A through H, respectively. This data is loaded into the flip-flops while the flip-flop outputsare isolated from the I/O terminals.† When one or both output-enable inputs are high, the eight I/O terminals are disabled to the high-impedance state; however, sequential operationor clearing of the register is not affected.
RECOMMENDED OPERATING CONDITIONS
MAX or MIN LS S ALS F CD74HC
CD74HCT
CD74AC
CD74ACT UNIT
MAX 53 225 40 95 0.16 0.16 0.16 0.16 mA
QA thru QH -2.6 -6.5 -2.6 -3 -6 -4 -24 -24
QA' or QH' -0.4 -0.5 -0.4 -1 -4 -4 -24 -24
QA thru QH 24 20 24 24 6 4 24 24
QA' or QH' 8 6 8 20 4 4 24 24
PARAMETER
ICC
mA
mA
IOH MAX
IOL MAX
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN LS S ALS F CD74HC
CD74HCT
CD74AC
CD74ACT
MIN 20 50 30 70 20 16 95 90
t CLK high 30 10 16.5 7 24 30 5.2 5.5CLK low 10 10 16.5 7 24 30 5.2 5.5
CLR 20 10 10 7 15 22 5 5DATA "H" 20 7 16 5.5 36 30 4.5 4.5DATA "L" 20 5 6 5.5 36 30 4.5 4.5SELECT 35 15 20 8.5 36 41 9 9
CLR INACTIVE 20 10 15 7 - - - -DATA 0 5 0 2 0 0 0 0
SELECT 10 5 0 0 0 0 0 033 20 15 10 60 68 12.9 12.939 20 18 9.5 60 68 12.9 12.925 21 13 10 60 68 13.5 14.539 21 19 12 60 68 13.5 14.5
CLR QA' or QH' 40 21 22 10.5 60 69 11.2 12.2
CLR QA thru QH 40 24 22 15 60 69 13.9 18.621 18 16 9 47 48 14.9 14.930 18 22 11 39 45 14.9 14.920 12 8 7 56 56 14.9 14.915 12 15 6.5 47 48 14.9 14.9
UNIT fmax : MHz, other : ns
CLK QA' or QB'
fmax
tsu
MAX
MIN
MIN
th
PARAMETER
MIN
tPHL
tPLH
tPHL
tPLH
CLK QA thru QH MAXtPHL
MAXtPHL
tPZHOE1, OE2 QA thru QH MAX
tPZL
OE1, OE2 QA thru QH MAXtPLZ
tPHZ
312
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
F/4
T
DRIVERSECTION
(6)
F/2(13)
T'LS321ONLY
OSC
F(10)
VCC
F(7)
F(12)
FFQ1D(4)
FFD(5)
TANK 2(2)
XTAL 1(14)
TANK 1(1)
XTAL 2(15)
F(9)
C1
321CRYSTAL-CONTROLLED OSCILLATOR
Crystal-Controlled Oscillator Operation from 1MHz to 20MHz Complementary Outputs
313PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
MAX or MIN LS UNIT
MAX 75 mA
F' or F' MAX -24 mA
F, F, F/2, F/4 MAX -0.4 mA
F' or F' MAX 24 mA
F, F, F/2, F/4 MAX 8 mA
PARAMETER
ICC
IOL
IOH
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN LS
F/2 MIN 10fmax F/4 MAX 5
ANY MIN 20F',F' MAX 14ANY MAX 40F',F' MAX 10ANY MAX 20
UNIT fmax : MHz, other : ns
tr
tf
314
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
C1
1D
C1
1D
SixIdenticalChannels
NotShown†
9
1
19
11
12
8
2
3
18
17
CLR
S0
S1
SR(shift right
serial input)
CLK
QA′
OE1
OE2
SL(shift leftserial input)
QH′
7 1 6
A/QA H/QH
† I/O ports not shown: B/QB (13), C/QC (6), D/QD (14), E/QE (5), F/QF (15), and G/QG (4).
3238-BIT BIDIRECTIONAL SHIFT/STORAGE REGISTERS
Multiplexed I/O Ports Provide Improved Bit Density Four Modes of Operation:
Hold (Store)Shift RightShift LeftLoad Data
3-State Outputs Drive Bus Lines Directly Can Be Cascaded for n-Bit Word Lengths
315PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
MAX or MIN LS ALS CD74AC
CD74ACT UNIT
MAX 225 40 0.16 0.16 mAIOH QA' or QH' -0.5 -0.4 -24 -24 mA
QA thru QH -6.5 -2.6 -24 -24 mA
QA' or QH' 6 8 24 24 mA
QA thru QH 20 24 24 24 mAMAX
PARAMETER
ICC
MAX
IOL
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN LS ALS CD74AC
CD74ACT
MIN 25 17 95 90tw CLK 30 16.5 5.2 5.5
CLR 20 - 5 5tsu DATA H 20 16 4.5 4.5
DATA L 20 6 4.5 4.5SELECT - 20 9 9
CLR - 20 5.5 5.5th SELECT - 0 0 0
DATA 0 0 0 033 15 12.9 12.939 18 12.9 12.925 13 13.5 14.539 19 13.5 14.521 16 14.9 14.930 22 14.9 14.920 8 14.9 14.915 15 14.9 14.921 16 14.9 14.930 22 14.9 14.920 8 14.9 14.915 15 14.9 14.9
UNIT fmax : MHz, other : ns
MIN
MIN
MIN
QA' or QB' MAX
QA thru QH MAX
tPLH
tPHL
tPLH
fmax
PARAMETER
CLK
CLKtPHL
tPZHOE1 QA thru QH MAX
tPZL
tPHZOE1 QA thru QH MAX
tPLZ
tPZHOE2 QA thru QH MAX
tPZL
tPHZOE2 QA thru QH MAX
tPLZ
FUNCTION TABLE
MODE
Clear
H
OUTPUTS
QA0Hold
LL
→
L
HHH
H
INPUTS
L
QBn
a
HH
CLR
OE1†S1
LLL
XSL
LH
XXX
X
X
CLK
X
→→
→
I/O BORD
QH0
LL
h
QGn
H/QH
QC0
LL
QDn
c
QBn
C/QC
QA0
LL
QCn
b
QAn
B/QB
QA0
LL
QBn
a
A/QA
H X XHH
S0
X
LH
SELECT
L
LLLL
H H
LL
LL
L
XL
L
X
OUTPUTCONTROL
OE2†
LLL
L
LLLL
X
L
X
→
SR
LH
XXX
X
X
X
X
SEREALQA'
QH0
LL
QGn
h
QGn
QH0
QH'
QD0
LL
QEn
d
QCn
C/QD
QE0
LL
QFn
e
QDn
C/QE
QF0
LL
QGn
f
QEn
C/QF
QG0
LL
QHn
g
QFn
C/QG
LH
LH
LH
QBnQDnQCnQBn QEn QFn QGn QHn
LHQA0QH0
QGn
QC0
QBn
QB0
QAn
QA0 QD0
QCn
QE0
QDn
QF0
QEn
QG0
QFn
→→
ShiftRight
ShiftLeft
Load
† a . ..h=t he level of the steady-state input at inputs A through H, respectively. This data is loaded into the flip-flops while the flip-flopoutputsare isolated from the I/O terminals.
316
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
0
A1(7)
A0(9)
GS(14)
A2(6)
EO(15)
E1
(10)
1(11)
(5)
2(12)
3(13)
4(1)
5(2)
6(3)
7(4)
3488-LINE TO 3-LINE PRIORITY ENCODER
3-State Outputs Drive Bus Lines Directly Encodes 8 Data Lines to 3-Line Binary (Octal)
317PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
FUNCTION TABLE
INPUTS
HL
0E1
HX
OUTPUTS
L
X
LXLXLXLXLXL
L
1
HX
L
X
H
XXXX
2
HX
L
X
H
XXXX
3
HX
L
X
H
XXX
4
HX
L
X
H
XX
5
HX
L
X
H
X
6
HXL
X
H
7
HL
X
HXLX
H H H H H H
H H H H HH H H H
H H HH H
H
A2
L
Z
H
A1
L
H
A0
L
H H H
H HH
H HH
H
GSH
L
E0HL
HH
HHHHH
L
L
L
L
LLL
LL
ZZZ
ZZ
HH
LLLLLLL
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LS UNIT
MAX 25 mAA0, A1, A2 MAX -2.6 mA
E0, ES MAX -0.4 mAA0, A1, A2 MAX 24 mA
E0, ES MAX 8 mA
ICC
IOL
IOH
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN LS
tPLH MAX 35tPHL MAX 35tPLH MAX 18tPHL MAX 40tPLH MAX 55tPHL MAX 21UNIT: ns
A0, A1, A21 to 7
0 to 7
0 to 7
E0
GS
318
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
15
DATA
REGISTERS
1
8
OF
SELECTOR
ADDRESSDECODE
A RDDRESS
EGISTER
16
17
9
8
7
6
5
4
3
2
1
11
14
13
12
OE1
OE2
OE3
E
D0
D1
D2
D3
D4
D5
D6
D7
LE
S0
S1
S2
19
18
Y
Y
BUFFERS
ENABLE LOGIC
3548-INPUT MULTIPLEXER/REGISTER WITH 3-STATE OUTPUTS
319PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LS SN74HC
CD74HC
SN74HCT UNIT
ICC MAX 46 0.08 0.16 0.16 mAIOH MAX -2.6 -6 -6 -4 mAIOL MAX 24 6 6 4 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN LS SN74HC
CD74HC
SN74HCT
tsu MAX 15 19 15 15th MAX 15 5 14 14tPLH MAX 36 59 63 71tPHL MAX 35 59 63 71tPLH MAX 27 59 63 71tPHL MAX 44 59 63 71tPLH MAX 42 68 75 81tPHL MAX 39 68 75 81tPLH MAX 33 68 75 81tPHL MAX 50 68 75 81UNIT:ns
Y
W(CD74: Y)
Y
W(CD74: Y)
DC(CD74: E)
DC(CD74: E)
D0 thru D7
D0 thru D7
OUTPUTSINPUTS
XX
SELECT†OUTPUT
ENABLES
L
XXXL
LL
XLLL
XX
G1H
LL
XX
LL
G2X
LL
XH
LL
G3X
HH
LX
HH
WZ
ZZ
YZ
ZZ
LL L L HH
X
S2 S1 S0
XXLLHH
X
LLL
H LL
LL
HHH
L L L HH
LHH
HH
L LL
LL
HHL
H L L HL
LLH
HH
L LL
LL
HHH
H L L HH
HLL
H L L HHH L L H
D1D1n
D0n
D0
D2D2nD3
D3nD4
D4nD5
D5nD6
D6nD7
D7nHHH D7n
D7D6n
D6D5n
D5D4n
D4D3n
D3D2n
D2D1n
D1D0n
D0LH
LH
LH
LH
LH
LH
LH
LH
DC
FUNCTION TABLE (SN74)
NOTES:
H = High Voltage Level (Steady State), L = Low Voltage Level (Steady State), X = Don’t Care, Z = High Impedance State (Off State), D0n ... D7n =the level of steady-state inputs D0 through D7, respectively, before the most recent low-to-high transition of data control.
† This column shows the input address setup with LE low.
TRUTH TABLE
INPUTS
OUTPUTSSELECT (NOTE 3)ENABLE
DATA OUTPUT ENABLES
S2 S1 S0 E OE1 OE2 OE3 Y Y
X X X X H X X Z Z
X X X X X H X Z Z
X X X X X X L Z Z
L L L L L L H D0 D0
L L L H L L H D0n D0n
L L H L L L H D1 D1
L L H H L L H D1n D1n
L H L L L L H D2 D2
L H L H L L H D2n D2n
L H H L L L H D3 D3
L H H H L L H D3n D3n
H L L L L L H D4 D4
H L L H L L H D4n D4n
H L H L L L H D5 D5
H HH LL L H D5n Dn5
H H L L L L H D6 D6
H H L H L L H D6n D6n
320
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
15
DATA
REGISTERS
1
8
OF
SELECTOR
ADDRESSDECODE
A RDDRESS
EGISTER
16
17
9
8
7
6
5
4
3
2
1
11
14
13
12
OE1
OE2
OE3
CP
D0
D1
D2
D3
D4
D5
D6
D7
LE
S0
S1
S2
19
18
Y
Y
BUFFERS
ENABLE LOGIC
356SYNCHRONOUS UP/DOWN DECADE COUNTER
321PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LS SN74HC
CD74HCT UNIT
ICC MAX 46 0.08 0.16 mAIOH MAX -2.6 -6 -4 mAIOL MAX 24 6 4 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN LS SN74HC
CD74HCT
tsu MIN 15 19 11th MIN 0 5 14tPLH 27 64 77tPHL 50 64 77tPLH 36 64 77tPHL 27 64 77tPLH 45 71 89tPHL 48 71 89tPLH 54 71 89tPHL 45 71 89UNIT: ns
MAX
MAX
MAX
MAX
S0, S1, S2
S0, S1, S2
W(CD74 : Y )
Y
W(CD74 : Y )
CLK
D0 thru D7D0 thru D7
CLK Y
OUTPUTSINPUTS
XX
SELECT†OUTPUT
ENABLES
L
XXXL
LL
XLLL
XX
G1H
LL
XX
LL
G2X
LL
XH
LL
G3X
HH
LX
HH
WZ
D1
ZZ
D1n
YZ
ZZ
D0n
D0
L
CLK
L L L H D2H
X
C2 C1 C0
XXLLHH
X
H or L
H or LL
LL
H
H or L
LL
LL
HH
D2nD3H
L L L H D3nH
LH
H or L
HHH
L LL
LL
HH
D4D4nL
H L L H D5L
LL H or LH
HH
L
H or L
LL
LL
HH
D5nD6H
H L L H D6nH
HL
H or L
LH
H or LL
↑
↑
↑
↑
↑
↑
↑
↑
↑ L H D7HH L L H D7n
D1D1n
D0n
D0
D2D2nD3
D3nD4
D4nD5
D5nD6
D6nD7
D7nHHH
FUNCTION TABLE (SN74)
NOTES:
H = High Voltage Level (Steady State), L = Low Voltage Level (Steady State), = Transition form Low to High Level, X = Don’t Care, Z = High Impedance State (Off State), D0n ... D7n = the level of steady-state inputs D0 through D7, respectively, before the most recent low-to-high transition of data control.
† This column shows the input address setup with LE low.
TRUTH TABLE
INPUTS
OUTPUTSSELECT (NOTE 3) CLOCK OUTPUT ENABLES
S2 S1 S0 CP OE1 OE2 OE3 Y Y
X H X X Z Z
X H X Z Z
X
X
X
X
X
X
X
X
X
X
X
X X L Z Z
L L L L H D0 D0
L L L H or L
H or L
H or L
H or L
H or L
H or L
H or L
L L H D0n D0n
L L H L H D1 D1
L L H L L H D1n D1n
L H L L H D2 D2
L H L L L H D2n D2n
L HH L H D3 D3
L H H L L H D3n D3n
H L L L H D4 D4
H L L L L H D4n D4n
H L H L H D5 D5
H L H L L H D5n D5n
H H L
↑
↑
↑
↑
↑
↑
↑ L
L
L
L
L
L
L
L H D6 D6
H H L L L H D6n D6n
322
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
365HEX BUS DRIVERS OE1
OE2
To Five Other Channels
A1 Y1
1
15
2 3
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS SN74HC
CD74HC
CD74HCT UNIT
ICC MAX 85 24 0.08 0.16 0.16 mAIOH MAX -5.2 -2.6 -6 -6 -4 mAIOL MAX 32 24 6 6 4 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN TTL LS SN74HC
CD74HC
CD74HCT
tPLH MAX 16 15 24 32 38tPHL MAX 22 18 24 32 38tPZH MAX 35 35 48 45 53tPZL MAX 37 45 48 45 53tPHZ MAX 11 32 48 45 53tPLZ MAX 27 35 48 45 53UNIT: ns
G Y
G
A Y
Y
323
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
NOTE: Inverter not included in HC/HCT365.
FIGURE 1. LOGIC DIAGRAM FOR THE HC/HCT365 AND HC366 (OUTPUTS FOR HC/HCT365 ARE COMPLEMENTS OF THOSESHOWN, i.e., 1Y, 2Y, ETC.)
42A
2Y5
63A
3Y7
104A
4Y9
125A
5Y11
146A
6Y13
OE11
15OE2
ONE OF SIX IDENTICAL CIRCUITS
VCC
31Y
GND8
(NOTE)
21A
16
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS SN74HC
CD74HC UNIT
ICC MAX 77 21 0.08 160 mAIOH MAX -5.2 -2.6 -6 -6 mAIOL MAX 32 24 6 6 mA
FUNCTION TABLE
INPUTS
G1
H
LLX
G2
XH
LL
A
XX
LH
OUTPUT
Z
HLZ
Y
NOTES:H = High Voltage LevelL = Low Voltage LevelX = Don’t CareZ = High Ompedance (OFF) State SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN TTL LS SN74HC
CD74HC
tPLH MAX 17 15 24 33tPHL MAX 16 18 24 33tPZH MAX 35 35 48 45tPZL MAX 37 45 48 45tPHZ MAX 11 32 48 45tPLZ MAX 27 35 48 45UNIT:ns
A
G(CD74 : OE )
G(CD74 : OE )
Y(CD74 : Y )
Y(CD74 : Y )
Y(CD74 : Y )
366HEX BUS DRIVERS HEX BUFFERS/LINE DRIVERS 3-STATE
324
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
Logic Diagram368HEX BUS DRIVERS 1OE
To Three Other Channels
1A1 1Y1
1
2 3
2OE
To One Other Channel
2A1 2Y1
15
12 11
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS SN74HC
CD74HC
CD74HCT UNIT
ICC MAX 77 21 0.08 0.16 0.16 mAIOH MAX -5.2 -2.6 -6 -6 -4 mAIOL MAX 32 24 6 6 4 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN TTL LS SN74HC
CD74HC
CD74HCT
tPLH MAX 17 15 24 32 45tPHL MAX 16 18 24 32 45tPZH MAX 35 35 48 45 53tPZL MAX 37 45 48 45 53tPHZ MAX 11 32 48 45 53tPLZ MAX 27 35 48 45 53UNIT: ns
A Y
G Y
G Y
367HEX BUS DRIVERS
1OE
To Three Other Channels
1A1 1Y1
1
2 3
2OE
To One Other Channel
2A1 2Y1
15
12 11
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS SN74HC
CD74HC
CD74HCT AHC AHCT LV
3VLV5V UNIT
ICC MAX 85 24 0.08 0.16 0.16 0.04 0.04 - 0.02 mAIOH MAX -5.2 -2.6 -6 -6 -4 -8 -8 -8 -16 mAIOL MAX 32 24 6 6 4 8 8 8 16 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN TTL LS SN74HC
CD74HC
CD74HCT AHC AHCT LV
3VLV5V
tPLH MAX 16 16 24 32 38 9 6.5 13.5 9tPHL MAX 22 22 24 32 38 9 6.5 13.5 9tPZH MAX 35 35 48 45 53 10.5 9.5 16 10.5tPZL MAX 47 40 48 45 53 10.5 8.5 16 10.5tPHZ MAX 11 30 48 45 53 10.5 9.5 15.5 10.5tPLZ MAX 27 35 48 45 53 10.5 8.5 15.5 10.5UNIT: ns
A Y
G Y
G Y
325
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
373OCTAL D-TYPE LATCHES
3-State Bus-Driving True Outputs Buffered Control Inputs 74AC11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series) 74ACT11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series)
OE
To Seven Other Channels
1
11
32
LE
1D
C1
1D1Q
LE D Q
LLLH
HLXX
H
LX
HHL
Q0Z
FUNCTION TABLE
OUTPUTCONTROL
INPUTS OUTPUT
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LS S ALS AS F SN74HC
CD74HC
SN74HCT
CD74HCT
SN74BCT ABT LVTH UNIT
ICC MAX 40 190 27 100 55 0.08 0.16 0.08 0.16 60 30 5 mAIOH MAX -2.6 -6.5 -2.6 -15 -3 -6 -6 -6 -6 -15 -32 -32 mAIOL MAX 24 20 24 48 24 6 6 6 6 64 64 64 mA
PARAMETER MAX or MIN AC11
SN74AC
CD74AC
ACT11
SN74ACT
CD74ACT AHC AHCT LV
3VLV5V
LVC3V
ALVCH3V UNIT
ICC MAX 0.08 0.04 0.16 0.08 0.04 0.16 0.04 0.04 - 0.02 0.01 0.02 mAIOH MAX -24 -24 -24 -24 -24 -24 -8 -8 -8 -16 -24 -24 mAIOL MAX 24 24 24 24 24 24 8 8 8 16 24 24 mA
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN LS S ALS AS F SN74HC
CD74HC
SN74HCT
CD74HCT
SN74BCT ABT LVTH
tw High MIN 15 6 10 4.5 6 20 24 25 24 7.5 3.3 3Low MIN 15 7.3 - - - - - - - - - -
MIN 5 0 10 2 2 13 15 13 20 2 1.9 1.1MIN 20 10 7 3 3 12 5 10 15 5.5 1 1.4MAX 18 12 12 6 8 38 45 44 48 9.3 5.9 3.9MAX 18 12 16 6 6 38 45 44 48 9.5 6.2 3.9MAX 30 14 22 11.5 13 44 53 44 53 9.3 6.6 4.2MAX 30 18 23 7.5 8 44 53 44 53 8.8 7.2 4.2MAX 28 15 18 6.5 12 38 45 44 53 11.8 5.2 4.8MAX 36 18 20 9.5 8.5 38 45 44 53 12 6.7 4.8MAX 25 9 10 6.5 7.5 38 45 44 53 7 6.9 4.6MAX 20 12 12 7 6 38 45 44 53 7.4 6.5 4.5
INPUT OUTPUT MAX or MIN AC11
SN74AC
CD74AC
ACT11
SN74ACT
CD74ACT AHC AHCT LV
3VLV5V
LVC3V
ALVCH3V
tw High MIN 4 4.5 4 5 8 4 5 6.5 5 5 3.3 3.3Low MIN - - 4 - - 4 - - - - - -
MIN 3.5 4.5 2 3.5 8 2 4 1.5 4 4 2 0.5MIN 2 1 3 3.5 1 3 1 3.5 1 1 1.5 1.2MAX 10.3 10.5 8.5 11.8 11.5 10.4 10.5 10.5 17 10.5 6.8 3.6MAX 8.4 10.5 8.5 10 11.5 10.4 10.5 10.5 17 10.5 6.8 3.6MAX 11.3 10.5 12 13 11.5 12.5 10.5 14.5 16.5 10.5 7.6 3.3MAX 10.2 10.5 12 12.2 11.5 12.5 10.5 14.5 16.5 10.5 7.6 3.3MAX 10.8 9.5 10.5 12.5 10.5 13.5 11.5 13.5 17 11.5 7.7 4.8MAX 9.7 9.5 10.5 12 10.5 13.5 11.5 13.5 17 11.5 7.7 4.8MAX 11.1 12.5 11.5 12.2 12.5 12.5 10.5 12 15 10.5 7 4.4MAX 8.7 10 11.5 10.1 10 12.5 10.5 12 15 10.5 7 4.4
UNIT fmax : MHz, other : ns
tPHZOE Q
tPLZ
tPZHOE Q
tPZL
tPHL
tPLHQ
tPHL
PARAMETER
tsuthtPLH
OE
D Q
LE
OE Q
Q
tsuth
tPLH
D Q
LE Q
PARAMETER
tPZH
tPZL
tPHZ
tPLZ
tPLH
tPHL
tPHL
326
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
374OCTAL D-TYPE FLIP-FLOPS
Buffered Control Inputs 74AC11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series) 74ACT11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series)
OE
To Seven Other Channels
1
11
32
CLK
1D
C1
1D1Q
FUNCTION TABLE
CLK D QOUTPUT
CONTROLINPUTS OUTPUT
LLLH
HL
↑↑
XX
LX
HL
Q0Z
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LS S ALS AS F SN74HC
CD74HC
SN74HCT
CD74HCT
SN74BCT ABT LVTH
3V UNIT
ICC MAX 40 160 31 128 86 0.08 0.16 0.08 0.16 60 30 5 mAIOH MAX -2.6 -6.5 -2.6 -15 -3 -6 -6 -6 -6 -15 -32 -32 mAIOL MAX 24 20 24 48 24 6 6 6 6 64 64 64 mA
PARAMETER MAX or MIN AC11
SN74AC
CD74AC
ACT11
SN74ACT
CD74ACT AHC AHCT LV
3VLV5V
LVC3V
ALVCH3V UNIT
ICC MAX 0.08 0.04 0.16 0.08 0.04 0.16 0.04 0.04 - 0.02 0.01 0.01 mAIOH MAX -24 -24 -24 -24 -24 -24 -8 -8 -8 -16 -24 -24 mAIOL MAX 24 24 24 24 24 24 8 8 8 16 24 24 mA
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN LS S ALS AS F SN74HC
CD74HC
SN74HCT
CD74HCT
SN74BCT ABT LVTH
3V
MIN 35 75 35 125 70 24 20 25 20 70 150 150tw High MIN 15 6 14 4 7 20 24 20 24 7 3.3 3.3
Low MIN 15 7.3 14 3 6 20 24 20 24 - 3.3 3.3MIN 20 5 10 2 2 25 18 25 18 6.5 1.9 1.5MIN 0 2 0 2 2 5 5 10 5 0 2.1 0.8MAX 28 15 12 8 10 45 50 45 50 10.6 6.2 4.5MAX 28 17 16 9 10 45 50 45 50 10 7.1 4.2MAX 26 15 17 6 12.5 38 45 38 42 12.3 5.2 4.7MAX 28 18 18 10 8.5 38 45 38 42 12.7 6.7 4.7MAX 28 9 10 6 8 38 41 38 45 6.8 6.7 4.6MAX 20 12 18 6 6.5 38 41 38 45 6.8 6.5 4.5
INPUT OUTPUT MAX or MIN AC11
SN74AC
CD74AC
ACT11
SN74ACT
CD74ACT AHC AHCT LV
3VLV5V
LVC3V
ALVCH3V
MIN 95 100 12.5 55 90 110 75 75 50 75 100 150tw High MIN 5 4.5 4 9 5 4.5 5 6.5 5.5 5 3.3 3.3
Low MIN 5 4.5 4 9 5 4.5 5 6.5 5.5 5 3.3 3.3MIN 2.5 4.5 2 3 5.5 2 3 2.5 4.5 3 2 1.8MIN 3.5 1.5 2 5.5 1.5 3 2 2.5 2 2 1.5 0.5MAX 10.2 10.5 10.8 12.4 11.5 11.2 11.5 11.5 18.5 11.5 7 3.6MAX 10.1 10 10.8 13 11 11.2 11.5 11.5 18.5 11.5 7 3.6MAX 9.1 9.5 14.5 12.3 10.5 14.5 11 12.5 16.5 11 7.5 5.2MAX 9.4 9.5 14.5 12.3 10.5 14.5 11 12.5 16.5 11 7.5 5.2MAX 11.2 12.5 14.5 13.2 12.5 14.5 10 12 16 10 6.5 4.5MAX 9.2 10 14.5 10.8 10 14.5 10 12 16 10 6.5 4.5
UNIT fmax : MHz, other : ns
tPHZOE Q
tPLZ
tPZHOE Q
tPZL
tPLHCLK Q
tPHL
PARAMETER
fmax
tsuth
CLK Q
OE Q
OE Q
PARAMETER
tPZH
tPLH
tPHL
tsuth
fmax
tPHZ
tPLZ
tPZL
327
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
3754-BIT BISTABLE LATCHES
Complementary Outputs (Q, Q)
TO OTHERLATCH
ENABLE
DATA
Q
Q
FUNCTION TABLE
CD QINPUTS OUTPUTS
LHX
LH
Q0
H
LH
HL
Q0
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LS SN74HC UNIT
ICC MAX 12 0.04 mAIOH MAX -0.4 -4 mAIOL MAX 8 4 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN LS SN74HC
tw MIN 20 20tsu MIN 20 25th MIN 0 5tPLH MAX 27 30tPHL MAX 17 30tPLH MAX 20 30tPHL MAX 15 30tPLH MAX 27 33tPHL MAX 25 33tPLH MAX 30 33tPHL MAX 15 33UNIT: ns
D Q
D Q
C Q
C Q
328: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
Logic Diagram
377OCTAL D-TYPE FLIP-FLOPS
Individual Data Input to Each Flip-Flop 74ACT11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)
1D
1Q1D
C1
CLK
CLKEN
To Seven Other Channels
11
1
3
2
FUNCTION TABLE
CLOCKCLKEN Q Q
INPUTS OUTPUTS
HL
X
H
Q0
X
L
DATA
X
X
H LL LL
↑↑ H
Q0
Q0 Q0
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LS F SN74HC
CD74HC
SN74HCT
CD74HCT ABT AC
11 UNIT
ICC MAX 28 90 0.08 0.16 0.08 0.16 30 0.08 mAIOH MAX -0.4 -1 -4 -4 -4 -4 -32 -24 mAIOL MAX 8 20 4 4 4 4 64 24 mA
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN LS F SN74HC
CD74HC
SN74HCT
CD74HCT ABT AC
11
MIN 30 110 20 20 17 16 150 100MIN 20 5 25 24 25 30 3.3 5
tsu DATA MIN 20 2 25 18 15 18 2.5 4
CLKEN ACTIVE MIN 25 2.5 25 - 15 - 3 6
CLKEN INACTIVE MIN 10 4.5 25 18 15 18 3 6MIN 5 1 5 3 3 3 1.8 0MAX 27 10 40 53 45 57 6.5 11.3MAX 27 10.5 40 53 45 57 7.3 12.9
UNIT fmax : MHz, other : ns
PARAMETER
CLK QtPLH
tPHL
th
fmaxtw
329PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
378HEX D-TYPE FLIP-FROPS
FUNCTION TABLE
CLOCKG Q Q
INPUTS OUTPUTS
HL
X
H
Q0
X
L
DATAX
X
H LL LL
↑↑ H
Q0
Q0 Q0
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LS F SN74HC UNIT
ICC MAX 22 45 0.08 mAIOH MAX -0.4 -1 -4 mAIOL MAX 8 20 4 mA
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN LS F SN74HC
MIN 30 110 20tw CLK H MIN 20 4 25
CLK L MIN 20 6 25tsu DATA MIN 20 5 25
G ACTIVE MIN 25 3.5 25
G INACTIVE MIN 10 5 25MIN 5 0 5MAX 27 6.7 40MAX 27 6.1 40
UNIT fmax : MHz, other : ns
PARAMETER
CLK Q
fmax
thtPLH
tPHL
Logic Diagram
Q('LS379ONLY)
CLOCK
Q
Q
DCKEN TO 7('LS377)
5('LS378)3('LS379)
OTHER FILIP-FLOPS
CK
D
Q
ENABLEG
330
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
nQ0 nQ2 nQ3
3(13) 6(10) 7(9)
Q
R
Φ
Q
R
Φ
Q
R
Φ
Q
R
Φ
nQ1
5(11)
VCC = 16GND = 8
4(12)nCP1
1(15)nCP0
2(14)nMR
390DUAL DECADE COUNTERS
Individual Clock for A and B Flip-Flops Provide Dual ÷ 2 and ÷ 5 Counters All Have Direct Clear for Each 4-Bit Counter Typical maximum Count Frequency: 35MHz Buffered Outputs Reduce Possibility of Collector Commutation
QB
BCD COUNT SEQUENCE
OUTPUTS
LL
QCQD
4
0123
COUNT
5
HH
67
QA
89
FUNCTION TABLE
LLLLLL
LLLL
LL
HH
HH
LLHHLLHHLL
L
HL
HL
HL
HL
H
QC
BI-QUINARY
OUTPUTS
LL
QDQA
4
0123
COUNT
5
HH
67
QB
89
LLLHHH
LLLL
LH
LL
HL
LLHHLLLHHL
L
HL
LH
HL
LH
L
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS SN74HC
CD74HC
CD74HCT UNIT
ICC MAX 69 26 0.08 0.16 0.16 mAIOH MAX -0.8 -0.4 -4 -4 -4 mAIOL MAX 16 8 4 4 4 mA
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN TTL LS SN74HC
CD74HC
CD74HCT
A QA MIN 25 25 25 20 18B QB MIN 20 12.5 25 20 18
tw A MIN 20 20 20 24 29B MIN 25 40 20 24 29
CLR H MIN 20 20 20 15 20MIN 25 25 5 - -MAX 20 20 30 53 60MAX 20 20 30 53 60MAX 60 60 72 - 126MAX 60 60 72 - 126MAX 21 21 33 56 65MAX 21 21 33 56 65MAX 39 39 46 74 83MAX 39 39 46 74 83MAX 21 21 33 54 63MAX 21 21 33 54 63
CLR Q MAX 39 39 41 57 63UNIT fmax : MHz, other : ns
B QD
PARAMETER
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPHL
A QA
A QC
B QB
B QC
tPHL
tPLH
fmax
tsutPLH
331
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
393DUAL 4-BIT BINARYCOUNTERS
Dual 4-Bit Binary Counter with Individual Clock All Have Direct Clear for Each 4-Bit Counter Typical maximum Count Frequency: 35MHz Buffered Outputs Reduce Possibility of Collector
Commutation
R
T
QA
CLR
CLK
R
T
QB
R
T
QC
R
T
QD
Q
Q
Q
Q
QB
INPUTS
LL
QCQD
4
0123
COUNT
5
HH
67
QA
89
FUNCTION TABLE
LLLLLL
LLLL
LL
HH
HH
LLHHLLHHLL
HL
HL
HL
L
HL
H1011
HH
12131415
HHHH
HH
HH
LL
HHLLHH
L
HL
HL
H
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN TTL LS SN74HC
CD74HC
CD74HCT
LV3V
LV5V UNIT
ICC MAX 64 26 0.08 0.16 0.16 - 0.02 mAIOH MAX -0.8 -0.4 -4 -4 -4 -6 -12 mAIOL MAX 16 8 4 4 4 6 12 mA
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN TTL LS SN74HC
CD74HC
CD74HCT
LV3V
LV5V
MIN 25 25 25 20 18 35 75tw A MIN 20 20 20 24 29 5 5
B MIN 25 40 20 24 29 5 5CLR H MIN 20 20 20 24 24 5 5
MIN 25 25 5 - - 5 4MAX 20 20 30 59 48 19 12MAX 20 20 30 59 48 19 12MAX 60 60 72 86 93 26.5 16.5MAX 60 60 72 86 93 26.5 16.5
CLR Q MAX 39 39 41 41 48 18 11.5UNIT fmax : MHz, other : nstPHL
fmax
tsu
PARAMETER
tPLH
tPHL
tPLH
tPHL
A QA
B QD
332
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
(7)
(10)
R
D
CLR
(6)
QD
(12)
QD'CASCADEOUTPUT
(11)
Q
S
CK
Q
R
C
CLR
(5)
QC
(13)
Q
S
CK
Q
R
B
DATA INPUTS
3-STATE OUTPUTS
CLR
(4)
QB
(14)
Q
S
CK
Q
R
A
CLR
(3)
QA
(15)
Q
LD/SH(2)
SER
(1)CLR
(9)OC
CLK
S
CK
Q
395CASCADABLE UNIVERSAL SHIFT REGISTERS
3-State Outputs Parallel-In, Parallel-Out Registers Low Power Dissipation: 75mW Typical (Enable)
333PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
FUNCTION TABLE
3-STATE OUTPUTSINPUTS
XH
LOAD/SHIFTCONTROL
SERIALPARALLEL
H
LHHH H
CLEAR
H
CASCADEOUTPUT
QD
HLLL
↓
↓↓
XH
XXXXHL
L
d
AX
XX
aX
X
BX
XX
bX
X
CX
XX
cX
X
DX
XX
dX
X
QC
L
QDn
QCn
dQD0 QD0
QCn
QA
L
QA0
L
aQA0
H
QB
L
QBn
QAn
bQB0
QAn
L
QCn
QBn
cQC0
QBn
QDO
QCn
QCn
CLOCK QD
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LS UNIT
MAX 34 mAQA, QB, QC, QD MAX -2.6 mA
QD' MAX -0.4 mAQA, QB, QC, QD MAX 24 mA
QD' MAX 8 mAIOL
ICC
IOH
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN LS
MIN 30MIN 16
tsu LD/SH MIN 40OTHER MIN 20
MIN 10MAX 30MAX 30
UNIT fmax : MHz, other : nstPHL
CLK Q
fmaxtw
thtPLH
PARAMETER
334
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1S
A1
WORDSELECT
A2
1R
C1
QA
1S
B1
B2
1R
C1
QB
1S
C1
C2
1R
C1
QC
1S
D1
D2
1R
C1
QD
CLOCK
399QUAD 2-INPUT MULTIPLEXER WITH STORAGE
Single-Rail Outputs (Q, Q) Select One of Two 4-Bit Data Sources and Stores Data Synchronously with System Clock
FUNCTION TABLE
CLOCKWORD
SELECTQC QD
INPUTS OUTPUTS
L
XC2
QC0L↑↑
QB
B1B2 D2H
QA
A1A2
QD0QA0 QB0
C1 D1
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LS UNIT
ICC MAX 13 mAIOH MAX -0.4 mAIOL MAX 8 mA
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN LS
MIN 20tsu DATA MIN 25
WORD SELECT MIN 45th DATA MIN 0
WORD SELECT MIN 0MAX 27MAX 32
UNIT: ns
CLK Q
PARAMETER
tPLH
tPHL
tw
335PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
Logic Diagram
CLR
B
A
Q
Q
R
Rext/Cext
Cext
423RE-TRIGGERABLE MONO-STABLE MULTIVIBRATOR
Will Not Trigger from Clear
FUNCTION TABLE
BINPUTS OUTPUTS
LX
ACLR Q
XHH
X LLL
H
X
LX
XL ↑↓
H
QH
HH
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LS CD74HC
CD74HCT UNIT
ICC MAX 20 0.16 0.16 mAIOH MAX -0.4 -4 -4 mAIOL MAX 8 4 4 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN LS CD74HC
CD74HCT
t MIN 40 30 30A 33 90 -B 44 90 -A 45 96 -B 56 96 -
tPLH Q MAX 27 65 -tPHL Q MAX 45 65 -UNIT: ns
CLR
tPLH
tPHL
MAX
MAX
Q
Q
336
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
B TRANSCEIVERS
COMMONCONTROLS
A
C
CS
GA
GB
S0
S1
GC
442QUADRUPLE TRIDIRECTIONAL BUS TRANSCEIVERS
337PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
FUNCTION TABLEINPUTS
L
HXX
S1 GA
XX
XH
TRANSFERSBUSESS0
L
XHX
X
XXH
XXH
XXH
GB
H
GC
H NoneLX H H X H NoneHX L
LHLLHLLHL
H H XX L LL X LLXHLXLH
LLXHHXL
XHLXLHX
NoneL L A → B, A → CL L B → C, B → ALLLL
HLLHLLH
C → A, C → BA → BB → CC → A
L A → CL B → AL C → B
None
NoneNone
CS
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LS UNIT
ICC MAX 95 mAIOH MAX -15 mAIOL MAX 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN LS
A B or CB A or CC A or BA B or CB A or CC A or B
Any G 33S0, S1 A, B, C 42
CS 36tPZH G, S, CS A, B, C MAX 32tPLZ G, S, CS A, B, C MAX 35tPHZ G, S, CS A, B, C MAX 25UNIT:ns
MAX
tPLH
tPHL
tPZL
14
20
MAX
MAX
338
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
Y817
Y715
Y613
Y511
Y49
Y37
Y25
Y13
18A8
16A7
14A6
12A5
8A4
6A3
4A2
2A1
19G2G1
1
† These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
465OCTAL BUFFERS 3-STATE OUTPUTS
339PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LS ALS UNIT
ICC MAX 37 33 mAIOH MAX -2.6 -15 mAIOL MAX 24 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN LS ALS
tPLH MAX 15 13tPHL 18 12tPZH MAX 40 23tPZL 45 25tPHZ MAX 40 10tPLZ 45 18UNIT:ns
YG
G
A Y
340
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
19
17
18
15
16
13
14
11
12
8
9
6
7
4
5
2
3
1
P = Q
P7
Q7
P6
Q6
P5
Q5
P4
Q4
P3
Q3
P2
Q2
P1
Q1
P0
Q0
G
5188-BIT IDENTITY COMPARATOR
Open-Collector Outputs 20-kΩ Pullup Resistors on Q Inputs
341PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
FUNCTION TABLEINPUTS OUTPUT
P = Q
P > Q
ENABLEG
DATAP, Q
P = Q
P < QX
L
L
H L
L
H
LL
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALS UNIT
ICC MAX 17 mAIOL MAX 24 mAVOH MAX 5.5 V
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALS
tPLH 33tPHL 15tPLH 33tPHL 15UNIT: ns
MAX
MAX
P or Q
G
P = Q
P = Q
342
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
19
17
18
15
16
13
14
11
12
8
9
6
7
4
5
2
3
1
P = Q
P7
Q7
P6
Q6
P5
Q5
P4
Q4
P3
Q3
P2
Q2
P1
Q1
P0
Q0
G
5208-BIT IDENTITY COMPARATOR
20-kΩ Pullup Resistors on Q Inputs 74AC11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)
343PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALS F AC11 UNIT
ICC MAX 19 32 8 mAIOH MAX -2.6 -1 -24 mAIOL MAX 24 20 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALS F AC11
tPLH 12 8.7 12.6tPHL 20 10.3 11.3tPLH 12 6.4 7.4tPHL 22 10.4 7.8UNIT: ns
MAX
MAX
P or Q
OE
P = Q
P = Q
FUNCTION TABLEINPUTS OUTPUT
P = Q
P > Q
ENABLEOE
DATAP, Q
P = Q
P < QX
L
L
H H
L
L
HH
344
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
19
17
18
15
16
13
14
11
12
8
9
6
7
4
5
2
3
1
P = Q
P7
Q7
P6
Q6
P5
Q5
P4
Q4
P3
Q3
P2
Q2
P1
Q1
P0
Q0
G
5218-BIT IDENTITY COMPARATOR
74AC11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)
345PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALS F AC11 UNIT
ICC MAX 19 32 0.08 mAIOH MAX -2.6 -1 -24 mAIOL MAX 24 20 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALS F AC11
tPLH 12 11 13tPHL 20 11 11.4tPLH 12 7.5 7.9tPHL 22 10 8.1UNIT: ns
P or Q
G
P = Q
P = Q
MAX
MAX
FUNCTION TABLEINPUTS OUTPUT
P = Q
P > Q
ENABLEG
DATAP, Q
P = Q
P < QX
L
L
H H
L
L
HH
346
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1D
C1
OE
1D
1Q
LE
1
11
3
2
To Seven Other Channels
533OCTAL D-TYPE TRANSPARENTLATCHES
3-State Bus-Driving Inverting Outputs Functionally Equivalent to '373, Except for Having
Inverted Outputs 74AC11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series) 74ACT11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series)
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALS AS SN74HC
CD74HC
SN74HCT
CD74HCT ABT AC
11SN74
ACACT11
SN74ACT UNIT
ICC MAX 28 110 0.08 0.16 0.08 0.16 30 0.08 0.04 0.08 0.04 mAIOH MAX -2.6 -15 -6 -6 -6 -6 -32 -24 -24 -24 -24 mAIOL MAX 24 48 6 6 6 6 64 24 24 24 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALS AS SN74HC
CD74HC
SN74HCT
CD74HCT ABT AC
11SN74
ACACT11
SN74ACT
t MIN 15 2 20 24 25 24 3.3 4 5 5 6tsu MIN 15 2 13 15 13 15 2.1 3.5 4.5 3.5 4th MIN 7 3 5 11 5 12 2.1 2 1 3.5 2.5tPLH 19 7.5 38 50 44 51 6.4 9.8 11 11.3 11.5tPHL 13 7 38 50 44 51 6.6 8 10.5 9.5 11tPLH 23 9 44 53 44 57 7.3 11.3 11.5 13 11.5tPHL 18 8 44 53 44 57 7.3 10.3 11 12.2 11.5tPZH 17 6.5 38 45 44 53 5.7 10.8 10.5 12.5 11tPZL 18 9.5 38 45 44 53 6.7 9.7 10.5 12 11tPHZ 10 6.5 38 45 44 45 6.9 11.4 11 12.8 11tPLZ 16 7 38 45 44 45 6.5 8.9 11 10.3 11UNIT: ns
MAX
MAX
MAX
MAX
D
LE(CD74: LE)
OE
OE
Q
Q
Q
Q
FUNCTION TABLEINPUTS
OUTPUT
L
L
DOC Q
LH
H
X
X Z
L
L
Q0
H
ENABLEC
H
L
X
H
347
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
534OCTAL D-TYPE EDEG-TRIGGERED FLIP-FLOPS
3-State Bus-Driving Inverting Outputs '534 Have Inverted Outputs, But Otherwise Are
Functionally Equivalent to '374 74AC11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series) 74ACT11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series)
1D
C1
OE
1D
1Q
CLK
1
11
3
2
To Seven Other Channels
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALS AS SN74HC
CD74HC
SN74HCT
CD74HCT ABT AC
11SN74
ACCD74
ACACT11
SN74ACT UNIT
ICC MAX 31 128 0.08 0.16 0.08 0.16 30 0.08 0.04 0.16 0.08 0.04 mAIOH MAX -2.6 -15 -6 -6 -6 -6 -32 -24 -24 -24 -24 -24 mAIOL MAX 24 48 6 6 6 6 64 24 24 24 24 24 mA
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN ALS AS SN74HC
CD74HC
SN74HCT
CD74HCT ABT AC
11SN74
ACCD74
AC
MIN 35 125 25 20 25 16 125 75 140 125tw CLK "H" 14 4 20 24 20 30 3.5 6.5 4 4
CLK "L" 14 3 20 24 20 30 3.5 6.5 4 410 2 25 18 25 30 1.6 3.5 4 20 2 5 5 5 5 2 4.5 1.5 2
12 8 45 50 45 53 6.7 11.7 12 11.316 9 45 50 45 53 7.6 12.1 11 11.317 6 38 45 37 53 5 10.4 11.5 14.518 10 38 45 37 53 6.8 10.4 11.5 14.510 6 38 45 37 45 7.3 11.6 12.5 14.514 6 38 45 37 45 6.5 9.2 11 14.5
INPUT OUTPUT MAX or MIN ACT11
SN74ACT
MIN 55 120
tw CLK "H" 9 3.5CLK "L" 9 3.5
3 45.5 1.5
14.5 12.515 12
13.3 12.513.5 11.513.5 13.512 10.5
UNIT fmax : MHz, other : ns
tPHZOE Q MAX
tPLZ
tPZHOE Q MAX
tPZL
tPLH CLK(CD74: CP) Q MAX
tPHL
PARAMETER
fmax
MIN
tsuMIN
th
PARAMETER
tPHZ
tPLZ
fmax
tsuthtPLH
tPHL
tPZH
tPZL
MAX
MIN
MAX
MIN
MAX
CLK(CD74: CP)
OE
OE
Q
Q
Q
FUNCTION TABLEINPUTS OUTPUT
L
L
DOC Q
LH
H
X
X Z
L
L
Q0
H
CLK
L
X
↑↑
348
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
540OCTAL BUFFERS ANDLINE DRIVERS
3-State Outputs Drive Bus Lines or Buffer MemoryAddress Registers
P-N-P Inputs Reduce D-C Loading Schmitt-Triggered Inputs (SN74LS540)
OE1
OE2
To Seven Other Channels
A1 Y1
1
19
2 18
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LS ALS ALSA-1
SN74HC
CD74HC
SN74HCT
CD74HCT
SN74BCT ABT LVTH
3VCD74
ACCD74ACT AHC AHCT UNIT
ICC MAX 52 22 22 0.08 0.16 0.08 0.16 71 30 5 0.16 0.16 0.04 0.04 mAIOH MAX -15 -15 -15 -6 -6 -6 -6 -15 -32 -32 -24 -24 -8 -8 mAIOL MAX 24 24 48 6 6 6 6 64 64 64 24 24 8 8 mA
PARAMETER MAX or MIN LV3V
LV5V
LVC3V UNIT
ICC MAX - 0.02 0.01 mAIOH MAX -8 -16 -24 mAIOL MAX 8 16 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN LS ALS ALSA-1
SN74HC
CD74HC
SN74HCT
CD74HCT
SN74BCT ABT LVTH
3V
tPLH 15 12 12 25 33 25 36 6.9 4.8 3.8tPHL 15 9 9 25 33 25 36 4 4.8 3.8tPZH 25 15 15 38 48 38 53 10.1 5.9 5.2tPZL 38 20 20 38 48 38 53 11.3 6.4 5.3tPHZ 25 10 10 38 48 38 53 9 7.3 5.6tPLZ 18 12 12 38 48 38 53 8.5 6.2 5
PARAMETER INPUT OUTPUT MAX or MIN CD74AC
CD74ACT AHC AHCT LV
3VLV5V
LVC3V
tPLH 68 7.2 8 10 12 8 5.3tPHL 68 7.2 8 10 12 8 5.3tPZH 12 13.4 10.5 12 16 10.5 6.6tPZL 12 13.4 10.5 12 16 10.5 6.6tPHZ 12 13.4 10 12 17.5 10 7.4tPLZ 12 13.4 10 12 17.5 10 7.4UNIT: ns
A
OE
OE
MAX
Y(CD74: Y) MAX
Y(CD74: Y) MAX
Y(CD74: Y)
A Y(CD74: Y) MAX
OE Y(CD74: Y) MAX
OE Y(CD74: Y) MAX
349
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
541OCTAL BUFFERS ANDLINE DRIVERS
3-State Outputs Drive Bus Lines or Buffer MemoryAddress Registers
P-N-P Inputs Reduce D-C Loading Schmitt-Triggered Inputs (SN74LS541)
OE1
OE2
To Seven Other Channels
A1 Y1
1
19
2 18
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LS ALS ALSA-1 F SN74
HCCD74
HCSN74HCT
CD74HCT
SN74BCT ABT LVTH
3VCD74
ACCD74ACT AHC UNIT
ICC MAX 55 25 25 75 0.08 0.16 0.08 0.16 72 30 5 0.16 0.16 0.04 mAIOH MAX -15 -15 -15 -15 -6 -6 -6 -6 -15 -32 -32 -24 -24 -8 mAIOL MAX 24 24 48 64 6 6 6 6 64 64 64 24 24 8 mA
PARAMETER MAX or MIN AHCT LV3V
LV5V
LVC3V UNIT
ICC MAX 0.04 - 0.02 0.01 mAIOH MAX -8 -8 -16 -24 mAIOL MAX 8 8 16 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN LS ALS ALSA-1 F SN74
HCCD74
HCSN74HCT
CD74HCT
SN74BCT ABT
tPLH 15 14 14 6 29 35 29 42 6 3.6tPHL 18 10 10 6 29 35 29 42 8.2 3.9tPZH 32 15 15 9.5 38 48 38 53 10.7 4tPZL 38 20 20 9.5 38 48 38 53 11.5 5.9tPHZ 29 10 10 6.5 38 48 38 53 8.6 5.8tPLZ 18 12 12 6 38 48 38 53 8.6 4.4
PARAMETER INPUT OUTPUT MAX or MIN LVTH3V
CD74AC
CD74ACT AHC AHCT LV
3VLV5V
LVC3V
tPLH 3.5 7.8 8.2 8 9.5 12 8 5.1tPHL 3.5 7.8 8.2 8 9.5 12 8 5.1tPZH 5.2 12 13.4 10.5 12 16 10.5 7tPZL 5.3 12 13.4 10.5 12 16 10.5 7tPHZ 5.6 12 13.4 10 12 17.5 10 7tPLZ 5 12 13.4 10 12 17.5 10 7UNIT: ns
MAX
A
OE
OE
Y
A Y MAX
MAX
Y MAX
Y
OE Y MAX
OE Y MAX
350
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
OEBA
CEBA
LEBA
OEAB
CEAB
LEAB
A1B1
To Seven Other Channels
2
23
1
13
11
14
322
C1
1D
C1
1D
543OCTAL REGISTERED TRANSCEIVERS
Back-to-Back Registers for Storage 3-State True Outputs 74ACT11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)
351PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
INPUTS OUTPUT
CEAB LEAB OEAB A B
H X X X Z
X X X Z
L H X B0‡
L L
H
L
L L L
L L L H H
† A-to-B data flow is shown; B-to-A flow control is thesame except that it uses CEBA, LEBA, and OEBA.
‡ Output level before the indicated steady-stateinput conditions were established
FUNCTION TABLE†
RECOMMENDED OPERATING CONDITIONS
MAX or MIN F SN74BCT ABT LVTH
3VACT11
LVC3V UNIT
MAX 100 8 0.25 0.19 0.08 0.01 mAMAX 125 71 30 5 0.08 0.01 mAMAX 125 15 0.25 0.19 0.08 0.01 mA
A MAX -3 -15 -32 -32 -24 -24 mA
B MAX -15 -15 -32 -32 -24 -24 mA
A MAX 24 64 64 64 24 24 mA
B MAX 64 64 64 64 24 24 mA
PARAMETER
IOL
ICCH
ICCL
ICCZ
IOH
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN F SN74BCT ABT LVTH
3VACT11
LVC3V
t MIN 5 7 3.5 3.3 4 3.3tsu LE before "H" 3.5 4.5 3.5 0.4 2.5 1.6
LE before "L" 3.5 4.5 3 1 2.5 1.6CE before "H" - - 3.5 0.2 3 1.6CE before "L" - - 3 0.7 3 1.6
th LE after "H" 3.5 1.5 0.5 1.5 2 2.1LE after "L" 3.5 1.5 0.5 1.3 2 2.1CE after "H" - - 0.5 1.6 1.5 2.1CE after "L" - - 0.5 1.4 1.5 2.1
8.5 8.8 6.9 3.7 10.2 77.5 9.6 6.9 3.7 12.1 7
12.5 12.9 6.6 4.7 11.2 8.512.5 12.7 7.1 4.7 13.2 8.512.5 12.9 6.6 4.7 11.2 8.512.5 12.7 7.1 4.7 13.2 8.510 10.7 6.4 4.9 11.5 7.712 12.3 7.5 4.9 15.3 7.79 8.1 8.4 5.3 10.4 7
8.5 7.2 8 5.3 10.5 710 12 6.4 5.3 12.2 812 13.5 7.5 5.3 16 89 8.5 8.4 5.4 11 7
8.5 7.6 8 5.4 11.1 7UNIT: ns
tPHLA or B
tPLZ
tPZH
PARAMETER
tPHL
tPZH
tPZL
tPHZ
tPLH
tPLH
tPHL
MAX
A
B
MIN
MIN
MAXB or A
LEAB
LEBAtPLH
MAX
OE A or B
OE A or B
MAX
MAX
CE A or B MAXtPZL
tPHZCE A or B MAX
tPLZ
352
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
RS
1DC1
RS
1DC1
RS
1DC1
RS
1DC1
17
12
7
9
11
2
8
1
3
4
5
6
18
19
16
15
14
13
CCO
RCO
QA
QB
QC
QD
OE
ENT
ENP
SCLR
SLOAD
CLK
ACLR
ALOAD
A
B
C
D
561SYNCHRONOUS 4-BIT COUNTER
3-State Outputs Choice of Asynchronous or Synchronous Clearing and Loading Internal Look-Ahead Circuitry for Fast Cascading
353PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
FUNCTION TABLE
ACLROE
INPUTS
HL
L
XALOAD
X
H
XL L
LH
L H
ENPX
X
XX
XL HL H
HHHH
SCLRX
L
XX
HHH
ENTX
X
XX
XHL
HX
CLKXXX
X
SLOADX
X
XX
LHH
L HH H X L XH
OPERATION
Q outputs disabledAsynchronous clearAsynchronous loadSynchronous clearSynchronous loadCountInhibit countingInhibit counting
↑↑↑
RECOMMENDED OPERATING CONDITIONS
MAX or MIN ALS UNIT
MAX 36 mAOUTPUT Q MAX -2.6 mACCO & RCO MAX -0.4 mAOUTPUT Q MAX 24 mACCO & RCO MAX 8 mA
PARAMETER
ICC
IOL
IOH
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN ALS
MIN 30tw 16.5
16.5tsu H 20
L 2020
L 15H 30L 15H 30
MIN 012182924352355331614
ACLR Q MAX 22UNIT fmax : MHz, other : ns
tPHL
tPLH
tPHL
tPHL
tPHL
tPLH
tPHL
tPLH
thtPLH
tPHL
tPLH
A, B, C, D
SCLR
SLOAD
PARAMETER
fmaxCLK "H"CLK "L"
ENP orENT
CLK
CLK
ALOAD
ALOAD
ENT RCO
CCO
Q
RCO
Q MAX
MAX
MIN
MAX
MAX
MAX
MIN
354
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
OE
LE
1D1Q
1
11
219
To Seven Other Channels
C1
1D
563OCTAL D-TYPE TRANSPARENT LATCHESWITH INVERTED OUTPUTS
3-State Buffer-Type Outputs Drive Bus LinesDirectly
Bus-Structured Pinout
FUNCTION TABLEINPUTS
OUTPUT
L
L
DOE Q
LH
H
X
X Z
L
L
Q0
H
ENABLELE
H
L
X
H
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALS SN74HC
CD74HC
SN74HCT
CD74HCT
SN74AC
CD74AC
SN74ACT UNIT
ICC MAX 29 0.08 0.16 0.08 0.16 0.08 0.16 0.04 mAIOH MAX -2.6 -6 -6 -6 -6 -24 -24 -24 mAIOL MAX 24 6 6 6 6 24 24 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALS SN74HC
CD74HC
SN74HCT
CD74HCT
SN74AC
CD74AC
SN74ACT
t 15 20 24 25 24 5 4 3tsu 10 13 15 13 15 2.5 2 4.5th 10 5 4 10 5 2 3 0tPLH 18 44 45 44 45 11.5 10.5 12.5tPHL 14 44 45 44 45 11 10.5 11tPLH 22 44 50 44 53 11 12 11.5tPHL 21 44 50 44 53 9.5 12 10.5tPZH 18 38 45 44 53 10 10.5 10tPZL 18 38 45 44 53 9.5 10.5 9.5tPHZ 10 38 45 44 53 12 11.5 11.5tPLZ 15 38 45 44 53 9 11.5 8.5UNIT: ns
OE Q
OE Q
MAX
Q
Q
MAX
MIN
MAX
MAX
D
LE(CD74: LE)
355
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
564OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
3-State Buffer-Type Inverting Outputs Drive BusLines Directly
Bus-Structured Pinout
OE
CLK
1D1Q
1
11
219
To Seven Other Channels
C1
1D
FUNCTION TABLEINPUTS OUTPUT
L
L
DOE Q
LH
H
X
X Z
L
L
Q0
H
CLK
L
X
↑
↑
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALS SN74HC
CD74HC
SN74HCT
CD74HCT
SN74AC
SN74ACT UNIT
ICC MAX 30 0.08 0.16 0.08 0.16 0.04 0.04 mAIOH MAX -2.6 -6 -6 -6 -6 -24 -24 mAIOL MAX 24 6 6 6 6 24 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALS SN74HC
CD74HC
SN74HCT
CD74HCT
SN74AC
SN74ACT
fmax MIN 30 25 20 25 16 85 75
tw CLK H 14 20 24 20 30 5 3.5
CLK L 14 20 24 20 30 5 3.5
tsu CLK 15 25 18 25 30 2.5 3
th CLK 0 5 5 5 3 2 1tPLH 14 45 50 45 53 11.5 11.5tPHL 14 45 50 45 53 10.5 10.5tPZH 18 38 45 38 53 9.5 9.5tPZL 18 38 45 38 53 9.5 9.5tPHZ 10 38 41 38 45 11.5 11.5tPLZ 15 38 41 38 45 9 8.5UNIT fmax : MHz, other : ns
OE
OE
CLK
Q
Q
Q
MAX
MAX
MIN
MAX
356
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
C11DR
C11DR
C11DR
C11DR
17
1
2
12
9
11
8
3
4
5
6
7
18
19
16
15
14
13
CCO
RCO
QA
QB
QC
QD
OE
U/D
CLK
ENT
ENP
SCLR
LOAD
ACLR
A
B
C
D
569SYNCHRONOUS 4-BIT UP/DOWN COUNTERS
3-State Q Outputs Drive Bus Lines Directly Fully Synchronous Clear, Count, and Load Asynchronous Clear Is Also Provided Fully Cascadable
357PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
FUNCTION TABLE
ACLROE
HL
L
XSCLR
X
H
XL L
LH
L H
U/D
X
X
XX
HL HL H
HHHH
LOAD
X
L
XX
HHH
ENP
X
X
XX
LLX
LX
CLK
XX
X
ENT
X
X
XX
LLH
L HH H H X XX
INPUTS
Q outputs disabledAsynchronous clear
↑↑↑↑
Synchronous clearLoadCount upCount downInhibit countInhibit count
OPERATION
RECOMMENDED OPERATING CONDITIONS
MAX or MIN ALS UNIT
ICC MAX 32 mAIOH OUTPUT Q -2.6 mA
CCO & RCO -0.4 mAIOL OUTPUT Q 24 mA
CCO & RCO 8 mA
PARAMETER
MAX
MAX
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN ALS
fmax MIN 30tw 15
16.516.5
tsu 20High 30Low 20High 15Low 30High 15Low 30
3010
th MIN 0131628191513
ACLR Q MAX 2018241013
UNIT fmax : MHz, other : ns
PARAMETER
ACLR, LOADMINCLK "H"
CLK "L"Data at A, B, C, D
MIN
ENP, ENT
SCLR
LOAD
UDACLR
tPLHCLK ANY Q MAX
tPHL
tPLHRCO MAX
tPHLCLK
tPHL
tPLHRCO MAX
tPHLENT
MAXtPZL
tPHZOE Q MAX
tPLZ
tPZHOE Q
358
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
573OCTAL D-TYPE TRANSPARENTLATCHES
3-State Buffer-Type Outputs Drive Bus LinesDirectly
Bus-Structured Pinout
OE
To Seven Other Channels
1
11
219
LE
1D
C1
1D1Q
FUNCTION TABLEINPUTS
OUTPUT
L
L
DOE Q
LH
H
X
X Z
L
H
Q0
L
ENABLELE
H
L
X
H
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALS AS F SN74HC
CD74HC
SN74HCT
CD74HCT
SN74BCT ABT LVTH
3VSN74
ACCD74
ACSN74ACT UNIT
ICC MAX 27 106 55 0.08 0.16 0.08 0.16 62 30 5 0.04 0.16 0.04 mAIOH MAX -2.6 -15 -3 -6 -6 -6 -6 -15 -32 -32 -24 -24 -24 mAIOL MAX 24 48 24 6 6 6 6 64 64 64 24 24 24 mA
PARAMETER MAX or MIN CD74ACT AHC AHCT LV
3VLV5V
LVC3V UNIT
ICC MAX 0.16 0.04 0.04 - 0.02 0.01 mAIOH MAX -24 -8 -8 -8 -16 -24 mAIOL MAX 24 8 8 8 16 24 mA
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN ALS AS F SN74HC
CD74HC
SN74HCT
CD74HCT
SN74BCT ABT LVTH
3V
t LE 10 4.5 6 20 24 25 24 4 3.3 3.3tsu LE MIN 10 2 2 13 15 13 20 1 1.9 0.7th LE 7 3 3 5 12 5 15 4 1.8 1.5tPLH 14 8 8 44 53 44 53 8.4 5.9 3.9tPHL 14 7 6 44 53 44 53 9.6 6.2 3.9tPLH 20 13 13 44 53 44 53 8.1 6.6 4.2tPHL 19 7.5 8 44 53 44 53 7.8 7.2 4.2tPZH 18 6.5 12 38 45 44 53 10.4 5.2 5.1tPZL 18 9.5 8.5 38 45 44 53 11 6.7 5.1tPHZ 10 6.5 7.5 38 45 44 53 6 7.1 4.9tPLZ 15 7 6 38 45 44 53 6 6.5 4.6
INPUT OUTPUT MAX or MIN SN74AC
CD74AC
SN74ACT
CD74ACT AHC AHCT LV
5VLV3V
LVC3V
t LE 5 4 4 4 5 5 5 5 3.3tsu LE MIN 3.5 2 3.5 2 3.5 3.5 3.5 3.5 2th LE 2 3 0 3 1.5 1.5 1.5 1.5 1.5tPLH 11.5 8.5 12 10.4 10 7.5 10 16.5 6.9tPHL 11 8.5 12 10.4 10 10 10 16.5 6.9tPLH 11 12 12 12.5 11 8.5 11 17.5 7.7tPHL 10 12 10.5 12.5 11 10 11 17.5 7.7tPZH 10 10.5 11 13.5 11 8 11 17 7.5tPZL 9.5 10.5 10.5 13.5 11 11 11 17 7.5tPHZ 12 11.5 12.5 12.5 11 12 11 16.5 6.5tPLZ 9 11.5 9.5 12.5 11 10.5 11 16.5 6.5UNIT: ns
MAX
PARAMETER
OE
OE
LE
D
PARAMETER
D Q
Q
Q
Q
Q
MAX
MAX
MAX
MAX
LE(CD74AC/ACT: LE) Q MAX
Q MAX
OE Q MAX
OE
359
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
574OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
3-State Buffer-Type Noninverting Outputs DriveBus Lines Directly
Bus-Structured Pinout
OE
CLK
1D1Q
To Seven Other Channels
C1
1
11
219
1D
FUNCTION TABLEINPUTS OUTPUT
L
L
DOE Q
LH
H
X
X Z
L
H
Q0
L
CLK
L
X
↑
↑
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALS AS F SN74HC
CD74HC
SN74HCT
CD74HCT
SN74BCT ABT LVTH
3VSN74
ACCD74
ACSN74ACT UNIT
ICC MAX 28 134 86 0.08 0.16 0.08 0.16 62 30 5 0.04 0.16 0.04 mAIOH MAX -2.6 -15 -3 -6 -6 -6 -6 -15 -32 -24 -24 -24 -24 mAIOL MAX 24 48 24 6 6 6 6 64 64 24 24 24 24 mA
PARAMETER MAX or MIN CD74ACT AHC AHCT LV
3VLV5V
LVC3V UNIT
ICC MAX 0.16 0.04 0.04 - 0.02 0.01 mAIOH MAX -24 -8 -8 -8 -16 -24 mAIOL MAX 24 8 8 8 16 24 mA
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN ALS AS F SN74HC
CD74HC
SN74HCT
CD74HCT
SN74BCT ABT LVTH
3V
fmax MIN 35 125 100 24 20 24 20 77 150 150
tw MIN 14 5.5 7 20 24 20 24 6.5 3.3 3.3
tsu MIN 15 5.5 2 25 18 25 18 6 1.5 2
th MIN 0 0 2 5 5 5 5 0 1.8 0.3tPLH 14 8 10 45 50 45 50 10 6.8 4.5tPHL 14 9 10 45 50 45 50 8.9 7.1 4.5tPZH 18 6 12.5 38 45 38 45 10.4 5.1 4.8tPZL 18 10 8.5 38 45 38 45 10.9 6.7 4.8tPHZ 10 6 8 38 41 38 42 7.5 7 4.8tPLZ 12 6 6.5 38 41 38 42 6.4 6.5 4.4
INPUT OUTPUT MAX or MIN SN74AC
CD74AC
SN74ACT
CD74ACT AHC AHCT LV
3VLV5V
LVC3V
fmax MIN 85 125 85 110 75 75 45 75 100
tw MIN 5 4 4 4.5 5 5.5 5 5 3.3
tsu MIN 2 2 2.5 2 3 3.5 3.5 3.5 2
th MIN 1.5 2 0 3 1.5 1.5 1.5 1.5 1.5tPLH 11 10.8 12 11.2 12 12 19 12 7tPHL 9.5 10.8 11 11.2 12 12 19 12 7tPZH 9 14.5 10 14.5 12.5 12.5 18.5 12.5 7.5tPZL 9 14.5 10 14.5 12.5 12.5 18.5 12.5 7.5tPHZ 10.5 14.5 11.5 14.5 11.5 11.5 17 11.5 6.4tPLZ 8.5 14.5 9 14.5 11.5 11.5 17 11.5 6.4UNIT fmax : MHz, other : ns
PARAMETER
MAXQ
Q
PARAMETER
CLK
OE
MAX
CLK Q MAX
OE Q MAX
OE Q MAX
OE Q MAX
360
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
575OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
3-State Buffer-Type Noninverting Outputs DriveBus Lines Directly
Bus-Structured Pinout Synchronous Clear
OE
CLK
1D
1Q
2
14
3
22
To Seven Other Channels
1D
C1
1CLR
FUNCTION TABLEINPUTS OUTPUT
L
L
DOE Q
LL
X
L
X
LH
L
Q0
H
CLK
L
L
H
CLR
HH
H X ZXX
↑
↑↑
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALS AS UNIT
ICC MAX 30 142 mAIOH MAX -2.6 -15 mAIOL MAX 24 48 mA
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN ALS AS
fmax MIN 30 90
tw CLK H 5.5CLK L 5.5
tsu 5.5
CLR L 6.5
th 30
tPLH 14 8tPHL 14 9tPZH 18 6tPZL 18 10tPHZ 10 6tPLZ 13 6UNIT fmax : MHz, other : ns
MIN
16.5
15
0
MAXQCLK
Q MAX
Q MAX
DATA
DATA
CLR
PARAMETER
OC
OC
361
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
576OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
3-State Buffer-Type Inverting Outputs Drive BusLines Directly
Bus-Structured Pinout Functionally Equivalent to '576, Except for Having
Inverted Outputs
OE
CLK
1D1Q
1
11
219
To Seven Other Channels
1D
C1
FUNCTION TABLEINPUTS OUTPUT
L
L
DOE Q
LH
H
X
X Z
L↑
↑
L
Q0
H
CLK
L
X
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALS AS UNIT
ICC MAX 30 135 mAIOH MAX -2.6 -15 mAIOL MAX 24 48 mA
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN ALS AS
fmax MIN 30 125
tw 42
tsu 15 2
th 0 2tPLH 14 8tPHL 14 9tPZH 18 6tPZL 18 10tPHZ 10 6tPLZ 15 6UNIT fmax : MHz, other : ns
Q
Q
16.5
CLK
MIN
MAXQ
OE MAX
MAX
DATA
OE
PARAMETER
HL
DATA
362
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
577OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS
3-State Buffer-Type Inverting Outputs Drive BusLines Directly
Bus-Structured Pinout Synchronous Clear
OE
CLK
1D
1Q
2
14
3
22
To Seven Other Channels
1D
C1
1CLR
FUNCTION TABLEINPUTS OUTPUT
L
L
DOE Q
LL
X
LX
HH
↑
↑↑
H
Q0
L
CLK
L
L
H
CLR
HH
H X ZXX
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALS AS UNIT
ICC MAX 30 142 mAIOH MAX -2.6 -15 mAIOL MAX 24 48 mA
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN ALS AS
fmax MIN 30 125
t 16.5 4
tsu DATA MIN 15 2
th CLR 0 2tPLH 14 8tPHL 14 9tPZH 18 6tPZL 18 10tPHZ 10 6tPLZ 15 6UNIT fmax : MHz, other : ns
MAX
MAX
MAX
Q
Q
Q
PARAMETER
CLK
OE
OE
363
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
580OCTAL D-TYPE TRANSPARENTLATCHES WITH INVERTEDOUTPUTS
3-State Buffer-Type Outputs Drive Bus LinesDirectly
Inverting-Logic Outputs Bus-Structured Pinout
OE
LE
1D1Q
1
11
219
To Seven Other Channels
C1
1D
FUNCTION TABLEINPUTS
OUTPUT
L
L
DOE LEQ
LH
H
X
X Z
L
L
Q0
H
ENABLE
H
L
X
H
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALS AS UNIT
ICC MAX 29 115 mAIOH MAX -2.6 -15 mAIOL MAX 24 48 mA
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN ALS AS
t C 15 2tsu C MIN 10 2th C 10 3tPLH 18 7.5tPHL 14 7tPLH 22 9tPHL 21 8tPZH 18 6.5tPZL 18 9.5tPHZ 10 6.5tPLZ 15 7UNIT: ns
D Q MAX
LE Q MAX
OE Q MAX
OE Q MAX
PARAMETER
364
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1RC1
1S
T
R
1RC1
1S
T
R
1RC1
1S
T
R
1RC1
1S
T
R
1RC1
1S
T
R
1RC1
1S
T
R
1RC1
1S
T
R
1RC1
1S
T
R
14
13
12
11
10
9
15
1
2
3
4
5
6
7
OE
RCLK
CCKEN
CCLK
CCLR
RCO
QA
QB
QC
QD
QE
QF
QG
QH
5908-BIT BINARY COUNTER WITH OUTPUT REGISTER
Parallel Register Outputs Counter Has Direct Clear 3-State Outputs Guaranteed Counter Frequency: DC to 20MHz
365PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
MAX or MIN LS SN74HC UNIT
ICC MAX 65 0.08 mA
RCO MAX -1 -4 mAQ MAX -2.6 -6 mA
RCO MAX 16 4 mAQ MAX 24 6 mA
PARAMETER
IOH
IOL
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN LS SN74HC
fmax CCK RCO MIN 20 13tw CCK 25 31
CCLR MIN 20 25RCK 20 31
tsu CCLRbofore CCK
CCKbofore RCK
tPLH 22 45tPHL 30 45tPLH CCLR RCO MAX 45 39tPLH 18 42tPHL 33 42tPZH 38 37tPZL 45 37tPHZ 30 37tPLZ 38 37UNIT fmax : MHz, other : ns
QG
G
RCK Q
Q
MAX
MAX
MAX
25
25
20
40
MAX
MIN
CCK RCO
PARAMETER
366
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1D
C1
S
R
T
RCO(9)
1D
C1
S
R
T
1D
C1
S
R
T
1D
C1
S
R
T
1D
C1
S
R
T
1D
C1
S
R
T
1D
C1
S
R
T
1D
C1
S
R
T
CCLR(10)
(12)
(11)
(14)
CCKEN
CCK
CLOAD
RCK(13)
A(15)
B(1)
C(2)
D(3)
E(4)
F(5)
G(6)
H(7)
5928-BIT BINARY COUNTER WITH INPUT REGISTER
Parallel Register Inputs Counter Has Directly Overriding Load and Clear Accurate Counter Frequency: DC to 20MHz
367PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LS UNIT
ICC MAX 60 mAIOH MAX -1 mAIOL MAX 16 mA
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN LS
fmax CCK RCO MIN 20tw CCK 25
CCLR 20RCK 20
CLOAD 40tsu CCLR
bofore CCK
CLOADbofore CCK
RCKbofore CLOAD
A to Hbofore RCK
th MIN 0tPLH 23tPHL 30tPLH 47tPHL 17tPLH CCLR RCO MAX 45tPLH 53tPHL 45UNIT fmax : MHz, other : ns
MIN
MAX
MAX
MAX
MIN
20
20
30
20
PARAMETER
RCO
RCO
RCO Q
CCK
CLOAD
RCK
368
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1D
C1
S
R
T
RCO(11)
Gating for RCKis similar in detailto that shown forCCK.
1D
C1
S
R
T
1D
C1
S
R
T
1D
C1
S
R
T
1D
C1
S
R
T
1D
C1
S
R
T
1D
C1
S
R
T
1D
C1
S
R
T
CCLR
G
G
(12)
(15)
(19)
(18)
(14)
(13)
(9)
CCKEN
CCKEN
CCK
CLOAD
RCKEN
RCK
(17)
(16)
A/QA
(1)
B/QB(2)
C/QC(3)
D/QD(4)
E/QE(5)
F/QF(6)
G/QG(7)
H/QH(8)
G2
2
1
5938-BIT BINARY COUNTER WITH INPUT REGISTER
Parallel 3-State I/O: Register Inputs/Counter Outputs Counter Has Directly Overriding Load and Clear Accurate Counter Frequency: DC to 20MHz 74ACT11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)
369PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
MAX or MIN LS ACT11 UNIT
ICC MAX 85 0.08 mA
RCO MAX -1 -24 mAQ MAX -2.6 -24 mA
RCO MAX 16 24 mAQ MAX 24 24 mA
PARAMETER
IOH
IOL
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN LS ACT11
fmax CCK RCO MIN 20 52tw CCK 25 9.6
CCLR 20 7.6RCK 20 5.8
CLOAD 40 6.2tsu CCLR
bofore CCK
CLOADbofore CCK
RCKbofore CLOAD
A to Hbofore RCK
th MIN 0 0.8tPLH 21 15.1tPHL 39 15tPLH 51 19.1tPHL 42 21.7tPHL CCLR Q MAX 38 16UNIT fmax : MHz, other : ns
CLOAD
CCK
MIN
MIN
MAX
MAX
Q
Q
20 1.2
5.120
30 7.4
2.420
PARAMETER
370
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
R3D
C31D
C1R
R3D
C32D
C2R
R3D
C32D
C2R
R3D
C32D
C2R
R3D
C32D
C2R
R3D
C32D
C2R
R3D
C32D
C2R
R3D
C32D
C2R
13
12
10
11
14 15
1
2
3
4
5
6
7
9
QA
QB
QC
QD
QE
QF
QG
QH
QH′
RCLR
SRCLR
RCLK
SRCLK
SER Q
Q
Q
Q
Q
Q
Q
Q Q
Q
Q
Q
Q
Q
Q
Q
5948-BIT SHIFT REGISTER WITH OUTPUT LATCHE
8-Bit Serial-In, Parallel-Out Shift Registers with Storage Independent Direct Overriding Clears on Shift and Storage Registers Independent Clocks for Shift and Storage Registers Guaranteed Shift Frequency: DC to 20MHz
371PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
MAX or MIN LS SN74HC AHC AHCT LV
3VLV5V UNIT
ICC MAX 65 0.08 0.04 0.02 - 0.02 mAQH' MAX -1 -4 -8 -8 -6 -12 mAQ MAX -2.6 -6 -8 -8 -6 -12 mA
QH' MAX 16 4 8 8 6 12 mAQA to QH MAX 24 6 8 8 6 12 mA
PARAMETER
IOH
IOL
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN LS SN74HC AHC AHCT LV
3VLV5V
tw SRCK 25 20 5 5.5 5.5 5RCK 20 20 5 5.5 5.5 5
tsu SRCLRto SRCK
SERto SRCK
SRCKto RCK
SRCLRto RCK
RCLRto RCK
th MIN 0 5 2 2 1.5 2tPLH 18 37 9.1 9.1 12.4 9.1tPHL 23 37 10.1 10.1 13.9 10.1tPLH 18 37 8.3 8.3 11.1 8.3tPHL 30 37 9.7 9.7 13.1 9.7tPHL SRCLR QH' 33 37 10.7 10.1 14 10.1tPHL RCLR QA to QH 57 31 10.1 10.7 14.4 10.7UNIT: ns
3.3
3
5
5
20
20
20
40
40
MAX
QA to QH
QH'
MIN
MIN
SRCK
RCK
3.7
MAX
MAX
5.3
13 5 5
5 3.7 3.8
PARAMETER
4.8
3.5
8.5
9
10 3.3 3.3
22 3 3
22 5 5
372
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
3DC3
1DC1
R
3DC3
2DC2
R
3DC3
2DC2
R
3DC3
2DC2
R
3DC3
2DC2
R
3DC3
2DC2
R
3DC3
2DC2
R
3DC3
2DC2
R
13
12
10
11
1415
1
2
3
4
5
6
7
9
QA
QB
QC
QD
QE
QF
QG
QH
QH′
OE
SRCLR
RCLK
SRCLK
SER Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
5958-BIT SHIFT REGISTER WITH OUTPUT LATCHE
8-Bit Serial-In, Parallel-Out Shift Registers with Storage 3-State Outputs Shift Register Has Direct Clear Accurate Shift Frequency: DC to 20MHz
373PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
MAX or MIN LS SN74HC AHC AHCT LV
3VLV5V UNIT
ICC MAX 65 0.08 0.04 0.04 - 0.02 mAQH' MAX -1 -4 -8 -8 -8 -16 mA
QA to QH MAX -26 -6 -8 -8 -8 -16 mAQH' MAX 16 4 8 8 8 16 mA
QA to QH MAX 24 6 8 8 8 16 mA
PARAMETER
IOH
IOL
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN LS HC AHC AHCT LV3V
LV5V
tw SRCK 25 20 5 5.5 5.5 5RCK 20 20 5 5.5 5.5 5
tsu SRCLRto SRCK
SER
to SRCKSRCKto RCK
SRCLRto RCK
th MIN 0 0 2 2 1.5 2tPLH 18 40 11.4 11.4 18.5 11.4tPHL 25 40 11.4 11.4 18.5 11.4tPLH 18 37 10.5 10.5 17 10.5tPHL 35 37 10.5 10.5 17 10.5tPHL SRCLR QH' MAX 35 44 11.1 11.1 17.2 11.1UNIT: ns
3.8
5
2.5
5
3
519 5
3
40
20 25 3
40
2.520 12
RCK QA to QH
QH'
3
3.5
8.5
9
5
13 5
MAX
PARAMETER
MIN
MIN
MAXSRCK
374
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
SER
QB(1)
3S
C3
3R2S
C2
2R
R
QA(15)
3S
C3
3R
QC(2)
3S
C3
3R2S
C2
2R
R
QD(3)
3S
C3
3R2S
C2
2R
R
QE(4)
3S
C3
3R2S
C2
2R
R
QF(5)
3S
C3
3R2S
C2
2R
R
QG(6)
3S
C3
3R2S
C2
2R
R
QH(7)
3S
C3
3R
QH'(9)
2S
C2
2R
R
SRCK
SRCLR
RCK
G
(14)
(11)
(10)
(12)
(13)
C1
1R
R
5968-BIT SHIFT REGISTER WITH OUTPUT LATCHE
8-Bit Serial-In, Parallel-Out Shift Registers with Storage Open-Collector Parallel Outputs Shift Register Has Direct Clear Accurate Shift Frequency: DC to 20MHz
375PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
MAX or MIN LS UNIT
ICC MAX 55 mAQH' MAX 16 mAQ MAX 24 mA
IOL QH' MAX -1 mAVOH QA to QH MAX 5.5 V
PARAMETER
IOH
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN LS
tw SRCK 25RCK 20
tsu SRCLRto SRCK
SER
to SRCKSRCKto RCK
SRCLRto RCK
th MIN 0tPLH 21tPHL 30tPLH 42tPHL 35tPHL SRCLR QH' MAX 35UNIT: ns
RCK
MIN
MIN
MAX
MAX
PARAMETER
20
20
40
40
QA to QH
QH'SRCK
376
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
QH'(9)
A
RCK
SRLOAD
(15)
(12)
SER(14)
(13)SRCK
(11)
1D
C1
SRCLR(10)
S
R
C2
B(1)
1D
C1
S
R
C3
2D
3R
3S
C(2)
1D
C1
S
R
C3
3R
3S
D(3)
1D
C1
S
R
C3
3R
3S
E(4)
1D
C1
S
R
C3
3R
3S
F(5)
1D
C1
S
R
C3
3R
3S
G(6)
1D
C1
S
R
C3
3R
3S
H(7)
1D
C1
S
R
C3
3R
3S
5978-BIT SHIFT REGISTER WITH INPUT LATCHE
8-Bit Parallel Storage Registers Inputs Shift Register Has Direct Overriding Load and Clear Accurate Shift Frequency: DC to 20MHz
377PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LS CD74HC
CD74HCT UNIT
ICC MAX 53 0.16 0.16 mAIOH MAX -1 -4 -4 mAIOL MAX 16 4 4 mA
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN LS CD74HC
CD74HCT
fmax SRCK 20 20 16
tw SRCK 35 24 30RCK 20 18 20
SRCLR 20 24 27
SRLOAD 40 21 24tsu SRCLR
to SRCK
SRLOADto SRCK
RCKto SRLOAD
SER
to SRCKDATA
to RCKth MIN 0 3 3tPLH 23 53 57tPHL 30 53 57tPLH 57 60 72tPHL 44 60 72tPHL SRCLR QH' MAX 36 53 66tPLH 60 72 84tPHL 48 72 84UNIT fmax : MHz, other : ns
RCK
SRLOAD
SRCK QH'
QH'
QH'
MAX
MAX
MAX
MIN 20
25
30
40
20
MIN
MIN
MIN
MIN15
15 15
PARAMETER
- -
- -
- -
15
378
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
QH'(11)
A/QA
RCK
SRLOAD
(1)
(15)
DS(19)
SER1(17)
SER0(18)
(9)SRCK
(13)
1D
C1
SRCLR(12)
S
R
C2
B/QB(2)
1D
C1
S
R
C3
2D
3R
3S
C/QC(3)
1D
C1
S
R
C3
3R
3S
D/QD(4)
1D
C1
S
R
C3
3R
3S
E/QE(5)
1D
C1
S
R
C3
3R
3S
F/QF(6)
1D
C1
S
R
C3
3R
3S
G/QG(7)
1D
C1
S
R
C3
3R
3S
H/QH(8)
1D
C1
S
R
C3
3R
3S
G(16)
SRCKEN(14)
5988-BIT SHIFT REGISTERS
379PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LS UNIT
ICC MAX 85 mAIOH MAX -2.6 mAIOL MAX 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN LS
fmax SRCK MIN 20tPLH 17tPHL 23tPLH 42tPHL 30tPHL SRCLR QH' MAX 27tPLH 48tPHL 36tPLH 18tPHL 28tPLH 48tPHL 40tPHL SRCLR Q MAX 38tPZH 31tPZL 43tPHZ 38tPLZ 30UNIT fmax : MHz, other : ns
G
G
SRCK
SRLOAD
SRCK
SRLOAD
RCK QH'
Q
Q
QH'
QH'
MAX
MAX
MAX
Q
Q
MAX
MAX
MAX
MAX
380
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
620OCTAL BUS TRANSCEIVERS
Local Bus-Latch Capability 3-State Inverting Outputs 74AC11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series) 74ACT11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series)
To Seven Other Channels
19
1
2 18
OEBA
B1
OEAB
A1
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LS ALS AS SN74HC
SN74BCT ABT AC
11ACT11 UNIT
ICCZ MAX 95 47 77 0.08 10 0.25 0.08 0.008 mAICCL MAX 90 44 122 0.08 84 30 0.08 0.008 mAIOH (A port) MAX -15 -15 -15 -6 -3 -32 -24 -24 mAIOH (B port) MAX -15 -15 -15 -6 -15 -32 -24 -24 mAIOL (A port) MAX 24 24 64 6 24 64 24 24 mAIOL (B port) MAX 24 24 64 6 64 64 24 24 mAIOL* MAX - 48 - - - - - - mA*620-1
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN LS ALS AS SN74HC
SN74BCT ABT AC
11ACT11
tPLH 10 10 7 26 5.8 4.8 7.4 9.4tPHL 15 10 6 26 3.6 4.8 7.1 8.6tPLH 10 10 7 26 6.9 4.8 7.4 9.4tPHL 15 10 6 26 3.9 4.8 7.1 8.6tPZH 40 17 8 53 10.6 5.5 8.9 10.3tPZL 40 25 9 53 11.1 7.1 8.5 10.1tPHZ 25 12 6 38 10 7 8.1 10.4tPLZ 25 18 12 38 7.8 5.8 8.7 10.9tPZH 40 18 8 53 7.4 6.8 8.8 11.3tPZL 40 25 9 53 9 6.4 8.8 11tPHZ 25 12 6 38 8.1 6.5 8.2 9.4tPLZ 25 18 13 38 5.9 5.6 8.6 9.6UNIT: ns
A
B
OEBA
OEBA
OEAB
OEAB B
B
A
B
MAX
MAX
MAX
MAX
MAX
MAX
A
A
FUNCTION TABLEENABLE INPUTS
OPERATION
LH
OEBA
H
L
L
LH
H B data to AbusA data to B bus
B data to Abus
IsorationA data to B bus
OEAB
381
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
621OCTAL BUS TRANSCEIVERS
Local Bus-Latch Capability Open-Collector True Outputs Schmitt-Triggered Inputs (SN74LS621)
A1B1
To Seven Other Transceivers
OEBA
OEAB
19
1
182
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LS ALS ALSA-1 AS UNIT
ICC MAX 90 48 48 189 mAVOH MAX 5.5 5.5 5.5 5.5 VIOL MAX 24 24 48 64 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN LS ALS ALSA-1 AS
tPLH 25 33 33 24tPHL 25 20 20 21tPLH 25 33 33 7.5tPHL 25 20 20 7.5tPLH 40 39 39 21tPHL 50 35 35 9tPLH 40 39 39 22tPHL 50 35 35 10UNIT: ns
B MAX
B
A
A
MAX
MAX
MAX
A
B
OEBA
OEAB
FUNCTION TABLEENABLE INPUTS
OPERATION
LH
OEBA
H
L
L
LH
H B data to AbusA data to B bus
B data to Abus
IsorationA data to B bus
OEAB
382
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
623OCTAL BUS TRANSCEIVERS
Local Bus-Latch Capability 3-State True Outputs Schmitt-Triggered Inputs (SN74LS623) 74AC11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series) 74ACT11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series)
A1 B1
OEBA
OEAB
To Seven Other Channels
19
1
2 18
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LS ALS AS F SN74HC
SN74HCT
SN74BCT ABT AC
11ACT11
CD74AC
CD74ACT UNIT
ICCZ MAX 95 55 116 130 0.08 0.08 11 0.25 0.08 0.04 0.16 0.16 mAICCL MAX 90 50 189 140 0.08 0.08 92 30 0.08 0.04 0.16 0.16 mAIOH (A port) MAX -15 -15 -15 -3 -6 -6 -3 -32 -24 -24 -24 -24 mAIOH (B port) MAX -15 -15 -15 -15 -6 -6 -15 -32 -24 -24 -24 -24 mAIOL (A port) MAX 24 24 64 24 6 6 24 64 24 24 24 24 mAIOL (B port) MAX 24 24 64 64 6 6 64 64 24 24 24 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN LS ALS AS F SN74HC
SN74HCT
SN74BCT ABT AC
11ACT11
CD74AC
CD74ACT
tPLH 15 13 9 6.5 26 28 5.2 4.6 7.8 8.5 9.6 10.6tPHL 15 11 8 7.5 26 28 7.4 4.6 7.1 7.9 9.6 10.6tPLH 15 13 9 6.5 26 28 6.7 4.6 7.8 8.5 9.6 10.6tPHL 15 11 8.5 7.5 26 28 8 4.6 7.1 7.9 9.6 10.6tPZH 40 22 11 12 53 53 10.6 7.5 9 9.7 13.4 14.4tPZL 40 22 10 10 53 53 10.7 7.5 9.1 10 13.4 14.4tPHZ 25 16 7.5 7.5 38 38 9.8 7.5 8.3 10.9 13.4 14.4tPLZ 25 19 11.5 7 38 38 7.8 7.5 8.8 11.5 13.4 14.4tPZH 40 22 11.5 11.5 53 53 7.6 7.5 9.2 10.7 13.4 14.4tPZL 40 22 11 9.5 53 53 8.9 7.5 9.4 10.9 13.4 14.4tPHZ 25 16 7 10 38 38 7.7 7.5 8.3 9.5 13.4 14.4tPLZ 25 19 9 10 38 38 7.1 7.5 8.8 10 13.4 14.4UNIT: ns
OEAB B
OEAB B
OEBA A
OEBA A
MAX
MAX
A B
B A
MAX
MAX
MAX
MAX
FUNCTION TABLEENABLE INPUTS
OPERATION
LH
OEBA
H
L
L
LH
H B data to AbusA data to B bus
B data to Abus
IsorationA data to B bus
OEAB
383PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
Logic Diagram
624VOLTAGE-CONTROLLED OSCILLATOR
This Voltage Oscillators (VCOs) is Improved Versions of The Original VCO Family: SN74124, 324, 325, 326, 327
Separate Supply Voltage Pins for Isolation of Frequency Control Inputs and Oscillators from OutputsCircuitry
Highly Stable Operation over Specified Temperature and / or Supply Voltage Ranges
Cx
FC
RC
EN
(’LS624,’LS628,’LS629 only)
G
Z
Y
FC
RCEN
T
R
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LS UNIT
ICC MAX 35 mAIOL MAX 24 mAIOH MAX -1.2 mA
SWITCHING CHARACTERISTICS
PARAMETER MAX or MIN LS
fo MAX 25UNIT: MHz
384
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
628VOLTAGE-CONTROLLED OSCILLATOR
This Voltage Oscillators (VCOs) is Improved Versions of The Original VCO Family: SN74124, 324, 325, 326, 327
Separate Supply Voltage Pins for Isolation of Frequency Control Inputs and Oscillators from OutputsCircuitry
Highly Stable Operation over Specified Temperature and / or Supply Voltage Ranges Two Rexternal Pins Can Offer More Precise Temprature Compensation
Cx
FC
RC
EN
(’LS624,’LS628,’LS629 only)
G
Z
Y
FC
RCEN
T
R
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LS UNIT
ICC MAX 35 mAIOH MAX -1.2 mAIOL MAX 24 mA
SWITCHING CHARACTERISTICS
PARAMETER MAX or MIN LS
fo MAX 25UNIT: MHz
385PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
Logic Diagram
629VOLTAGE-CONTROLLED OSCILLATOR
This Voltage Oscillators (VCOs) is Improved Versions of The Original VCO Family: SN74124, 324, 325, 326, 327
Separate Supply Voltage Pins for Isolation of Frequency Control Inputs and Oscillators from OutputsCircuitry
Highly Stable Operation over Specified Temperature and / or Supply Voltage Ranges
Cx
FC
RC
EN
(’LS624,’LS628,’LS629 only)
G
Z
Y
FC
RCEN
T
R
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LS UNIT
ICC MAX 55 mAIOH MAX -1.2 mAIOL MAX 24 mA
SWITCHING CHARACTERISTICS
PARAMETER MAX or MIN LS
fo MAX 25UNIT: MHz
386
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
638OCTAL BUS TRANSCEIVERS
Bidirectional Bus Tranceivers Inverting Logic Outputs A-Bus: Open-Collector 3-State Schmitt-Triggered Inputs (SN74LS638)
To Seven Other Transceivers
OE
A1
DIR
B1
19
2
1
18
FUNCTION TABLE
OPERATION
B data to A busA data to B bus
CONTROL INPUTS
LL
DIROE
H Isoration
L
XH
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LS ALS AS UNIT
ICCZ MAX 95 30 61 mAICCL MAX 90 41 122 mAIOH (B) MAX -15 -15 -15 mAVOH (A) MAX 5.5 5.5 5.5 VIOL MAX 24 24 64 mAIOL* MAX - 48 - mA*638-1
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN LS ALS AS
tPLH 10 12 7tPHL 15 12 6.5tPLH 25 25 20tPHL 25 30 7tPLH 40 25 19tPHL 60 45 9tPZH 40 20 8tPZL 40 22 10tPHZ 25 10 7tPLZ 25 15 10UNIT: ns
OE
A
B
OE
OE
MAX
B
A
A
B
B
MAX
MAX
MAX
MAX
387
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
639OCTAL BUS TRANSCEIVERS
Bidirectional Bus Tranceivers True Logic Outputs A-Bus: Open-Collector 3-State Schmitt-Triggered Inputs (SN74LS638)
To Seven Other Transceivers
OE
A1
DIR
B1
19
2
1
18
FUNCTION TABLE
OPERATION
B data to A busA data to B bus
CONTROL INPUTS
LL
DIROE
H Isoration
L
XH
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LS ALS AS UNIT
ICCZ MAX 95 54 100 mAICCL MAX 90 50 154 mAIOH (B) MAX -15 -15 -15 mAVOH (A) MAX 5.5 5.5 5.5 VIOL MAX 24 24 64 mAIOL* MAX - 48 - mA*639-1
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN LS ALS AS
tPLH 15 12 9.5tPHL 15 12 9tPLH 25 30 22tPHL 25 22 9tPLH 40 30 21.5tPHL 50 35 11.5tPZH 40 21 10.5tPZL 40 25 10.5tPHZ 25 10 7tPLZ 25 16 10.5UNIT: ns
OE MAXB
A
B
OE
OE
B
A
A
B
MAX
MAX
MAX
MAX
388
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
640OCTAL BUS TRANSCEIVERS
Bidirectional Bus Tranceivers Inverting Logic 3-State Outputs Schmitt-Triggered Inputs (SN74LS640, 640-1) 74ACT11xxx: Product Available in Reduced-Noise
Advanced CMOS (11000 Series)A1 B1
OE
DIR
To Seven Other Transceivers
19
1
2 18
FUNCTION TABLE
OPERATION
B data to A busA datato B bus
CONTROL INPUTS
LL
DIROE
H Isoration
L
XH
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LS ALS AS SN74HC
CD74HC
SN74HCT
CD74HCT
SN74BCT ABT ACT
11 UNIT
ICCZ MAX 95 50 80 0.08 0.16 0.08 0.16 11 0.25 0.08 mAICCL MAX 90 55 123 0.08 0.16 0.08 0.16 94 30 0.08 mAIOH (A port) MAX -15 -15 -15 -6 -6 -6 -6 -3 -32 -24 mAIOH (B port) MAX -15 -15 -15 -6 -6 -6 -6 -15 -32 -24 mAIOL (A port) MAX 24 24 64 6 6 6 6 24 64 24 mAIOL (B port) MAX 24 24 64 6 6 6 6 64 64 24 mAIOL* MAX 48 48 - - - - - - - - mA*640-1
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN LS ALS AS SN74HC
CD74HC
SN74HCT
CD74HCT
SN74BCT ABT ACT
11
tPLH 10 11 7 26 27 28 33 6.5 4.9 10.5tPHL 15 10 6 26 27 28 33 3.7 4.9 9.5tPLH 10 11 7 26 27 28 33 6.5 4.9 10.5tPHL 15 10 6 26 27 28 33 3.7 4.9 9.5tPZH 40 21 8 58 45 58 45 10.2 5.8 13.4tPZL 40 24 10 58 45 58 45 10.7 7.3 13.6tPHZ 25 10 8 38 45 50 45 10.2 6.8 13.9tPLZ 25 15 13 38 45 50 45 7.8 5.5 14.2tPZH 40 21 8 58 45 58 45 10.2 5.8 13.4tPZL 40 24 10 58 45 58 45 10.7 7.3 13.6tPHZ 25 10 8 38 45 50 45 10.2 6.8 13.9tPLZ 25 15 13 38 45 50 45 7.8 5.5 14.2UNIT: ns
B
B
OE
OE
OE
MAX
MAXA
MAX
MAX
A B MAX
B A MAX
OE A
389
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
641OCTAL BUS TRANSCEIVERS
Bidirectional Bus Tranceivers True Logic 3-State Outputs Schmitt-Triggered Inputs (SN74LS641)
A1B1
19
1
182
OE
DIR
To Seven Other Transceivers
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LS ALS AS UNIT
ICCZ MAX 95 - - mAICCL MAX 90 47 136 mAVOH MAX 5.5 5.5 5.5 VIOL MAX 24 24 64 mAIOL* MAX 48 48 - mA*641-1
FUNCTION TABLE
OPERATION
B data to A busA datato B bus
CONTROL INPUTS
LL
DIRG
H Isoration
L
XH
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN LS ALS AS
tPLH 25 25 21tPHL 25 18 7.5tPLH 25 25 21tPHL 25 18 7.5tPLH 40 30 21tPHL 50 30 9tPLH 40 32 22tPHL 50 32 10UNIT: ns
OE
DIR
A,B
A,B
B
A B
A
MAX
MAX
MAX
MAX
390
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
642OCTAL BUS TRANSCEIVERS
Bidirectional Bus Tranceivers Inverting Logic 3-State Outputs Schmitt-Triggered Inputs (SN74LS642)
A1B1
19
1
182
OE
DIR
To Seven Other Transceivers
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LS ALS AS UNIT
ICCZ MAX 95 - - mAICCL MAX 90 28 104 mAVOH MAX 5.5 5.5 5.5 VIOL MAX 24 24 64 mAIOL* MAX 48 48 - mA*642-1
FUNCTION TABLE
OPERATION
B data to A busA data to B bus
CONTROL INPUTS
LL
DIROE
H Isoration
L
XH
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN LS ALS AS
tPLH 25 30 24tPHL 25 22 7.5tPLH 25 30 24tPHL 25 22 7.5tPLH 40 30 23.5tPHL 60 38 11.5tPLH 40 30 23.5tPHL 60 38 11.5UNIT: ns
B
OE, DIR
OE, DIR MAX
A
A
B
MAX
MAX
B MAXA
391
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
645OCTAL BUS TRANSCEIVERS
Bidirectional Bus Tranceivers True Logic 3-State Outputs Schmitt-Triggered Inputs (SN74LS645, 645-1)
A1 B1
OE
DIR
To Seven Other Transceivers
19
1
2 18
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LS ALS AS SN74HC
SN74HCT UNIT
ICCZ MAX 95 58 123 0.08 0.08 mAICCL MAX 90 55 149 0.08 0.08 mAIOH MAX -15 -15 -15 -6 -6 mAIOL MAX 24 24 64 6 6 mAIOL* MAX 48 48 - - - mA*645-1
FUNCTION TABLE
OPERATION
B data to A busA data to B bus
CONTROL INPUTS
LL
DIROE
H Isoration
L
XH
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN LS ALS AS SN74HC
SN74HCT
tPLH 15 10 9.5 26 28tPHL 15 10 9 26 28tPLH 15 10 9.5 26 28tPHL 15 10 9 26 28tPZH 40 20 11 58 58tPZL 40 20 10 58 58tPHZ 25 10 7 50 50tPLZ 25 15 12 50 50tPZH 40 20 11 58 58tPZL 40 20 10 58 58tPHZ 25 10 7 50 50tPLZ 25 15 12 50 50UNIT: ns
OE
A
B
OE
B
A
A
A
MAX
MAX
MAX
MAX
OE
OE
MAX
MAX
B
B
392
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
646OCTAL BUS TRANSCEIVERS AND REGISTERS
Bidirectional Bus Tranceivers Independent Registers for A and B Buses Multiplexed Real-Time and Stored Data True Data Paths 3-State Outputs 74AC11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series) 74ACT11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)
A1B1
One of Eight Channels
SAB
CLKAB
SBA
CLKBA
DIR
OE
To Seven Other Channels
21
3
23
22
1
2
420
1D
C1
1D
C1
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LS ALS AS SN74HC
CD74HC
SN74HCT
CD74HCT
SN74BCT ABT ABT
Ver.ALVTH
3V UNIT
ICC MAX 165 88 211 0.08 0.16 0.08 0.08 67 30 30 5 mAIOH MAX -15 -15 -15 -6 -6 -6 -6 -15 -32 -32 -32 mAIOL MAX 24 24 48 6 6 6 6 64 64 64 64 mAIOL* MAX - 48 - - - - - - - - - mA
PARAMETER MAX or MIN AC11
CD74AC
ACT11
CD74ACT
LVC3V UNIT
ICC MAX 0.08 0.08 0.08 0.08 0.01 mAIOH MAX -24 -24 -24 -24 -24 mAIOL MAX 24 24 24 24 24 mAIOL* MAX - - - - - mA
*646-1
393PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN LS ALS AS SN74HC
CD74HC
SN74HCT
CD74HCT
SN74BCT
fmax MIN - 40 90 27 25 27 20 8315 12.5 5 19 20 19 31 630 12.5 6 19 20 19 31 630 - - - - - - -15 10 6 25 15 25 15 615 10 6 25 15 25 15 6
th MIN 0 0 0 5 9 5 5 0.5tPLH 25 30 8.5 45 55 45 55 11.2tPHL 35 17 9 45 55 45 55 10.6tPLH 18 20 9 34 34 34 46 9.5tPHL 20 12 7 34 34 34 46 10.5tPLH 40 25 11 48 43 48 58 13.8tPHL 35 20 9 48 43 48 58 9.1tPLH 50 35 11 48 43 48 58 12tPHL 25 20 9 48 43 48 58 12.9tPZH 55 17 9 61 44 61 56 13.2tPZL 65 20 14 61 44 61 56 14.4tPHZ 35 10 9 61 44 61 44 10.9tPLZ 35 16 9 61 44 61 44 10.5tPZH 45 30 16 61 44 61 56 13.1tPZL 60 25 18 61 44 61 56 14.6tPHZ 30 10 10 61 44 61 44 12.6tPLZ 30 16 10 61 44 61 44 11.8
PARAMETER INPUT OUTPUT MAX or MIN ABT ABTA Ver.
LVTH3V
AC11
CD74AC
ACT11
CD74ACT
LVC3V
fmax MIN 125 125 150 100 125 105 110 1504 4 3.3 5 4 4.8 4.5 3.34 4 3.3 5 4 4.8 4.5 3.3- - - - - - - -
3.5 3 1.2 4.5 2.5 4.5 2.5 1.53 3 1.6 4.5 2.5 4.5 2.5 1.5
th MIN 0 0 0.8 1 2 2.5 2 1.7tPLH 7.8 5.6 4.7 11 13.5 13.5 15.5 8.4tPHL 8.4 5.6 4.7 12.2 13.5 14.9 15.5 8.4tPLH 6.9 4.8 3.5 8.8 11 11.5 12.5 7.4tPHL 6.9 5.4 3.5 9.8 11 12 12.5 7.4tPLH 7.1 6.5 4.9 9.4 12 11.5 14.5 8.6tPHL 7.9 5.9 4.9 10.7 12 13.5 14.5 8.6tPLH 7.1 6.5 4.9 9.9 12 12.4 14.5 8.6tPHL 7.9 5.9 4.9 11 12 13.1 14.5 8.6tPZH 6.3 6.3 5.2 12 13.5 14.4 15.5 8.2tPZL 8.8 8.8 5.2 13.1 13.5 15.3 15.5 8.2tPHZ 8.3 5 5.5 8.9 13.5 11.6 15.5 7.5tPLZ 7.5 4.5 5.5 8.3 13.5 10.6 15.5 7.5tPZH 6.7 6.7 5.2 12.6 13.5 15.3 15.5 8.3tPZL 9.5 9.5 5.2 13.7 13.5 16.5 15.5 8.3tPHZ 7.7 5.7 5.6 8.7 13.5 11.3 15.5 7.9tPLZ 8.2 6 5.6 8.1 13.5 10.3 15.5 7.9UNIT fmax : MHz other : ns
A,B
A,B
MAXOE
A,B MAXOE
MAXSAB,SBA(sored data low)
tsuCLKBA,CLKAB "H"
MINCLKBA,CLKAB "L"
A,B
SAB,SBA(sored data high)
SAB,SBA(sored data high)
SAB,SBA(sored data low)
A,B
CLOCK
MIN
MIN
tsuCLKBA,CLKAB "H"CLKBA,CLKAB "L"
CLKBA,CLKAB
DIR
DIR A,B
OE
OE
A,B
twCLKBA,CLKAB "H"CLKBA,CLKAB "L"
DATA
MAX
MAX
MAX
A,B
A,B
A,B
A,B
MAXB,A
A,B
MAX
MAX
MAX
MAX
DIR A,B MAX
twCLKBA,CLKAB "H"
MINCLKBA,CLKAB "L"DATA
A,B MAX
DIR A,B MAX
CLKBA,CLKAB
CLOCK
B,A MAX
A,B MAX
FUNCTION TABLE
DIROE
INPUTSOPERATION OR FUNCTION
H
L
CLKAB
X
H to LH
XX
L X
CLKBA
X
H to L↑ ↑
H to L
L XL H to L
LL
HH
XX
SAB
X
XX
X
LH
SBA
L
XX
H
XX
A1–A8 B1–B8
DATA I/O†
Input Input IsolationInput Input Store A and B data
Output Input Real-time B data to A busOutput Input Stored B data to A bus
Input Output Real-time A data to B busInput Output Stored A data to B bus
† The data output functions can be enabled or disabled by various signals at OE and DIR. Data input functions are always enabled;i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs.
394
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
G
CBA
B1(20)
A1(4)
(21)
DIR(3)(23)
1D
C1
1D
C1
TO 7 OTHER CHANNELS
SBA(22)
CAB(1)
SAB(2)
I OF 8 CHANNELS
647OCTAL BUS TRANSCEIVERS AND REGISTERS
Bidirectional Bus Tranceivers Independent Registers for A and B Buses Multiplexed Real-Time and Stored Data True Data Paths Open-Collector Outputs
395PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LS UNIT
ICC MAX 150 mAVOH MAX 5.5 VIOL MAX 24 mA
SWITCHING CHARACTERISTICS
PARAMETER OUTPUT MAX or MIN LS
tw MIN 30tsu MIN 15th MIN 0tPLH 35tPHL 45tPLH 26tPHL 27tPLH 50tPHL 45tPLH 60tPHL 30tPLH 40tPHL 50tPLH 35tPHL 40UNIT: ns
MAX
A,B MAX
MAX
B,A MAX
MAX
MAX
A,B
INPUT
G
DIR
CLOCK
A,B
SAB,SBA(With Bus Input High)
SAB,SBA(With Bus Input Low)
A,BA,B
A,B
A,B
A,B
FUNCTION TABLE
DIRGINPUTS
OPERATION OR FUNCTION
H
L
CAB
X
H to LH
XX
L X
CBA
X
H to L↑ ↑
H to L
L XL H to L
LL
HH
XX
SAB
X
XX
X
LH
SBA
L
XX
H
XX
A1–A8 B1–B8DATA I/O†
Input Input IsolationInput Input Store A and B data
Output Input Real-time B data to A busOutput Input Stored B data to A bus
Input Output Real-time A data to B busInput Output Stored A data to B bus
† The data output functions can be enabled or disabled by various signals at OE and DIR. Data input functions are always enabled; i.e., data atthe bus terminals is stored on every low-to-high transition of the clock inputs.
396
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
A1B1
1DC1
1DC1
One of Eight Channels
204
2
1
22
23
21
3
SAB
CLKAB
SBACLKBA
DIR
OE
To Seven Other Channels
648OCTAL BUS TRANSCEIVERS AND REGISTERS
Bidirectional Bus Tranceivers Independent Registers for A and B Buses Multiplexed Real-Time and Stored Data Inverting Data Paths 3-State Outputs
397PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LS ALS AS SN74HC
SN74HCT UNIT
ICC MAX 180 88 195 0.08 0.08 mAIOH MAX -15 -15 -15 -6 -6 mAIOL MAX 24 24 48 6 6 mA
SWITCHING CHARACTERISTICS
PARAMETER OUTPUT MAX or MIN LS ALS AS SN74HC
SN74HCT
fmax MIN - 40 90 27 27MIN 15 12.5 5 19 19MIN 30 12.5 6 19 19MIN 30 - - - -
tsu MIN 15 10 6 25 25th MIN 0 0 0 5 5tPLH 25 33 8.5 45 45tPHL 40 20 9 45 45tPLH 18 17 8 34 34tPHL 25 10 7 34 34tPLH 55 25 11 48 48tPHL 40 21 9 48 48tPLH 40 39 11 48 48tPHL 40 22 9 48 48tPZH 50 22 9 61 61tPZL 55 22 15 61 61tPHZ 45 10 9 61 61tPLZ 35 15 9 61 61tPZH 40 27 16 61 61tPZL 45 19 18 61 61tPHZ 35 14 10 61 61tPLZ 30 15 10 61 61UNIT fmax : MHz other : ns
A,B
CLKAB, CLKBA "H"CLKAB, CLKBA "L"
DATACLKAB, CLKBA
A,B
CLKAB, CLKBA
B,A
A,B
MAX
MAX
MAX
MAX
CLOCK
A,B
SAB,SBA(With Bus Input High)
SAB,SBA(With Bus Input Low)
MAX
MAX
DIR
A,B
A,B MAX
MAX
DIR
OE
A,B
A,B
tw
OE
INPUT
FUNCTION TABLE
DIROE
INPUTSOPERATION OR FUNCTION
H
L
CLKAB
X
H to LH
XX
L X
CLKBA
X
H to L↑ ↑
H to L
L XL H to L
LL
HH
XX
SAB
X
XX
X
LH
SBA
L
XX
H
XX
A1–A8 B1–B8DATA I/O†
Input Input IsolationInput Input Store A and B data
Output Input Real-time B data to A busOutput Input Stored B data to A bus
Input Output Real-time A data to B busInput Output Stored A data to B bus
† The data output functions can be enabled or disabled by various signals at OE and DIR. Data input functions are always enabled;i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs.
398
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
OEBA
A1B1
1D
C1
1D
C1
One of Eight Channels
20
4
2
1
22
23
21
3
SAB
CLKAB
SBA
CLKBA
OEAB
To Seven Other Channels
651OCTAL BUS TRANSCEIVERS AND REGISTERS
Bus Tranceivers / Registers Independent Registers and Enables for A and B Buses Multiplexed Real-Time and Stored Data Inverting Data Paths 3-State Outputs
399PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
SWITCHING CHARACTERISTICS
PARAMETER OUTPUT MAX or MIN LS ALS AS SN74HC
SN74HCT
SN74BCT ABT CD74
ACT
fmax MIN - 40 90 27 20 85 125 110MIN 15 12.5 5 19 25 4.8 4 4.5MIN 15 12.5 6 19 25 7 4 4.5MIN 15 - - - - - - -
tsu MIN 15 10 6 25 19 6 3 2.5th MIN 0 0 0 5 5 1 0 2tPLH 24 32 8.5 45 45 11.7 5.6 15.5tPHL 35 17 9 45 45 11.8 5.6 15.5tPLH 18 18 9 34 34 12.6 6.2 12.5tPHL 30 10 7 34 34 9.8 5.4 12.5tPLH 47 38 11 48 48 9.8 6.5 15.5tPHL 33 21 9 48 48 15.5 5.9 15.5tPLH 35 25 11 48 48 14.6 6.5 15.5tPHL 30 21 9 48 48 12.8 5.9 15.5tPZH 44 20 10 61 61 12 5.8 15.5tPZL 60 18 16 61 61 13.1 8.5 15.5tPHZ 38 9 9 61 61 10.2 5 15.5tPLZ 30 12 9 61 61 9.6 4.1 15.5tPZH 29 22 11 61 61 8.3 6.5 15.5tPZL 40 21 16 61 61 9.7 7.4 15.5tPHZ 38 12 10 61 61 15 5.5 15.5tPLZ 30 14 11 61 61 12.3 5.1 15.5UNIT fmax : MHz other : ns
MAX
MAX
MAX
OEBA
OEBA
tw
MAX
MAX
MAX
CLOCK
A,B
SAB,SBA(With Bus Input High)
A,B
MAX
A,B
B,A
A,B
A,B
A
A
B
B
MAX
INPUT
OEAB
SAB,SBA(With Bus Input Low)
OEAB
CLKBA, CLKAB "H"CLKBA, CLKAB "L"
DATAA,B
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LS ALS AS SN74HC
SN74HCT
SN74BCT ABT CD74
ACT UNIT
ICC MAX 165 82 195 0.08 0.08 62 30 160 mAIOH MAX -15 -15 -15 -6 -6 -15 -32 -24 mAIOL MAX 24 24 48 6 6 64 64 24 mAIOL* MAX - 48 - - - - - - mA*651-1
FUNCTION TABLE
OEBAOEAB
INPUTSOPERATION OR FUNCTION
L
X
CLKABH to L
↑
↑↑
↑
↑
↑
↑↑
LHH
H
CLKBAH to L
H to L
LL
H to L
HH
XL
SAB
X
XX
X
XX
SBA
X
XX
X
XX
A1–A8 B1–B8
DATA I/O
L XL X
LL
XH to L
XX
LH
H XH H to L
HH
XX
LH
XX
H H to L H to LL H H
Input Input IsolationInput Input Store A and B data
Input Unspecified Store A, hold BInput Output Store A in both registers
Unspecified Input Hold A, store BOutput Input Store B in both registers
Output Input Real-time B data to A busOutput Input Stored B data to A bus
Input Output Real-time A data to B busInput Output Stored A data to B bus
Output OutputStored A data to B bus and
stored B data to A bus
400
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
OEBA
A1B1
1D
C1
1D
C1
One of Eight Channels
SAB
CLKAB
SBA
CLKBA
OEAB
To Seven Other Channels
21
3
23
22
1
2
420
652OCTAL BUS TRANSCEIVERS AND REGISTERS
Bus Tranceivers / Registers Independent Registers and Enables for A and B Buses Multiplexed Real-Time and Stored Data True Data Paths 3-State Outputs 74AC11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series) 74ACT11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)
FUNCTION TABLE
OEBAOEAB
INPUTSOPERATION OR FUNCTION
L
X
CLKABH to L
LHH
H
CLKBAH to L
H to L
LL
H to L
HH
XL
SAB
X
XX
X
XX
SBA
X
XX
X
XX
A1–A8 B1–B8
DATA I/O
L XL X
LL
XH to L
XX
LH
H XH H to L
HH
XX
LH
XX
H H to L H to LL H H
↑
↑↑
↑
↑
↑
↑↑
Input Input IsolationInput Input Store A and B data
Input Unspecified Store A, hold BInput Output Store A in both registers
Unspecified Input Hold A, store BOutput Input Store B in both registers
Output Input Real-time B data to A busOutput Input Stored B data to A bus
Input Output Real-time A data to B busInput Output Stored A data to B bus
Output OutputStored A data to B bus and
stored B data to A bus
401PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN LS ALS AS SN74HC
CD74HC
SN74HCT
CD74HCT
SN74BCT
fmax MIN - 40 90 27 20 20 17 77MIN 15 12.5 5 19 24 25 38 6.5MIN 15 12.5 6 19 24 25 38 6.5MIN 15 - - - - - - -
tsu MIN 15 10 6 25 18 19 18 5tsu MIN 15 10 6 25 18 19 18 5th MIN 0 0 0 5 11 5 5 1tPLH 25 30 8.5 45 66 45 66 10.5tPHL 36 17 9 45 66 45 66 9.9tPLH 18 18 9 34 41 34 56 8.9tPHL 20 12 7 34 41 34 56 9.8tPLH 35 35 11 48 51 48 69 13.1tPHL 32 20 9 48 51 48 69 8.5tPLH 50 25 11 48 51 48 69 11.3tPHL 23 20 9 48 51 48 69 12.5tPZH 45 17 10 61 53 61 68 10.6tPZL 54 18 16 61 53 61 68 12tPHZ 38 10 9 61 53 61 53 10tPLZ 30 16 9 61 53 61 53 9.5tPZH 30 22 11 61 53 61 68 8.1tPZL 38 18 16 61 53 61 68 9.3tPHZ 38 10 10 61 53 61 53 11.6tPLZ 30 16 11 61 53 61 53 11.3
PARAMETER INPUT OUTPUT MAX or MIN ABT ABTVer.A
LVTH3V
AC11
CD74AC
ACT11
CD74ACT
LVC3V
fmax MIN 125 125 150 105 125 105 110 100MIN 4 4 3.3 4.8 4 4.8 4.5 3.3MIN 4 4 3.3 4.8 4 4.8 4.5 3.3MIN - - - - - - - -
tsu MIN 3.5 3 1.2 4.5 2.5 4 2.5 1.9tsu MIN 3.5 3 1.6 4.5 2.5 4 2.5 1.9th MIN 0 0 0.8 1 2 2.5 2 1.7tPLH 7.8 5.6 4.7 10.7 13.5 13.1 15.5 8tPHL 8.4 5.6 4.7 12 13.5 14.4 15.5 8tPLH 6.7 4.8 3.5 8.6 11 11.1 12.5 7.4tPHL 6.7 5.4 3.5 9.6 11 11.6 12.5 7.4tPLH 6.9 6.5 4.9 9.1 12 11 14.5 8.7tPHL 7.7 5.9 4.9 10.7 12 13.3 14.5 8.7tPLH 6.9 6.5 4.9 9.9 12 12.2 14.5 8.7tPHL 7.7 5.9 4.9 10.9 12 12.6 14.5 8.7tPZH 5.8 5.8 5.2 10.9 13.5 12.6 15.5 7.4tPZL 8.5 8.5 5.2 12.2 13.5 13.8 15.5 7.4tPHZ 8.2 5 5.5 7.6 13.5 9.9 15.5 7.5tPLZ 6.8 4.1 5.5 7.1 13.5 9.3 15.5 7.5tPZH 6.5 6.5 4.7 11.3 13.5 15.2 15.5 7.1tPZL 7.4 7.4 4.7 12.3 13.5 16.1 15.5 7.1tPHZ 6.9 5.5 5.6 7.6 13.5 10.3 15.5 7.4tPLZ 6.2 5.1 5.6 7.2 13.5 9.3 15.5 7.4UNIT fmax : MHz other : ns
A,B B,A MAX
A
B
B
OEBA
OEAB
OEAB
DATA
A,B
SAB,SBA(With Bus Input High)
SAB,SBA(With Bus Input Low)
OEBA
B,A
A,B
A,B
A
MAX
MAX
OEAB B
OEAB B
MAX
MAX
OEBA A
OEBA A
MAX
MAX
SAB,SBA(With Bus Input High) A,B
SAB,SBA(With Bus Input Low) A,B
CLOCK A,B MAX
A,B HighA,B Low
A,B
MAX
twCLKBA, CLKAB "H"CLKBA, CLKAB "L"
DATAA,B HighA,B Low
A,B
CLOCK A,B
twCLKBA, CLKAB "H"CLKBA, CLKAB "L"
MAX
MAX
MAX
MAX
MAX
MAX
MAX
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LS ALS AS SN74HC
CD74HC
SN74HCT
CD74HCT
SN74BCT ABT ABT
Ver.AUNIT
ICC MAX 180 88 211 0.08 0.16 0.08 0.16 69 30 30 mAIOH MAX -15 -15 -15 -6 -6 -6 -6 -15 -32 -32 mAIOL MAX 24 24 48 6 6 6 6 64 64 64 mA
PARAMETER MAX or MIN LVTH3V
AC11
CD74AC
ACT11
CD74ACT
LVC3V UNIT
ICC MAX 5 0.08 0.16 0.08 0.16 0.01 mAIOH MAX -32 -24 -24 -24 -24 -24 mAIOL MAX 64 24 24 24 24 24 mA
402
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
OEBA
A1B1
1D
C1
1D
C1
One of Eight Channels
204
2
1
22
23
21
3
SAB
CLKAB
SBA
CLKBA
OEAB
To Seven Other Channels
653OCTAL BUS TRANSCEIVERS AND REGISTERS
Bus Tranceivers / Registers Independent Registers and Enables for A and B Buses Multiplexed Real-Time and Stored Data Inverting Data Paths Outputs
A Bus: Open-CollectorB Bus: 3-State
403PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN LS ALS
CLK "H" MIN 15 14.5CLK "L" MIN 30 14.5DATA MIN 30 -
tsu A, B MIN 15 10th A, B MIN 0 0tPLH 38 64tPHL 39 22tPLH 23 30tPHL 36 17tPLH 18 18tPHL 30 15tPLH 32 56tPHL 24 15tPLH SBA 57 62tPHL (B "H") 39 25tPLH SBA 51 62tPHL (B "L") 35 25tPLH SAB 48 35tPHL (A "H") 33 22tPLH SAB 36 25tPHL (A "L") 30 22tPLH 35 30tPHL 55 24tPZH 29 22tPZL 38 22tPHZ 39 14tPLZ 29 16UNIT:ns
tw
MAX
MAX
MAX
B
A
B
MAX
MAX
MAX
MAX
MAX
MAX
MAX
MAX
A
A
A
B
OEAB
OEAB
OEBA
B
A
B
B
B
A
CLKBA
CLKAB
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LS ALS UNIT
ICC MAX 165 88 mAIOH MAX -15 -15 mAIOL MAX 24 24 mA
OEBAOEABINPUTS
OPERATION OR FUNCTION
L
X
CLKABH or L
LHH
H
CLKBAH or L
H or L Store A, hold BStore A in both registers
Hold A, store BStore B in both registers
IsolationStore A and B data
LL
H or L
HH
XL
SAB
X
XX
X‡
XX
SBA
X
XX
X
XX‡
A1–A8
Inpu
InputInput
OutputUnspeciffied‡
B1–B8
Input
DATA I/O†
Real-time B data to A busStored B data to A bus
L XL X
LL
XH or L
XX
LH
Output Input
Real-time A data to B busStored A data to B bus
H XH H or L
HH
XX
LH
XX
Input Output
Stored A data to B bus andstored B data to A busH H or L H or LL H H Output Output
OutputUnspeciffied‡
InputInput
FUNCTION TABLE
NOTES:† The data output functions can be enabled or dissabled by a variety of level combinations at GAB or GBA. Data input functions always are enabled;
i.e., data at the bus teminals is storedd on evry low-to-high transition on the clock inputs.‡ Select control = L: clocks can occur simultaneously.
Select control = H: clock must be staggered to load both registers.
↑
↑
↑
↑
↑↑
↑
↑
404
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
OEBA
A1B1
1D
C1
1D
C1
One of Eight Channels
204
2
1
22
23
21
3
SAB
CLKAB
SBA
CLKBA
OEAB
To Seven Other Channels
654OCTAL BUS TRANSCEIVERS AND REGISTERS
Bus Tranceivers / Registers Independent Registers and Enables for A and B Buses Multiplexed Real-Time and Stored Data True Data Paths Outputs
A Bus: Open-CollectorB Bus: 3-State
405PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LS ALS UNIT
ICC MAX 180 88 mAIOH MAX -15 -15 mAIOL MAX 24 24 mA
SWITCHING CHARACTERISTICS
PARAMETER OUTPUT MAX or MIN LS ALS
MIN 15 14.5MIN 30 14.5MIN 30 -
tsu MIN 15 10th MIN 0 0tPLH 33 64tPHL 36 22tPLH 21 30tPHL 33 17tPLH 18 18tPHL 30 15tPLH 27 56tPHL 21 21tPLH 48 62tPHL 32 25tPLH 54 62tPHL 29 25tPLH 35 25tPHL 27 22tPLH 45 35tPHL 21 22tPLH 35 30tPHL 53 24tPZH 29 22tPZL 33 22tPHZ 39 14tPLZ 29 16UNIT: ns
MAX
MAX
MAX
MAX
MAX
MAX
MAX
MAX
MAX
MAX
MAXB
B
A
B
B
A
A
A
B
B
A
OEAB
CLKBA, CLKAB "H"CLKBA, CLKAB "L"
DATAA,BA,B
SBA (B "H")
SBA (B "L")
SAB (A "H")
SAB (A "L")
tw
INPUT
OEBA
OEAB
CLKBA
CLKAB
A
B
FUNCTION TABLE
OEBAOEAB
INPUTSOPERATION OR FUNCTION
L
X
CLKABH to L
↑
↑↑
↑
↑
↑
↑↑
LHH
H
CLKBAH to L
H to L
LL
H to L
HH
XL
SAB
X
XX
X
XX
SBA
X
XX
X
XX
A1–A8 B1–B8
DATA I/O
L XL X
LL
XH to L
XX
LH
H XH H to L
HH
XX
LH
XX
H H to L H to LL H H
Input Input IsolationInput Input Store A and B data
Input Unspecified Store A, hold BInput Output Store A in both registers
Unspecified Input Hold A, store BOutput Input Store B in both registers
Output Input Real-time B data to A busOutput Input Stored B data to A bus
Input Output Real-time A data to B busInput Output Stored A data to B bus
Output OutputStored A data to B bus and
stored B data to A bus
406
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
T/R
OE
ERR
A1
A2
A3
A4
A5
A6
A7
A8
ODD/EVEN PARITY
B2
B3
B4
B5
B6
B7
B8
B1
1
2
3
4
5
6
8
9
10
11
24
13
12
23
22
21
20
17
16
15
14
657OCTAL BUS TRANSCEIVERS WITH 8-BIT PARITY GENERATORS/CHECKERS
Combines SN74F245 and SN74F280B Functions in One Package 3-State Outputs 74ACT11xxx: Product Available in Reduced-Noise Advanced CMOS (11000 Series)
407PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN F SN74BCT ABT ACT
11
tPLH MAX 8 6.6 4.6 9.4tPHL MAX 8 9 4.3 9.4tPLH MAX 16 15.4 8.1 14.4tPHL MAX 16 15.9 7.7 15tPLH MAX 12 7.1 4.9 10.7tPHL MAX 12.5 9 4.9 11.3tPLH MAX 22.5 15.3 7.9 23.6tPHL MAX 22.5 15.5 7.8 24.6tPLH MAX 16.5 13.2 7.7 14.6tPHL MAX 17 13.9 7.5 14.7tPZH MAX 9 9.1 6.5 12.1tPZL MAX 11 16.3 6.5 13.8tPZH MAX 9 9.1 6.6 12.1tPZL MAX 11 16.3 9.2 13.8tPHZ MAX 8 9.1 6.2 12.1tPLZ MAX 6.5 8 7.8 11.6UNIT: ns
ERR
A, B, PARITY, ERR
ERR
PARITY, ERR
ERR
A, B, PARITY
A,B
A
ODD/EVEN
B
PARITY
OE
OE
OE
B,A
PARITY
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN F SN74BCT ABT ACT
11 UNIT
ICCH MAX 125 2 0.25 0.08 mAICCL MAX 150 90 40 0.08 mAICCZ MAX 145 1 0.25 0.08 mAIOH A1-A9 MAX -3 -3 -32 -24 mA
IOH B1-B9,PARITY, ERR MAX -12 -15 -32 -24 mA
IOL A1-A8 MAX 24 24 64 24 mA
IOL B1-B8,PARITY, ERR MAX 64 64 64 24 mA
408
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
S
1D
C1
R
To Seven Other Channels
2
23
1
14
11
13
322
OE1
OE2
OERB
PRE
CLR
LE
1D 1Q
6668-BIT D-TYPE TRANSPARENT READ-BACK LATCHES
3-State I/O-Type Read-Back Inputs True Outputs Bus-Structured Pinout
409PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN ALS
LE "H" MIN 10
CLR "L" MIN 10
PRE "L" MIN 10DATA (LE) MIN 10
DATA (OERB) MIN 10th DATA (LE) MIN 5tPLH 14tPHL 18tPLH 21tPHL 27
Q 29D 32
tPLH Q 22tPHL D 28
21142114
UNIT: nstdis
OE1 , OE2
tPHL
ten
tdis
ten
OERB
MAXQD
MAX
MAXQ
D
MAX
MAX
MAX
PRE
PARAMETER
LE
CLR
Q
tsu
tw
RECOMMENDED OPERATING CONDITIONS
MAX or MIN ALS UNIT
ICC MAX 73 mAQ MAX -2.6 mAD MAX -0.4 mAQ MAX 24 mAD MAX 8 mA
PARAMETER
IOL
IOH
410
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
6678-BIT D-TYPE TRANSPARENT READ-BACK LATCHES
3-State I/O-Type Read-Back Inputs Inverted Outputs Bus-Structured Pinout
S
1D
C1
R
To Seven Other Channels
2
23
1
14
11
13
322
OE1
OE2
OERB
PRE
CLR
LE
1D1Q
411PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN ALS
LE "H" MIN 10
CLR "L" MIN 10
PRE "L" MIN 10DATA (LE) MIN 10
DATA (OERB) MIN 10th DATA (LE) MIN 5tPLH 20tPHL 15tPLH 28tPHL 22
Q 24
D 26tPLH Q 25tPHL D 28
21142114
UNIT: ns
tw
tsu
ten
tdis
tdis
tPHL CLR
PRE
OERB
MAX
MAX
Q
Q
MAX
MAX
MAX
MAX
PARAMETER
D
Q
LE
D
OE1 , OE2ten
RECOMMENDED OPERATING CONDITIONS
MAX or MIN ALS UNIT
ICC MAX 79 mAQ MAX -2.6 mAD MAX -0.4 mAQ MAX 24 mAD MAX 8 mA
PARAMETER
IOL
IOH
412
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1D(14)
QA
(13)QB
(12)QC
(11)QD
(15)RCO
C1
(2)CLOCK
(1)U/D
(9)LOAD
DATA A
(7)ENABLEP
(10)
(3)
DATA B(4)
DATA C(5)
DATA D(6)
ENABLET
1D
C1
1D
C1
1D
C1
669SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTER
Fully Synchronous Operation for Counting and Programming Internal Look-Ahead for Fast Counting Carry Output for n-Bit Cascading
413PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN LS
fmax MIN 25tw MIN 20
A,B,C,D MIN 25
ENP,ENT MIN 40
LOAD MIN 30
U/D MIN 45th MIN 0tPLH 40tPHL 60tPLH 27tPHL 27tPLH 17tPHL 45tPLH 35tPHL 40UNIT fmax : MHz other : ns
tsu
MAXCLOCK RCO
RCO
MAX
MAX
MAX
Q
RCO
PARAMETER
U/D
CLOCK
ENT
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LS UNIT
ICC MAX 34 mAIOH MAX -0.4 mAIOL MAX 8 mA
414
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
D2(1)
GW
Q2(9)
D
G
QD
G
QD
G
QD
G
Q
D1(15)
WORD 0 WORD 1 WORD 2 WORD 3 Q1(10)
D
G
QD
G
QD
G
QD
G
Q
D3(2)
Q3(7)
D
G
QD
G
QD
G
QD
G
Q
D4
(12)
GR
(11)WB
WRITE INPUT
(13)WA
(14)
(3)
Q4(6)
D
G
QD
G
QD
G
QD
G
Q
RB
READ INPUT
OU
TP
UT
S
DA
TA IN
PU
TS
(4)RA
(5)
6704-BY-4 REGISTER FILE
Separate Read / Write Addressing Permits Simultaneous Reading and Writing Organized as 4 Words of 4 Bits Expandable to 512 Words of n-Bits 3-State Outputs
415PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN LS CD74HC
CD74HCT
tw MIN 25 24 30tsu (D) MIN 10 18 18tsu (W) MIN 15 18 30th (D) MIN 15 5 5th (W) MIN 5 5 5tlatch MIN 25 30 38tPLH 40 59 53tPHL 45 59 53tPLH 45 75 75tPHL 50 75 75tPLH 45 75 75tPHL 40 75 75tPZH 35 45 57tPZL 40 45 57tPHZ 50 45 53tPLZ 35 45 53UNIT: ns
MAX
Q
Q
Q
Q
Q
MAX
MAX
MAX
MAX
PARAMETER
ReadDisable
ReadSelect
WriteEnable
Data
ReadEnable
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LS CD74HC
CD74HCT UNIT
ICC MAX 50 0.16 0.16 mAIOH MAX -2.6 -6 -6 mAIOL MAX 8 6 6 mA
FUNCTION TABLE
WRITE INPUTS WORD
L
L
L
H
GWWB 3
H
H
L
L
L
L
Q0
2
Q = D
Q0Q0
1
Q0
Q0Q0Q0Q = D
0Q = D
Q0
Q0Q0Q0Q0
Q0Q0Q0
Q0
WA
L
HX H
Q = D
X
READ INPUTS OUTPUTS
L
L
L
H
GRRB Q4
H
H
L
L
L
L
W2B4
Q3
W2B3
W1B4W1B3
Q2
W2B2
W0B4W0B3W0B2
W1B2
Q1W0B1
W2B1
ZZZZ
W3B3W3B2W3B1
W1B1
RA
L
HX H
W3B4
X
416
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
SH CLK(2)
STRCLR
CS
(4)
Q15
Q0-Q15
CLK
16
PE†
16-BIT SHIFT REGISTER
SER/Q15
P0-P15
SER IN
16
Y0-Y15Y0-Y15
CLK
16
CLR
D0-D15
(6)
(7-11, 13-23)
16BITSTORAGEREGISTER
MODE/STRCLK(5)
(1)
R/W(3)
† When PE is active, data synchronously parallel loaded into the shift registers form the 16 P inputs and no shifting takes place.
67316-BIT SHIFT REGISTER
16-Bit Serial-In, Serial-Out Shift Register with 16-Bit Parallel-Out Storage Register Performs Serial-to-Parallel Conversion
417PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN LS
fmax MIN 20CLK MIN 20CLR MIN 20
SER/Q15 MIN 20Y0-Y15 MIN 20Mode MIN 35
R/W,CS MIN 35SER/Q15 MIN 0Y0-Y15 MIN 0Mode MIN 0
tPLH STRCLR Y0-Y15 MAX 40tPLH 45tPHL 45tPLH 33tPHL 40UNIT fmax : MHz other : ns
MAX
MAX
MODE/STRCLK
SH CLK SER/Q15
Y0-Y15
tw
tsu
th
PARAMETER
RECOMMENDED OPERATING CONDITIONS
MAX or MIN LS UNIT
ICC MAX 80 mASER/Q15 MAX -2.6 mAY0-Y15 MAX -0.4 mA
SER/Q15 MAX 24 mAY0-Y15 MAX 8 mA
PARAMETER
IOH
IOL
FUNCTION TABLE
R/WCS
INPUTS
H
L
SH CLK
XX
XX X L
L
STRCLR
X
LL
LH XHH
MODE/STRCLK
X
XX
XLX
XXXL
SER/Q15
Z
Z
Q15Q14nL
WRITE INTOSERIAL INPUT
SHIFT REGISTER FUNCTIONS
LL X
HL
HH
X Y15nZ
SHIFT
YES
NO
YESNONO
READ FROMSERIAL INPUT
NO
NO
YESYESYESYESNO
YES
NO
NONO
PARALLELLOAD
NO
NO
NOYESYES
CLEAR
YES
YES;NONO
LOADNO
NONONONOYES
→→
→→
→
STORAGE REGISTERFUNCTIONS
418
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
CLK(2)
CS
Q15
CLK
PE†
16-BIT SHIFT REGISTER
P0-P15
P0-P15
SER IN
16
(6)
SER/Q15
(7-11, 13-23)MODE
(5)
(1)
R/W(3)
† When PE is active, data synchronously parallel loaded into the shift registers form the 16 P inputs and no shifting takes place.
67416-BIT SHIFT REGISTER
16-Bit Parallel-In, Serial-Out Shift Register Performs Parallel-to-Serial Conversion
419PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN LS
fmax MIN 20
CLK 20
CLR 20
SER/Q15 20
P0-P15 20
Mode 35
R/W,CS 35
SER/Q15 0
P0-P15 0
Mode 0tPLH 33tPHL 40tPZH 45tPZL 45tPHZ 40tPLZ 40UNIT fmax : MHz other : ns
MAX
MAX
SER/Q15
SER/Q15
CS, R/W
CS, R/W
tw
PARAMETER
MIN
SER/Q15
th
CLK
tsu
MIN
MAX
MIN
RECOMMENDED OPERATING CONDITIONS
MAX or MIN LS UNIT
ICC MAX 40 mASER/Q15 MAX -2.6 mAP0-P15 MAX -0.4 mA
SER/Q15 MAX 24 mAP0-P15 MAX 8 mA
PARAMETER
IOH
IOL
FUNCTION TABLE
MODESER/Q15
INPUTS
H
L
R/WCS CLK
L
L
L
H
H
X X
H
X
L
X
Z
Q14n
Z
P15
OPERATION
Do nothing
Shift and read
Shift and write (serial load)
parallel load
→→
→
420
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1
2
3
4
5
6
7
8
9
11
12
14
15
16
17
19
18
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
Y
P0
P1
P2
P3
G
13A12
679ADDRESS COMPARATOR
12-Bit Address Comparator with Enable
421PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALS SN74HC
tPLH 25 375tPHL 35 375tPLH 22 78tPHL 30 78tPLH 13 31tPHL 25 31UNIT: ns
G Y MAX
Y MAX
Any P Y MAX
Any A
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALS SN74HC UNIT
ICC MAX 28 0.08 mAIOH MAX -2.6 -4 mAIOL MAX 24 4 mA
A2
FUNCTION TABLE
OUTPUTINPUTS
LL
P0P2G P3LLL L
LL
P1
H
LHL
HHL
A1HLL
YLLL
A3HHH
A4HHH
A5HHH
A6HHH
A7HHH
A8HHH
A9HHH
A10HHH
A11HHH
A12HHH
LLL
L L H H LL LL H H H H H H H H HLHH
LLL H
LLH
LHL
LLL
LLL
LLL
LLL
LLL
HLL
HHL
HHH
HHH
HHH
HHH
HHH
HHH
LLL
L H H H LL LL L L L L H H H H HL
LL
LLL L
LLH
LHL
LLL
LLL
LLL
LLL
LLL
LLL
LLL
LLL
LLL
HLL
HHL
HHH
HHH
HHH
L L H H LL LL L L L L L L L L HH
HH
LLL H
LLH
LHL
LLL
LLL
LLL
LLL
LLL
LLL
LLL
LLL
LLL
HLL
HHL
HHH
LLL
HHH
L H H H LL L
H
H
L L L L L L L L L LH
L All other combinations
H Any combination
422
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
2
3
4
5
6
7
8
9
11
12
13
14
15
16
17
18
1
19
P0
P1
P2
P3
P4
P5
P6
P7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
P = Q
P > Q
6828-BIT IDENTITY COMPARATOR
Totem-Pole Outputs Hysteresis at P and Q Inputs 20kΩ Pullup Resistors on the Q Inputs
423PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN LS SN74HC
tPLH 25 69tPHL 25 69tPLH 25 69tPHL 25 69tPLH 30 69tPHL 30 69tPLH 30 69tPHL 30 69UNIT: ns
P = Q
P > Q
P = Q
P > Q
MAX
Q
P
Q
P
MAX
MAX
MAX
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LS SN74HC UNIT
ICC MAX 70 0.11 mAIOH MAX -0.4 -4 mAIOL MAX 24 4 mA
FUNCTION TABLE
INPUTDATA OUTPUTS
P=QP>Q
P=QP, Q P>Q
P<Q
L
HH
H
HL
424
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
2
3
4
5
6
7
8
9
11
12
13
14
15
16
17
18
1
19
P0
P1
P2
P3
P4
P5
P6
P7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
P = Q
P > Q
6848-BIT IDENTITY COMPARATOR
Totem-Pole Outputs Hysteresis at P and Q Inputs
425PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN LS SN74HC
tPLH 25 69tPHL 25 69tPLH 25 69tPHL 25 69tPLH 30 69tPHL 30 69tPLH 30 69tPHL 30 69UNIT: ns
P > Q MAX
P > Q MAX
P = Q MAX
P = Q MAX
P
Q
P
Q
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LS SN74HC UNIT
ICC MAX 65 0.08 mAIOH MAX -0.4 -4 mAIOL MAX 24 4 mA
FUNCTION TABLE
INPUTDATA OUTPUTS
P=QP>Q
P=QP, Q
P>Q
P<Q
L
HH
H
HL
426
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
P7
P = Q
(17)
(19)
Q7(18)
P6(15)
Q6(16)
P5(13)
Q5(14)
P4(11)
Q4(12)
P3(8)
Q3(9)
P2(6)
Q2(7)
P1(4)
Q1(5)
P0(2)
Q0(3)
P > Q(1)
6868-BIT IDENTITY COMPARATOR
Totem-Pole Outputs Hysteresis at P and Q Inputs
427PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN LS
tPLH 25tPHL 30tPLH 25tPHL 30tPLH 20tPHL 30tPLH 30tPHL 30tPLH 30tPHL 30tPLH 30tPHL 25UNIT: ns
MAX
MAX
MAX
MAX
Q P > Q
G2 P > Q
G1 P = Q
P P > Q
P P = Q MAX
Q P = Q MAX
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LS UNIT
ICC MAX 75 mAIOH MAX -0.4 mAIOL MAX 24 mA
FUNCTION TABLEINPUTS
DATA ENABLEOUTPUTS
P=QP>Q
P=QP, Q
P>Q
P<Q
LL
G1
L
LL
G2
L
L
HH
H
H
X H H H H
L
428
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
2
3
4
5
6
7
8
9
11
12
13
P0
P1
P2
P3
P4
P5
Q0
Q1
Q2
Q3
Q4
P = Q
14
15
16
17
18
1
P6
Q5
P7
Q6
Q7
19
OE
6888-BIT IDENTITY COMPARATOR
Totem-Pole Outputs Hysteresis at P and Q Inputs
429PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN LS ALS SN74HC
CD74HC
CD74HCT
tPLH 18 12 53 51 51tPHL 23 20 53 51 51tPLH 18 12 53 51 51tPHL 23 20 53 51 51tPLH 18 12 30 36 36tPHL 20 22 30 36 36UNIT: ns
P
Q
G
MAX
P = Q MAX
P = Q MAX
P = Q
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LS ALS SN74HC
CD74HC
CD74HCT UNIT
ICC MAX 65 19 0.08 0.16 0.16 mAIOH MAX -0.4 -2.6 -4 -4 -4 mAIOL MAX 24 24 4 4 4 mA
FUNCTION TABLEINPUTS
DATA ENABLEOUTPUT
P=QP>Q
P=QP, Q
P<Q
LL
G
L
L
HH
X H H
430
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
(18)
(17)
(15)
(19)
(16)
(12)
(11)
(9)
(8)
(1)
(13)
(7)
(14)
(2)
(6)D
(4)B
(3)A
G
QA
QB
QC
QD
RCO
1D
C1
R
2D
C2
C2
2D
2D
C2
2D
C2
R/C
RCK
CCLR
U/D
LOAD
ENP
ENT
CCK
1D
C1
R
1D
C1
R
1D
C1
R
(5)C
697SYNCHRONOUS UP/DOWN COUNTER WITH OUTPUT REGISTER, MULTIPLEXEDTHREE-STATE OUTPUT
Multiplexed Outputs for Counter or Latched Data 3-State Outputs Drive Bus Lines Directly Binary Counter, Direct Clear
431PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN LS
CCK 25
RCK 25
A thru D 30
ENT, ENP 30
U/D 35th MIN 0tPLH 40tPHL 40tPLH 20tPHL 20tPLH 20tPHL 25tPLH 20tPHL 25tPHL CCLR Q MAX 40tPLH 25tPHL 25UNIT: ns
MAX
MAX
MAX
MIN
MIN
MAX
MAX
RCK
R / C
RCO
Q
Q
Q
CCK RCO
CCK
tsu
tw
PARAMETER
ENT
RECOMMENDED OPERATING CONDITIONS
MAX or MIN LS UNIT
ICC MAX 70 mA
Q -2.6 mA
RCO -0.4 mA
Q 24 mA
RCO 8 mAMAX
MAX
PARAMETER
IOH
IOL
432
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1D (18)
(17)
(15)
(19)
(16)
(12)
(11)
(9)
(8)
(1)
(13)
(7)
(14)
(2)
(3)
(4)
(5)
(6)D
C
B
A
G
QA
QB
QC
QD
RCO
C1
2D
C2
1D
C1 C2
2D
1D
C1
2D
C2
1D
C1
2D
C2
R/C
RCK
CCLR
U/D
LOAD
ENP
ENT
CCK
699SYNCHRONOUS UP/DOWN COUNTER WITH OUTPUT REGISTER, MULTIPLEXEDTHREE-STATE OUTPUT
Multiplexed Outputs for Counter or Latched Data 3-State Outputs Drive Bus Lines Directly Binary Counter, Synchronous Clear
433PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN LS
CCK 25
RCK 25
A thru D 30
ENT, ENP 30
U/D 35
CCLR 30th MIN 0tPLH 40tPHL 40tPLH 20tPHL 20tPLH 20tPHL 25tPLH 20tPHL 25tPLH 25tPHL 25UNIT: ns
MAX
RCK
MIN
MAX
MAX
MAX
MAX
Q
Q
ENT
CCK
RCO
RCO
R/C
CCK Q
MIN
tsu
tw
PARAMETER
RECOMMENDED OPERATING CONDITIONS
MAX or MIN LS UNIT
ICC MAX 70 mA
Q MAX -2.6 mA
RCO MAX -0.4 mA
Q MAX 24 mA
RCO MAX 8 mA
PARAMETER
IOL
IOH
434
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
756OCTAL BUFFER/LINE DRIVER/LINE RECEIVER WITH OPEN-COLLECTOR OUTPUTS
Eliminate the Need for 3-State Overlap Protection pnp Inputs Reduce dc Loading Open-Collector Versions of SN74AS240A
1
218
1OE
1A11Y1
416
1A21Y2
614
1A31Y3
812
1A41Y4
19
119
2OE
2A12Y1
137
2A22Y2
155
2A32Y3
173
2A42Y4
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN AS SN74BCT UNIT
ICC MAX 80 86 mAVOH MAX 5.5 5.5 VIOL MAX 64 64 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN AS SN74BCT
tPLH 19 11.3tPHL 6 4.2tPLH 19.5 16.5tPHL 7.5 10.3UNIT:ns
A
OE
Y MAX
Y MAX
435
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
757OCTAL BUFFER/LINE DRIVER/LINE RECEIVER WITH OPEN-COLLECTOR OUTPUTS
Eliminate the Need for 3-State Overlap Protection pnp Inputs Reduce dc Loading Open-Collector Versions of SN74AS241
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN AS SN74BCT
SN64BCT
UNIT
ICC MAX 95 77 77 mAVOH MAX 5.5 5.5 5.5 VIOL MAX 64 64 64 mA
1
2
4
6
8
19
11
13
15
17 3
5
7
9
12
14
16
181A1
1A2
1A3
1A4
1Y1
2OE
2A1
2A2
2A3
2A4
2Y1
1Y2
1Y3
1Y4
2Y2
2Y3
2Y4
1OE
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN AS SN74BCT
SN64BCT
tPLH 18.5 10.1 10.1tPHL 6 6.6 6.6tPLH 20 19.7 19.7tPHL 7 6.9 6.9tPLH 21 18 18tPHL 7.5 8.5 8.5UNIT:ns
A Y MAX
MAX
1Y
2Y
1OE
2OE
MAX
436
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
760OCTAL BUFFER/LINE DRIVER/LINE RECEIVER WITH OPEN-COLLECTOR OUTPUTS
Open-Collector Outputs Drive Bus Lines or Buffer Memory Address Registers pnp Inputs Reduce dc Loading Open-Collector Versions of SN74ALS244 and SN74AS244
1
2
4
6
8
19
11
13
15
17 3
5
7
9
12
14
16
181A1
1A2
1A3
1A4
1Y1 2A1
2A2
2A3
2A4
2Y1
1Y2
1Y3
1Y4
2Y2
2Y3
2Y4
2OE1OE
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALS AS SN74BCT UNIT
ICC MAX 19 94 76 mAVOH MAX 5.5 5.5 5.5 VIOL MAX 24 64 64 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALS AS SN74BCT
tPLH 15 18.5 10tPHL 12 6 7.2tPLH 16 18.5 17.5tPHL 13 7 9.9UNIT:ns
A Y
Y
MAX
MAXOE
437
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
804HEX 2-INPUT NAND DRIVERS
Y = A•B High Capacitive-Drive Capability
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALS AS SN74HC UNIT
ICC MAX 12 27 0.08 mAIOH MAX -15 -48 -6 mAIOL MAX 24 48 6 mA
FUNCTION TABLE
INPUTS
AHLX
B
L
HX
OUTPUT
LHH
Y
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALS AS SN74HC
tPLH MAX 7 4 25tPHL MAX 8 4 25UNIT:ns
A, B Y
1Y3
11A
21B
2Y6
42A
52B
3Y9
73A
83B
4Y11
124A
134B
5Y14
155A
165B
6Y17
186A
196B
438
Logic Diagram
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
805HEX 2-INPUT NOR DRIVERS
Y = A + B High Capacitive-Drive Capability
1Y3
2Y6
3Y9
4Y11
5Y14
6Y17
11A
21B
42A
52B
73A
83B
124A
134B
155A
165B
186A
196BRECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALS AS SN74HC UNIT
ICC MAX 14 32 0.08 mAIOH MAX -15 -48 -6 mAIOL MAX 24 48 6 mA
INPUTS OUTPUT
L
Y
L
A
HXL
X
L H
B
H
FUNCTION TABLE
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALS AS SN74HC
tPLH MAX 7 4.3 24tPHL MAX 8 4.3 24UNIT:ns
A, B Y
808HEX 2-INPUT AND DRIVERS
Y = A + B High Capacitive-Drive Capability
1Y3
11A
21B
2Y6
42A
52B
3Y9
73A
83B
4Y11
124A
134B
5Y14
155A
165B
6Y17
186A
196BRECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN SN74HC AS UNIT
ICC MAX 0.08 33 mAIOH MAX -6 -48 mAIOL MAX 6 48 mA
INPUTS OUTPUT
L
Y
H
A
HLX
H
L L
B
X
FUNCTION TABLE
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN SN74HC AS
tPLH MAX 25 6tPHL MAX 25 6UNIT:ns
A, B Y
439
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN AS ABT LVC UNIT
ICC MAX 113 38 0.01 mAIOH MAX -24 -32 -24 mAIOL MAX 48 64 24 mA
INPUTS
FUNCTION TABLE
OUTPUT
L
QH
OELL
↑↑
L
H
X Q0H
CLK
LX X Z
D
L
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN AS ABT LVC3V
MIN 8 2.9 3.3MIN 8 3.8 3.3
tsu MIN 6 2.1 1.9th MIN 0 1.3 1.5tPLH 7.5 6.2 7.3tPHL 13 6.7 7.3tPZH 11 5.8 7.6tPZL 12 6.3 7.6tPHZ 8 6.7 6.2tPLZ 8 6.5 6.2UNIT: ns
CLK
tw
OE
OE
HighLow
MAX
MAX
MAX
Q
Q
Q
1D
OE
1Q
CLK
C1
1D
1
13
223
To Nine Other Channels
82110-BIT BUS INTERFACE FLIP-FLOPSWITH 3-STATE OUTPUT
Outputs Have Undershoot-Protection Circuitry Power-Up High-Impedance State
440
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
To Eight Other Channels
1D
1Q
CLKEN
CLK
OE
CLR
1
11
14
13
2
R
1D
C1 23
8239-BIT BUS INTERFACE FLIP-FLOP WITH 3-STATE OUTPUT
Functionally Equivalent to AMD’s AM29823 and AM29824 Outputs Have Undershoot-Protection Circuitry Power-Up High-Impedance State
441PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN AS ABT LVC3V UNIT
ICC MAX 103 38 0.01 mAIOH MAX -24 -32 -24 mAIOL MAX 48 64 24 mA
FUNCTION TABLE
OUTPUT
H
QL
OELLL
X
L LL
CLKX
X X Q0
D
H
CLRLHHH
CLKENINPUTS
XLLH
H X X ZX X
↑↑
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN AS ABT LVC3V
CLR "L" 6.5 5.5 3.3CLK "H" 8 2.9 3.3CLK "L" 8 3.8 3.3
CLR 8 2.5 1DATA 6 2.1 1.3
CLKEN "H" 7.5 2 1.8
CLKEN "L" - 3.3 1.8DATA - 1.3 2
CLKEN "H" - 1 -
CLKEN "L" 0 2 1.3tPLH 7.5 6.8 8tPHL 13 6.7 8tPHL CLR Q MAX 15.5 7.1 7.9tPZH 11 6 7.2tPZL 12 6.5 7.2tPHZ 8 7.5 6tPLZ 8 6.9 6UNIT: ns
OE
OE
PARAMETER
th
tw
tsu
Q
MAX
MAX
MAX
Q
MIN
MIN
MIN
CLK Q
442
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
To Seven Other Channels
22
3
1
1D
1Q
R
C1
1D
CLKEN
CLK
11
14
13
OE1
CLR
OE2
OE3
2
23
8258-BIT BUS INTERFACE FLIP-FLOP WITH 3-STATE OUTPUT
Improved IOH Specifications (Max: -24mA) Outputs Have Undershoot-Protection Circuitry Power-Up High-Impedance State
443PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN AS UNIT
ICC MAX 95 mAIOH MAX -24 mAIOL MAX 48 mA
FUNCTION TABLE
OUTPUT
H
QL
OELLL
X
L LL
CLKX
X X Q0
D
H
CLRLHHH
CLKENINPUTS
XLLH
H X X ZX X
↑↑
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN AS
CLR "L" 4
CLK "H" 8
CLK "L" 8
CLR 8
DATA 6
CLKEN 6th MIN 0tPLH 7.5tPHL 13tPHL CLR Q MAX 15.5tPZH 11tPZL 12tPHZ 8tPLZ 8UNIT: ns
PARAMETER
tw
tsu
OE
OE
MIN
MIN
CLK Q MAX
Q
MAX
MAX
Q
444
Logic Diagram
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
82710-BIT BUFFERS/BUS DRIVERS
3-State Outputs Drive Bus Lines or Buffer MemoryAddress Registers
74AC11xxx: Product Available in Reduced-NoiseAdvanced CMOS (11000 Series)
74ACT11xxx: Product Available in Reduced-NoiseAdvanced CMOS (11000 Series)
82810-BIT BUFFERS/BUS DRIVERS
3-State Outputs Drive Bus Lines or Buffer MemoryAddress Registers
74AC11xxx: Product Available in Reduced-NoiseAdvanced CMOS (11000 Series)
74ACT11xxx: Product Available in Reduced-NoiseAdvanced CMOS (11000 Series)
Y1
To Nine Other Channels
OE1
OE2
A1
1
13
2 23
Y1
To Nine Other Channels
OE1
OE2
A1
1
13
2 23
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ABT AC11
ACT11
LVC3V UNIT
ICC MAX 40 0.08 0.08 0.01 mAIOH MAX -32 -24 -24 -24 mAIOL MAX 64 24 24 24 mA
FUNCTION TABLE
OUTPUT
L
Y
HOE1
LL
LL
X
H
X ZH
OE2INPUTS
HX X Z
A
L
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ABT AC11
ACT11
LVC3V
tPLH 4.8 8.7 9.2 6.7tPHL 4.7 9.7 11.2 6.7tPZH 5.9 9.7 11.3 7.3tPZL 6.9 13 14 7.3tPHZ 6.8 9.1 12 6.7tPLZ 6.9 8.8 11.6 6.7UNIT: ns
MAX
MAX
MAX
YOE
OE
A
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN AC11
ACT11
LVC3V UNIT
ICC MAX 0.08 0.08 0.01 mAIOH MAX -24 -24 -24 mAIOL MAX 24 24 24 mA
FUNCTION TABLE
OUTPUT
H
Y
LOE1
LL
LL
X
H
XZH
OE2INPUTS
HX X
Z
A
L
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN AC11
ACT11
LVC3V
tPLH 9.5 10.2 6.7tPHL 10.4 11.7 6.7tPZH 10.7 12.1 7.3tPZL 13.2 14.7 7.3tPHZ 9.6 12.3 6.7tPLZ 9.2 11.7 6.7UNIT: ns
OE
Y
MAX
MAX
MAX
A
OE
445
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
832HEX 2-INPUT OR DRIVERS
Y = A + B High Capacitive-Drive Capability
1Y3
11A
21B
2Y6
42A
52B
3Y9
73A
83B
4Y11
124A
134B
5Y14
155A
165B
6Y17
186A
196B
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALS AS SN74HC UNIT
ICC MAX 16 36 0.08 mAIOH MAX -15 -48 -6 mAIOL MAX 24 48 6 mA
INPUTS OUTPUT
H
Y
H
A
HXL
X
L L
B
H
FUNCTION TABLE
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALS AS SN74HC
tPLH MAX 9 6.3 25tPHL MAX 8 6.3 25UNIT:ns
A, B Y
446
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
ERR
CLR
OEA
OEB
88
8
8
8
9 P
MUX
1
1
1
G1
1
2k
1D
R
C1
EN
EN
8x
8x
A1–A8
CLK
PARITY
B1–B8
15
10
14
1
13
11
2–916–23
83310-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
447PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
CLR
† The state of ERR before any changes at CLR, CLK, or point P
A data to B bus andgenerate parity
A data to B bus andgenerate inverted parity
INPUTS OUTPUTS AND I/OFUNCTION
CLKAi
Σ OF H’sBi
Σ OF H’s B PARITY ERROEA
XOddEven
OddEven
OddEven
X
X X X
XX
X
XX
X X
X
LH NAAH
H
H H
H
HH
OEB
L
NALLHLA
NC
L
L
H
H
LH
NoNo
Isolation
Check error flag register
B data to A bus andcheck parity
L
H
A
NA
NA NA
HNA NA
NA
Z Z Z
B
NA
OddEven NA
NAL
CLR
Clear
INPUTSINTERNALTO DEVICE
OUTPUTPRE-STATE OUTPUT
ERRFUNCTION
CLK POINT P ERRn-1†
X X
XX
HH
HL
HH
HH
LL
X
LH
Sample
FUNCTION TABLE
↑↑↑
↑
↑↑
↑
↑
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ABT UNIT
ICC MAX 38 mAIOH MAX -32 mAIOL MAX 64 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ABT
tPLH 5.3tPHL 5.3tPLH 11.2tPHL 11tPZH 10.5tPZL 10tPLH CLR 5.2tPHL CLK 6.2tPZH 6.5tPZL 6.5tPHZ 7.9tPLZ 8.1UNIT: ns
A
A or B
PARITY
OE
OE
OE
PARITY
ERR
A,B, or PARITY
A,B, or PARITY MAX
B or A MAX
MAX
MAX
MAX
MAX
448
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
OE
To Nine Other Channels
1
13
223
LE
1D
C1
1D1Q
84110-BIT BUS INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS
3-State Buffer-Type Outputs Drive Bus Lines Directly Bus-Structured Pinout Provide Extra Bus-Driving Latches Necessary for Wider Address/Data Paths or Buses with Parity Power-Up High-Impedance State
449PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALS AS ABT LVC3V UNIT
ICC MAX 62 94 38 0.01 mAIOH MAX -2.6 -24 -32 -24 mAIOL MAX 24 48 64 24 mA
FUNCTION TABLE
OUTPUT
H
QL
OELL
HH
L
H
X Q0H
LEINPUTS
LX X Z
D
L
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALS AS ABT LVC3V
tw 20 4 3.3 3.3tsu 10 2.5 2.5 2.1tsu 10 2.5 1.5 2.1th 5 2.5 1.5 1tPLH 13 6.5 6.2 6.7tPHL 13 10.5 6.2 6.7tPLH 21 12 6.5 7.6tPHL 26 12 6.7 7.6tPZH 12 14 5.3 7.2tPZL 12 16 6.3 7.2tPHZ 10 8 7.1 5.9tPLZ 12 8 6.5 5.9UNIT: ns
LE Q MAX
MIN
D Q MAX
HighLow
OE
OE Q MAX
Q MAX
450
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1D
OE
PRE
1Q
CLR
LE
To Eight Other Channels
1
14
11
13
223
S2
C1
1D
R
8439-BIT BUS INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS
3-State Buffer-Type Outputs Drive Bus Lines Directly Bus-Structured Pinout Provides Extra Bus-Driving Latches Necessary for Wider Address/Data Paths or Buses with Parity Power-Up High-Impedance State
451PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALS AS ABT UNIT
ICC MAX 67 92 34 mAIOH MAX -2.6 -24 -32 mAIOL MAX 24 48 64 mA
INPUTS
FUNCTION TABLE
OUTPUT
LH
PRE OECLRLH
XX
L
X
X HH
LE
XH L L
H H H HH L X Q0
D
X
X
HLLHHHX
LLLLLLH X X Z
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN ALS AS ABT
CLR "L" 35 4 5.5
PRE "L" 35 4 4.5
LE "H" 20 4 -
LE "L" - 4 3.4
LE "L" 10 2.5 2.5
LE "H" 10 2.5 3
PRE inactive - 15 1.6
CLR inactive - 14 2
LE "L" 5 2.5 1
LE "H" 5 2.5 1.5tPLH 13 6.5 6.7tPHL 18 9 7.2tPLH 21 12 7.2tPHL 26 12 6.9tPLH - - 7.1tPHL 23 13 8tPLH 22 10 7.4tPHL - - 7.2tPZH 12 10.5 5.7tPZL 14 13.5 6.5tPHZ 10 8 6.8tPLZ 12 8 5.9UNIT: ns
PARAMETER
tw MIN
tsu MIN
Q MAXOE
MIN
D Q MAX
Q MAX
Q
th
MAX
Q MAX
MAX
Q
LE
CLR
PRE
OE
452
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
PARITY
ERR
CLR
B1–B8A1–A8
LE
OEA
OEB
EN
EN
8x
8x
MUX1
1
G1
1
12k
P
8
9
8
8
8
8
2–9
14
1
13
11
23–16
15
10
8538-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
453PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ABT UNIT
ICC MAX 38 mAIOH MAX -32 mAIOL MAX 64 mA
CLR
A data to B bus and generate parity
A data to B bus and generate inverted parity
INPUTS OUTPUT AND I/OsFUNCTION
LEAi
Σ OF HBi†
Σ OF H B PARITY ERR‡OEA
XOddEven
L OddH Even
OddEven
X
XX
X
XX
X X
X
LH NAAH
H
H H
H
HH
OEB
L
NALLHLA
NC
NC
L
L
HLHHLL
HIsolation§
(parity check)
Store error flag
B data to A bus and check parityH
H HH
A
NA
NA NAX X X X X H Clear error flag registerL NA NA
HNA NA
NA
Z Z Z
B
NA
OddEven NA
NAL L
H L
CLR
Clear
INPUTSINTERNALTO DEVICE
OUTPUTPRE-STATE OUTPUT
ERRFUNCTION
LE POINT P ERRn-1†
X
XX
H
H H
H H
L
L
L
L
H
HHHL
L L
LHL
X
L
HL
Sample
Pass
StoreX H
L
X
FUNCTION TABLE
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ABT
tPLH 5.3tPHL 5.3tPLH 11.2tPHL 11tPLH 10.5tPHL 10tPLH CLR ERR MAX 6.2tPLH 6tPHL 6.6tPLH 11.7tPHL 12.8tPZH 6.7tPZL 6.7tPHZ 7.9tPLZ 8.1UNIT: ns
MAX
ERR
OE
OE
ERR
MAX
MAX
MAX
MAX
MAX
A PARITY MAX
A or B B or A
OE PARITY
LE
A or Bor PARITY
B or RARITY
A or Bor PARITY
454
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
Details ofFour Identical Channels
Not Shown
1
23
13
2
3
5
6
8
916
15
1918
22
21
4
7
20
10
17
14
11
S0
S1
COMP
1A
1B
2A
2B
3A3B
4A
4B5A
5B
6A
6B
1Y
2Y
3Y
4Y
5Y
6Y
OPER = 0
857HEX 2-TO-1 UNIVERSAL MULTIPLEXERS
Select True or Complementary Data Perform AND/NAND (Masking) of A or B Operand Cascadable to Expand Number of Operands Detect Zeros on A or B Operands 3-State Outputs Interface Directly with System Bus
455PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
MAX or MIN ALS AS UNIT
ICCZ MAX 36 135 mAICCL MAX 33 175 mA
Y MAX -2.6 -15 mAOPER = 0 MAX -2.6 -2 mA
Y MAX 24 48 mAOPER = 0 MAX 24 20 mA
PARAMETER
IOL
IOH
FUNCTION TABLEINPUTS OUTPUTS
COMP S1 S0 Y OPER = 0
L L L A H = all A inputs L
L L H B H = all B inputs L
L H L A•B
A•B
Z
L H H L L
H L L H = all A inputs L
H L H
A
B H = all B inputs L
H H L Z
H H H Z Z
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALS AS
tpd S0 or S1 Y 33 13tpd COMP Y 18 13tpd A or B OPER = 0 37 14tpd S0 to S1 OPER = 0 23 18ten 35 12tdis 23 11ten 24 12tdis 21 9ten 20 12tdis 27 9ten 25 12tdis 19 9ten 25 13tdis 20 9UNIT: ns
tpd
tpd
MAX
MAXYinverting
Ynon-inverting
COMP
S0
S1
A or B(COMP = "H")
A or B(COMP = "L")
MAX
MAX
10
COMP OPER = 0
Y
Y
OPER = 0
OPER = 0
S0 to S1
1214
14
MAX
MAX
MAX
MAX
456
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
86110-BIT TRANSCEIVERSWITH 3-STATE OUTPUTS
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ABT LVC3V UNIT
ICC MAX 38 0.01 mAIOH MAX -32 -24 mAIOL MAX 64 24 mA
A data to B busB data to A busIsolation
INPUTSOPERATION
HOEBAOEAB
L
HHH L
L LLatch A and B (A = B)
FUNCTION TABLE
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ABT LVC3V
tPLH 5.2 6.4tPHL 4.9 6.4tPZH 5.9 7tPZL 6.9 7tPHZ 7.5 5.9tPLZ 7.1 5.9UNIT: ns
MAX
MAX
MAXOEAB or OEBA B or A
A or B B or A
OEAB or OEBA B or A
A1 B1
OEBA
OEAB
To Nine Other Channels
1
13
2 23
457
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
A1 B1
OEBA2
OEAB2
To Eight Other Channels
OEAB1
OEBA11
11
13
14
2 23
8639-BIT BUS TRANSCEIVERWITH 3-STATE OUTPUTS
3-State Outputs
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ABT LVC3V UNIT
ICC MAX 38 0.01 mAIOH MAX -32 -24 mAIOL MAX 64 24 mA
FUNCTION TABLE
INPUTS
L
OPERATION
B to AL
Latch A and BOEAB1
X
IsolationXX
X
XX
L
HXHHXX
XA to B
XLL
L
OEAB2L
OEBA1L
OEBA2L
L
X
LL
H
HH
H
H
HH
HH
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ABT LVC3V
tPLH 5.7 6.1tPHL 3.9 6.1tPZH 5.5 7.2tPZL 5.4 7.2tPHZ 6.7 6.3tPLZ 6.9 6.3UNIT: ns
OE A or B MAX
MAXA or B B or A
OE A or B MAX
458
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
A
1D
RC1 22 QA
1412
23
3
B
1D
RC1 21 QB
4
C
1D
RC1 20 QC
5
D
1D
RC1 19 QD
6
E
1D
RC1 18 QE
7
ENP
S1S0
CLK
F
1D
RC1 17 QF
8
G
1D
RC1 16 QG
9
H
1D
RC1 15 QH
10
13RCO
ENT 11
SN74ALS867A Only(asynchronous clear)
8678-BIT SYNCHRONOUS BIDIRECTIONAL COUNTER
Fully Programmable with Synchronous Counting and Loading Asynchronous Clear Ripple-Carry Output for n-Bit Cascading
459PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALS AS UNIT
ICC MAX 45 195 mAIOH MAX -0.4 -2 mAIOL MAX 8 20 mA
FUNCTION TABLE
S1L
HHL
FUNCTION
Count downClear
S0
Count upLoad
L
H H
L
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALS AS
fmax MIN 35 50tw 14 10
10 10tsu 10 4
15 812 10- 10
12 4012 40
th3 -
0 0tPLH 14 22tPHL 14 16tPLH 16 11tPHL 16 15tPLH 14 10tPHL 9 17tPLH - 14tPHL - 17
tPHLS0, S1
(clear mode) Any Q MAX 26 -
tPLH 16 -tPHL 16 -tPHL
UNIT fmax : MHz other : ns
S0 or S1(count up/down)
S0 or S1(clear mode)
S0 and S1 low (clear)S0 high and S1 low (count down)
S0 and S1 high (count up)
S0 high after S1 or S1high after S0
CLK
CLK
ENT
ENP
Data input A-H
ENP or ENTS0 low and S1 high (load)
Data input A-H
RCO
RCO
RCO
RCO
Any Q
RCO
MAX
MAX
MAX
S0 and S1 (clear)
21
MIN
MAX
MAX
16MAX
MIN
MIN
CLK (clock)
460
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
A
1D
RC1 22 QA
1412
23
3
B
1D
RC1 21 QB
4
C
1D
RC1 20 QC
5
D
1D
RC1 19 QD
6
E
1D
RC1 18 QE
7
ENP
S1S0
CLK
F
1D
RC1 17 QF
8
G
1D
RC1 16 QG
9
H
1D
RC1 15 QH
10
13RCO
ENT 11
SN74ALS867A Only(asynchronous clear)
8698-BIT SYNCHRONOUS BIDIRECTIONAL COUNTER
Fully Programmable with Synchronous Counting and Loading Synchronous Clear Ripple-Carry Output for n-Bit Cascading
461PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALS AS UNIT
ICC MAX 45 195 mAIOH MAX -0.4 -2 mAIOL MAX 8 20 mA
FUNCTION TABLE
S1L
HHL
FUNCTION
Count downClear
S0
Count upLoad
L
H H
L
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALS AS
fmax MIN 35 45tw MIN 14 11tsu 10 5
15 913 1113 1113 5013 50
th3 -
0 0tPLH 14 35tPHL 14 18tPLH 16 11tPHL 16 15tPLH 14 15tPHL 9 17tPLH - 19tPHL - 18tPLH 15 -tPHL 15 -tPLH 16 -tPHL 12 -UNIT fmax : MHz other : ns
CLKData input A-H
ENP or ENTS0 low and S1 high (load)
RCO
MAX
RCO MAX
RCO
MIN
Any Q MAX
RCO MAX
Data input A-H
S0 and S1 low (clear)S0 high and S1 low (count down)
S0 and S1 high (count up)
S0 high after S1 or S1high after S0
MAX
MIN
CLK RCO MAX
CLK
ENT
ENP
S1(count up/down)
S0(clear/load)
462
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
REG1
REG2
Decoder
BIN/Y
161234
150
Decoder
BIN/Y
161234
150
16 16
Three Identical Channels Not Shown
2A02A12A22A3
DQB1
1A01A11A21A3
S0
S1
S2
S3
1W
2W
DQA1
RAM 16×1
A
A,D150
A
A
A,D150
A
RAM 16×1
2345
1
23
7
17
6
18
8
19202122
13
870DUAL 16-BY 4-BIT REGISTER FILES
3-State Buffer-Type Outputs Drive Bus Lines Directly Each Register File Has Individual Write-Enable Controls and Address Lines
463PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
FUNCTION TABLE
FILE SELECT
HL
S1S0
H
L 1R to A, 1R to B
HL
H
L
FILE SEL
2R to A, 1R to B1R to A, 2R to B2R to A, 2R to B
HL
H
L A to 1R, 1R to B
HL
H
L A to 2R, 1R to BA to 1R, 2R to BA to 2R, 2R to B
HL
H
L
HL
H
L
HL
H
L
HL
H
L
1R to A, B to 1R
B to 1RA to 2R, B to 1RA to 1R, B to 2R
B to 2R
2R to A, B to 1R1R to A, B to 2R2R to A, B to 2R
LS3S2L A out B A out, B out
I/O SEL
H A in B A in, B outL
HL
H H
A out B A out, B in
A in Bin A in, B
INPUT/OUTPUT
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALS AS
tw MIN 12 12tsu 5 5
15 1512 12
th 0 00 0
12 12ta(A) Any A Any DQ MAX 19 15ta(S) S0 Any DQA 15 13
S1 Any DQB 15 13tdis S2 Any DQA 14 11
S3 Any DQB 14 11ten S2 Any DQA 17 12
S3 Any DQB 17 12tpd W Any DQ 23 19
DA DQB 26 22DQB DQA 26 22
UNIT: ns
MAX
MAX
MAX
MAX
Select before writeData before write
Address before write
MIN
MIN
Select before writeData before write
Address before write
write
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALS AS UNIT
ICC MAX 110 190 mAIOL MAX 24 48 mAIOH MAX -2.6 -15 mA
464
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
RC1
1DD1Q1
RC1
1DD2Q2
RC1
1DD3Q3
RC1
1DD4Q4
OE
LE
CLR
873DUAL 4-BIT D-TYPE LATCHES
3-State Buffer-Type Outputs Drive Bus LinesDirectly
Bus-Structured Pinout Asynchronous Clear
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALS AS UNIT
ICC MAX 31 129 mAIOH MAX -2.6 -15 mAIOL MAX 24 48 mA
FUNCTION TABLE
INPUTS
LL
ENABLELE
H
OUTPUT
HLL
L
XH
CLR
LQ0Z
OE D
L
LXHHH
XX
X LX
HH
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN ALS AS
CLR low 15 5LE high 10 5
tsu 10 2th 7 4.5tPLH 14 9.5tPHL 14 7.5tPLH 22 13tPHL 21 7.5tPHL CLR Q MAX 20 9tPZH 18 6.5tPZL 18 10.5tPHZ 10 7.5tPLZ 15 7.5UNIT: ns
MAX
LE
OE
OE
D
PARAMETER
twMIN
Q MAX
Q MAX
Q MAX
Q
465
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
874DUAL 4-BIT D-TYPE EDGE-TRIGGERD FLIP-FLOPS
3-State Buffer-Type Outputs Drive Bus LinesDirectly
Bus-Structured Pinout Asynchronous Clear
RC1
1DD1Q1
RC1
1DD2Q2
RC1
1DD3Q3
RC1
1DD4Q4
OE
CLK
CLR
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALS AS UNIT
ICC MAX 32 160 mAIOH MAX -2.6 -15 mAIOL MAX 24 48 mA
FUNCTION TABLE
INPUTS
LL
CLK
H
OUTPUTS
HLL
L
XH
CLR
LQ0Z
OE DL
LXHHH
↑↑
XX
X LX
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALS AS
fmax MIN 30 125tw 10 2
16.5 316.5 4
tsu 15 210 4
th MIN 0 1tPLH 14 8.5tPHL 14 10.5tPHL CLR Q MAX 17 9.5tPZH 18 7tPZL 18 10.5tPHZ 10 6tPLZ 12 7.5UNIT fmax : MHz other : ns
CLK
OE
MINPRE or CLR low
CLK "H"CLK "L"
MAX
MAX
MAXOE
Data
PRE or CLR inactive
Q
Q
Q
MIN
466
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
SC1
1DD1Q1
SC1
1DD2Q2
SC1
1DD3Q3
SC1
1DD4Q4
OE
CLK
PRE
876DUAL 4-BIT D-TYPE FLIP-FLOPS
3-State Buffer-Type Outputs Drive Bus Lines Directly Bus-Structured Pinout Asynchronous Clear
467PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALS AS UNIT
ICC MAX 31 160 mAIOH MAX -2.6 -15 mAIOL MAX 24 48 mA
LL
CLK
H LLL
L
XH
PRE
H
Z
OE QDL
LXHHH
XX
X LX
Q0
FUNCTION TABLE(each filip-flop)
INPUTS OUTPUT
↑↑
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN ALS AS
fmax MIN 30 80
PRE "L" 10 4.5CLK "H" 16.5 6.2CLK "L" 16.5 6.2
Data 15 4.5
PRE inactive 10 5th MIN 0 2tPLH 14 8.5tPHL 14 10.5tPHL PRE Q MAX 19 9.5tPZH 18 7tPZL 18 11tPHZ 10 7tPLZ 13 7
Q
PARAMETER
MAX
tw MIN
UNIT fmax : MHz, other : ns
MAX
MAX
MINtsu
CLK
OE
OE
Q
Q
468
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
Q0
ARITHLOGIC
1
2
11
3
10
9
8
7
6
5
4
15
16
17
18
19
20
21
22
23
4MSB =
P0 = Q0
P1 = Q1
P2 = Q2
P3 = Q3
P5 = Q5
P7 = Q7
P6 = Q6
14
13
PLE
P7
P6
P5
P4
P3
P2
P1
P0
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
P > QINP < QIN
L/A
P < QOUT
P > QOUT
C1
P7
P7
P6
P6P5
P5
P4
P4P3
P3P2
P2
P1
P1P0
P0
Q7
Q7Q6
Q6Q5
Q5Q4
Q4Q3
Q3Q2
Q2Q1
Q1Q0
1D
8858-BIT MAGNITUDE COMPARATOR
SN54AS885 Latchable P-Input Ports with Power-Up Clear Choice of Logical or Arithmetic (Two's Complement) Comparison Data and PLE Inputs Utilize pnp Input Transistors to Reduce dc Loading Effects Cascadable to n Bits While Maintaining High Performance
469PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN AS UNIT
ICC MAX 210 mAIOH MAX -2 mAIOL MAX 20 mA
FUNCTION TABLE
INPUTS OUTPUTS
COMPARISONL/A
DATAP0–P7,Q0–Q7
P > QIN P < QIN P > QOUT P < QOUT
Logical H P > Q X X H L
Logical H P < Q X X H
Logical† H P = Q H or L H or L H or L H or L
Arithmetic L P AG Q X X L
Arithmetic L Q AG P X X
L
H
L H
Arithmetic† L P = Q H or L H or L H or L H or L
† In these cases, P > QOUT follows P > QIN and P < QOUT follows P < QIN.AG = arithmetically greater than
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN AS
tsu 2th 4tPLH 13tPHL 13tPLH 8tPHL 8tPLH 17.5tPHL 15UNIT: ns
Any P or Qdata input
P < QOUT,P > QOUT
L / A
MIN
MAX
Data before PLEData after PLE
P < QIN,P > QIN
P < QOUT,P > QOUT
P < QOUT,P > QOUT MAX
MAX
470
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1D
C1
To Seven Other Channels
1
11
219
OERB
LE
1D1Q
9908-BIT D-TYPE TRANSPARENT READ-BACK LATCHES
3-State I/O-Type Read-Back Inputs True Logic Outputs Bus-Structured Pinout
RECOMMENDED OPERATING CONDITIONS
MAX or MIN ALS UNIT
ICC MAX 70 mAQ -2.6 mAD -0.4 mAQ 24 mAD 8 mA
IOL
IOH
PARAMETER
MAX
MAX
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALS
tw MIN 10tsu 10
10th MIN 5tPLH 17tPHL 24tPLH 26tPHL 26ten MAX 21tdis MAX 19UNIT: ns
Data before OERBMIN
LE high
Data before LE
Data after LE
OERB
LE
D Q
Q
D
MAX
MAX
471PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
Logic Diagram
1D
C1
To Eight Other Channels
1
13
2 23
OERB
LE
1D 1Q
14OEQ
11CLR
R
9929-BIT D-TYPE TRANSPARENT
3-State I/O-Type Read-Back Inputs True Logic Outputs Bus-Structured Pinout Designed with Nine Bits for Parity Applications
RECOMMENDED OPERATING CONDITIONS
MAX or MIN ALS UNIT
ICC MAX 80 mAQ -2.6 mAD -0.4 mAQ 24 mAD 8 mA
MAX
MAX
PARAMETER
IOH
IOL
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALS
tw 1010
tsu 1010
th MIN 5tPLH 14tPHL 16tPLH 20tPHL 25tPHL Q 20
D 26ten 21tdis 14ten 18tdis 14UNIT:ns
MAX
MAX
MAX
Q
Q
Q
D
MAX
MAX
MIN
MIN
C "H"CLR "L"
Data befor LE
Data befor OERBData affter LE
OEQ
D
LE
CLR
OERB
472
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1D
C1
To Nine Other Channels
1
13
2 23
OERB
LE
1D 1Q
99410-BIT D-TYPE TRANSPARENT READ-BACK LATCHES
3-State I/O-Type Read-Back Inputs True Logic Outputs Bus-Structured Pinout
473PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
MAX or MIN ALS UNIT
ICC MAX 82 mAQ -2.6 mAD -0.4 mAQ 24 mAD 8 mA
PARAMETER
IOH
IOL MAX
MAX
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALS
tw MIN 10tsu 10
10th MIN 5tPLH 14tPHL 18tPLH 21tPHL 27ten 21tdis 16UNIT:ns
D
C "H"Data befor LE
Data befor OERBData affter LE
Q
LE
OERB
MIN
D
Q
MAX
MAX
MAX
474
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
To Seven Other Channels
15
23
OE
1Q
14T/C
13CLR
10RD
1D
C1
R
9EN
11CLK
11D
9968-BIT D-TYPE EDGE-TRIGGERED READ-BACK LATCHES
3-State I/O-Type Read-Back Inputs True Logic Outputs T/C Determines True or Complementary Data at Q Outputs
475PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
MAX or MIN ALS UNIT
ICC MAX 85 mAQ 24 mAD 8 mAQ -2.6 mAD -0.4 mA
PARAMETER
IOL MAX
IOH MAX
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALS
tw 1014.514.5
tsu 15101510
th 055
tPLH 28tPHL 28tPLH CLR ( T/C = L ) 27tPHL CLR ( T/C = H ) 23tPLH 23tPHL 23tPHL CLR D MAX 30ten*3 16tdis*4 19ten*3 16tdis*4 19ten*3 15tdis*4 10UNIT: ns *1 This setup time ensures that EN will not false clock the date register.
*2 This hold time ensures that there will be no conflict on the input date bus.*3 = t PZH or t PZL
*4 = t PHZ or t PLZ
Q
EN
DRD
T / C
D
RD high after CLK *2
CLK( T/C = H or L )
Data after CLK
CLK high before EN *1
CLR high (inactive) before CLK
EN low after CLK
MIN
MIN
MIN
CLR lowCLK lowCLK high
Data before CLK
EN low before CLK
MAX
MAXOE
MAX
MAX
MAX
MAX
Q
Q
Q
476
Logic Diagram
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1000QUAD 2-INPUT NANDBUFFERS/DRIVERS
Buffer Version of SN74ALS00A Driver Version of SN74AS00 High Capacitive-Drive Capability
1004HEX INVERTING DRIVERS
Driver Version of SN74ALS04B and SN74AS04 High Capacitive-Drive Capability
1Y3
11A
21B
2Y6
42A
52B
3Y8
93A
103B
4Y11
124A
134B
6A 6Y
5A 5Y
4A 4Y
3A 3Y
2A 2Y
1Y1A
3
5
9
11
13
1 2
4
6
8
10
12
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALS AS UNIT
ICC MAX 7.8 19 mAIOH MAX -2.6 -48 mAIOL MAX 24 48 mA
FUNCTION TABLE
INPUTS
HL
BAHX
OUTPUTY
HX L
L
H
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALS AS
tPLH 8 4tPHL 7 4UNIT: ns
A or B Y MAX
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALS AS UNIT
ICC MAX 12 27 mAIOH MAX -15 -48 mAIOL MAX 24 48 mA
FUNCTION TABLE
OUTPUTY
HL
INPUTAHL
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALS AS
tPLH 7 4tPHL 6 4UNIT: ns
A or B Y MAX
477
Logic Diagram
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
1005HEX INVERTING BUFFER GATESWITH OPEN-COLLECTOR OUTPUTS
Buffer Version of SN74ALS05A
1008QUADRUPLE 2-INPUT POSITIVE-AND BUFFERS/DRIVERS
Buffer Version of SN74ALS08 Driver Version of SN74AS08
6A 6Y
5A 5Y
4A 4Y
3A 3Y
2A 2Y
1Y1A1
3
5
9
11
13
2
4
6
8
10
12
4A
4B4Y
3A
3B3Y
2A
2B2Y
1Y1B
1A1
2
4
5
9
10
12
13
3
6
8
11
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALS UNIT
ICC MAX 12 mAVOH MAX 5.5 VIOL MAX 24 mA
FUNCTION TABLE
OUTPUTY
HL
INPUTAHL
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALS
tPLH 30tPHL 10UNIT: ns
A Y MAX
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALS AS UNIT
ICC MAX 9.3 22 mAIOH MAX -2.6 -48 mAIOL MAX 24 48 mA
FUNCTION TABLE
INPUTS
HL
BAHX
OUTPUTYH
X L LL
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALS AS
tPLH 9 6tPHL 9 6UNIT: ns
A or B Y MAX
478
Logic Diagram
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1032QUAD 2-INPUT OR BUFFERS/DRIVERS
Y = A + B Driver Version of SN74AS32 High Capacitive-Drive Capability
1A
1B
2A
2B
3A
3B
4A
4B
1Y
2Y
3Y
4Y
1
2
4
5
9
10
12
13
3
6
8
11
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALS AS UNIT
ICC MAX 10.6 24 mAIOH MAX -2.6 -48 mAIOL MAX 24 48 mA
FUNCTION TABLE(each gate)
INPUTS OUTPUT
H
Y
H
A
HXL
X
L L
B
H
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALS AS
tPLH A or B Y MAX 9 6.3tPHL or B Y MAX 12 6.3UNIT:ns
1034HEX DRIVERS
SN74AS1034A Offer High Capacitive-DriveCapability
Noninverting Drivers
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALS AS UNIT
ICC MAX 14 35 mAIOH MAX -15 -48 mAIOL MAX 24 48 mA
FUNCTION TABLE
OUTPUTYHL
INPUTAHL
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALS AS
tPLH 8 6tPHL 8 6UNIT: ns
A Y MAX
6A 6Y
5A 5Y
4A 4Y
3A 3Y
2A 2Y
1Y1A
3
5
9
11
13
1 2
4
6
8
10
12
479
Logic Diagram
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
1035HEX BUFFERS WITHOPEN-COLLECTOR OUTPUTS
Noninverting Buffers with Open-Collector Outputs
6A 6Y
5A 5Y
4A 4Y
3A 3Y
2A 2Y
1Y1A
3
5
9
11
13
1 2
4
6
8
10
12
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALS UNIT
ICC MAX 14 mAVOH MAX 5.5 VIOL MAX 24 mA
FUNCTION TABLE
OUTPUTYHL
INPUTAHL
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALS
tPLH 30tPHL 12UNIT: ns
A Y MAX
1240OCTAL BUFFERS/LINE DRIVERS/LINE RECEIVERS
Low-Power Versions of SN74ALS240A 3-State Outputs Drive Bus Lines or Buffer Memory
Address Registers 3-State Outputs Drive Bus Lines or Buffer Memory
Address Registers
1
2
4
6
8
19
11
13
15
17 3
5
7
9
12
14
16
181A1
1A2
1A3
1A4
1Y1
2A1
2A2
2A3
2A4
2Y1
1Y2
1Y3
1Y4
2Y2
2Y3
2Y4
1OE
2OE
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALS UNIT
ICCZ MAX 13 mAICCL MAX 14 mAIOH MAX -15 mAIOL MAX 16 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALS
tPLH MAX 13tPHL 13tPZH MAX 20tPZL 22tPHZ MAX 10tPLZ 13UNIT: ns
OE Y
A
OE
Y
Y
480
Logic Diagram
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1244OCTAL BUFFERS/LINEDRIVERS/LINE RECEIVERS
3-State Outputs Drive Bus Lines or Buffer MemoryAddress Registers
pnp Inputs Reduce dc Loading Low-Power Versions of SN74ALS244 Series
1
2
4
6
8
19
11
13
15
17 3
5
7
9
12
14
16
181A1
1A2
1A3
1A4
1Y1
2A1
2A2
2A3
2A4
2Y1
1Y2
1Y3
1Y4
2Y2
2Y3
2Y4
2OE
1OE
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALS UNIT
ICCZ MAX 20 mAICCL MAX 17 mAIOH MAX -15 mAIOL MAX 16 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALS
tPLH 14tPHL 14tPZH 22tPZL 22tPHZ 13tPLZ 16UNIT: ns
MAX
MAX
MAX
Y
Y
A
OE
OE
Y
1245OCTAL BUS TRANSCEIVERS
Low-Power Versions of 4ALS245 SeriesDIR
A1 B1
19
2 18
To Seven Other Transceivers
1
OE
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALS UNIT
ICCZ MAX 36 mAICCL MAX 33 mAIOH MAX -15 mAIOL MAX 16 mA
FUNCTION TABLE
CONTROL INPUTS
HL
DIR
HX
OPERATION
A data to B busL B data to A bus
Isolation
OEL
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALS
tPLH 13tPHL 13tPZH 25tPZL 25tPHZ 12tPLZ 18UNIT: ns
MAX
MAX
MAX
OE
OE
A or B
A or B
A or B B or A
481
Logic Diagram
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
1640OCTAL BUS TRANSCEIVERS
Lower-Power Versions of SN74ALS640B Inverting Logic 3-State Outputs
A1 B1
OE
DIR
To Seven Other Transceivers
19
1
2 18
FUNCTION TABLE
CONTROL INPUTS
HL
DIR
HX
OPERATION
L
Isolation
OEL
A data to B busB data to A bus
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALS UNIT
ICC MAX 32 mAIOH MAX -15 mAIOL MAX 16 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALS
tPLH 15tPHL 10tPZH 20tPZL 22tPHZ 10tPLZ 13UNIT: ns
B or A
A or B
A or B
A or B
OE
OE
MAX
MAX
MAX
1645OCTAL BUS TRANSCEIVERS
Lower-Power Versions of SN74ALS645A 3-State Outputs
A1 B1
OE
DIR
To Seven Other Transceivers
19
1
2 18
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALS UNIT
ICC MAX 38 mAIOH MAX -15 mAIOL MAX 16 mA
FUNCTION TABLE
CONTROL INPUTS
HL
DIR
HX
OPERATION
A data to B busL B data to A bus
Isolation
OEL
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALS
tPLH 13tPHL 13tPZH 25tPZL 25tPHZ 12tPLZ 18UNIT: ns
MAX
A or B B or A
A or B
A or B
OE
OE
MAX
MAX
482
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1
2 181Y1
1OE
1A1
4 161Y21A2
6 141Y31A3
8 121Y41A4
19
11 92Y1
2OE
2A1
13 72Y22A2
15 52Y32A3
17 32Y42A4
2240OCTAL BUFFERS AND LINE DRIVERS / MOS DRIVERS WITH 3-STATE OUTPUTS
I/O Ports Have 25-Ω Series Resistors, So No External Resistors Are Required (SN74ALS2240, SN74ABT2240A) Output Ports Have Equivalent 33-Ω Series Resistors, So No External Resistors Are Required (SN74BCT2240)
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALS BCT ABT UNIT
ICCZ MAX 20 8 0.25 mAICCL MAX 23 76 30 mAIOH MAX -15 -12 -32 mAIOL MAX 15 12 12 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALS BCT ABT
tPLH 10 5.7 4.8tPHL 10 4.4 5.4tPZH 17 9.3 5.2tPZL 20 12.4 6.8tPHZ 10 8.7 6.4tPLZ 15 10.6 6.2UNIT: ns
A Y MAX
OE Y MAX
Y MAXOE
483PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
Logic Diagram
2241OCTAL BUFFERS AND LINE DRIVERS / MOS DRIVERS WITH 3-STATE OUTPUTS
Output Ports Have Equivalent 25-Ω Series Resistors, So No External Resistors Are Required (SN74ABT2241A) Output Ports Have Equivalent 33-Ω Series Resistors, So No External Resistors Are Required (SN74BCT2241)
1
2 181Y1
1OE
1A1
4 161Y21A2
6 141Y31A3
8 121Y41A4
19
11 92Y1
2OE
2A1
13 72Y22A2
15 52Y32A3
17 32Y42A4
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN SN74BCT ABT UNIT
ICCZ MAX 9 0.25 mAICCL MAX 76 30 mAIOH MAX -12 -32 mAIOL MAX 12 12 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN SN74BCT ABT
tPLH 4.9 4.7tPHL 6.9 5.6tPZH 8.9 5.8tPZL 10.3 8.4tPHZ 8.7 6.6tPLZ 11.3 6.4tPZH 8.9 5.8tPZL 10.3 8.4tPHZ 8.7 6.6tPLZ 11.3 6.4UNIT: ns
2OE
A
1OE
1OE
2OE
MAX
Y
Y
Y
Y
Y
MAX
MAX
MAX
MAX
484
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1
2 181Y1
1OE
1A1
4 161Y21A2
6 141Y31A3
8 121Y41A4
19
11 92Y1
2OE
2A1
13 72Y22A2
15 52Y32A3
17 32Y42A4
2244OCTAL BUFFERS AND LINE DRIVERS / MOS DRIVERS WITH 3-STATE OUTPUTS
Output Ports Have Equivalent 25-Ω Series Resistors, So No External Resistors Are Required (SN74ABT2244A) Output Ports Have Equivalent 33-Ω Series Resistors, So No External Resistors Are Required (SN74BCT2244) Output Ports Have Equivalent 26-Ω Series Resistors, So No External Resistors Are Required (SN74LVC2244A)
FUNCTION TABLE
INPUTS
HL
A
H
X
OUTPUTY
HL L
OE
L
Z
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALS SN74BCT ABT LVC
3V UNIT
ICCZ MAX 23 10 0.25 0.01 mAICCL MAX 22 77 30 0.01 mAIOH MAX -15 -12 -32 -12 mAIOL MAX 15 12 12 12 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALS SN74BCT ABT LVC
3V
tPLH 16 4.9 4.7 5.5tPHL 17 6.7 5.6 5.5tPZH 17 8.7 5.5 7.1tPZL 14 10.4 8.3 7.1tPHZ 9 7.8 6.6 6.8tPLZ 9 9.8 5.8 6.8UNIT: ns
A Y MAX
OE Y MAX
Y MAXOE
485
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
2245OCTAL TRANSCEIVER AND LINE/MOS DRIVERS WITH 3-STATE OUTPUTS
B Port Has Equivalent 33-Ω Series Resistors, SoNo External Resistors Are Required(SN74BCT2245)
B-Port Outputs Have Equivalent 25-Ω SeriesResistors, So No External Resistors Are Required(SN74ABT2245)
Outputs Have Equivalent 25-Ω Series Resistors, SoNo External Resistors Are Required(SN74ABTR2245)
All Outputs Have Equivalent 26-Ω Series Resistors,So No External Resistors Are Required(SN74LVCR2245)
B-Port Outputs Have Equivalent 22-Ω SeriesResistors, So No External Resistors Are Required(SN74LVTH2245)
DIR
OE
A1
B1
To Seven Other Channels
1
2
19
18
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN SN74BCT ABT ABTR LVCR
3VLVTH
3V UNIT
ICCZ MAX 15 0.25 0.25 0.01 0.19 mAICCL MAX 100 32 32 0.01 5 mAIOH (A port) MAX -3 -32 -12 -12 -32 mAIOH (B port) MAX -12 -12 -12 -12 -12 mAIOL (A port) MAX 24 64 12 12 64 mAIOL (B port) MAX 12 12 12 12 12 mA
FUNCTION TABLE
INPUTS
HL
DIR
HX
OPERATION
Isolation
L B data to A busA data to B bus
LOE
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN SN74BCT ABT ABTR LVCR
3VLVTH
3V
tPLH 5.8 3.8 3.8 6.3 4.4tPHL 7.8 4.5 4.5 6.3 4.4tPLH 7 3.6 3.8 6.3 3.5tPHL 7.7 4 4.5 6.3 3.5tPZH 9.9 6.1 6.1 8.2 6.2tPZL 12.2 6.3 6.3 8.2 6.2tPHZ 8.2 5.3 5.3 7.8 5.9tPLZ 9.2 4.8 4.8 7.8 5.4tPZH 11.1 5.5 6.1 8.2 5.5tPZL 11.4 5.7 6.3 8.2 5.5tPHZ 9.4 5.6 5.3 7.8 5.9tPLZ 7.6 4.5 4.8 7.8 5UNIT: ns
OE
OE
OE
OE
A MAX
A MAX
B MAX
B MAX
A B MAX
A MAXB
486
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
OE
LE
1D1Q
1
11
32
To Seven Other Channels
C1
1D
237325-Ω OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
3-State True Outputs with 25-Ω Sink Resistors Full Parallel Access for Loading Buffered Control Inputs
487PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN F UNIT
ICC MAX 66 mAIOH MAX -3 mAIOL MAX 12 mA
FUNCTION TABLE(each latch)
INPUTS
H
LLL
LE D
XL
HH
OUTPUTQ
X
HLX
ZQ0
HL
OE
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN F
tw MIN 6tsu MIN 2th MIN 6tPLH 9tPHL 7tPLH 13tPHL 8tPZH 12tPZL 9.5tPHZ 7.5tPLZ 6UNIT:ns
OE
LE highData before LEData after LE
D
OE
MAX
MAX
MAX
MAX
Q
Q
Q
Q
LE
488
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1
18
17
16
15
14
13
12
11
20
19
2
3
5
7
8
9
4
6
VS
1Y0
1Y1
1Y2
1Y3
2Y0
2Y1
2Y2
2Y3
VCC
Vbat
SD
1A
1B
1G
2G
G
2A
2B
VCOMP
2414MEMORY DECODER WITH ON-CHIP VCC MONITOR
Built-In Supply-Voltage Monitor for VCC
Separate Enable Inputs for Easy Cascading
489PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN SN74BCT UNIT
ICC MAX 3 mAIOH MAX -0.4 mAIbat (Output low) MAX 3 mAIOL MAX 8 mA
FUNCTION TABLE
INPUTS
HHX
OUTPUTS
X
L H
XL
SELECT
H
X
LH
X
L
H
L
CONTROL1B 1A 1Y0
X
LLLLLLL
X
H
X
HH
H H
LL
X X
X X1GG SD
HH
HHH
H
L
1Y1
HH
HH
H
L
1Y2
HH
H
H
H
L
1Y3
HH
HH
H H H
INPUTS
HHX
OUTPUTS
X
H
XL
SELECT
H
X
LH
X
L
H
L
CONTROL2B 2A 2Y0
X
LLLL
X
H
X
HH
H H
LL
X X
X X2GG SD
HH
HHH
H
L
2Y1
HH
HH
H
L
2Y2
HH
H
H
H
L
2Y3
HH
HH
H H H
HHHH
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN SN74BCT
tPLH 12tPHL 12tPLH 10tPHL 11tPLH 12tPHL 12tPLH 250tPHL 250tPLH 250tPHL 250UNIT: ns
VS MAX
SD
VCC
VCC
Any Y MAX
Any Y MAX
A or B Any Y MAX
Any Y MAXAny G
490
Logic Diagram
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
2541OCTAL LINE DRIVERS/MOS DRIVERSWITH 3-STATE OUTPUTS
Outputs Have 25-Ω Series Resistor So No ExternalResistors Are Required
282710-BIT BUS/MOS MEMORY DRIVERSWITH 3-STATE OUTPUTS
Output Ports Have Equivalent 25-Ω SeriesResistors, So No External Resistors Are Required(SN74ABT2827)
Output Ports Have Equivalent 25-Ω Resistors; NoExternal Resistors Are Required (SN74BCT2827C)
A2
A3
A4
3
4
5
Y2
Y3
Y4
17
16
15
A5
A6
A7
A8
6
7
8
9
Y5
Y6
Y7
Y8
14
13
12
11
A1 2 Y118
19
1
OE2
OE1
All output resistors are 25 Ω.
13
2
1
23
OE1
OE2
A1 Y1
To Nine Other Channels
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALS UNIT
ICCZ MAX 22 mAICCL MAX 25 mAIOH MAX -0.4 mAIOL MAX 12 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALS
tPLH 15tPHL 12tPZH 15tPZL 20tPHZ 10tPLZ 12UNIT: ns
A Y MAX
Y MAX
OE
OE
Y MAX
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN SN74BCT ABT UNIT
ICCZ MAX 6 0.25 mAICCL MAX 40 40 mAIOH MAX -1 -12 mAIOL MAX 12 12 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN SN74BCT ABT
tPLH 6 5.5tPHL 7.8 5.1tPZH 10.7 6.7tPZL 12.9 7.8tPHZ 13 7.2tPLZ 10 7.5UNIT: ns
A
OE
OE
MAX
MAX
MAX
Y
Y
Y
491
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
282810-BIT BUS/MOS MEMORY DRIVERSWITH 3-STATE INVERTING OUTPUTS
Output Ports Have Equivalent 33-Ω SeriesResistors, So No External Resistors Are Required(SN74BCT2828)
Y1
To Nine Other Channels
OE1
OE2
A12 23
13
1
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN SN74BCT UNIT
ICCZ MAX 6 mAICCL MAX 40 mAIOH MAX -1 mAIOL MAX 12 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN SN74BCT
tPLH 6.6tPHL 5tPZH 9tPZL 11.5tPHZ 10.8tPLZ 8.7UNIT: ns
OE Y MAX
A Y MAX
OE Y MAX
492
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
To Seven Other Channels
B1A1
OEBA
CLKBA
CLKENBA
OEAB
CLKAB
CLKENAB
8
C1
1D
C1
1D
11
10
9
13
14
15
16
2952OCTAL BUS TRANSCEIVERS AND REGISTERS
Two 8-Bit Back-to-Back Registers Store Data Flowing in Both Directions Noninverting Outputs 3-State Outputs
493PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
MAX or MIN SN74BCT ABT LVC
3VLVT3V UNIT
ICC MAX 55 35 0.01 5 mAA -3 -32 -24 -32 mAB -15 -32 -24 -32 mAA 24 64 24 64 mAB 64 64 24 64 mA
PARAMETER
MAXIOH
IOL MAX
X
FUNCTION TABLE†
INPUTS
CLKABOUTPUT
B0HA
LL
X
CLKENAB
X X
BOEABL
LLH
H
L↑↑
LHZ
X
† A-to-B data flow is shown; B-to-A data flow is similar but usesCLKENBA, CLKBA, and OEBA.‡ Level of B before the indicated steady-state input conditions wereestablished
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN SN74BCT ABT LVC
3VLVT3V
fmax MIN 125 150 150 150tw 4 3.3 3.3 3.3
4 3.3 3.3 3.3tsu 2.5 2.5 1.3 1.5
2.5 2.5 1.3 1.52 3 1.1 1.52 3 1.1 1.9
th 1.5 1.5 1.1 12.5 2 1.1 1.2
tPLH CLKBA 9 5.9 8.2 4.6tPHL CLKAB 10.5 6.3 8.2 4.6tPZH OEBA 8.2 5.6 7.8 4.6tPZL OEAB 12.9 6.6 7.8 4.6tPHZ OEBA 8.4 6.4 7.8 5.4tPLZ OEAB 7 6.2 7.8 5.1UNIT fmax : MHz other : ns
MIN
MAX
CLKENAB or CLKENBA
A or B
A,B
MIN
A or B HighA or B Low
CLKENAB or CLKENBA High
MINCLK "H"CLK "L"
MAX
MAX
CLKENAB or CLKENBA Low
A,B
A,B
494
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
C1
C1
1D
1D
To Seven Other Channels
B1A1816
OEBA
CLKBA
CLKENBA
OEAB
CLKAB
CLKENAB11
10
9
13
14
15
2953OCTAL BUS TRANSCEIVERS AND REGISTERS
Two 8-Bit, Back-to-Back Registers Store Data Flowing in Both Directions Inverting Outputs 3-State Outputs
495PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
MAX or MIN SN74BCT UNIT
ICC MAX 55 mAA -3 mAB -15 mAA 24 mAB 64 mA
PARAMETER
IOH MAX
IOL MAX
X
FUNCTION TABLE†INPUTS
CLKABOUTPUT
A0HA
LL
X
OEAB
X X
BOEABL
LLH
H
L HLZ
† A-to-B data flow is shown; B-to-A data flow is similar but usesCEBA, CLKBA, and OEBA.‡ Level of B before the indicated steady-state input conditions wereestablished
↑
↑
↑
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN SN74BCT
fmax MIN 110tw 4.5
4.5tsu 2.5
2.522
th 1.52
tPLH CLKBA 9.5tPHL CLKAB 10.2tPZH OEBA 8.8tPZL OEAB 14tPHZ OEBA 9.1tPLZ OEAB 7.6UNIT fmax : MHz other : ns
A,B
MIN
MIN
MINA or B Low
CLKENAB or CLKENBA HighCLKENAB or CLKENBA Low
CLKENAB or CLKENBA
A or B
CLK "H"CLK "L"
A or B High
A,B
A,B
MAX
MAX
MAX
496
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
3245OCTAL BUS TRANSCEIVER WITHADJUSTABLE OUTPUT VOLTAGEAND 3-STATE OUTPUTS
DIR
OE
A1
B1
To Seven Other Channels
2
3
22
21
RECOMMENDED OPERATING CONDITIONS
MAX or MIN VCCA(V) VCCB(V) LVCC UNIT
OPEN 0.05 mA
3.6 0.05 mA
5.5 0.05 mA
3.6 0.05 mA
5.5 0.08 mA
2.7 -12 mA
3.3 -24 mA
2.7 3.3 -12 mA
3.3 3 -24 mA
2.7 12 mA
3.3 24 mA
2.7 3.3 12 mA
3.3 3 24 mA
3MAX
3
IOHB
IOHA
IOLA
IOLB
3.6
3.6
MAX
MAX
PARAMETER
MAX
MAX
B to A
A to B
MAX
ICCA
ICCB
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MINLVCC
VCCA = 2.5VVCCB = 3.3V
LVCCVCCA = 3.6VVCCB = 5V
tPLH 9.4 6tPHL 9.1 5.3tPLH 11.2 5.8tPHL 9.9 7tPZL 14.5 9.2tPZH 12.9 9.5tPZL 13 8.1tPZH 12.8 8.4tPLZ 7.1 7tPHZ 6.9 7.8tPLZ 8.8 7.3tPHZ 8.9 7UNIT: ns
MAX
MAX
MAX
MAX
MAX
MAX
OE A
BOE
OE
OE
A
B
A
B
B
A
FUNCTION TABLE
INPUTS
L
DIR
H
OPERATION
B data to A bus
IsolationX
OEL L
HA data to B bus
497
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
4002DUAL 4-INPUT POSITIVE-NOR GATES
Y = A + B + C + D
nAnB
nY
nCnD
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN SN74HC
CD74HC UNIT
ICC MAX 0.02 0.04 mAIOH MAX -4 -4 mAIOL MAX 4 4 mA
INPUTS
L
BA
XX
OUTPUTY
H
X
L
L
C
XH
LH
LLL
D
X
X
L
XX HX
HX
XX
FUNCTION TABLE
NOTES:H = High Voltage LevelL = Low Voltage LevelX = Irrelevant
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN SN74HC
CD74HC
tPLH MAX 28 30tPHL MAX 28 30UNIT:ns
YA, B, C, D
498
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
5(13)
Q0
D Q
CP QR
D Q
CP QR
4(12)
Q1
D Q
CP QR
3(11)
Q2
D Q
CP QR
2(10)
Q3
DATA
MR
6(14)
7(15)
CP
9(1)
4015DUAL 4-STAGE STATIC SHIFT REGISTER
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN CD74HC UNIT
ICC MAX 0.16 mAIOH MAX -4 mAIOL MAX 4 mA
FUNCTION TABLEINPUTS
CP
X
↑
↑
↓
D
XX
lh
R
HL
LL
OUTPUT
L
LH
q’0L
q’1
q’0q’0
Q1
Lq’2
q’1q’1
Q2
Lq’3
q’2q’2
Q3Q0
NOTES:H = High Voltage Levelh = High Voltage Level One Set-up Time Prior to the Low to High
Clock TransitionL = Low Voltage Levell = Low Voltage Level One Set-up Time Prior to the Low to High
Clock TransitionX = Don’t Care.↑ = Low to High Clock Transition↓ = High to Low Clock Transition
q’n = Lower case letters indicate the state of the referenced output one set-up time prior to the Low to High clock transition.
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN CD74HC
fmax MIN 45tW 24
45tSUL MIN 18tSUH MIN 18tH MIN 0tPLH 54tPHL 54tPLH 83tPHL 83tPLH 98tPHL 98
UNIT fmax : MHz other : ns
MAX
MAX
MR
MR
Qn(Clock High)
Qn(Clock Low)
MIN
Data-In to CP
Clock Qn MAX
ClockMR
Data-In to CP
499PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
Logic Diagram
4016QUAD BILATERAL SWITCH
VCC
GND
nZ
nY
nE
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN CD74HC UNIT
ICC MAX 0.32 mA
NOTES:H = High Level VoltageL = Low Level Voltage
FUNCTION TABLEINPUT
nE
HL
SWITCH
ONOFF
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN CD74HC
tPLH 18tPHL 18tPZH 57tPZL 57tPHZ 44tPLZ 44UNIT:ns
Switch In Switch Out MAX
MAX
MAX
En Z
En Z
500
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
CLR(15)
Y0(3)
Y1(2)
Y2(4)
Y3(7)
Y4(10)
Y5(1)
Y6(5)
Y7(6)
Y8(9)
Y9(11)
CO(12)
CLK(14)
CLKEN(13)
C11D
R
C11D
R
C11D
R
C11D
R
C11D
R
4017DECADE COUNTERS/DRIVERS
501PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
INPUTS
H
LCLK
OUTPUTSTATE†
X
No ChangeCLKEN
XX
H
LX
X
X H
LCLR
No Change“0” = H, “1”-“9” = LIncrements Counter
Increments Counter
No ChangeNo Change
L
LLLL
FUNCTION TABLE
↑↓
↑↓
NOTES:H = High LevelL = Low Level↑ = High to Low Transition↓ = Low to High TransitionX = Don’t Care† If n < 5 TC = H, Otherwise = L
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN SN74HC
CD74HC UNIT
ICC MAX 0.08 0.16 mAIOH MAX -4 -4 mAIOL MAX 4 4 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN SN74HC
CD74HC
fmax MIN 25 2020 2420 2413 2213 -
th MIN 5 0tPLH 58 69tPHL 58 69tPLH 63 75tPHL 63 75tPLH 58 69tPHL 58 69tPLH - 69tPHL 58 69UNIT fmax : MHz, other : ns
CLR(MR)
CLKEN to CLK (CE to CP )
CLK Inactive
tw
tsu
CLR(MR)
CLKEN(CE)
CLK(CP)
CLK (CP)CLR (MR) H
MAX
MAX
MAX
Y, C0(0 to 9, TC)
Y, C0(0 to 9, TC)
Y(0 to 9)
C0(TC)
CLKEN to CLK (CE to CP )
MIN
MIN
MAX
502
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
R
T
R
T
R
T
R
T
R
T
R
T
R
T
R
T
R
T
R
T
R
T
R
T
R
T
R
T
9 7 5 4
6 13 12 14 15 1 2 3
11
10
CLR
CLK
QA QD QE QF
QI QL QM QNQG QH QJ QK
4020
14-STAGE BINARY COUNTERS
Same Pinouts as CMOS4020 VCC: 2V to 6V
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN SN74HC
CD74HC
CD74HCT UNIT
ICC MAX 0.08 0.16 0.16 mAIOH MAX -4 -4 -4 mAIOL MAX 4 4 4 mA
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN SN74HC
CD74HC
CD74HCT
fmax MIN 22 20 16CLK 23 24 30
CLR high 18 24 30tsu CLK CLR inactive before CLK MIN 15 - -tPLH 38 42 60tPHL 38 42 60tPHL CLR Any MAX 35 51 60UNIT fmax : MHz other : ns
MAX
MINtw
PARAMETER
CLK QA
FUNCTION TABLECLR OUTPUTCLK
→ No ChangeAdvance to Next StateAll Outputs Are Low
LH
L
→
X
NOTE: H = High Voltage Level, L = Low Voltage Level,X = Don’t Care, =↑ Transition from Low to High Level,↓= Transition from High to Low.
503PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
Logic Diagram
12
Q1’
CP Q
CP Q
1
R
CP Q
CP Q
2
R
11
Q2
CP Q
CP Q
3
R
9
Q3
CP Q
CP Q
4
R
6
Q4
CP Q
CP Q
5
R
5
Q5
CP Q
CP Q
6
R
4
Q6
CP Q
CP Q
7
R
3
Q7
CP
MR
2
1
GND
VCC
7
14
Q1
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN SN74HC
CD74HC
CD74HCT UNIT
ICC MAX 0.08 0.16 0.16 mAIOH MAX -4 -4 -4 mAIOL MAX 4 4 4 mA
CLR OUTPUT STATECLKNo Change
Advance to Next State
All outputs Are Low
L
H
L
X
FUNCTION TABLE
↑
↓
NOTES:H = High Voltage Level, L = Low Voltage Level, X = Don’t Care, ↑ = Transition form Low to High Level, ↓ = Transition High to Low.
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN SN74HC
CD74HC
CD74HCT
fmax MIN 22 20 16tw 23 24 30
20 24 30tsu MIN 20 - -tPLH 30 42 60tPHL 30 42 60tPLH - 51 60tPHL 33 51 60UNIT fmax : MHz, other : ns
MINCLK (CP)
CLR (MR) HCLR iow before CLK
CLR (MR) any Q
MAX
MAX
CLK(CP)
QA(Q1)
40247-STAGE BINARY COUNTERS
504
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
R
T
R
T
R
T
R
T
R
T
R
T
R
T
R
T
R
T
R
T
R
T
R
T
9 5 3
2 4 13 12 14 15 1
11
10
CLR
CLK
QA QD QE
QH QK QLQF QG QI QJ
7
QB
6
QC
404012-STAGE BINARY COUNTERS
Same Pinouts as CMOS4040 VCC: 2V to 6V
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN SN74HC
CD74HC
CD74HCT
LV3V
LV5V UNIT
ICC MAX 0.08 0.16 0.16 - 0.02 mAIOH MAX -4 -4 -4 -6 -12 mAIOL MAX 4 4 4 6 12 mA
FUNCTION TABLECLR OUTPUTCLK
No Change
Advance to Next State
All Outputs Are Low
L
H
L
X
NOTE: H = High Voltage Level, L = Low Voltage Level,X = Don’t Care, ↑ = Transition from Low to High Level, ↓ = Transition from High to Low.
↑
↓
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN SN74HC
CD74HC
CD74HCT
LV3V
LV5V
fmax MIN 22 20 16 50 80CLK 23 24 30 5 5
CLR high 18 24 30 5 5tsu CLK CLR inactive before CLK MIN 15 - - 5 5tPLH 38 42 60 17.5 10.5tPHL 38 42 60 17.5 10.5tPHL CLR Any MAX 35 51 60 18.5 12UNIT fmax : MHz other : ns
tw
PARAMETER
MIN
CLK QA MAX
505PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
Logic Diagram
DEMOUT
R2
12
R1
R5
11
10
C1
R3
C2
PC2OUT13
p
n
GND
VCC
PCPOUT
1
15
2
PC3OUT
PC1OUT
DOWN
RD
Q
Q
D
CP
RD
Q
Q
D
CP
UPVC
C
VCC
RD
Q
Q
SD
INH
5 9
VCOIN
VCO
- +
VC
OO
UT COMPIN
- +
SIGINC1BC1A
VREFR2
R1
6 7 4 3 14
-
+
4046PHASE-LOCKED-LOOP WITH VCO
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN CD74HC
CD74HCT UNIT
ICC MAX 0.16 0.16 mAIOH MAX -4 -4 mAIOL MAX 4 4 mA
Pin Descriptions
PIN NUMBER SYMBOL NAME AND FUNCTION
1 PCPOUT Phase Comparator Pulse Output
2 PC1OUT Phase Comparator 1 Output
3 COMPIN Comparator Input
4 VCOOUT VCO Output
5 INH Inhibit Input
6 1A Capacitor C1 Connection A
7
C
C1B Capacitor C1 Connection B
8 GND Ground (0V)
9 VCOIN VCO Input
10 DEMOUT Demodulator Output
11 R1 Resistor R1 Connection
12 R2 Resistor R2 Connection
13 PC2OUT Phase Comparator 2 Output
14 SIGIN Signal Input
15 PC3OUT Phase Comparator 3 Output
16 VCC Positive Supply Voltage
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN CD74HC
CD74HCT
tPLH SIGIN 60 68tPHL COMPIN 60 68tPLH SIGIN 90 102tPHL COMPIN 90 102tPLH SIGIN 74 87tPHL COMPIN 74 87tTLH 22 22tTHL 22 22tPZH SIGIN 80 90tPZL COMPIN 80 90tPLZ SIGIN 95 102tPHZ COMPIN 95 102UNIT:ns
MAXPCIOUT
MAX
PC2OUT
PC2OUT
MAX
MAX
PCPOUT
PC3OUT
A Y MAX
MAX
506
Logic Diagram
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
4050HEX NON-INVERTING BUFFERS YA
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN CD74HC UNIT
ICC MAX 0.04 mAIOH MAX -4 mAIOL MAX 4 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN CD74HC
tPLH 26tPHL 26UNIT:ns
MAXnYnA
4049HEX INVERTING BUFFERS A Y
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN CD74HC UNIT
ICC MAX 0.04 mAIOH MAX -4 mAIOL MAX 4 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN CD74HC
tPLH 26tPHL 26UNIT:ns
nA nY MAX
507
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
40518-CHANNEL ANALOG MULTIPLEXERS / DEMULTIPLEXERS
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
COM
INH
C
B
A11
10
9
6
3
13
14
15
12
1
5
2
4
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN CD74HC
CD74HCT
LV3V
LV5V UNIT
ICC MAX 0.16 0.16 - 0.02 mA
FUNCTION TABLE
INPUTSAB
L
L
ONCHANNELY0
Y2H
INH
H
LL
X
Y3
LC
X
L
HLHLH
LY4
L
X
LLLL
Y5Y6Y7None
LL
HH
LL
LL
HH
HH
HH
Y1
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN CD74HC
CD74HCT
LV3V
LV5V
tPLH 18 18 12 8tPHL 18 18 12 8tPZH 68 83 25 18tPZL 68 83 25 18tPHZ 68 68 25 18tPLZ 68 68 25 18UNIT: ns
COM or Yn
INH COM or Yn
MAX
MAX
MAX
COM or Yn Yn or COM
INH
508
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1Y0
1Y1
1Y2
1Y3
2Y0
2Y1
2Y2
2Y3
1-COM
INH
B
A
2-COM
10
9
6
13
12
14
15
11
1
5
2
4
3
4052DUAL 4-CHANNEL ANALOG MULTIPLEXERS / DEMULTIPLEXERS
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN CD74HC
CD74HCT
LV3V
LV5V UNIT
ICC MAX 0.16 0.16 - 0.02 mA
FUNCTION TABLE
INPUTSAB
L
L
ONCHANNEL1Y0, 2Y0
1Y2, 2Y2H
INH
H
LL
X1Y3, 2Y3
L
HLX None
LL
HH
1Y1, 2Y1
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN CD74HC
CD74HCT
LV3V
LV5V
tPLH 18 18 12 8tPHL 18 18 12 8tPZH 98 105 25 18tPZL 98 105 25 18tPHZ 75 75 25 18tPLZ 75 75 25 18
COM or Yn Yn or COM
INH COM or Yn
MAX
INH COM or Yn MAX
MAX
509PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
Logic Diagram
1Y0
1Y1
2Y0
2Y1
3Y0
1-COM
INH
B
A
3-COM
3Y1
2-COM
C
11
10
9
6
15
14
12
13
2
1
5
3
4
4053TRIPLE 2-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN CD74HC
CD74HCT
LV3V
LV5V UNIT
ICC MAX 0.16 0.16 - 0.02 mA
FUNCTION TABLE
INPUTSAC
L
L
ON CHANNEL
1Y0, 2Y0, 3Y0
1Y0, 2Y1, 3Y0H
INH
H
LL
X
1Y1, 2Y1, 3Y0
L
HLLLLL
X None
LL
H
L
H
L
H
H
B
X
LL
HH
L
LH
H
LL
HH
1Y1, 2Y0, 3Y0
1Y0, 2Y0, 3Y1
1Y0, 2Y1, 3Y11Y1, 2Y1, 3Y1
1Y1, 2Y0, 3Y1
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN CD74HC
CD74HCT
LV3V
LV5V
tPLH 18 18 12 8tPHL 18 18 12 8tPZH 66 72 25 18tPZL 66 72 25 18tPHZ 63 66 25 18tPLZ 63 66 25 18UNIT: ns
INH COM or Yn
COM or Yn Yn or COM MAX
MAX
INH COM or Yn MAX
510
Function Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
J1
12
1
GND
CLOCKINPUT
VCC
3
14
2
Ka
MODESELECTINPUTS
LATCHENABLE
Kb
Kc23
13
11
24
J2
4
J3
5
J4
6
J5
22
J6
21
J7
20
J8
19
J9
18
J10
17
J11
16
J12
15
J13
10
J14
9
J15
8
J16
7
PRESETTABLE LOGIC
PROGRAM JAM INPUTS (BCD)
FIRSTCOUNTINGSECTION
+10, 8, 5, 4, 2 +10 +10 +10
LASTCOUNTINGSECTION
+1, 2, 2, 4, 8
RECOGNITIONGATING
PRESETENABLE
DIVIDE-BY-NOUTPUT
OUTPUTSTAGE
Function 4059
MODECONTROL
INTERMEDIATE COUNTING SECTION
4059CMOS PROGRAMMABLE DIVIDE-BY-N COUNTER
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN CD74HC UNIT
ICC MAX 0.16 mAIOH MAX -4 mAIOL MAX 4 mA
INPUTSELECTMODE
KbKa
LHX
HLH
LHL
HHL
HLL
HHH
Kc
FUNCTION TABLE
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN CD74HC
fmax MIN 18tw MIN 27tsu MIN 22tPLH 60tPHL 60tPLH 53tPHL 53
UNIT fmax : MHz other : ns
MAX
Q
Q
CP
LE
CPCP
Kb, Kc to CP
MAX
511PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
Logic Diagram
4060ASYNCHRONOUS 14-STAGE BINARY COUNTERS AND OSCILLATORS
Same Pinouts as CMOS4060 Allow Design of Either RC or Crystal Oscillator Circuits VCC: 2V to 6V
R
T
R
T
R
T
R
T
R
T
R
T
R
T
R
T
6 14 13 15 1 2 3
11CLKI
QI QL QM QNQG QH QJ
R
T
4
QF
R
T
R
T
R
T
R
T
R
T
7 5
QD QE
12CLR
9
10
CLKO
CLKO
OPERATING CONDITIONS
MAX or MIN SN74HC
CD74HC
CD74HCT UNIT
MAX 0.08 0.16 0.16 mAMAX -4 -4 -4 mAMAX 4 4 4 mA
FUNCTION TABLE
INPUTSCLR
OUTPUTSCLKI QD to QN CLKO
No ChangeAdvance to Next State
All Outputs are LowL
HH
L↑↓
↓↑
↓↑
LX
CLKO
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN SN74HC
CD74HC
CD74HCT
fmax MIN 22 20 20tw 23 24 24
23 24 38tsu CLR inactive before CLK MIN 40 - -tPLH 123 90 100tPHL 123 90 100tPHL CLR Any MAX 35 53 66UNIT fmax : MHz other : ns
MIN
CLKI QD MAX
CLKICLR high
512
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
A
VCCVCC
B
One of Four Switches
C
4066QUADRUPLE BILATERAL SWITCHES
Same Pinouts as CMOS4016, 4066 Low On-State Impedance: 50-Ω TYP at VCC = 6V Individual Switch Controls Extremely Low Input Current High On-Off Output Voltage Ratio Low Crosstalk Between Switches
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN SN74HC
CD74HC
CD74HCT
LV3V
LV5V UNIT
ICC MAX 0.02 0.04 0.04 - 0.02 mA
FUNCTION TABLE
INPUT(C) SWITCH
OFFHL
ON
NOTE:H = High LevelL = Low Level
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN SN74HC
CD74HC
CD74HCT
LV3V
LV5V
tPLH 15 18 18 12 8tPHL 15 18 18 12 8tPZH 45 30 36 22 16tPZL 45 30 36 22 16tPHZ 50 45 53 22 16tPLZ 50 45 53 22 16UNIT: ns
MAX
MAX
MAX
A or B
A or B
A or B
B or A
C
C
513PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
Function Diagram
E
P N
I0
9
P N
I15
16
14 - OUTPUT CIRCUITSSAME AS ABO VE
(WITH ANALOG INPUTS)I1 TO I14
BINARY1 OF 16
DECODERSN = 5 STAGESE = 4 STAGES
10
11
14
13S3
S2
S1
S0
15
1 COMMONINPUT/OUTPUT
406716-CHANNEL ANALOG MULTIPLEXER/DEMULTIPLEXER
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN CD74HC
CD74HCT UNIT
ICC MAX 0.16 0.16 mA
FUNCTION TABLE
S0X
S1X
SELECTEDCHANNEL
X XS3
XE
None
0 0 0 0 0 0
1
0
1 1
1
1
10
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
S2
NOTES:H = High LevelL = Low Level
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN CD74HC
CD74HCT
tPLH 22 22tPHL 22 22tPZH 83 90tPZL 83 90tPZH 90 90tPZL 90 90tPHZ 83 83tPLZ 83 83tPHZ 87 87tPLZ 87 87UNIT:ns
E
Switch In COMON I/O
E
Sn
Sn COMON I/O
MAX
MAX
MAX
MAX
MAX
COMON I/O
COMON I/O
COMON I/O
514
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
4075TRIPLE 3-INPUT OR GATES
Y = A + B + C
nA
nB nY
nC
515PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN SN74HC
CD74HC
CD74HCT UNIT
ICC MAX 0.02 0.04 0.04 mAIOH MAX -4 -4 -4 mAIOL MAX 4 4 4 mA
INPUTS
HL
BA
HX
OUTPUTY
H
HX
L L
C
HX
L
XXX
H
FUNCTION TABLE
NOTES:H = High Voltage LevelL = Low Voltage LevelX = Don’t Care
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN SN74HC
CD74HC
CD74HCT
tPLH A, B or C Y MAX 25 30 36tPHL A, B or C Y MAX 25 30 36UNIT:ns
516
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
FFO
D Q
CPCP
FF1 FF2 FF3 FF4 FF5 FF6 FF7
L8
CP CP
Q
D
9
QS1
QS2
10
L7L6L5L4L3L2L1LO
STR STR
Q
DATA2
CP3
STR1
OE
15
Q0
OE OE4
Q15
Q26
Q37
Q414
Q513
Q612
Q711
40948-STAGE SHIFT AND STORE BUS REGISTER, THREE-STATE
517PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN CD74HC
CD74HCT UNIT
ICC MAX 0.16 0.16 mAIOL MAX 4 4 mAIOH MAX -4 -4 mA
FUNCTION TABLE
INPUTS
CP OE
H
LL
HHH
STR
H
LHH
XX
D
H
L
XXX
H
PALALLELOUTPUT
Z
LH
Qn-1Qn-1
NC
NC
Z
NC
NC
ZZ
QnQ0
SERIALOUTPUT
NC
Q’6NCQ’6
Q’7
NCQ’6 NCQ’6 NC
NCQ’7
QS2QS1‡
NOTES:†. H = High Voltage Level, L = Low Voltage Level, X = Don’t Care,
NC = No charge, Z = High Impedance Off-state, ↑ = Transition from Low to High Level, ↓ = Transition from High Low.
‡. At the positive clock edge the information in the seventh resister stage is transferred to the 8th register stage and QS1 output.
↑
↑
↑
↑
↓
↓
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN CD74HC
CD74HCT
tW MIN 24 24tWH MIN 24 24tSU 15 15
30 30tH 3 4
0 0tPLH 45 -tPHL 45 -tPLH 41 -tPHL 41 -tPLH 59 -tPHL 59 -tPLH 54 -tPHL 54 -tPZH 53 -tPZL 53 -tPLZ 38 -tPHZ 38 -UNIT:ns
CPSTRDataSTR
MIN
MIN
MAX
MAX
MAX
MAX
MAX
MAXQn
CP
CP
CP
STR
OE
OE
QS1
QS2
Qn
DataSTR
Qn
Qn
518
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
DIR
OE
A1
B1
To Seven Other Channels
2
3
22
21
4245OCTAL BUS TRANSCEIVER AND 3.3-V TO 5-V SHIFTER WITH 3-STATE OUTPUTS
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LVC LVCC UNIT
ICCA MAX 0.08 0.08 mAICCB MAX 0.05 0.08 mAIOH MAX -24 -24 mAIOL MAX 24 24 mA
FUNCTION TABLE
INPUTS
L
DIR
H
OPERATION
B data to A bus
IsolationX
OEL L
HA data to B bus
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN LVCLVCCVCCB
3.3V
tPLH 6.3 7tPHL 6.7 7tPLH 6.1 6.2tPHL 5 5.3tPZL 9 9tPZH 8.1 8tPZL 8.8 10tPZH 9.8 10.2tPLZ 7 5.2tPHZ 5.8 5.2tPLZ 7.7 5.4tPHZ 7.8 7.4UNIT: ns
OE
OE
OE
B
A
B
A B
OE A
B A
MAX
MAX
MAX
MAX
MAX
MAX
519PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
Logic Diagram
4316QUAD ANALOG SWITCH WITH LEVEL TRANSLATION
VCC
VEE
nZ
nY
ELOGICLEVELCONV.
VCC
VEE
TO 3 OTHERSWITCHES
nS
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN CD74HC
CD74HCT UNIT
ICC MAX 0.16 0.16 mA
INPUTSSWITCH
OFF
E
H
LL ON
OFFS
X
LH
FUNCTION TABLE
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN CD74HC
CD74HCT
tPLH 18 18tPHL 18 18tPZH 62 66tPZL 62 85tPZH 53 60tPZL 53 75tPLZ 62 75tPHZ 62 -tPLZ 53 -tPHZ 53 66UNIT:ns
nS MAX
Switch outSwitch in
Z
Z
Z
Z
E
nS
E
MAX
MAX
MAX
MAX
520
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
17A0
18A1
19A2
16A3
1A4
6A5
2A6
5A7
4A COMMON
13S1
15S0
12S2
11LE
7E1
8E2
MULTIPLEXER/DEMULTIPLEXER
CHANNELADDRESS
LATCH
4351ANALOG MULTIPLEXERS/DEMULTIPLEXERS WITH LATCH
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN CD74HC
CD74HCT UNIT
ICC MAX 0.16 0.16 mA
FUNCTION TABLE
INPUTS
E1
H
L
L
L
L
L
L
L
L
E2
H
L
H
“ON”†
SWITCCHES
LE = H
A3A4A5A6A7
None
A0A1A2
NOTES:† When LE is low S0-S2 data are latched and switches cannot change state.
H = High Voltage Level, L = Low Voltage Level, X = Don’t Care
S2
X X X
L
L
H
H
L
L
H
H
H
H
H H
H
H
S1
H
L
L
H
H
L
L
H
S0
H
L
H
L
H
L
L
H
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN CD74HC
CD74HCT
tW MIN 30 28tsu MIN - -tH MIN 5 5tPLH 11 11tPHL 11 11tPZH 90 113tPZL 90 113tPZH 90 113tPZL 90 113tPLZ 75 83tPHZ 75 83tPLZ 75 90tPHZ 75 90tPLZ 83 90tPHZ 83 90tPLH 83 98tPHL 83 98UNIT:ns
E1, E2, LE
Sn
E1
E2
LESn to LESn to LE
Switch In Switch Out
VOS
VOS
VOS
VOS
MAX
MAX
MAX
MAX
MAX
MAX
MAXVOS
VOS
LE
Sn
521PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
Function Diagram
TG
4
A COMMONOUT/IN
16181915
A3 A2 A1 A0
BINARYTO
1 OF 4DECODER
WITHENABLE
13
12
8E2
S1
S0
10 9
GND VEE
20
VCC
A CHANNELS IN/OUT
TG
LATCHES
7E1
11LE LOGICLEVEL
CONVERSION
S0
S0
S1
S1
17
B COMMONOUT/IN
TG
TG
TG
TG
TG
TG1625
B3B2B1B0
B CHANNELS IN/OUT
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN CD74HC UNIT
ICC MAX 0.16 mA
FUNCTION TABLE
INPUTS
E1
H
LLLL
E2
H
L
H
“ON”†
SWITCCHESLE = H
A3, B3None
A0, B0A1, B1A2, B2
NOTES:† When LE is low S0-S2 data are latched and switches
cannot change state.H = High Voltage Level, L = Low Voltage Level, X = Don’t Care
X X
HH
S1
H
LL
H
S0
HL
LH
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN CD74HC
tW MIN 30tsu MIN -tH MIN 5tPLH 11tPHL 11tPZH 105tPZL 105tPZH 113tPZL 113tPLZ 83tPHZ 83UNIT:ns
E1, E2, LE VOS
VOS
VOS
Sn
E1, E2, LE
Switch In
LESn to LESn to LE
Switch Out MAX
MAX
MAX
MAX
4352ANALOG MULTIPLEXERS/DEMULTIPLEXERS WITH LATCH
522
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
4374OCTAL EDGE-TRIGGERED D-TYPEDUAL-RANK FLIP-FLOP WITH3-STAE OUTPUTS
3-State Outputs Drive Bus Lines Directly1D
CLK
1Q1
11
20
10
1D
OE
C1
To Seven Other Channels
1D
C1
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN AS UNIT
ICC MAX 150 mAIOH MAX -15 mAIOL MAX 48 mA
FUNCTION TABLE
INPUTS
H
LDH
X
OUTPUTQ
Z
L LL
CLK
XXQO
HOE
LL
↑↑
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN AS
fmax MIN 125tw MIN 4tsu MIN 4th MIN 1tPLH 8tPHL 8tPZH 6tPZL 8tPHZ 6.5tPLZ 7UNIT fmax : MHz other : ns
MAX
MAX
MAX
CLK
OE
OE
Q
Q
Q
523PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
Logic Diagram
4511BCD-TO-7 SEGMENT LATCH/DECODER/DRIVERS
D07
5
D11
D22
D3
13a
12b
11c
10d
9e
15f
14
3
g
6
4
LATCH
D Q
Q
LELE
BI
LELE
LATCH
D Q
Q
Q
Q
LELE
LELE
LATCH
D Q
LELE
LELE
D Q
LELE
LE
LE
LT
LELE
LE
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN CD74HC
CD74HCT UNIT
ICC MAX 0.16 0.16 mAIOH MAX -7.4 -7.4 mAIOL MAX 4 4 mA
FUNCTION TABLE
LE
H
XXL
Bt LT
H
H
X L
D3X
D2 D1 D0
XXX
XX
X
X X X X
XL L LL LL LL L
LL
HH
HLH
LL
L
HH
HLH
LL
L
HH
HLH
LL
L
HH
HLH
a
H
b
H
c
H
d
H
e
H
f
H
g
H
L L L L LL
L
LL L
L L L
L L L L L L LL L L L L L LL L L L L L LL L L L L L LL L L L L L L
LH H
HHH H
HHH
H HH
HH
H H HLHH
HH
HHH
HH H H H H
H H HL H H
H H
H
H H H
LHL L
L
L L
L
L L L LL
H H HL
HHL
L L
LL
L
LL
L H
L HH
L HH
L HH
L HH
L HH H
HHH
L
L
L
L
L
L
LHHHHHHHH
LHHHH
L HH
L HH
L HH
L HH
L HH
L HH
L HH
L HH
L HH
L HHHH
BlankBlankBlankBlankBlankBlank
8Blank
0123456789
Display
NOTES:X = Don’t CareDepends on BCD code previously appied when LE = LDisplay is blank for all illegal input codes (BCD > HLLH).
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN CD74HC
CD74HCT
tW MIN 20 20tsu MIN 20 20tH MIN 3 5tPLH 75 75tPHL 75 75tPLH 68 68tPHL 68 68tPLH 55 55tPHL 55 55tPLH 40 41tPHL 40 41UNIT:ns
a to g
a to g
a to g
Dn
LE
BI
LT
Latch Enable
Dn to LEDn to LE
a to g
MAX
MAX
MAX
MAX
524
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
A0 S Q
Q
Q
Q
Q
S
S
S
R
R
R
R
A1
A2
A3
LE
E
2
3
21
22
1
23
Q
Q
Q
11
9
10
8
7
6
5
4
18
17
20
19
14
13
16
15
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
45144-LINE TO 16-LINE DECODERS/DEMULTIPLEXERS WITH INPUT LATCHES
525PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN SN74HC
CD74HC
CD74HCT UNIT
ICC MAX 0.08 0.16 0.08 mAIOH MAX -4 -4 -6 mAIOL MAX 4 4 6 mA
(LE = H)
DECODER INPUTSADDRESSED OUTPUT H
A3 A2 A1 A0
L L L L L Y0
L L L L H Y1
L L L H L Y2
L L L H H Y3
L L H L L Y4
L L H L H Y5
L L H H L Y6
L L H H H Y7
L H L L L Y8
L H L L H Y9
L H L H L Y10
L H L H H Y11
L H H L L Y12
L H H L H Y13
L H H H L Y14
L H H H H Y15
H X X X X All outputs = L
FUNCTION TABLE
E
H = high, L = low, X = don’t care
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN SN74HC
CD74HC
CD74HCT
tw MIN 20 22 38tsu MIN 25 30 25th MIN 5 0 5tPLH MAX 58 83 69tPHL 58 83 69tPLH MAX 58 68 63tPHL 58 68 63tPLH MAX 44 53 50tPHL 44 53 50UNIT:ns
Y
YG(E)
LE(LE)
LE (LE)LE (LE)LE (LE)
YA, B, C, D(A1, 2, 3, 4)
526
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
A0 S Q
Q
Q
Q
Q
S
S
S
R
R
R
R
A1
A2
A3
LE
E
2
3
21
22
1
23
Q
Q
Q
11
9
10
8
7
6
5
4
18
17
20
19
14
13
16
15
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
45154-LINE TO 16-LINE DECODERS/DEMULTIPLEXERS WITH INPUT LATCHES
527PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
(LE = H)
DECODER INPUTSADDRESSED OUTPUT L
A3 A2 A1 A0
L L L L L Y0
L L L L H Y1
L L L H L Y2
L L L H H Y3
L L H L L Y4
L L H L H Y5
L L H H L Y6
L L H H H Y7
L H L L L Y8
L H L L H Y9
L H L H L Y10
L H L H H Y11
L H H L L Y12
L H H L H Y13
L H H H L Y14
L H H H H Y15
H X X X X All outputs = H
FUNCTION TABLE
E
H = high, L = low, X = don’t care
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN SN74HC
CD74HC
CD74HCT UNIT
ICC MAX 0.08 0.16 0.08 mAIOH MAX -4 -4 -6 mAIOL MAX 4 4 6 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN SN74HC
CD74HC
CD74HCT
tw MIN 20 22 38tsu MIN 25 30 25th MIN 5 0 5tPLH 58 83 69tPHL 58 83 69tPLH 58 68 63tPHL 58 68 63tPLH 44 53 50tPHL 44 53 50UNIT:ns
MAX
MAX
MAX
Y(CD74HCT:Y)
Y(CD74HCT:Y)
Y(CD74HCT:Y)
G(E)
LE(LE)
A, B, C, D(A1, 2, 3, 4)
LE (LE)LE (LE)LE (LE)
528
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
D
Q0 Q1 Q23(11) 4(12) 5(13)
Q36(14)
MR
CP
E
VCC
GND
7(15)
1(9)
2(10)
16
8
FF
R
Q
CL Q
DFF
R
Q
CL Q
DFF
R
Q
CL Q
DFF
R
Q
CL Q
4518DUAL SYNCHRONOUS COUNTERS
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN CD74HC UNIT
ICC MAX 0.16 mAIOH MAX -4 mAIOL MAX 4 mA
INPUTS
X
E OUTPUT STATE
No ChangeNo ChangeNo ChangeQ0 thru Q3 = L
CP
H
L
L
MR
LL
Increment CounterHIncrement CounterNo Change
LL
LH
X HLL
FUNCTION TABLE
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN CD74HC
fmax MIN 20tw 24
30tsu 24
24tPLH 72tPHL 72tPLH 72tPHL 72tPLH 45tPHL 45
UNIT fmax : MHz other : ns
MAX
MIN
MIN
MAX
MAXEnable
Qn
Qn
QnMR
CP
CPMR
Enable to CPCP to Enable
529
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
4520DUAL SYNCHRONOUS COUNTERS
Q36(14)
D
Q0 Q1 Q23(11) 4(12) 5(13)
MR
CP
E
VCC
VCC
GND
7(15)
1(9)
2(10)
16
8
FF
R
Q
CL Q
DFF
R
Q
CL Q
DFF
R
Q
CL Q
DFF
R
Q
CL Q
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN CD74HC
CD74HCT UNIT
ICC MAX 0.16 0.16 mAIOH MAX -4 -4 mAIOL MAX 4 4 mA
INPUTS
X
E OUTPUT STATE
No ChangeNo ChangeNo ChangeQ0 thru Q3 = L
CP
X
L
L
MR
LL
Increment CounterHIncrement CounterNo Change
LL
XH
X HLL
FUNCTION TABLE
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN CD74HC
CD74HCT
fmax MIN 20 17tw 24 30
30 30tsu 24 24
24 -tPLH 72 80tPHL 72 80tPLH 72 83tPHL 72 83tPLH 45 53tPHL 45 53
UNIT fmax : MHz other : ns
MAX
MIN
MIN
MAX
MAXQn
Qn
CP
Enable
MR
Qn
CPMR
Enable to CPCP to Enable
530
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
D
CLCL Q
QR2R1FF
VCC
VCC
RX
CX
2(14)
1(15)
8
R
A
B
3(13)
4(12)
5(11)
VCC
VCC
HIGH Z
VCC
VCC
R1
R2
COMP II
-
+ 6(10)
7(9)
Q
Q
VCC
16
4538DUAL RETRIGGERABLE PRECISION MONO STABLE MULTIVIBRATOR
531PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN CD74HC
CD74HCT UNIT
ICC MAX 0.16 0.16 mAIOH MAX -4 -4 mAIOL MAX 4 4 mA
FUNCTION TABLEINPUTS
XX
AOUTPUTS
R
X H
B
L
XLXX
HH L
H
Q
HHH
L
ELL
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN CD74HC
CD74HCT
tW 24 24tWL 24 24tWL 24 30tPLH Q 75 83tPHL Q 75 83tPLH Q - 75tPHL Q 75 60UNIT:ns
R
MAX
MIN
MAX
A, BA, B
R
A, B
532
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
DnDn
Qn
Qn
p
p
n
nQn
Qn
LD
LD
LD
LD
LD
LD
LATCH
D0D0
B1
5
7
Q0
Q0
LDLD
LDLD
LATCH
D1D13
Q1
Q1
LDLD
LDLD
LATCH
D2D22
Q2
Q2LDLD
LDLD
LATCH
D3D34
1
Q3
Q3LDLD
LD
LDLD
LD LD
9a
11c
10b
12d
13
PH6
e
15f
14g
4543BCD-TO-7 SEGMENT LATCH/DECODER/DRIVERS
533PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN CD74HC
CD74HCT UNIT
ICC MAX 0.16 0.16 mAIOH MAX -1 -1 mAIOL MAX 1 1 mA
FUNCTION TABLE
LD
HX
LL
B1 PH
L
H
H LLLLLLLLLLLLLLLLL
NL
D3X
D2 D1 D0X X X
X Xas above
X X
L L LL LL LL L
LL
HH
HLH
LL
L
HH
HLH
LL
L
HH
HLH
LL
L
HH
HLH
a b c d e f g
L L L L L
L
LL L
L L L
L L L L L L LL L L L L L LL L L L L L LL L L L L L LL L L L
inverse above
L L L
LH H
HHH H
HHH
H HH
H
HH
H H HLHH
HH
HHH
HH H
HH H H
H H HL H H
H H
H
H H H
LHH L
L
L L
L
L L L LL
H HL
HHL
L LL
LL
L
LL
LH
LH
LH
LH
LH
HHHH
L
L
L
L
L
L
LHHHHHHHH
LHHHH
LH
LH
LH
LH
LH
LH
LH
LHHLas above
Blank
as above
BlankBlankBlankBlankBlank
Blank0123456789
Display
NOTES:Depends open the BCD code previously appied when LE = High
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN CD74HC
CD74HCT
tW MIN 13 13tsu MIN 15 15tH MIN 8 10tPLH 85 100tPHL 85 100tPLH 93 96tPHL 93 96tPLH 66 83tPHL 66 83tPLH 50 83tPHL 50 83UNIT:ns
Latch DisableDn to LDDn to LD
Dn a to g
LD
MAX
MAX
MAX
MAX
B1
PH
a to g
a to g
a to g
534
Logic Diagram
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
540011-BIT LINE/MEMORY DRIVERSWITH 3-STATE OUTPUTS
Output Ports Have Equivalent 25-Ω SeriesResistors, So No External Resistors Are Required(SN74ABT5400A)
540111-BIT LINE/MEMORY DRIVERSWITH 3-STATE OUTPUTS
Output Ports Have Equivalent 25-Ω Series Resistors,So No External Resistors Are Required(SN74ABT5401)
Y1
To Ten Other Channels
OE1
OE2
D1
14
15
28 1
Y1
To Ten Other Channels
OE1
OE2
D128 1
15
14
FUNCTION TABLE
INPUTS
HL
D
HX
INPUTY
L L
H
L
XXX
ZH
OE1L
L
OE2
Z
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ABT UNIT
ICC MAX 45 mAIOH MAX -12 mAIOL MAX 12 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ABT
tPLH 6.2tPHL 5.6tPZH 8.7tPZL 7.5tPHZ 5.2tPLZ 6.9UNIT: ns
OE
D
OE
Y
MAX
MAX
MAX
Y
Y
FUNCTION TABLE
INPUTS
HL
D
H
X
OUTPUTYH
ZX
LL
OE1
H
LX
OE2L
X
L
Z
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ABT UNIT
ICC MAX 45 mAIOH MAX -12 mAIOL MAX 12 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ABT
tPLH 6.9tPHL 5.7tPZH 8.5tPZL 6.8tPHZ 5.2tPLZ 6.9UNIT: ns
OE Y MAX
D Y MAX
OE Y MAX
535
Logic Diagram
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
540212-BIT LINE/MEMORY DRIVERSWITH 3-STATE OUTPUTS
Output Ports Have Equivalent 25-Ω SeriesResistors, So No External Resistors Are Required(SN74ABT5402A)
540311-BIT LINE/MEMORY DRIVERSWITH 3-STATE OUTPUTS
Output Ports Have Equivalent 25-Ω SeriesResistors, So No External Resistors Are Required(SN74ABT5403)
Y1
To Eleven Other Channels
OE1
OE2
D1
14
15
28 1
Y1
To 11 Other Channels
OE1
OE2
D128 1
15
14
FUNCTION TABLE
INPUTS
HL
D
H
X
OUTPUTY
H
ZX
L LOE1
H
LX
OE2L
X
L
Z
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ABT UNIT
ICC MAX 48 mAIOH MAX -12 mAIOL MAX 12 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ABT
tPLH 6.2tPHL 5.6tPZH 8.7tPZL 7.5tPHZ 5.2tPLZ 6.9UNIT: ns
OE Y MAX
OE Y MAX
D Y MAX
FUNCTION TABLE
INPUTS
HL
D
H
X
OUTPUTYH
ZX
LL
OE1
H
LX
OE2L
X
L
Z
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ABT UNIT
ICC MAX 45 mAIOH MAX -12 mAIOL MAX 12 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ABT
tPLH 6.9tPHL 5.7tPZH 8.5tPZL 6.8tPHZ 5.2tPLZ 6.9UNIT: ns
OE Y MAX
D Y MAX
OE Y MAX
536
Logic Diagram
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
7001QUADRUPLE POSITIVE-AND GATESWITH SCHMITT-TRIGGER INPUTS
Same Pinouts as SN74HC08 VCC: 2V to 6V Schmitt-Triggered Inputs Y = A•B
7002QUADRUPLE POSITIVE-NOR GATESWITH SCHMITT-TRIGGER INPUTS
Same Pinouts as SN74HC36 VCC: 2V to 6V Schmitt-Triggered Inputs Y = A + B
A
B
Y
A
B
Y
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN HC UNIT
ICC MAX 0.02 mAIOH MAX -4 mAIOL MAX 4 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN HC
tPLH 33tPHL 33UNIT: ns
A or B Y MAX
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN HC UNIT
ICC MAX 0.02 mAIOH MAX -4 mAIOL MAX 4 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN HC
tPLH 33tPHL 33UNIT: ns
A or B Y MAX
537
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
7032QUADRUPLE 2-INPUT POSITIVE-OR GATESWITH SCHMITT-TRIGGER INPUTS
Same Pinouts as SN74HC32 VCC: 2V to 6V Schmitt-Triggered Inputs Y = A + B
A
B
Y
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN HC UNIT
ICC MAX 0.02 mAIOH MAX -4 mAIOL MAX 4 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN HC
tPLH 33tPHL 33UNIT: ns
A or B Y MAX
538
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
DE
MO
UT
R2
12
R1
R5
11
10
C1
R3
C2
PC2OUT13
p
n
GND
VCC
2PC1OUT
DOWN
RD
Q
Q
D
CP
RD
Q
Q
D
CP
UPVC
C
VCC
INH
5 9
VCOIN
VCO
- +
VC
OO
UT COMPIN
- +
SIGINC1BC1A
VREFR2
R1
6 7 4 3 14
-
+
1
15
150Ω
1.5KLOCKDETECTOROUTPUT
LOCKDETECTORCAPACITOR
CLD
LOCK DETECTOR
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN CD74HC
CD74HCT UNIT
ICC MAX 0.16 0.16 mAIOH MAX -4 -4 mAIOL MAX 4 4 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN CD74HC
CD74HCT
tPLH 60 68tPHL 60 68tPZH 84 90tPZL 84 90tPHZ 98 105tPLZ 98 105UNIT:ns
MAX
MAX
MAX
SIGIN,COMPIN
SIGIN,COMPIN
SIGIN,COMPIN
PC1OUT
PC2OUT
PC2OUT
7046PHASE-LOCKED LOOP WITH VCO AND LOCK DETECTOR
539
Logic Diagram
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
8003DUAL 2-INPUT POSITIVE-NAND GATES
1Y3
11A
21B
2Y5
62A
72B
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALS AS UNIT
ICC MAX 1.5 8.7 mAIOH MAX -0.4 -2 mAIOL MAX 8 20 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALS AS
tPLH 11 4.5tPHL 8 4UNIT: ns
A or B Y MAX
nA
nB
nY
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN SN74HC
CD74HC UNIT
ICC MAX 0.02 0.04 mAIOH MAX -4 -4 VIOL MAX 4 4 V
INPUTS
H
L
BAL
OUTPUTY
L
H
HH
LL
HLH
FUNCTION TABLE
NOTES:H = High Voltage LevelL = Low Voltage Level
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN SN74HC
CD74HC
tPLH Y MAX 25 35tPHL Y MAX 25 35UNIT:ns
A or B
7266QUAD 2-INPUT EXCLUSIVE-NOR GATES
Y = A ⊕ B
540
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1OE
1A1
1A2
1A3
1A4
1Y1
1Y2
1Y3
1Y4
1
47
46
44
43
2
3
5
6
2OE
2A1
2A2
2A3
2A4
2Y1
2Y2
2Y3
2Y4
48
41
40
38
37
8
9
11
12
3OE
3A1
3A2
3A3
3A4
3Y1
3Y2
3Y3
3Y4
25
36
35
33
32
13
14
16
17
4OE
4A1
4A2
4A3
4A4
4Y1
4Y2
4Y3
4Y4
24
30
29
27
26
19
20
22
23
1624016-BIT BUS BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
541PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ABT LVT3V
LVTH3V
ALVT3V AC ACT AHC AHCT LVCH
3VLVCZ
3VALVCH
3V UNIT
ICC MAX 34 5 5 5 0.08 0.08 0.04 0.04 0.02 0.1 0.04 mAIOH MAX -32 -32 -32 -32 -24 -24 -8 -8 -24 -24 -24 mAIOL MAX 64 64 64 64 24 24 8 8 24 24 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ABT LVT3V
LVTH3V
ALVT3V AC ACT AHC AHCT
tPLH 4.7 3.5 3.5 3.3 5.8 8.5 8.5 10.5tPHL 4.8 3.5 3.5 3.2 7.1 10.2 8.5 10.5tPZH 5.3 4 4 3.7 6.6 9.4 10.5 13tPZL 7.1 4.4 4.4 3.1 8.1 11.4 10.5 13tPHZ 6.1 4.5 4.5 5 8.1 12 10.5 13tPLZ 5.6 4.2 4.2 4.1 7.3 10.7 10.5 13
PARAMETER INPUT OUTPUT MAX or MIN LVCH3V
LVCZ3V
ALVCH3V
tPLH 4.2 4.2 3.9tPHL 4.2 4.2 3.9tPZH 4.7 4.7 5tPZL 4.7 4.7 5tPHZ 5.9 5.9 4.4tPLZ 5.9 5.9 4.4UNIT: ns
MAX
Y MAX
Y MAX
A
OE
OE
Y
OE Y MAX
A Y MAX
OE Y MAX
FUNCTION TABLE (each 4-bit buffer)
INPUTS
HL
AH
OUTPUTY
HLL
OEL
X Z
542
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1OE
1A1
1A2
1A3
1A4
1Y1
1Y2
1Y3
1Y4
1
47
46
44
43
2
3
5
6
2OE
2A1
2A2
2A3
2A4
2Y1
2Y2
2Y3
2Y4
48
41
40
38
37
8
9
11
12
3OE
3A1
3A2
3A3
3A4
3Y1
3Y2
3Y3
3Y4
25
36
35
33
32
13
14
16
17
4OE
4A1
4A2
4A3
4A4
4Y1
4Y2
4Y3
4Y4
24
30
29
27
26
19
20
22
23
1624116-BIT BUS BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
543PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ABT LVTH3V ACT UNIT
ICC MAX 34 5 0.08 mAIOH MAX -32 -32 -24 mAIOL MAX 64 64 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ABT LVTH3V ACT
tPLH 3.7 3.5 9.5tPHL 4.5 3.5 9.1tPZH 5 4.5 9.4tPZL 6.9 4.5 10.5tPHZ 6.2 5.3 11.6tPLZ 5.6 4.9 10.7UNIT: ns
OE or OE Y MAX
A Y MAX
OE or OE Y MAX
FUNCTION TABLE
INPUTS
HL
1A, 4AH
OUTPUTS1Y, 4Y
HLL
1OE, 4OEL
X Z
INPUTS
HL
2A, 3AH
OUTPUTS2Y, 3YH
L L
2OE, 3OE
X Z
H
544
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1OE
1A1
1A2
1A3
1A4
1Y1
1Y2
1Y3
1Y4
1
47
46
44
43
2
3
5
6
2OE
2A1
2A2
2A3
2A4
2Y1
2Y2
2Y3
2Y4
48
41
40
38
37
8
9
11
12
3OE
3A1
3A2
3A3
3A4
3Y1
3Y2
3Y3
3Y4
25
36
35
33
32
13
14
16
17
4OE
4A1
4A2
4A3
4A4
4Y1
4Y2
4Y3
4Y4
24
30
29
27
26
19
20
22
23
1624416-BIT BUS BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
545PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ABT ABTH LVT3V
LVTH3V
ALVTH3V AC ACT AHC AHCT LVC
3VLVCH
3V UNIT
ICC MAX 32 32 5 5 5 0.08 0.08 0.04 0.04 0.02 0.02 mAIOH MAX -32 -32 -32 -32 -32 -24 -24 -8 -8 -24 -24 mAIOL MAX 64 64 64 64 64 24 24 8 8 24 24 mA
PARAMETER MAX or MIN LVCZ3V
ALVC3V
ALVCH3V
AVC3V UNIT
ICC MAX 0.1 0.04 0.04 0.04 mAIOH MAX -24 -24 -24 -12 mAIOL MAX 24 24 24 12 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ABT ABTH LVT3V
LVTH3V
ALVTH3V AC ACT AHC
tPLH 3.5 3.5 3.2 3.2 2.4 7.1 9.4 8.5tPHL 4.1 4.1 3.2 3.2 2.5 7.9 9.5 8.5tPZH 4.8 4.8 4 4 3.8 7.5 8.9 10.5tPZL 4.8 4.8 4 4 2.9 9 10.3 10.5tPHZ 4.8 4.8 4.5 4.5 4.2 8.4 11.3 10.5tPLZ 4.1 4.1 4.2 4.2 3.6 7.6 10.3 10.5
PARAMETER INPUT OUTPUT MAX or MIN AHCT LVC3V
LVCH3V
LVCZ3V
ALVC3V
ALVCH3V
AVC3V
tPLH 10.5 4.1 4.1 4.1 3 3 1.7tPHL 10.5 4.1 4.1 4.1 3 3 1.7tPZH 13 4.6 4.6 4.6 4.4 4.4 3.5tPZL 13 4.6 4.6 4.6 4.4 4.4 3.5tPHZ 13 5.8 5.8 5.8 4.1 4.1 3.5tPLZ 13 5.8 5.8 5.8 4.1 4.1 3.5UNIT: ns
OE Y MAX
A Y MAX
OE Y MAX
OE Y MAX
A Y MAX
OE Y MAX
FUNCTION TABLE(each buffer)
INPUTS
HL
AH
OUTPUTYH
L L
OEL
X Z
546
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
To Seven Other Channels
1DIR
1A1
1B1
1OE
To Seven Other Channels
2DIR
2A1
2B1
2OE
1
47
24
36
48
2
25
13
1624516-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
547PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ABT ABTH LVT3V
LVTH3V
ALVTH3V AC ACT AHCT UNIT
ICC MAX 32 32 5 5 5 0.08 0.08 0.04 mAIOH MAX -32 -32 -32 -32 -32 -24 -24 -8 mAIOL MAX 64 64 64 64 64 24 24 8 mA
PARAMETER MAX or MIN LVC3V
LVCH3V
LVCHR3V
LVCZ3V
ALVCH3V
ALVCHR3V
AVC3V UNIT
ICC MAX 0.02 0.02 0.02 0.06 0.04 0.04 0.04 mAIOH MAX -24 -24 -12 -24 -24 -12 -12 mAIOL MAX 24 24 12 24 24 12 12 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ABT ABTH LVT3V
LVTH3V
ALVTH3V AC ACT AHCT
tPLH 3.9 3.9 3.3 3.3 3.1 7.9 10.5 10.5tPHL 4.2 4.2 3.3 3.3 2.9 8.9 10.2 10.5tPZH 6.3 6.3 4.5 4.5 4.2 8.6 10 15tPZL 6.4 6.4 4.6 4.6 3.5 10.7 11.6 15tPHZ 6.3 6.3 5.1 5.1 5.3 9.8 12.6 15tPLZ 5.2 5.2 5.1 5.1 5 8.7 11.8 15
PARAMETER INPUT OUTPUT MAX or MIN LVC3V
LVCH3V
LVCHR3V
LVCZ3V
ALVCH3V
ALVCHR3V
AVC3V
tPLH 4 4 4.8 4 3 4.2 1.7tPHL 4 4 4.8 4 3 4.2 1.7tPZH 5.5 5.5 6.3 5.6 4.4 5.6 3.7tPZL 5.5 5.5 6.3 5.6 4.4 5.6 3.7tPHZ 6.6 6.6 7.4 6.6 4.1 5.5 3.9tPLZ 6.6 6.6 7.4 6.6 4.1 5.5 3.9UNIT: ns
OE B or A MAX
A or B B or A MAX
OE B or A MAX
OE B or A MAX
A or B B or A MAX
OE B or A MAX
FUNCTION TABLE(each 8-bit section)
INPUTS
HL
DIR
H
OPERATION
B data to A busLOEL
X IsolationA data to B bus
548
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
C1
1D
C1
1D
C1
1D
C1
1D
To 11 Other Channels
LE1B
LE2B
LEA1B
LEA2B
OE2B
OE1B
OEA
SEL
A1 1B1
2B1
27
2
30
55
56
29
1
28
8 23
6
G1
1
1
1626012-BIT TO 24-BIT MULTIPLEXES D-TYPE LATCH WITH 3-STATE OUTPUTS
549PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ABTH ALVCH3V UNIT
ICC MAX 63 0.04 mAIOH MAX -32 -24 mAIOL MAX 64 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ABTH ALVCH3V
tw Pulse duration, LE1B, LE2B, LEA1B, or LEA2B high MIN 3.3 3.3tsu Setup time, data before LE1B, LE2B, LEA1B, or LEA2B MIN 1.5 1.1th Hold time, data after LE1B, LE2B, LEA1B, or LEA2B MIN 1 1.5tPLH 5.6 4.3tPHL 5.9 4.3tPLH 5.8 4.4tPHL 5.3 4.4
SEL (B1) 5.3 5.6SEL (B2) 6 5.6SEL (B1) 4.4 5.6SEL (B2) 5.9 5.6
tPZH 5.7 5.4tPZL 5.8 5.4tPHZ 6.4 4.6tPLZ 4.8 4.6UNIT: ns
MAX
MAX
tPLH
tPHL
AMAX
MAX
A or B B or A
A or BLE
OE A or B MAX
OE A or B MAX
FUNCTION TABLE
INPUTS
HL
OUTPUTA1BHL
XX HX LX A0X
HL
2BXXX
XX
H
L
H
L
H
L
SEL
X
HHL
LE1B
XXXX
HHL
LE2B
XXX
X H
LLLLLL
OEA
Z
A0
B TO A (OEB = H)
INPUTS
H
HL
HL
L
OUTPUTS1B
HL
XX
H
X
L
X
2B0
2B02B0
X
HL
1B 2B
Active
Active ActiveActive
HHHH
LLL
LEA1B
XXXX
HHL
HHLL
LEA2B
XXX
X
H
LLL
L
L
L
OE1B
ZZZ
Z
1B0
HL
1B01B0
H
HH
LLL
L LL LL L
L
LL
OE2B
A TO B (OEA = H)
550
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
CLK
SEL
A1 1B1
2B1
CLKENA1
CLKENA2
1D
CE
1D
CE
G1
1
1
OEA
1D
C11 of 12 Channels
OEB1
OEB2 1D
1D
C1
C1
C1
C1
1D
C1
1D
C1
29
2
56
30
55
28
1
8 23
6
1626912-BIT TO 24-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS
551PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALVCH3V
ALVCHR3V
AVC3V UNIT
ICC MAX 0.04 0.04 0.04 mAIOH MAX -24 -12 -12 mAIOL MAX 24 12 12 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALVCH3V
ALVCHR3V
AVC3V
fmax MIN 135 135 175tw Pulse duration, CLK high or low MIN 3.3 3.3 3.5
A data before CLK MIN 1.7 1 1.9B data before CLK MIN 1.8 1.1 1.9SEL before CLK MIN 1.3 1.3 1.3CLKENA1 or CLKENA2 before CLK MIN 0.9 0.8 1.1OE before CLK MIN 1.3 1.2 1.1A data after CLK MIN 0.6 1.2 1B data after CLK MIN 0.6 1 0.7SEL after CLK MIN 0.7 1.7 0.4CLKENA1 or CLKENA2 after CLK MIN 1.1 1.6 1OE after CLK MIN 0.8 1.2 0.3
B 6.2 5.8 3A 5 5.2 2.7B 6.1 5.8 3.8A 5.9 5.3 3.4B 6.1 6 3.7A 5.6 6 3.4
UNIT fmax : MHz other : ns
tsu Setup time
th Hold time
CLK
CLK MAX
CLK
tpd
ten
MAX
MAX
tdis
FUNCTION TABLE
INPUTS OUTPUTSCLK
Z
H
L
HL H
L
OEA A 1B,2BHL
OEB
OUTPUT ENABLE
Active
ZActiveZ
Active
Z
Active
→→
→→
1B0† 2B0†
INPUTS OUTPUTSCLK
H
X
LL H
L
CLKENA1 1B 2B
LHL
HL
A
A-TO-B STORAGE (OEB = L)
→→
XXX
XX
XX
X XH
L
CLKENA2
LH
→→
† Output level before the indicated steady-state input conditions were established
A0†
INPUTS OUTPUTACLK
XL
XHL
2B1BSEL
B-TO-A STORAGE (OEA = L)
→→
X XA0†
HL
X X
H
HL
XX
XX
H
LL
HLH
→→
† Output level before the indicated steady-state input conditions were established
552
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
CLK
OEB
SEL
A1
1B1
2B1
CLKENA1
CLKENA2
1D 1D
CE
C1
1D
CE
C1
G1
1
1 1D
1D
CLKEN1B
C1
1D
1D
C1
CEOEA
1D
C1
C1
CLKEN2B
1 of 12 Channels
CE
CE
C1
2
27
30
55
56
28
1
29
8
23
6
1627012-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS
553PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALVCH3V UNIT
ICC MAX 0.04 mAIOH MAX -24 mAIOL MAX 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALVCH3V
fmax MIN 150tw Pulse duration, CLK high or low MIN 3.3
A data before CLK MIN 3.1B data before CLK MIN 0.9CLKENA1 or CLKENA2 before CLK MIN 2.7CLKEN1B or CLKEN2B before CLK MIN 2.6OE before CLK MIN 3.2A data after CLK MIN 0.2B data after CLK MIN 1.7CLKENA1 or CLKENA2 after CLK MIN 0.3CLKEN1B or CLKEN2B after CLK MIN 0.6OE after CLK MIN 0.1
5.14.7
SEL A MAX 5.566
5.85.8
UNIT fmax : MHz other : ns
MAX
CLKten
MAX
MAX
tpd
tdis
A or B
A or B
A or B
tsu Setup time
th Hold time
CLK
CLK
FUNCTION TABLE
INPUTS OUTPUTSCLK
Z
H
L
HL H
L
OEA A 1B,2BHL
OEB
1B0‡1B0‡1B0‡
2B0‡2B0‡
2B0‡
OUTPUT ENABLE
Active
ZActiveZ
Active
Z
Active
→→
→→
INPUTS OUTPUTSCLK
H
L
H
L
H
L
L HL
CLKENA1 1B 2B
LHL
H†L†
H†L†
H
HL
L
A
A-TO-B STORAGE (OEB = L)
→→
→→
X X
H
L
CLKENA2
LH
L
H
L
CLK
LX
XX
H
L
CLKEN1B
L
CLKEN2B
H
XX
X
L
H
→→
† Two CLK edges are needed to propagate data.‡ Output level before the indicated steady-state input conditions were established
A0‡
INPUTS OUTPUTA
LHL
2B1BSEL
B-TO-A STORAGE (OEA = L)
→→
X XA0‡
HL
X XXX
H
HL
XX
XX
H
LL
HLH
→→
‡ Output level before the indicated steady-state input conditions were established
554
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
CLK
OEA
SEL
A1
1B1
2B1
1D
CE
C1
1D
CE
C1
G1
1
1
LE1B
LE
1D
1D
LE
OEB
CLKENA2
CLKENA1
LE2B
1 of 12 Channels
2
27
30
55
56
28
1
29
8
23
6
1627112-BIT TO 24-BIT MULTIPLEXED BUS EXCHANGER WITH 3-STATE OUTPUTS
555PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALVCH3V UNIT
ICC MAX 0.04 mAIOH MAX -24 mAIOL MAX 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALVCH3V
fmax MIN 130tw Pulse duration, CLK high or low MIN 3.3
A before CLK MIN 1.7B before LE MIN 1.3CLKEN before CLK MIN 1A after CLK MIN 0.7B after LE MIN 1.1CLKEN after CLK MIN 0.9
CLK B MAX 4.3B 4
LE 4.8
SEL 5.2ten OEB or OEA B or A MAX 5.1tdis OEB or OEA B or A MAX 4.2UNIT fmax : MHz other : ns
MAX
tsu Setup time
th Hold time
tpdA
INPUTS
XOEB
L
Z
ActiveH
OEAOUTPUTS
1B, 2BAH
LL
L
Active
L ZZ
ZActive
Active
OUTPUT ENABLE
INPUTS
XACLKENA2
HL
OUTPUTS
1B0†
HL
CLKENA1 CLK 2B1BH
X
X
LX
L
→→
→
HX
HX
LLX
A0→
L2B0†
XLH
X
A-TO-B STORAGE (OEB = L)
INPUTS
X1BSEL
H
X
OUTPUTA
A0†
H
L
LEH
L
H
L
X
XX
2B
H
XXXL
X
LL
XHH
L
LHL
† Output level before the indicated steady-state input conditions were established
L
A0†
FUNCTION TABLE
B-TO-A STORAGE (OEA = L)
556
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
C1
1D
C1
G1
1
1
C1
CE
1D
C1
CE
C1
CE
1D
1D
C1
CE
1D
1 of 18 Channels
39
40
42
41
27
25
24
CLK
SEL
OE
DIR
A1
1B1
2B1
1D
1628218-BIT TO 36-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS
557PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALVCH3V UNIT
ICC MAX 0.04 mAIOH MAX -24 mAIOL MAX 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALVCH3V
fmax MIN 150tw Pulse duration, CLK high or low MIN 3.3
A data before CLK MIN 2B data before CLK MIN 1.8DIR before CLK MIN 1.7SEL before CLK MIN 1.8A data after CLK MIN 0.7B data after CLK MIN 0.6DIR after CLK MIN 0.5SEL after CLK MIN 0.8
A 5B 5.3A 5.7B 7.4A 5.7B 6.4
UNIT fmax : MHz other : ns
tdis OE
MAX
MAX
MAX
tpd
tsu Setup time
th Hold time
CLK
OEten
INPUTS
XDIR
H
Z
Active
OEOUTPUTS
1B, 2BAH
LLL Z
Z
ZActive
OUTPUT ENABLE
INPUTS
XA
HL
OUTPUTS
1B0†
H‡
CLK 2B1BH X
LL
→→
→→
→→
L‡2B0†
XX
A-TO-B STORAGE (OE = L, DIR = H)
INPUTS1BSEL
SEL
H
OUTPUTA
HL
CLK
→→
→
CLK
XX
2B
HXX
L
L
HH
L
L§H§L
§ Two CLK edges are needed to propagate the data. The data is loaded in the first register when SEL is low and propagates to the second register when SEL is high.
FUNCTION TABLE
† Output level before the indicated steady-state input conditions were established
‡ Two CLK edges are needed to propagate the data.
B-TO-A STORAGE (OE = L, DIR = L)
558
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1
48
25
471D
C1
CLK
2
To 15 Other Channels
OE
CLK
LE
A1
Y1
1633416-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
559PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALVC3V
ALVCH3V
AVC3V UNIT
ICC MAX 0.04 0.04 0.04 mAIOH MAX -24 -24 -12 mAIOL MAX 24 24 12 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALVC3V
ALVCH3V
AVC3V
fmax MIN 150 150 150LE low 3.3 3.3 3.3CLK high or low MIN 3.3 3.3 3.3Data before CLK MIN 1.5 1.5 0.7Data before LE CLK high MIN 1.3 1.3 0.9Data before LE CLK low MIN 1.2 1.2 1Data after CLK MIN 0.9 0.9 0.7Data after LE CLK high MIN 1.1 1.1 1.5Data after LE CLK low MIN 1.1 1.1 1.3
A MAX 3.3 3.3 2.5
LE 4.4 4.4 4
CLK MAX 4.1 4.1 3.1ten OE Y 4.6 4.6 6.2tdis OE Y MAX 4.4 4.4 5.3UNIT fmax : MHz other : ns
tpd Y
tw Pulse duration
tsu Setup time
th Hold time
FUNCTION TABLE
INPUTS
XL
ACLK
L
L
OUTPUTY
Z
HH
OEH
L
X
LXX
L or H
L
† Output level before the indicated steady-state input conditions were established
LEX
HHL HHXL Y0†H
LL L
↑↑
560
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
56
29
28
1
21B1
31B2
51B3
61B4
8
OE4
OE3
OE2
OE1
1A
92B1
102B2
122B3
132B4
142A
163B1
173B2
193B3
203B4
153A
234B1
244B2
264B3
274B4
214A
345B1
335B2
315B3
305B4
365A
416B1
406B2
386B3
376B4
426A
487B1
477B2
457B3
447B4
437A
558B1
548B2
528B3
518B4
498A
163441-BIT TO 4-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS
561PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALVCH3V UNIT
ICC MAX 0.04 mAIOH MAX -24 mAIOL MAX 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALVCH3V
tPLH 4tPHL 4tPZH 5.1tPZL 5.1tPHZ 4tPLZ 4UNIT: ns
OE B MAX
A B MAX
OE B MAX
FUNCTION TABLEINPUTS
OE
H
LL
A
HLH
OUTPUTBn
Z
HL
562
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1637316-BIT TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
1OE
1LE
1D1
To Seven Other Channels
1Q1
2OE
2LE
2D12Q1
To Seven Other Channels
1
48
47
24
25
36C1
1D132C1
1D
563PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ABT LVTH3V
ALVTH3V AC ACT AHC AHCT LVC
3VLVCH
3VALVCH
3VAVC3V UNIT
ICC MAX 85 5 5 0.08 0.08 0.04 0.04 0.02 0.02 0.04 0.04 mAIOH MAX -32 -32 -32 -24 -24 -8 -8 -24 -24 -24 -12 mAIOL MAX 64 64 64 24 24 8 8 24 24 24 12 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ABT LVTH3V
ALVTH3V AC ACT AHC AHCT
tw Pulse duration, LE high or low MIN 3.3 3 1.5 4 1 5 6.5Data before LE , data high MIN 1.5 1 1.4 1.5 1 4 1.5Data before LE , data low MIN 1.5 1 0.9 1.5 1 4 1.5Data after LE , data high MIN 1 1 0.9 2.4 5 1 3.5Data after LE , data low MIN 1 1 1.4 2.4 5 1 3.5
tPLH 6.3 3.8 3.1 9.7 11.1 10.5 10.5tPHL 6.2 3.6 3.3 10.1 12.3 10.5 10.5tPLH 6.7 4.3 3.3 11.9 12.8 10.5 10.5tPHL 6.1 4 3.5 10.9 12.2 10.5 10.5tPZH 6.1 4.3 4 10.8 12.1 11.5 11.5tPZL 5.6 4.3 3.4 12.8 14.2 11.5 11.5tPHZ 8.1 5 4.9 8.8 10.7 11.5 12tPLZ 6.5 4.7 4.5 8.1 9.4 11.5 12
PARAMETER INPUT OUTPUT MAX or MIN LVC3V
LVCH3V
ALVCH3V
AVC3V
tw Pulse duration, LE high or low MIN 3.3 3.3 3.3 1.8
Data before LE , data high MIN 1.7 1.7 1.1 0.8
Data before LE , data low MIN 1.7 1.7 1.1 0.8
Data after LE , data high MIN 1.2 1.2 1.4 1
Data after LE , data low MIN 1.2 1.2 1.4 1tPLH 4.2 4.2 3.6 2.8tPHL 4.2 4.2 3.6 2.8tPLH 4.6 4.6 3.9 3.2tPHL 4.6 4.6 3.9 3.2tPZH 4.7 4.7 4.7 3.4tPZL 4.7 4.7 4.7 3.4tPHZ 5.9 5.9 4.1 3.9tPLZ 5.9 5.9 4.1 3.9UNIT: ns
OE Q MAX
OE Q MAX
th Hold time
tsu Setup time
MAX
MAX
D Q
QLE
tsu Setup time
th Hold time
D Q MAX
LE Q MAX
OE Q MAX
OE Q MAX
FUNCTION TABLE(each latch)
INPUTS
H
L
DH
X
OUTPUTQH
Z
L L
OE
H
X
LEL
XL QOL
H
564
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1OE
1CLK
1D1
To Seven Other Channels
1Q1
2OE
2CLK
2D12Q1
To Seven Other Channels
1
48
47
24
25
36C1
1D132C1
1D
1637416-BIT EDGE-TRIGGERD D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
565PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ABT LVTH3V
ALVTH3V AC ACT AHC AHCT LVC
3VLVCH
3VALVCH
3VAVC3V UNIT
ICC MAX 72 5 5 0.08 0.08 0.04 0.04 0.02 0.02 0.04 0.04 mAIOH MAX -32 -32 -32 -24 -24 -8 -8 -24 -24 -24 -12 mAIOL MAX 64 64 64 24 24 8 8 24 24 24 12 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ABT LVTH3V
ALVTH3V AC ACT AHC AHCT
fmax MIN 150 160 250 100 65 110 110CLK high 3.3 3 1.5 5 7.5 5 6.5CLK low 3.3 3 1.5 5 4.5 5 6.5
Data before CLK , data high 1.1 1.8 1 5 4.5 3 2.5
Data before CLK , data low 1.1 1.8 1.5 5 4.5 3 2.5
Data after CLK , data high 1.3 0.8 0.5 0 6.5 2 2.5
Data after CLK , data low 1.3 0.8 1 0 6.5 2 2.5tPLH 6.2 4.5 3.2 10.8 12.4 11.5 11.5tPHL 5.9 4 3.2 10.6 12.2 11.5 11.5tPZH 5.6 4.5 3.8 10.2 11.9 11.5 11.5tPZL 5.3 4.4 3.3 12.1 13.4 11.5 11.5tPHZ 8.2 5 4.6 8.2 10.4 11.5 12tPLZ 6.6 4.6 4.2 7.9 9.8 11.5 12
PARAMETER INPUT OUTPUT MAX or MIN LVC3V
LVCH3V
ALVCH3V
AVC3V
fmax MIN 150 150 150 200CLK high 3.3 3.3 3.3 2.5CLK low 3.3 3.3 3.3 2.5
Data before CLK , data high 1.9 1.9 1.9 1.4
Data before CLK , data low 1.9 1.9 1.9 1.4
Data after CLK , data high 1.9 1.1 0.5 1.1
Data after CLK , data low 1.9 1.1 0.5 1.1tPLH 4.5 4.5 4.2 3.3tPHL 4.5 4.5 4.2 3.3tPZH 4.6 4.6 4.8 3.4tPZL 4.6 4.6 4.8 3.4tPHZ 5.5 5.5 4.3 3.9tPLZ 5.5 5.5 4.3 3.9
UNIT fmax : MHz other : ns
OE Q MAX
MIN
Q MAX
tw Pulse duration MIN
OE
tw Pulse duration MIN
tsu Setup time MIN
th Hold time
OE Q MAX
MIN
CLK Q MAX
tsu Setup time
OE Q MAX
th Hold time MIN
CLK Q MAX
FUNCTION TABLE(each fllp-flop)
INPUTS
H
L
DH
X
OUTPUTQH
Z
L L
OE
X
CLKL
XH or L QOL
→→
566
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
Flow and Storage Control
One of Nine Channels
3 3
33
CLK
CLK
D
D
CLK
CLK
D
D
1Ax
2Ax
1Bx
2Bx
1Ax
1Bx2Bx
2Ax
1Bx2Bx
1Ax
2Ax1Bx
1Ax
2Ax2Bx
SEL2
SEL3
SEL4
1B
2B
CLK
SELEN
SEL0
SEL1
1A
2A
56
55
2
27
28
29
30
PRE1
164099-BIT, 4-PORT UNIVERSAL BUS EXCHANGER WITH 3-STATE OUTPUTS
567PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALVCH3V
ALVCHR3V
UNIT
ICC MAX 0.04 0.04 mAIOH MAX -24 -12 mAIOL MAX 24 12 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALVCH3V
ALVCHR3V
fmax MIN 120 120tw Pulse duration, CLK high or low MIN 3 3
A or B data before CLK MIN 1.4 1.4SEL before CLK MIN 3.5 3.5SELEN before CLK MIN 1.8 1.8PRE before CLK MIN 0.7 0.7A or B data after CLK MIN 1 1SEL after CLK MIN 0 0SELEN after CLK MIN 0.8 0.8
tpd CLK A or B MAX 5.1 6.2ten CLK A or B MAX 5.7 6.8
5.7 6.16.1 6.4
UNIT fmax : MHz other : ns
MAXA or B
tsu Setup time
th Hold time
tdis PRE
FUNCTION TABLEINPUTS OUTPUT
CLK SEND PORT RECEIVE PORT
X X B0†
X L
X H
↑ L
↑ H
L
H
L
H
H X †
L X B0
B0†
† Output level before the indicated steady-stateinput conditions were established
DATA-FLOW CONTROLINPUTS
PRE SELEN CLK SEL0 SEL1 SEL2 SEL3 SEL4
H X X X X X X X All outputs disabled
L H ↑ X X X X X No change
L L ↑ 0 0 0 0 0 None, all I/Os off
L L ↑ 0 0 0 0 1 Not used
L L ↑ 0 0 0 1 0 Not used
L L ↑ 0 0 0 1 1 Not used
L L ↑ 0 0 1 0 0 Not used
L L ↑ 0 0 1 0 1 Not used
L L ↑ 0 0 1 1 0 Not used
L L ↑ 0 0 1 1 1 Not used
L L ↑ 0 1 0 0 0 2A to 1A and 1B to 2B
L L ↑ 0 1 0 0 1 2A to 1A
L L ↑ 0 1 0 1 0 2B to 1B
L L ↑ 0 1 0 1 1 2A to 1A and 2B to 1B
L L ↑ 0 1 1 0 0 1A to 2A and 1B to 2B
L L ↑ 0 1 1 0 1 1A to 2A
L L ↑ 0 1 1 1 0 1B to 2B
L L ↑ 0 1 1 1 1 1A to 2A and 2B to 1B
L L ↑ 1 0 0 0 0 1A to 1B and 2B to 2A
L L ↑ 1 0 0 0 1 1A to 1B
L L ↑ 1 0 0 1 0 2A to 2B
L L ↑ 1 0 0 1 1 1A to 1B and 2A to 2B
L L ↑ 1 0 1 0 0 1B to 1A and 2A to 2B
L L ↑ 1 0 1 0 1 1B to 1A
L L ↑ 1 0 1 1 0 2B to 2A
L L ↑ 1 0 1 1 1 1B to 1A and 2B to 2A
L L ↑ 1 1 0 0 0 2B to 1A and 2A to 1B
L L ↑ 1 1 0 0 1 1B to 2A
L L ↑ 1 1 0 1 0 2B to 1A
L L ↑ 1 1 0 1 1 2B to 1A and 1B to 2A
L L ↑ 1 1 1 0 0 1A to 2B and 1B to 2A
L L ↑ 1 1 1 0 1 1A to 2B
L L ↑ 1 1 1 1 0 2A to 1B
L L ↑ 1 1 1 1 1 1A to 2B and 2A to 1B
DATA FLOW
568
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
LED
CLKCE
LED
CLKCE
CLKCE
DLE
CLKCE
DLE
LECLKCED
LECLKCED
LECLKCED
LECLKCED
MUX
CECLK
DLE
P
CE_SEL0
CE_SEL1
CLKENAB
1B1
1B2
1B3
1B4
CLKENAB Selector
One of FourChannels
CLKAB
OEA
1A
OEB
OEB4
OEB3
OEB2
OEB1
CLKENBA
CLKBA
LEBA
SEL0
SEL1
CLKENB
LEB1
LEB2
LEB3
LEB4 LEAB4
LEAB3
LEAB2
LEAB1
24
23
6
5
31
54
3
8
21
10
26
12
48
49
51
52
19
15
14
9
29
30
55
56
1
2
27
28
20
164604-TO-1 MULTIPLEXED/DEMULTIPLEXED TRANSCEIVERS WITH 3-STATE OUTPUTS
569PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
SWITCHING CHARACTERISTICS
MAX or MIN ABTH
fmax MIN 160CLKAB high or low MIN 3.8CLKBA high or low MIN 4.5LEAB1, 2, 3 or 4 high MIN 2.2LEBA high MIN 2.1LEB1, 2, 3 or 4 high MIN 2.4
A bus MIN 2.5CE_SEL0/1 MIN 3.2CLKENAB MIN 3.2
Before LEAB1, 2, 3, or 4 A bus MIN 3.6B bus MIN 3.8CLKENB MIN 2.3CLKENBA MIN 2.5LEB1, 2, 3 or 4 MIN 4.3SEL0/1 MIN 4.5
Before LEB1, 2, 3, or 4 B bus MIN 3.2B bus MIN 4LEB1, 2, 3 or 4 MIN 4.4SEL0/1 MIN 4.3A bus MIN 0.5
CE_SEL0/1 MIN 1.1
CLKENAB MIN 0.5
after LEAB1, 2, 3, or 4 A bus MIN 1.2B bus MIN 1.3
CLKENB MIN 1
CLKENBA MIN 1SEL0/1 MIN 0
after LEB1, 2, 3, or 4 B bus MIN 1.5B bus MIN 0.4SEL0/1 MIN 0.1
Before CLKBA
th Hold time
after CLKAB
after CLKBA
after CLKBA
tsu Setup time
PARAMETER
tw Pulse duration
Before CLKAB
Before CLKBA
PARAMETER INPUT OUTPUT MAX or MIN ABTH
tPLH 6.5tPHL 6.5tPZH 5.6tPZL 5.2tPHZ 5.9tPLZ 6.5tPLH 5.7tPHL 5.7tPZH 6.4tPZL 6.3tPHZ 7tPLZ 6.1tPZH 5.8tPZL 5.6tPHZ 6.1tPLZ 5.3tPLH 7.4tPHL 7.7tPLH 6.2tPHL 5.9tPLH 5.6tPHL 5.3tPLH 5.8tPHL 5.6tPLH 7.2tPHL 6.8tPLH 7.5tPHL 6.9UNIT fmax : MHz other : ns
LEBA1, 2, 3, 4 A MAX
SEL A MAX
LEBA A MAX
LEAB1, 2, 3, 4 B MAX
CLKBA A MAX
CLKAB B MAX
OEB1, 2, 3, 4 B MAX
OEB1, 2, 3, 4 B MAX
OEB B MAX
OEB B MAX
OEA A MAX
A B MAX
B A MAX
OEA A MAX
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ABTH UNIT
ICC MAX 32 mAIOH MAX -32 mAIOL MAX 64 mA
FUNCTION TABLE
INPUTS
H
LH
L
OUTPUTBnOEB
H
HL
L
OEBn
ZZZ
A-TO-B OUTPUT ENABLE
INPUTS
HLLLLL
OUTPUTSCLKENAB
XX
A0A0A0
A0
H or LH or L
L
CLKAB
HLHL
CE_SEL0XXX
XH
LH
L
CE_SEL1XXX
X
H
LH
LL
LEAB1
HL
LEAB2
HL
L L
LEAB3LLLLLL
LEAB4 B1
A0A
A
B2
A0A
B3
A0A
AA
A
B4
A0
A0 A0 A0A0
A0 A0 A0A0
A0A0
A0A0A0A0
A0
A0
A
A-TO-B OUTPUT ENABLE(assuming OEB = L, OEBn = L) ‡
Active
‡ Output level before the indicated steady-state input conditions were established
†n = 1, 2, 3, 4
→
L
L L
L
→
L
L L
L
→
L
L L
→ L LL L→
INPUTS
X
LLLH
OUTPUTACLKENBA
XX
XXXX
L
CLKBAX XHHLL
LEBAHL
OEA
HL
X
XHL
L
B
HL
A0†
HL
A0†
Z
B-TO-A STORAGE(after point P)
L
L
→
L
L
→ LL
INPUTS
L
L
PCLKENBXX
XXXX
L
CLKBAH
L
LEB1
B1
B40†B30†B20†B10†
B1
B2
B2
B3
B3
B4
B4
B-TO-A STORAGE(after point P)
L
L
H
L
LEB2
L
L
HL
L LLL
L LLEB3
L
L
H
L
XL
XL
LEB4
L
L
H
H
H
LSEL1
L
L
H
H
H
HH
L
H
L
H
HH
L
SEL0
L
L
L
L
L
L
→
570
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
C1
1D
1D
C1
56
54
55
1
3
2
5 52
To Seven Other Channels
C1
1D
1D
C1
29
31
30
28
26
27
15 42
To Seven Other Channels
1B1
1OEBA
1CLKENBA
1CLKBA
1OEAB
1CLKENAB
1CLKAB
1A1
2B1
2OEBA
2CLKENBA
2CLKBA
2OEAB
2CLKENAB
2CLKAB
2A1
1647016-BIT REGISTERD TRANSCEIVERS WITH 3-STATE OUTPUTS
571PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
FUNCTION TABLE
INPUTS
H
L
OUTPUTB
H
B0‡X
L
CLKENAB
→† A-to-B data flow is shown: B-to-A flow is similar but
uses CLKENBA, CLKBA, and OEBA.‡ Output level before the indicated steady-state input
conditions were established.
L
CLKABX
HL
X
HL
A
X
OEAB
LL
X
→
LL
XX
ZZ
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ABT ACT UNIT
ICC MAX 35 0.08 mAIOH MAX -32 -24 mAIOL MAX 64 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ABT ACT
fmax MIN 150 55tw Pulse duration, CLKAB or CLKBA high MIN 3.3 4tw Pulse duration, CLKAB or CLKBA low 3.3 8.5tsu Setup time, data before CLKAB or CLKBA MIN 4 6th Hold time, data after CLKAB or CLKBA MIN 1 1tPLH 4.9 11.8tPHL 4.9 11.7tPZH 4.9 11.9tPZL 6.8 13.4tPHZ 5.5 9.9tPLZ 5.3 9.5tPZH 5.7 12.5tPZL 7.2 14.3tPHZ 5.8 11.2tPLZ 5.4 10.9UNIT fmax : MHz other : ns
CLKEN A or B MAX
OE A or B MAX
CLKEN A or B MAX
CLK A or B MAX
OE A or B MAX
572
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1DC1
CLK
1D
C1CLK
B1
OEAB
CLKAB
LEAB
LEBA
CLKBA
OEBA
A1
1
55
2
28
30
27
354
To 17 Other Channels
1650018-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
573PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
FUNCTION TABLE
INPUTS
H
OUTPUTB
H
B0‡
XL
LEAB
† A-to-B data flow is shown: B-to-A flow is similar but uses OEBA, LEBA, and CLKBA.
‡ Output level befor the indicated steady-state input conditions were established.
§ Output level before the indicated steady-state input conditions were established, provided that CLKAB was low before LEAB went low.
LOEAB
H
X
HL
A
X
CLKAB
L
L LX
X Z
LL
→HHHHHHH
→
HLX
X
B0§
HL
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ABT LVTH3V
ALVCH3V UNIT
ICC MAX 36 5 0.04 mAIOH MAX -32 -32 -24 mAIOL MAX 64 64 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ABT LVTH3V
ALVCH3V
fmax MIN 150 150 150LEAB or LEBA high 2.5 3.3 3.3CLKAB or CLKBA high or low 3 3.3 3.3A before CLKAB 3 2.9 1.3B before CLKBA 3 2.9 1.3A before LEAB or LEBA CLK high 1 1.4 1A before LEAB or LEBA CLK low 2.5 2.9 1.4A after CLKAB or B after CLKBA 0 0.4 1.3A after LEAB or B after LEBA high 2 1.6 1.5A after LEAB or B after LEBA low 2 1.6 1.2
tPLH 4 3.7 3.9tPHL 4.9 3.7 3.9tPZH 5 5.1 4.7tPZL 5 5.1 4.7tPHZ 5.3 5 5.5tPLZ 5.3 5 5.5tPZH 5.1 4.8 4.6tPZL 5.4 4.8 4.6tPHZ 6.5 5.8 5tPLZ 5.4 5.8 5tPZH 5.1 4.8 5.2tPZL 5.4 4.8 5.2tPHZ 6.5 5.8 4.3tPLZ 5.4 5.8 4.3UNIT fmax : MHz other : ns
OEBA A MAX
OEAB B MAX
OEBA A MAX
CLKAB or CLKBA B or A MAX
OEAB B MAX
A or B B or A MAX
LEAB or LEBA B or A MAX
th Hold time MIN
tw Pulse duration
tsu Setup time
MIN
MIN
574
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1DC1
CLK
1D
C1CLK
B1
OEAB
CLKAB
LEAB
LEBA
CLKBA
OEBA
A1
1
55
2
28
30
27
354
To 17 Other Channels
1650118-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
575PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
FUNCTION TABLE
INPUTS
H
OUTPUTB
H
B0‡
XL
LEAB
† A-to-B data flow is shown: B-to-A flow is similar but uses OEBA, LEBA, and CLKBA.
‡ Output level before the indicated steady-state input conditions were established, provided that CLKAB was high before LEAB went low.
§ Output level before the indicated steady-state input conditions were established.
LOEAB
H
X
HL
A
X
CLKAB
L
L LX
X Z
LL
HHHHHHH
HLX
X
B0§
HL→
→
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ABT LVTH3V
ALVCH3V UNIT
ICC MAX 76 5 0.04 mAIOH MAX -32 -32 -24 mAIOL MAX 64 64 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ABT LVTH3V
ALVCH3V
fmax MIN 105 150 150LEAB or LEBA high MIN 3.3 3.3 3.3CLKAB or CLKBA high or low MIN 4.7 3.3 3.3A before CLKAB MIN 3.5 2.1 1.7B before CLKBA MIN 3.5 2.1 1.7A before LEAB or LEBA CLK high MIN 4 2.4 1.5A before LEAB or LEBA CLK low MIN 1.5 1.4 1A after CLKAB or B after CLKBA MIN 1 1 0.7A after LEAB or B after LEBA MIN 2.5 1.7 1.4
tPLH 3.7 3.7 3.9tPHL 4 3.7 3.9tPZH 5.1 5.1 4.6tPZL 4.4 5.1 4.6tPHZ 5 5.1 4.9tPLZ 4.4 5.1 4.9tPZH 4.7 4.8 4.6tPZL 6.5 4.8 4.6tPHZ 5.8 5.8 5tPLZ 4.9 5.8 5tPZH 4.7 4.8 5tPZL 6.5 4.8 5tPHZ 5.8 5.8 4.2tPLZ 4.9 5.8 4.2UNIT fmax : MHz other : ns
tw Pulse duration
MAX
LEAB or LEBA MAX
tsu Setup time
th Hold time
CLKAB or CLKBA MAX
OEBA
B
MAX
B
MAX
MAX
OEBA A MAX
A or B B or A
B or A
B or A
A
OEAB
OEAB
576
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
B1
CLK
CLKENBA
OEAB
OEBA
SEL
CE
C11DA1
CE
C11D
CE
C11D
CE
C11D
1
1
1 of 18 Channels
G1
30
28
2
27
55
3 54
1652418-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS
577PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
FUNCTION TABLE
† Output level before the indicated steady-state input conditions were established
‡ Four positive CLK edges are needed to propagate data from B to A when SEL is low.
INPUTS
H
LLLL
OUTPUTACLKENBA
X XCLK
X
HH
SEL
HL
HL
B
HLA0†
H‡L‡
B-TO-A STORAGE (OEBA = L)
L→→
→L→
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALVCH3V
fmax MIN 150tw Pulse duration, CLK high or low MIN 3
B data before CLK MIN 1.1SEL before CLK MIN 2.1CLKENBA before CLK MIN 2B data after CLK MIN 1.2SEL after CLK MIN 0.8CLKENBA after CLK MIN 0.3
A B 3.2
CLK A 5.2ten OEAB or OEBA A or B 5.1tdis OEAB or OEBA A or B 4.9UNIT fmax : MHz other : ns
tsu Setup time
th Hold time
MAX
MAX
tpd
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALVCH3V UNIT
ICC MAX 0.04 mAIOH MAX -24 mAIOL MAX 24 mA
578
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
B1
CLKAB
CLK1BA
CLK2BA
CLKENBA
CLKENAB
OEAB
OEBA
SEL
CE
C1
1DA1
CE
C1
1D
CE
C11D
CE
C11D
CE
C11D
1
1
1 of 18 Channels
G1
55
30
29
28
1
2
27
56
3 54
1652518-BIT REGISTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS
579PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
INPUTS
XA
HL
B0†
H
CLKENAB CLKABH X
LL
→→ L
A-TO-B STORAGE (OEAB = L)
† Output level before the indicated steady-state input conditions were established
FUNCTION TABLE
INPUTS
XBCLK2BA CLK1BA
HL
A0†
HL
CLKENA SELH X
H
L
H
L
X
LLL
L‡
L
→
X
→
X
→→
→
H
X
H‡→
L
B-TO-A STORAGE (OEBA = L)
OUTPUTB
OUTPUTA
† Output level before the indicated steady-state input conditions were established
‡ Three CLK1BA edges and one CLK2BA edge are needed to propagate data from B to A when SEL is low.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALVCH3V UNIT
ICC MAX 0.04 mAIOH MAX -24 mAIOL MAX 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALVCH3V
fmax MIN 150tw Pulse duration, CLK high or low MIN 3
A data before CLKAB MIN 1.3B data before CLK2BA MIN 1.7B data before CLK1BA MIN 1.1SEL before CLK2BA MIN 3.3CLKENAB before CLKAB MIN 1.6CLKENBA before CLK1BA MIN 2.1CLKENBA before CLK2BA MIN 2.2A data after CLKAB MIN 0.9B data after CLK2BA MIN 0.6B data after CLK1BA MIN 1SEL after CLK2BA MIN 0.1CLKENAB after CLKAB MIN 0.3CLKENBA after CLK1BA MIN 0.1CLKENBA after CLK2BA MIN 0
tpd CLKAB or CLK2BA A or B 4.2ten OEAB or OEBA A or B 5.1tdis OEAB or OEBA A or B 4.9UNIT fmax : MHz other : ns
MAX
tsu Setup time
th Hold time
580
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1OE1
1OE2
2OE1
2OE2
1A1 1Y1 2Y12A1
To Seven Other Channels To Seven Other Channels
1
48
47
24
25
362 13
1654016-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
FUNCTION TABLE(each 8-bit section)
INPUTS
H
L
A
H
X
OUTPUTYH
ZX
L
OE2
HL
X
OE1L LL
X Z
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ABT ACT AHC AHCT LVCH3V UNIT
ICC MAX 34 0.08 0.04 0.04 0.02 mAIOH MAX -32 -24 -8 -8 -24 mAIOL MAX 64 24 8 8 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ABT ACT AHC AHCT LVCH3V
tPLH 4.1 7.5 8.5 10.5 3.7tPHL 4.3 9.5 8.5 10.5 3.7tPZH 5.1 8.9 10.5 13 4.8tPZL 5.9 10.5 10.5 13 4.8tPHZ 5.7 11.9 10.5 13 5.9tPLZ 4.7 11.1 10.5 13 5.9UNIT: ns
OE Y MAX
A Y MAX
OE Y MAX
581PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
Logic Diagram
1654116-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
1OE1
1OE2
2OE1
2OE2
1A1 1Y1 2Y12A1
To Seven Other Channels To Seven Other Channels
1
48
47
24
25
362 13
FUNCTION TABLE(each 8-bit section)
INPUTS
H
L
A
H
X
OUTPUTY
H
ZX
LOE2
HL
X
OE1L LL
X Z
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ABT LVTH3V ACT AHC AHCT LVCH
3V UNIT
ICC MAX 34 5 0.08 0.04 0.04 0.02 mAIOH MAX -32 -32 -24 -8 -8 -24 mAIOL MAX 64 64 24 8 8 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ABT LVTH3V ACT AHC AHCT LVCH
3V
tPLH 3.4 3.5 9 8.5 10.5 4.2tPHL 4.2 3.5 9.2 8.5 10.5 4.2tPZH 5.2 4.6 9.7 10.5 13 5.6tPZL 6 4.6 11 10.5 13 5.6tPHZ 5.4 5.9 11.3 10.5 13 6.8tPLZ 4.3 5.4 10.7 10.5 13 6.8UNIT: ns
OE Y MAX
A Y MAX
OE Y MAX
582
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1OEBA
1CEBA
1LEBA
1OEAB
1CEAB
1LEAB
1A11B1
To Seven Other Channels
2OEBA
2CEBA
2LEBA
2OEAB
2CEAB
2LEAB
2A12B1
To Seven Other Channels
56
54
55
1
3
2
5
29
31
30
28
26
27
15
C1
1D
C1
1D
C1
1D
C1
1D 42
52
1654316-BIT REGISTERD TRANSCEIVERS WITH 3-STATE OUTPUTS
583PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
FUNCTION TABLE(each 8-bit section)
INPUTS OUTPUTB
B0‡
X
† A-to-B data flow is shown: B-to-A flow control is the same except that it uses CEBA, LEBA, and OEBA.
‡ Output level before the indicated steady-state input conditions were established.
LHX
HL
AOEAB
LL
X Z
L
H
H
HL
OEAB LEAB
X X
L L
X Z
L L
X
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ABT LVTH3V AC ACT LVC
3VLVCH
3VALVCH
3V UNIT
ICC MAX 35 5 0.08 0.08 0.04 0.02 0.04 mAIOH MAX -32 -32 -24 -24 -24 -24 -24 mAIOL MAX 64 64 24 24 24 24 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ABT LVTH3V AC ACT LVC
3VLVCH
3VALVCH
3V
tw Pulse duration, LEAB or LEBA low MIN 4 3.3 4 7.5 4 3.3 3.3Data before LEAB or LEBA , high MIN 1.5 0.5 1 2.5 2 1.1 1.2Data before LEAB or LEBA , low MIN 3.5 0.8 1 2.5 2 1.1 1.2Data before CEAB or CEBA , high MIN - 0 - - 2 1.1 1.2Data before CEAB or CEBA , low MIN - 0.6 - - 2 1.1 1.2Data after LEAB or LEBA , high MIN 1.5 1.5 3 4 2 1.9 1.3Data after LEAB or LEBA , low MIN 2 1.2 3 4 2 1.9 1.3Data after CEAB or CEBA , high MIN - 1.7 - - 2 1.9 1.3Data after CEAB or CEBA , low MIN - 1.6 - - 2 1.9 1.3
tPLH 3.8 3.2 8.8 10.5 8 5.4 4.3tPHL 5.1 3.2 9.2 11.6 8 5.4 4.3tPLH 5.2 3.9 11.5 13.8 9 6.1 5tPHL 5.6 3.9 10.9 13.5 9 6.1 5tPZH 5.2 4.3 9.6 11.4 8.5 6.3 5.3tPZL 7 4.3 11.3 13.2 8.5 6.3 5.3tPHZ 5.7 4.7 8.9 11.1 8.5 6.3 4.6tPLZ 4.6 4.4 8.4 9.6 8.5 6.3 4.6tPZH 6.2 4.5 9.8 11.7 9 6.6 5.6tPZL 7.8 4.5 11.5 13.5 9 6.6 5.6tPHZ 6.6 4.9 9.3 11.6 9 6.6 5.1tPLZ 5.4 4.7 8.8 10.5 9 6.6 5.1UNIT: ns
MAX
MAXA or B B or A
OE A or B MAX
LE A or B MAX
CE A or B MAX
tsu Setup time
th Hold time
OE A or B MAX
CE A or B
584
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
CE
1DC1
CLK
CE
1D
C1CLK
B1
OEAB
CLKENAB
CLKAB
LEAB
LEBA
CLKBA
CLKENBA
OEBA
A1
1
56
55
2
28
30
29
27
354
To 17 Other Channels
1660018-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
585PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
FUNCTION TABLE
INPUTS
H
OUTPUTB
H
B0‡
XL
† A-to-B data flow is shown: B-to-A flow is similar but uses OEBA, LEBA, CLKBA and CLKENBA.
‡ Output level before the indicated steady-state input conditions were established.
§ Output level before the indicated steady-state input conditions were established, provided that CLKAB was low before LEAB went low.
H
X
HL
A
X
L
L
LX
X Z
LL
HHH
HLX
X
B0§
HL
LH
CLKENAB OEAB LEAB CLKABX
L
→ XX
B0‡B0‡
L
XL
X
L
→
L
XL
X
L
L
L
LLLL
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ABT ALVCH3V UNIT
ICC MAX 36 0.04 mAIOH MAX -32 -24 mAIOL MAX 64 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ABT ALVCH3V
fmax MIN 150 150tw Pulse duration LEAB or LEBA high MIN 2.5 3.3
CLKAB or CLKBA high or low MIN 3 3.3tsu Setup time A before CLKAB or B before CLKBA MIN 3 -
Data before CLK - 1.2
A before LEAB or B before LEBA , CLK high MIN 2.5 1.1
A before LEAB or B before LEBA , CLK low MIN 2.5 1.5
CLKEN after CLK 2.5 -
CLKEN after CLK MIN 2.5 0.8th Hold time A after CLKAB or B after CLKBA MIN 0 -
Data after CLK - 1.5
A after LEAB or B after LEBA , CLK high MIN 2 1.6
A after LEAB or B after LEBA , CLK low MIN 2 1.3
CLKEN after CLK 1 -
CLKEN after CLK MIN - 1.4tPLH 4 4tPHL 4.9 4tPLH 5 4.8tPHL 5 4.8tPLH 5.3 5.7tPHL 5 5.7tPZH 5.1 5.2tPZL 5.4 5.2tPHZ 6.2 4.4tPLZ 5.4 4.4tPZH 5.1 5.2tPZL 5.4 5.2tPHZ 6.2 4.4tPLZ 5.4 4.4UNIT fmax : MHz other : ns
OEBA A MAX
OEBA A MAX
A or B MAX
OEAB
B or A
MAX
B or A
MAX
MAX
B or A
LEAB or LEBA
CLKAB or CLKBA
OEAB B MAX
B
586
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
CE
1DC1
CLK
CE
1D
C1CLK
B1
OEAB
CLKENAB
CLKAB
LEAB
LEBA
CLKBA
CLKENBA
OEBA
A1
1
56
55
2
28
30
29
27
354
To 17 Other Channels
1660118-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
587PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
FUNCTION TABLE
INPUTS
H
OUTPUTB
H
B0‡
XL
† A-to-B data flow is shown: B-to-A flow is similar but uses OEBA, LEBA, CLKBA and CLKENBA.
‡ Output level before the indicated steady-state input conditions were established.
§ Output level before the indicated steady-state input conditions were established, provided that CLKAB was low before LEAB went low.
L
X
HL
A
X
L
L
HX
X Z
LL
HHH
HLX
X
B0§
HL
LH
CLKENAB OEAB LEAB CLKABX
LXX
B0‡B0‡
L
XL
X
L
L
XL
X
L
L
L
LLLL
→→
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ABT ALVTH3V
ALVCH3V
ALVCHR3V UNIT
ICC MAX 36 5 0.04 0.04 mAIOH MAX -32 -32 -24 -12 mAIOL MAX 64 64 24 12 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ABT ALVTH3V
ALVCH3V
ALVCHR3V
fmax MIN 150 150 150 150
LEAB or LEBA high MIN 2.5 1.8 3.3 3.3
CLKAB or CLKBA high or low MIN 3 2.3 3.3 3.3
Data before CLK high 4 2.4 2.1 2.1
Data before CLK low 4 3.8 2.1 2.1
A before LEAB or B before LEBA , CLK high MIN 2.5 1 1.6 1.6
A before LEAB or B before LEBA , CLK low MIN 1 0.6 1.1 1.1
CLKEN before high 2.5 1.4 1.7 1.7
CLKEN before low 2.5 1.9 1.7 1.7
Data after CLK high 0 0.5 0.8 0.8
Data after CLK low 0 0.5 0.8 0.8
A after LEAB or B after LEBA , CLK high MIN 2 2 1.4 1.4
A after LEAB or B after LEBA , CLK low MIN 2 2.3 1.7 1.7
CLKEN after high 0 0.6 0.6 0.6
CLKEN after low 0 0.5 0.6 0.6tPLH 4 3.9 4.1 4.4tPHL 4.9 3.9 4.1 4.4tPLH 5 4.6 4.7 5.1tPHL 5.2 4.6 4.7 5.1tPLH 4.7 4.5 5 5.4tPHL 4.6 4.6 5 5.4tPZH 5.5 4.2 5.2 5.6tPZL 5.8 4.4 5.2 5.6tPHZ 6.2 5.3 4.4 4.7tPLZ 5.4 4.6 4.4 4.7tPZH 5.5 4.2 5.2 5.6tPZL 5.8 4.4 5.2 5.6tPHZ 6.2 5.3 4.4 4.7tPLZ 5.4 4.6 4.4 4.7
UNIT fmax : MHz other : ns
OEBA A MAX
A or B B or A
B or A
B or A
A
OEAB
OEAB
CLKAB or CLKBA MAX
OEBA
B
MAX
B
MAX
MAX
tw Pulse duration
MAX
LEAB or LEBA MAX
tsu Setup time
th Hold time
MIN
MIN
MIN
MIN
588
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
2B113
2A1
2OEAB
2OEBA
36
24
25
1B12
1A1
1OEAB
1OEBA
47
1
48
To Seven Other ChannelsTo Seven Other Channels
1662016-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
589PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
FUNCTION TABLE
INPUTS
L
L
OEAB
H
OPERATION
LOEBA
B data to A bus
A data to B bus
H Isolation
B data to A bus,A data to B bus
H H
L
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN AC ACT UNIT
ICC MAX 0.08 0.08 mAIOH MAX -24 -24 mAIOL MAX 24 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN AC ACT
tPLH 6.8 8.5tPHL 8.2 10.5tPLH 6.8 8.5tPHL 8.2 10.5tPZH 7.9 9.1tPZL 9.4 10.9tPHZ 9.2 11.9tPLZ 8.3 10.6tPZH 7.3 8.9tPZL 9.1 10.5tPHZ 9 10.8tPLZ 8 9.6UNIT: ns
OEAB B MAX
A
A
OEAB B MAX
OEBA MAX
A B MAX
OEBA MAX
B A MAX
590
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
To Seven Other Channels
48
1
47
2
1OEBA
1OEBA
1OEBA
1B1
To Seven Other Channels
25
24
36
13
2OEBA
2OEBA
2OEBA
2B1
1662316-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
FUNCTION TABLE(each 8-bit section)
INPUTS
H
LOEAB
H
OPERATION
LOEBA
B data to A bus
A data to B busH Isolation
L H
L
B data to A bus, A data to B bus
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ABT ACT UNIT
ICC MAX 35 0.08 mAIOH MAX -32 -24 mAIOL MAX 64 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ABT ACT
tPLH 3.6 7.7tPHL 4.3 8.6tPZH 4.9 9.5tPZL 6 11.1tPHZ 6 12tPLZ 5.4 10.7tPZH 4.9 9.3tPZL 6 10.6tPHZ 6 10.4tPLZ 5.4 9.5UNIT: ns
OEAB B MAX
OEAB B MAX
OEBA A MAX
A or B B or A MAX
OEBA A MAX
591PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
Logic Diagram
1OE
1DIR
1A1 1B1247
1
48
To Seven Other Channels
2OE
2DIR
2A1 2B11336
24
25
To Seven Other Channels
1664016-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
FUNCTION TABLE(each 8-bit section)
INPUTS
L
DIR OPERATION
L
OE
H IsolationL H
X
B data to A busA data to B bus
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ABT AC ACT UNIT
ICC MAX 32 0.08 0.08 mAIOH MAX -32 -24 -24 mAIOL MAX 64 24 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ABT AC ACT
tPLH 4.3 7.3 9.1tPHL 3.9 8.6 10.5tPZH 5.5 8 9.8tPZL 6.3 9.9 11.5tPHZ 6.3 9.9 12.5tPLZ 4.2 9 11UNIT: ns
OE A or B MAX
A or B B or A MAX
OE A or B MAX
592
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1A11B1
1D
C1
1D
C1
One of Eight Channels
525
3
2
54
55
56
1
1SAB
1CLKAB
1SBA
1CLKBA
1DIR
1OE
To Seven Other Channels
2A12B1
1D
C1
1D
C1
4215
26
27
31
30
29
28
2SAB
2CLKAB
2SBA
2CLKBA
2DIR
2OE
To Seven Other Channels
One of Eight Channels
1664616-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
593PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
FUNCTION TABLE
INPUTSSBASAB OPERATION OR FUNCTION
Store B, A unspecitied †X Store A, B unspecitied †
→
† The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled; i.e., data at the bus pins will be stored on every low-to-high transition of the clock inputs.
X
L
DATA I/O
Isolation, hold storageStore A and B data
Stored B data to A busReal-time B data to A bus
Stored A data to B busReal-time A data to B bus
A1 THRU A8Input
Unspecified †
OutputOutputInputInput
InputInput disabled
B1 THRU B8
InputUnspecified †
OutputOutput
InputInput
InputInput disabled
CLKBAX
CLKAB
X
H or LL
H
DIRXX
HL
H
L
XX
L
L
L
H
OE
XX
H or L
H or L
H or L
→
→
→
X
XX
X
XX H
XXXX
XX
LH
XX
XX
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ABT LVTH3V AC ACT LVCH
3VALVCH
3V AVC UNIT
ICC MAX 32 5 0.08 0.08 0.02 0.04 0.04 mAIOH MAX -32 -32 -24 -24 -24 -24 -12 mAIOL MAX 64 64 24 24 24 24 12 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ABT LVTH3V AC ACT LVCH
3VALVCH
3V AVC
fmax MIN 125 150 75 90 150 150 350tw Pulse duration CLKAB or CLKBA high or low MIN 4.3 3.3 6.5 5.5 3.3 3.3 1.4
A or B before CLKAB or CLKBA , data high MIN 3 1.2 5 4 2.9 1.4 0.8
A or B before CLKAB or CLKBA , data low MIN 3 2 5 6 2.9 1.4 0.8
A or B after CLKAB or CLKBA , data high MIN 0 0.5 1 1.5 0.3 0.7 0.6
A or B after CLKAB or CLKBA , data low MIN 0 0.5 1 1.5 0.3 0.7 0.6tPLH 4.9 4.2 12.1 12.2 6.7 4.5 3.3tPHL 4.7 4.2 11.9 12.3 6.7 4.5 3.3tPLH 3.9 3.4 9.5 10.6 5.7 3.9 2.6tPHL 4.6 3.4 9.7 11.4 5.7 3.9 2.6tPLH 5 4.5 12.5 15.6 7.7 5.3 4tPHL 5 4.5 13.1 16.7 7.7 5.3 4tPZH 5.5 4.3 10.5 11.9 6.9 5.1 4tPZL 5.7 4.3 12.2 13.5 6.9 5.1 4tPHZ 5.4 5.6 8.9 10.2 6.9 4.7 4.2tPLZ 4.5 5.4 8.6 9.9 6.9 4.7 4.2tPZH 5.4 4.4 10.9 15.2 7.2 5.1 4.3tPZL 5.6 4.4 12.2 13.1 7.2 5.1 4.3tPHZ 6.7 5.7 9.4 10.8 7 5.3 4.3tPLZ 5.9 5.2 8.8 10.4 7 5.3 4.3
UNIT fmax : MHz other : ns
DIR A or B MAX
A or B B or A
MAX
MAX
MAX
MAX
MAX
B or A
A or B
OE
OE
SAB or SBA
DIR
A or B
A or B
MAX
tsu Setup time
th Hold time
B or ACLKAB or CLKBA
594
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
TG
TG
TG
TG
C1
1D
C1
1D
1OEBA
1OEAB
1CLKBA
1SBA
1CLKAB
1SAB
1A1
1B1
To Seven Other Channels
56
1
55
54
2
3
5
52
TG
TG
TG
TG
C1
1D
C1
1D
2OEBA
2OEAB
2CLKBA
2SBA
2CLKAB
2SAB
2A1
2B1
To Seven Other Channels
29
28
30
31
27
26
15
42
1665116-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
595PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
FUNCTION TABLE
INPUTS
X
X
CLKABOEAB
XX
X
OPERATION OR FUNCTION
IsolationStore A and B data
Store A data to B bus and
Store A, hold B
Store B data to A bus
Store A data to B bus
Store A in both registersHold A, store B
Store B in both registersReal-time B data to A bus
Real-time A data to B busL
L
L
LCLKBA
X
XX
L
L
SAB
H
H H
X
L
SBA
H
XX XX XX‡
XX‡
XX
X
XXX
X
L
OEBA
HH
HHHH
L
LL
L
DATA I/O †B1-B8A1-A8
InputOutput
Unspecified‡Output
Output
Output
Output
Output
InputInput
Output InputOutput Input
Unspecified‡ Input
Input
Input
Input
Input InputInput
† The data-output functions may be enabled or disabled by a variety of level combinations at OEAB or OEBA. Data-input functions arealways enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs.
‡ Select control = L; clocks can occur simultaneously.Select control = H; clocks must be staggered to load both registers.
LH
H
H
H
L
LL
LL
→→
→ L
L
→→
→ →→
Store B data to A bus
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ACT UNIT
ICC MAX 0.08 mAIOH MAX -24 mAIOL MAX 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ACT
fmax MIN 90tw Pulse duration CLKAB or CLKBA high or low MIN 5.5tsu Setup time A before CLKAB or B before CLKBA MIN 5.3th Hold time A after CLKAB or B after CLKBA MIN 1tPLH 11.3tPHL 11.9tPLH 13.7tPHL 13.6tPLH 17.3tPHL 17.8tPZH 12.3tPZL 13.9tPHZ 10.6tPLZ 10.8tPZH 11.9tPZL 13.5tPHZ 11.4tPLZ 11.6
UNIT fmax : MHz other : ns
MAX
OEBA
A or B
A or B
A
A
CLKAB or CLKBA
B
OEBA
SAB or SBA
OEAB
OEAB B MAX
A or B B or A
MAX
MAX
MAX
MAX
MAX
596
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1A11B1
One of Eight Channels
1SAB
1CLKAB
1SBA
1CLKBA
1OEAB
1OEBA
To Seven Other Channels
2A12B1
One of Eight Channels
2SAB
2CLKAB
2SBA
2CLKBA
2OEAB
2OEBA
To Seven Other Channels
1
55
54
2
3
5
29
28
30
31
27
26
15
1D
C1
1DC1
52
56
42
1D
C1
1DC1
1665216-BIT BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
597PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
FUNCTION TABLE
INPUTSSBASAB OPERATION OR FUNCTION
Store B in both registers
X
→
† The data output functions may be enabled or disabled by a variety of level combinations at the OEAB or OEBA inputs. Data input functions are always enabled; i.e., data at the bus pins is stored on every low-to-high transition of the clock inputs.
‡ Select control = L; clocks can occur simultaneously.Select control = H; clocks must be staggered in order to load both registers.
X
DATA I/O†
IsolationStore A and B data
Store A data to B bus
Real-time B data to A bus
Stored A data to B bus and stored B data A bus
Real-time A data to B bus
A1 THRU A8Input
Output
Output
InputInput
InputUnspecified ‡
B1 THRU B8Input
Output
Output
InputInput
InputUnspecified ‡
CLKBACLKAB
H or L
HL
OEAB
L
H
H
LX
L
L
LH
OEBA
X
H or L
H or L
H or L
→→X
XX
X
XX
XX‡XX
XX
LH
XX
XX
LL
H
H
HH
HH
L
L
H or L→
→
H or L
→→
→
H or L
H or L
LH
H
XX
H
XX‡
OutputOutput
Output
InputInput
Output
InputInput
Stored B data to A bus
Store A, hold BStore A in both registers
Hold A, store B
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ABT LVTH3V AC ACT LVCH
3V UNIT
ICC MAX 32 5 0.08 0.08 0.02 mAIOH MAX -32 -32 -24 -24 -24 mAIOL MAX 64 64 24 24 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ABT LVTH3V AC ACT LVCH
3V
fmax MIN 125 150 95 90 150tw Pulse duration CLKAB or CLKBA high or low MIN 4.3 3.3 5 5.5 3.3
A before CLKAB or B before CLKBA , high MIN 3 1.2 4.5 4.5 3
A before CLKAB or B before CLKBA , low MIN 3 2 4.5 4.5 3
A after CLKAB or B after CLKBA , high MIN 0 0.5 0 1 0.2
A after CLKAB or B after CLKBA , low MIN 0 0.5 0 1 0.2tPLH 4.9 4.2 12.2 12.3 6.4tPHL 4.7 4.2 12.3 12.3 6.4tPLH 3.9 3.4 9.9 10.5 6.3tPHL 4.6 3.4 10.2 11.6 6.3tPLH 5 4.5 13.8 16 7.4tPHL 5 4.5 13.8 16.9 7.4tPZH 5 4.3 10.7 11.7 6.3tPZL 5.3 4.3 13.2 13.4 6.3tPHZ 4.9 5.6 8.8 9.5 6.2tPLZ 4 5.4 8.7 9.2 6.2tPZH 4.2 4.2 10.5 10.8 6.3tPZL 4.6 4.2 13 12.4 6.3tPHZ 5.9 5.5 8 10.5 6.2tPLZ 5.2 5.5 7.8 9.9 6.2
UNIT fmax : MHz other : ns
tsu Setup time
th Hold time
OEAB B
CLKAB or CLKBA
MAX
A or B B or A
MAX
MAX
MAX
MAXA
MAX
B
OEBA
SAB or SBA
OEAB
MAX
OEBA
A or B
A or B
A
598
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
T/R
OE
ERR
A1
A2
A3
A4
A5
A6
A7
A8
ODD/EVEN PARITY
B2
B3
B4
B5
B6
B7
B8
B1
1665716-BIT TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS
599PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ABT ACT UNIT
ICC MAX 36 0.08 mAIOH MAX -32 -24 mAIOL MAX 64 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ABT ACT
tPLH 4.1 10.7tPHL 4.3 10.6tPLH 6.7 14.3tPHL 6.1 14.3tPLH 6.7 13.7tPHL 6.1 14.1tPLH 6.7 14.6tPHL 6.1 14.7tPLH 6.7 13.8tPHL 6.1 14.2tPZH 5.6 11.3tPZL 6 13tPHZ 5.4 11.2tPLZ 4.3 10.5tPZH 5.6 11.3tPZL 6 13tPHZ 5.4 11.2tPLZ 4.3 10.5UNIT: ns
MAX
MAX
A or B B or A MAX
PARITY ERR
OE MAX
A or B
ODD / EVEN PARITY, ERR MAX
ERR
PARITY MAX
B
OE PARITY, ERR MAX
A or B
A or B
OE PARITY, ERR MAX
OE MAX
FUNCTION TABLE(each 8-bit section)
INPUTS
L
INPUT/OUTPUTPARITYOE
NUMBER OF A OR BINPUTS THAT ARE HIGH
LLLLLLLLLLLH
T/R
LLLL
LLLLX
ODD/EVEN
L
LL
L
LL
HH
HH
0, 2, 4, 6, 8
1, 3, 5, 7
Don't care X
H
H
H
H
H
H
L
L
Z
H
H
L
L
H
H
L
LH
H
ERR
Z
LL
L
L
H
H
HH
Z
Z
ZZ
OUTPUTS
OUTPUT MODE
Z
Receive
Transmit
Receive
Transmit
ReceiveReceive
Receive
Transmit
Receive
Transmit
ReceiveReceive
600
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1672120-BIT FLIP-FLOP WITH 3-STATE OUTPUTS
D1
CLK
CLKEN
To 19 Other Channels
C1
OE
Q1
CE
1D
1
56
29
552
FUNCTION TABLE(each filp-flop)
INPUTS OUTPUTQ
LX H
L
DCLK
LX
ZL
H
HL
OE CLKEN
X
LL
X
QO
L
→→
X
HLL H
QO
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALVCH3V UNIT
ICC MAX 0.04 mAIOH MAX -24 mAIOL MAX 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALVCH3V
fmax MIN 150tw Pulse duration CLK high or low MIN 3.3
Data before CLK MIN 3.1
CLKEN before CLK MIN 2.7
Data after CLK MIN 0
CLKEN after CLK MIN 0tPLH 4.3tPHL 4.3tPZH 4.8tPZL 4.8tPHZ 4.4tPLZ 4.4
UNIT fmax : MHz other : ns
MAX
MAXQ
Q MAX
tsu Setup time
th Hold time
CLK
Q
OE
OE
601
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
1672222-BIT FLIP-FLOP WITH 3-STATE OUTPUTS
D1
CLK
CLKEN
To 21 Other Channels
C1
OE
Q1
CE
1D
1
64
33
63 2
FUNCTION TABLE(each filp-flop)
INPUTS OUTPUTQ
LX X
L
DCLK
LX
ZL
H
HL
OE CLKEN
X
LL or H
X
QO
LX
HLL H
QO
↑↑
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN AVC3V UNIT
ICC MAX 0.04 mAIOH MAX -12 mAIOL MAX 12 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN AVC3V
fmax MIN 150tw Pulse duration CLK high or low MIN 2.8
Data before CLK MIN 2.5
CLKEN before CLK MIN 1.4
Data after CLK MIN 0
CLKEN after CLK MIN 1.2tPLH 2.6tPHL 2.6tPZH 4.3tPZL 4.3tPHZ 3.4tPLZ 3.4
UNIT fmax : MHz other : ns
tsu Setup time
th Hold time
CLK
Q
OE
OE MAX
MAXQ
Q MAX
602
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1682010-BIT EDGE-TRIGGERD D-TYPE FLIP-FLOPSWITH DUAL OUTPUTS
D1
2OE
1Q1CLK
1D
To Nine Other Channels
C1
1OE
1Q2
1
28
56
55
2
3
FUNCTION TABLE(each fllp-flop)
INPUTS
H
L
DH
X
OUTPUTQn†H
Z
L L
OEn†
X
CLKL
X Q0L
→→
L
† n = 1, 2
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALVCH3V UNIT
ICC MAX 0.04 mAIOH MAX -24 mAIOL MAX 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALVCH3V
fmax MIN 150tw Pulse duration CLK high or low MIN 3.3tsu Setup time Data before CLK MIN 1.4th Hold time Data after CLK MIN 1tPLH 4.8tPHL 4.8tPZH 5tPZL 5tPHZ 4.5tPLZ 4.5
UNIT fmax : MHz other : ns
MAX
MAXQ
Q MAXCLK
Q
OE
OE
603
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
1682120-BIT BUS INTERFACE FLIP-FLOPSWITH 3-STATE OUTPUTS
1D1
1OE
1Q1
1CLK
1D
To Nine Other Channels
C1
2D1
2OE
2Q1
2CLK
1D
To Nine Other Channels
C1
1
56
55
28
29
42
2
15
One of TenChannels
One of TenChannels
FUNCTION TABLE(each fllp-flop)
INPUTS
H
L
DH
X
OUTPUTQH
Z
L L
OE
X
CLKL
X Q0L
→→
L
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ABT ALVTH3V ACT ALVCH
3V UNIT
ICC MAX 89 5 0.08 0.04 mAIOH MAX -32 -32 -24 -24 mAIOL MAX 64 64 24 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ABT ALVTH3V ACT ALVCH
3V
fmax MIN 150 150 70 150tw Pulse duration CLK high or low MIN 3.3 1.5 7 3.3
Data before CLK , low MIN 1.8 1.5 7.5 3.4Data before CLK , high MIN 1.8 1.5 7.5 3.4Data after CLK , high MIN 1.3 1 0.5 0Data after CLK , low MIN 1.3 1 0.5 0
tPLH 6.1 3.5 13.4 4.5tPHL 5.4 3.5 14 4.5tPZH 5.7 4.1 11.9 5.1tPZL 5.6 3.6 14.7 5.1tPHZ 6.5 4.8 10.7 4.6tPLZ 7.1 4.8 10 4.6UNIT fmax : MHz other : ns
tsu Setup time
th Hold time
CLK
Q
OE
OE MAX
MAXQ
Q MAX
604
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1682318-BIT EDGE-TRIGGERDD-TYPE FLIP-FLOPSWITH DUAL OUTPUTS
To Eight Other Channels
1D1
1Q1
1CLKEN
1OE
1CLR
2
1
55
54
R
1D
C13
CE
561CLK
To Eight Other Channels
2D1
2Q1
2CLKEN
2OE
2CLR
27
28
30
42
R
1D
C115
CE
292CLKFUNCTION TABLE
(each 9-bit filp-flop)
INPUTS OUTPUTQ
LX
L
DCLK
LX
Z
L
H
HL
OE CLKEN
X
LL
XQ0
L
→→
XH
LL H
Q0
CLR
X
HL
HH
XL H
X
X
X L
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ABT ABTH AC ACT ALVCH3V UNIT
ICC MAX 80 80 0.08 0.08 0.04 mAIOH MAX -32 -32 -24 -24 -24 mAIOL MAX 64 64 24 24 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ABT ABTH AC ACT ALVCH3V
fmax MIN 150 150 115 90 150
CLR low MIN 3.3 3.3 3.3 3.3 3.3CLK high or low MIN 3.3 3.3 4.4 5.5 3.3
CLR inactive MIN 1.6 1.6 0.6 0.5 0.8
Data high before CLK MIN 1.7 1.7 5 7 1
Data low before CLK MIN 1.7 1.7 5 7 1.3
CLKEN low before CLK MIN 2.8 2.8 4.2 3.5 1.5
Data high after CLK MIN 1.2 1.2 1.3 0.5 0.8
Data low after CLK MIN 1.2 1.2 1.3 0.5 0.5
CLKEN low after CLK MIN 0.6 0.6 1.4 2.5 0.4tPLH 6.8 6.8 12 12.1 4.5tPHL 6 6 12.7 12.9 4.5tPLH - - - - 4.6tPHL 6.1 6.7 11 12.5 4.6tPZH 4.9 4.9 9.7 10.7 4.8tPZL 5.5 5.5 11.8 12.8 4.8tPHZ 6.1 6.1 9.3 10.3 4.5tPLZ 8.7 8.7 8.6 9.4 4.5
UNIT fmax : MHz other : ns
Q MAX
Q MAX
Q
OE
OE MAX
MAXQ
tsu Setup time
th Hold time
tw Pulse duration
CLR
CLK
605
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
1682518-BIT BUS BUFFERS/DRIVERSWITH 3-STATE OUTPUTS
1OE1
1Y1
1
2
1OE256
1A155
To Eight Other Channels
2OE1
2Y1
28
16
2OE229
2A141
To Eight Other Channels
FUNCTION TABLE(each 9-bit section)
INPUTS
H
L
A
H
X
OUTPUTY
H
ZX
LOE2
HL
X
OE1L LL
X Z
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ABT ACT ALVCH3V UNIT
ICC MAX 32 0.08 0.04 mAIOH MAX -32 -24 -24 mAIOL MAX 64 24 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ABT ACT ALVCH3V
tPLH 3.9 10.5 3.4tPHL 4.4 10.3 3.4tPZH 6.1 11 4.7tPZL 6 13.2 4.7tPHZ 6.9 11.5 4.5tPLZ 6.6 10.6 4.5UNIT: ns
OE Y MAX
A Y MAX
OE Y MAX
606
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1682720-BIT BUS BUFFERS/DRIVERSWITH 3-STATE OUTPUTS
1Y12
1
55
1OE11OE2
56
2Y115
28
42
292OE12OE2
To Nine Other Channels
To Nine Other Channels
1A1
2A1
FUNCTION TABLE(each 10-bit section)
INPUTS
H
L
A
H
X
OUTPUTY
H
ZX
LOE2
HL
X
OE1L LL
X Z
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ABT ALVTH3V ACT ALVCH
3V AVC UNIT
ICC MAX 32 6 0.08 0.04 0.04 mAIOH MAX -32 -32 -24 -24 -12 mAIOL MAX 64 64 24 24 12 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ABT ALVTH3V ACT ALVCH
3V AVC
tPLH 3.4 3 11 3.4 1.7tPHL 4.2 2.8 10.8 3.4 1.7tPZH 5.6 3.9 11.7 4.7 5.1tPZL 5.5 3.4 14 4.7 5.1tPHZ 6.6 5.8 12.4 4.5 4.7tPLZ 6.1 4.6 11.5 4.5 4.7UNIT: ns
OE Y MAX
A Y MAX
OE Y MAX
607PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
168311-TO-4 ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS
Logic Diagram20
21
19
8
CLK
D Q
22
To Eight Other Channels
5
4
2
1
OE1
OE2
CLK
A1
SEL
1Y1
2Y1
3Y1
4Y1
FUNCTION TABLE
INPUTS
XHH
CLKSELOUTPUT
YZ
OEHLLLL
XXX
AX
LL
LH
LH
LH
LH
→→
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALVCH3V UNIT
ICC MAX 0.04 mAIOH MAX -24 mAIOL MAX 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALVCH3V
fmax MIN 150tw Pulse duration CLK high or low MIN 3.3tsu Setup time A data before CLK MIN 1.6th Hold time A data after CLK MIN 1.1tPLH 3.6tPHL 3.6tPLH 3.9tPHL 3.9tPLH 4.4tPHL 4.4tPZH 4.3tPZL 4.3tPHZ 4.5tPLZ 4.5
UNIT fmax : MHz other : ns
MAX
SEL Y MAX
YCLK
OE
OE
Y
A Y
MAX
MAX
MAX
Y
608
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
16
17
15
7
CLK
D Q
18
To Six Other Channels
5
4
2
1
OE1
OE2
CLK
A1
SEL
1Y1
2Y1
3Y1
4Y1
168321-TO-4 ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS
609PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
FUNCTION TABLE
INPUTS
XHH
CLKSELOUTPUT
YZ
OEHLLLL
XXX
AX
LL
LH
LH
LH
LH
→→
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALVCH3V UNIT
ICC MAX 0.04 mAIOH MAX -24 mAIOL MAX 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALVCH3V
fmax MIN 150tw Pulse duration CLK high or low MIN 3.3tsu Setup time A data before CLK MIN 1.6th Hold time A data after CLK MIN 1.1tPLH 3.6tPHL 3.6tPLH 3.9tPHL 3.9tPLH 4.4tPHL 4.4tPZH 4.3tPZL 4.3tPHZ 4.5tPLZ 4.5
UNIT fmax : MHz other : ns
MAX
MAX
MAX
Y
OE
OE
Y
A Y MAX
SEL Y MAX
YCLK
610
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1ERR
1CLR
1OEA
1OEB
88
8
9 P
MUX
1
1
1
G1
12k
1D
RC1
EN
EN
8x
8x
1A1–1A8
1CLK
1PARITY
1B1–1B8
2ERR
2CLR
2OEA
2OEB
8
8
8
8
9 P
MUX
1
1
1
G1
12k
1D
RC1
EN
EN
8x
8x
2A1–2A8
2CLK
2PARITY
2B1–2B8
8
8
1
56
255
28
29
27
30
26
54
3
31
8
16833DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
611PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
CLR
A data to B bus andgenerate parity
A data to B bus andgenerate inverted parity
INPUTS OUTPUT AND I/OFUNCTION
CLKAi
Σ OF HBi†
Σ OF H B PARITY ERR‡OEA
XOddEven
OddEven
OddEven
X
X X X
XX
X
XX
X X
X
LH NAAH
H
H H
H
H ↑↑↑
↑
↑H
OEB
L
NALLHLA
NC
L
L
H
H
LH
NoNo
Isolation§
Check error flag register
B data to A bus andcheck parity
L
H
A
NA
NA NA
HNA NA
NA
Z Z Z
B
NA
OddEven NA
NAL
FUNCTION TABLE
† State of ERR before any changes at CLR, CLK, or point P
CLR
Clear
INPUTSINTERNALTO DEVICE
OUTPUTPRE-STATE OUTPUT
ERRFUNCTION
CLK POINT P ERRn-1†
X X
XX
HH
HL
HL
HH
LL
X
LH
Sample
ERROE-FLAG FUNCTION TABLE
↑↑↑
NA = not applicable, NC = no change, X = don’t care† Summation of high-level inputs includes PARITY along with Bi inputs.
‡ Output states shown assume ERR was previousiy high.§ In this mode, ERR (when clocked) shows inverted panrity of the A bus.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ABT ACT UNIT
ICC MAX 36 0.08 mAIOH MAX -32 -24 mAIOL MAX 64 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ABT ACT
CLK high or low 3 4
CLR low - 4
A data before CLK , A port 4..5 -
A data before CLK , CLR 1 1.5
A data before CLK , OEA 5 -th Hold time A data after CLK , A port or OEA MIN 0 0tPLH 4.1 10.4tPHL 4.3 10.7tPLH 6.7 13.5tPHL 6.1 13.8tPZH 5.6 11.2tPZL 6 13tPHZ 5.4 10.8tPLZ 4.3 10.1tPLH CLK, CLR 4.6 15.8tPHL CLK 3.9 11.6tPLH 6.7 -tPHL 6.1 -tPLH 6.7 13.2tPHL 6.1 13.6tPZH 5.7 9.5tPZL 6.5 10.7tPHZ 4.7 10.2tPLZ 4.1 9.7tPZH 5.7 -tPZL 6.5 -tPHZ 4.7 -tPLZ 4.1 -UNIT: ns
OEA PARITY MAX
OEA PARITY
OEB PARITY MAX
MAX
MAX
MAX
MAX
MIN
MIN
MAX
MAX
MAX
MAX
MAX
A PARITY
OEA PARITY
ERR
OEB PARITY
tw Pulse duration
OEB PARITY
OEB or OEA
tsu Setup time
B or A
A or B
A or B
OEB or OEA
A or B
612
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1683416-BIT UNIVERSAL BUS DRIVERWITH 3-STATE OUTPUTS
OE
CLK
Y1
1D
C1
CLK
To 17 Other Channels
LE
A1
27
30
28
54
3
FUNCTION TABLE
INPUTS
XL
ACLK
L
L
OUTPUTYZ
HH
OEH
L
X
LXX
H
L
LEX
HHL
LHH
XL
Y0†HL X Y0‡H
LL
→→
L
† Output level before the indicated steady-state input conditions were established, provided that CLK is high before LE goes high
‡ Output level before the indicated steady-state input conditions were established
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALVC3V
AVC3V UNIT
ICC MAX 0.04 0.04 mAIOH MAX -24 -12 mAIOL MAX 24 12 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALVC3V
AVC3V
fmax MIN 150 150
LE low MIN 3.3 3.3
CLK high or low MIN 3.3 3.3
Data before CLK MIN 1.7 0.7
Data before LE , CLK high 1.9 1
Data before LE , CLK low 1.5 1
A data after CLK MIN 0.7 0.9
Data after LE , CLK high 0.9 1.4
Data after LE , CLK low 0.9 1.3tPLH 3.6 2.5tPHL 3.6 2.5tPLH 4.9 4tPHL 4.9 4tPLH 4.6 3.1tPHL 4.6 3.1tPZH 5 6.2tPZL 5 6.2tPHZ 4.5 5.3tPLZ 4.5 5.3
UNIT fmax : MHz other : ns
MIN
MIN
MAX
MAX
MAX
th Hold time
Y
tsu Setup time
tw Pulse duration
OE
Y
A Y
LE Y
OE
CLK
MAX
MAX
Y
613
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
168353.3-V ABT 18-BIT UNIVERSAL BUS DRIVERWITH 3-STATE OUTPUTS
OE
CLK
Y1
1D
C1
CLK
To 17 Other Channels
LE
A1
27
30
28
54
3
FUNCTION TABLE
† Output level before the indicated steady-state input conditions were established, provided that CLK was high before LE went low.
‡ Output level before the indicated steady-state input conditions were established
INPUTS
H
LLL
L
OUTPUTYOE
X XLE
X
XX
H
CLK
HL
A
HLHL
Y0†Y0‡
Z
L
HH
L
X
→
LX
HLLL
LL
→
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LVTH3V
ALVC3V
ALVCH3V
AVC3V UNIT
ICC MAX 5 0.04 0.04 0.04 mAIOH MAX -32 -24 -24 -12 mAIOL MAX 64 24 24 12 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN LVTH3V
ALVC3V
ALVCH3V
AVC3V
fmax MIN 150 150 150 150
LE low MIN 3.3 3.3 3.3 3.3
CLK high or low MIN 3.3 3.3 3.3 3.3
Data before CLK MIN 2.1 1.7 1.7 0.7
Data before LE , CLK high MIN 2.3 1.5 1.5 0.8
Data before LE , CLK low MIN 1.5 1 1 0.5
A data after CLK MIN 1 0.7 0.7 1.3
Data after LE , CLK high MIN 0.8 1.4 1.4 1.6
Data after LE , CLK low MIN 0.8 1.4 1.4 1.4tPLH 3.7 3.6 3.6 2.5tPHL 3.7 3.6 3.6 2.5tPLH 5.1 4.2 4.2 3.8tPHL 5.1 4.2 4.2 3.8tPLH 5.1 4.5 4.5 3.1tPHL 5.1 4.5 4.5 3.1tPZH 4.6 4.6 4.6 6.2tPZL 4.6 4.6 4.6 6.2tPHZ 5.8 3.9 3.9 5.3tPLZ 5.8 3.9 3.9 5.3
UNIT fmax : MHz other : ns
YCLK
th Hold time
MAXY
LE Y MAX
tsu Setup time
tw Pulse duration
MAX
MAX
MAX
Y
OE
OE
Y
A
614
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1OE
To Nine Other Channels
1
56
552
1LE
1D1
C1
1D1Q1
2OE
To Nine Other Channels
28
29
4215
2LE
2D1
C1
1D2Q1
1684120-BIT BUS INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS
FUNCTION TABLE(each 10-bit latch)
INPUTS
H
L
DH
X
OUTPUTQH
Z
L L
OE
X
LEL
X Q0L L
HH
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ABT ACT ALVCH3V UNIT
ICC MAX 89 0.08 0.04 mAIOH MAX -32 -24 -24 mAIOL MAX 64 24 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ABT ACT ALVCH3V
tw Pulse duration LE high or low MIN 4 4 3.3tsu Setup time Data before LE MIN 1 1.5 1.1
Data after LE , high MIN 2 3 1.1
Data after LE , low MIN 2 4.5 1.1tPLH 5 11.8 3.9tPHL 5.1 12.2 3.9tPLH 5 12.7 4.3tPHL 5 12.7 4.3tPZH 5.7 11.3 4.9tPZL 5.6 13.7 4.9tPHZ 6.5 10.2 4.1tPLZ 7.1 9.6 4.1UNIT: ns
D
th Hold time
LE MAX
MAX
Q
Q
MAX
MAX
Q
OE
OE
Q
615PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
Logic Diagram
1684318-BIT BUS INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS
1Q1
S2C11DR
1OE 2
To Eight Other Channels
1PRE 55
1CLR 1
3
1LE 56
1D1 54 2Q1
S2C11DR
2OE 27
To Eight Other Channels
2PRE 30
2CLR 28
15
2LE 29
2D1 42
INPUTS OUTPUTQ
X
L
DLE
L
ZL
H
HL
LX
Q0H
L
LH
CLR
X
HL
HH X
X
XL
OEPRE
X
X
H
HX
HX
HHH
LL
FUNCTION TABLE(each 9-bit latch)
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ABT UNIT
ICC MAX 85 mAIOH MAX -32 mAIOL MAX 64 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ABT
tw Pulse duration 3.33.33.3
tsu Setup time 0.90.6
th Hold time 1.71.8
tPLH 4.8tPHL 4.8tPLH 5.9tPHL 5.3tPLH 6.1tPHL 5tPLH 5.4tPHL 6tPZH 5.4tPZL 5.8tPHZ 6.3tPLZ 5.2UNIT: ns
Q
MIN
MIN
MAX
MAX
MAX
MAX
MAX
MAX
Q
Q
Q
Q
Q
LE
PRE
CLR
MIN
OE
OE
CLR lowPRE lowLE high
Data before LE , highData before LE , lowData after LE , highData after LE , low
D
616
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
PARITY
ERR
CLR
B1–B8A1–A8
LE
OEA
OEB
EN
EN
8x
8x
MUX1
1
G1
1
12k
P
8
9
8
8
8
8
16853DUAL 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS
CLR
A data to B bus and generate parity
A data to B bus and generate inverted parity
INPUTS OUTPUT AND I/OsFUNCTION
LEAi
Σ OF HBi†
Σ OF H B PARITY ERR‡OEA
XOddEven
L OddH Even
OddEven
X
XX
XX
X X
X
LH NAAH
H
H H
H
XX
OEB
L
NALLHLA
NC
NC
L
L
HLHHLL
HIsolation§
(parity check)
Store error flag
B data to A bus and check parityH
H HH
A
NA
NA NAX X X X X H Clear error flag registerL NA NA
HNA NA
NA
Z Z Z
B
NA
OddEven NA
NA
NAL L
H L
CLR
Clear
INPUTSINTERNALTO DEVICE
OUTPUT OUTPUTERR
FUNCTIONLE POINT P ERRn-1†
X
XX
H
H H
H H
L
L
L
L
H
HHHL
L L
LHL
X
L
HL
Sample
Pass
StoreX H
L
X
FUNCTION TABLE
ERROR-FLAG FUNCTION TABLE
NA = not applicable, NC = no change, X = don’t care† Summation of high-level inputs includes PARITY along with Bi inputs.‡ Output states shown assume ERR was previousiy high.§ In this mode, ERR (when clocked) shows inverted panrity of the A bus.
† State of ERR before changes at CLR, LE, or point P
617PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ABT UNIT
ICC MAX 40 mAIOH MAX -32 mAIOL MAX 64 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ABT
LE high or low MIN 8.5
CLR low 4
A, B and PARITY before LE MIN 10
CLR before LE 0
A, B and PARITY after LE MIN 0
CLR after LE 0tPLH 4.1tPHL 4.3tPLH 7.1tPHL 7.2tPLH CLR ERR MAX 5.7tPZH 5.6tPZL 6tPHZ 5.4tPLZ 4.3tPZH 5.7tPZL 6.5tPHZ 4.7tPLZ 4.1tPLH 4.8tPHL 4.9tPLH 7.2tPHL 7.4UNIT: ns
MAX
MAX
MAX
MAX
LE ERR
MAX
MAX
tw Pulse duration
OE A or B
B or A
A or OE PARITY
tsu Setup time
th Hold time
A or B
A, B or PARITY ERR MAX
OE A or B
OE PARITY MAX
OE PARITY
618
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1OEBA
1OEAB
1A1 1B1255
1
56
To Nine Other Channels
2OEBA
2OEAB
2A1 2B11542
28
29
To Nine Other Channels
1686120-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ACT UNIT
ICC MAX 0.08 mAIOH MAX -24 mAIOL MAX 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ACT
tPLH 10.4tPHL 11.1tPZH 10tPZL 12.7tPHZ 10.7tPLZ 10UNIT: ns
OEBA or OEAB A or B MAX
A or B B or A MAX
OEBA or OEAB A or B MAX
A to BB to AIsolation
INPUTSOPERATION
H
OEBAOEAB
L
HHH L
L LLatch A and B (A = B)
FUNCTION TABLE(each 10-bit section)
619PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
Logic Diagram
1OEBA
1OEAB
1A1 1B1255
1
56
To Nine Other Channels
2OEBA
2OEAB
2A1 2B11542
28
29
To Nine Other Channels
1686318-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ABT ACT ALVCH3V UNIT
ICC MAX 32 0.08 0.04 mAIOH MAX -32 -24 -24 mAIOL MAX 64 24 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ABT ACT ALVCH3V
tPLH 3.5 11.1 3.4tPHL 3.9 11.8 3.4tPZH 5.4 10.6 4.7tPZL 4.8 13.6 4.7tPHZ 6 11.6 4.2tPLZ 5 11 4.2UNIT: ns
OEBA or OEAB A or B MAX
A or B B or A MAX
OEBA or OEAB A or B MAX
FUNCTION TABLE(each 9-bit section)
INPUTS
HL
H
OPERATION
LOEAB
B data to A busA data to B bus
H Isolation
OEBA
H
620
Block Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
A-PortParity
Generateand
CheckB Data
B-PortParity
Generateand
CheckA Data
18-BitStorage
18-BitStorage
18 18
1818
2
2
LEAB
1CLKENAB2CLKENAB
CLKAB
OEAB
1A1–1A8
1APAR
1ERRB
2A1–2A8
2APAR
2ERRB
ODD/EVENSEL
OEBA
1B1–1B8
1BPAR
1ERRA
2B1–2B8
2BPAR
2ERRA
1CLKENBA2CLKENBA
CLKBA
LEBA
QA
QB
5
61
28
36
34
31
35
60
4
37
29
62
64, 33
63
2
1, 32
3
30
INPUTS
HHHH
HH
LLLL
OPERATION OR FUNCTIONSEL
H
H
LL
OEBA
L
LParity is checked on port A and is generated on port B.Parity is checked on port B and is generated on port A.Parity is checked on port B and port A.Parity is generated on port A and B if device is in FF mode.Parity funcions aredisabled; device acts as astandard 18-bit registeredtransceiver.
QA data to B, QB data to AQB data to AQA data to BIsolation
OEAB
H
H
H
H
L
L
L
L
PARITY-ENABLE FUNCTION TABLEFUNCTION TABLE
INPUTS
H
LLLL
OUTPUTBCLKENAB
H
LLLL
OEABX
XL
XLL
X XLEAB
X
X
XXH
CLKAB
HL
HL
A
HL
HLZ
B0‡
B0§B0‡L
HH
L
X
L
X
L
X↑↑
LL
‡ Output level before the indicated steady-state input conditions were established
§ Output level before the indicated steady-state input conditions were established, provided that CLKAB was low before LEAB went low
INPUTS OUTPUTS
H
N/A N/A0, 2, 4, 6, 81, 3, 5, 7
0, 2, 4, 6, 81, 3, 5, 7
N/AN/AN/AN/A
0, 2, 4, 6, 81, 3, 5, 7
0, 2, 4, 6, 81, 3, 5, 7
N/A
N/A
N/A
N/A
N/A
N/A
N/AN/AN/A
N/AN/AN/AN/A
N/AN/AN/AN/A
N/AN/AN/AN/A
N/AN/AN/AN/A
N/AN/AN/AN/A
N/AN/A0, 2, 4, 6, 8
1, 3, 5, 70, 2, 4, 6, 8
1, 3, 5, 70, 2, 4, 6, 8
1, 3, 5, 70, 2, 4, 6, 8
1, 3, 5, 70, 2, 4, 6, 8
1, 3, 5, 70, 2, 4, 6, 8
1, 3, 5, 7
0, 2, 4, 6, 81, 3, 5, 7
0, 2, 4, 6, 81, 3, 5, 7
0, 2, 4, 6, 81, 3, 5, 7
0, 2, 4, 6, 81, 3, 5, 7
0, 2, 4, 6, 81, 3, 5, 7
0, 2, 4, 6, 81, 3, 5, 7
N/A
N/A
N/A
N/AN/AN/A
N/AN/A
N/AN/AN/A
N/A
N/A
N/A
N/A
BPAR ERRA BPAR ERRB
H
L
H
L
N/AN/AN/AN/A
H
L
H
L
H
L
H
L
H
LH
L
H
LH
L
H
L
H
L
HL
HL
HL
H
H
HL
L
H
LH
L
H
LH
L
HL
LH
HL
LH
HL
LH
L
HL
HL
LH
LH
H
L
H
L
APAR APAR
Z
Z
Z
Z
ZZ
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
ZZZZ
ZZZZ
ZZZZ
ZZZZ
Z
LH
L
H
H
L
H
L
LH
L
PO‡PE† Z
ZPO‡PE†
ODD/EVENΣ OF INPUTS
A1-A8 = HΣ OF INPUTS
B1-B8 = HH
L
H
L
H
L
H
LH
L
H
L
H
L
H
H
L
H
L
HH
L
LLLLH
L
H
L
H
L
H
L
HHHH
H
L
H
L
HH
HHHH
LLLL
H
L
H
H
HH
HHHH
LLLL
LLLL
HHHH
HHHH
LLLLLLLLLLLLLLLLLLLLLLLLLL
SEL OEBA OEAB
PARITY FUNCTION TABLE
† Parity output is set to the level so that the specific bus side is set to even parity.‡ Parity output is set to the level so that the specific bus side is set to odd parity.
1690118-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY GENERATORS/CHECKERS
621PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LVCH3V
ALVCH3V UNIT
ICC MAX 0.02 0.04 mAIOH MAX -24 -24 mAIOL MAX 24 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN LVCH3V
ALVCH3V
fmax MIN 125 125
CLK MIN 3 3
LE high MIN 3 3
A, APAR or B, BPAR before CLK MIN 2.5 1.7
CLKEN before CLK MIN 2.5 1.7
A, APAR or B, BPAR before LE MIN 2 1.2
A, APAR or B, BPAR after CLK MIN 1.3 0.5
CLKEN after CLK MIN 1.5 0.7
A, APAR or B, BPAR after LE MIN 1.7 0.9tPLH 5.4 4.4tPHL 5.4 4.4tPLH 7.7 6.7tPHL 7.7 6.7tPLH 5.7 4.7tPHL 5.7 4.7tPLH 8.5 7.5tPHL 8.5 7.5tPLH 7.8 6.8tPHL 7.8 6.8tPLH 7.5 6.5tPHL 7.5 6.5tPLH 6.1 5.1tPHL 6.1 5.1tPLH 6.1 5.1tPHL 6.1 5.1tPLH 6.6 5.6tPHL 6.6 5.6tPLH 8.7 7.7tPHL 8.7 7.7tPLH 8.9 7.9tPHL 8.9 7.9tPLH 5.8 4.8tPHL 5.8 4.8tPLH 6.3 5.3tPHL 6.3 5.3tPLH 8.4 7.4tPHL 8.4 7.4tPLH 8.5 7.5tPHL 8.5 7.5tPZH 6.3 5.3tPZL 6.3 5.3tPHZ 5.9 4.9tPLZ 5.9 4.9tPZH 5.9 4.9tPZL 5.9 4.9tPHZ 6.7 5.7tPLZ 6.7 5.7tPZH 6.5 5.5tPZL 6.5 5.5tPHZ 5.9 4.9tPLZ 5.9 4.9
UNIT fmax : MHz other : ns
MAX
BPAR or APAR
th Hold time
tw Pulse duration
A or B
A or B MAX
B or A
tsu Setup time
MAX
BPAR or APAR
ERRA or ERRB
MAX
MAX
BPAR or APAR MAX
APAR or BPAR
APAR or BPAR
MAXODD / EVEN BPAR or APAR
ODD / EVEN
SEL
ERRA or ERRB
CLKAB or CLKBA
CLKAB or CLKBA
CLKAB or CLKBA
CLKAB or CLKBA
A or B MAX
MAX
MAX
MAX
BPAR or APARparity feedthrough
BPAR or APARparity generated
ERRA or ERRB
LEAB or LEBA
LEAB or LEBA
LEAB or LEBA
LEAB or LEBA
A or B
BPAR or APARparity feedthrough
BPAR or APARparity generated
ERRA or ERRB
MAX
MAX
MAX
MAX
B, BPARor A, APAR
B, BPARor A, APAR
OEAB or OEBA
OEAB or OEBA
MAX
SEL
SEL
ERRA or ERRB
ERRA or ERRB
MAX
OEAB or OEBA
OEAB or OEBA
ERRA or ERRB
ERRA or ERRB
MAX
MAX
MAX
MAX
622
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
13
8(1A–8A)13
5(9A–12A, APAR)
Flip-Flop
13
Flip-Flop
5
13
D Q
ParityCheck
12
11
D Q
D Q XORD Q
APAR
APAR
10(1A–10A)
(1A–11A/YERREN, APAR)
12(1A–12A)
11A/YERREN
12
1
33
56
29
28
36
30
OE
MODE
CLK
CLKEN
1A–12A,APAR
PAROE
PARI/O
YERR
1Y2–12Y2
1Y1–12Y1
169033.3-V 12-BIT UNIVERSAL BUS DRIVER WITH PARITY CHECKER AND DUAL 3-STATE OUTPUTS
11A/YERREN§
FUNCTION TABLE
INPUTS
X
LL
A 1Yn† – 8Yn†CLK
L
L
L
Z
H
H
HOE
H
L
X
L
XX L
MODE
X
HLL
HH
Y0Y0
H
LL
LL
CLKEN
XXX
HH
LL
→→
→→ L
9Yn† – 12Yn†
Z
H
LH
LHL
OE
†n =1, 2
OUTPUTS INPUTS
PARITY FUNCTION
H
PAROE‡OUTPUT
YERR
H
LLL
HHH H
‡ When used as a single device, PAROE must be tied high.§ Valid after appropriate number of clock pulses have set internal register.
LL
LLLL
PARI/O
LLLL
APAR
HHLL
Σ OF INPUTS1A – 10A = H
1, 3, 5, 7, 9
H X X X XX
L X H X XX
0, 2, 4, 6, 8, 101, 3, 5, 7, 9
0, 2, 4, 6, 8, 10L
HH
LLL
HHH
HHHH
H
H
H
LL
LLLL
HHLL
1, 3, 5, 7, 90, 2, 4, 6, 8, 10
1, 3, 5, 7, 90, 2, 4, 6, 8, 10 L
INPUTS
PARI/O FUNCTION†
PAROEOUTPUTPARI/O
L
HLL L
† This table applies to the first device of a cascaded pair of ALVCH16903 devices.
LL
APAR
HHLL
Σ OF INPUTS1A – 10A = H
1, 3, 5, 7, 9H ZXX
0, 2, 4, 6, 8, 101, 3, 5, 7, 9
0, 2, 4, 6, 8, 10H
623PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALVCH3V UNIT
ICC MAX 0.04 mAIOH MAX -24 mAIOL MAX 24 mA
SWITCHING CHARACTERISTICS
INPUT OUTPUT MAX or MIN ALVCH3V
MIN 125tw Pulse duration CLK MIN 3
1A-12A before CLK , resister mode MIN 1.45
1A-10A before CLK , buffer mode MIN 4.4
APAR before CLK , resister mode MIN 1.3
APAR before CLK , buffer mode MIN 3.1
PARI/O before CLK , both mode MIN 1.7
11A/YERREN before CLK , buffer mode MIN 1.6
CLKEN before CLK , resister mode MIN 2.2
1A-12A after CLK , resister mode MIN 0.55
1A-10A after CLK , buffer mode MIN 0.25
APAR after CLK , resister mode MIN 0.7
APAR after CLK , buffer mode MIN 0.25
PARI/O before CLK , resister mode MIN 0.4
PARI/O before CLK , buffer mode MIN 0.5
11A/YERREN after CLK , buffer mode MIN 0.4
CLKEN after CLK , resister mode MIN 0.4tPLH 3.8tPHL 3.8tPLH 4.4tPHL 4.4tPLH 6.6tPHL 6.6tPLH 4.9tPHL 4.9tPLH 4.8tPHL 4.6tPZH 5.4tPZL 5.4tPZH 4.8tPZL 4.8tPHZ 5tPLZ 5tPHZ 3.8tPLZ 3.8tPLH 4tPHL 4.2
UNIT fmax : MHz other : ns
MAX
MAX
MAX
CLK
MODE
OE
PAROE
CLK
PARAMETER
A Y
CLK PARI / O
tsu Setup time
th Hold time
fmax
YERR
MAXBuffer mode
Both mode
Both mode
MAX
MAX
Both mode
Both mode
Y
PARI / O
Both mode OE Y
Both mode PAROE PARI / O MAX
OEBoth mode YERR MAX
Both mode
Y MAX
Y MAX
Resister mode
624
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
One of EightChannels
1A1
One of EightChannels
To Seven Other Channels
1CLKAB 1CLKBA
1OEBA 1OEAB
1B1
1CLKENAB 1CLKENBA
To Seven Other Channels
2CLKAB 2CLKBA
2OEBA 2OEAB
2A1 2B1
2CLKENAB 2CLKENBA
3
2
56
5
26
27
29
15
C1CE1D
54
55
1
52
31
30
28
42
C1CE1D
C1CE1D
C1CE1D
1695216-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
625PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ABT AC LVTH3V
LVCH3V
ALVCH3V UNIT
ICC MAX 35 0.08 5 0.02 0.04 mAIOH MAX -32 -24 -32 -24 -24 mAIOL MAX 64 24 64 24 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ABT AC LVTH3V
LVCH3V
ALVCH3V
fmax MIN 150 75 150 150 150
CLKEN high - - - - 3.3
CLK high or low 3.3 6.7 3.3 3.3 3.3
Data before CLK 3.5 5 1.7 2.8 1.5
CLKEN before CLK 3 6.5 2 1.4 1
Data after CLK 1 1 0.8 0.5 0.8
CLKEN after CLK 1 0 0.4 1.9 1.1tPLH 4.3 11.8 4.4 6.6 3.9tPHL 4.5 11.7 4.4 6.6 3.9tPZH 4.6 11.2 4.9 6.6 4.4tPZL 6 13 4.9 6.6 4.4tPHZ 5.5 9.4 6.2 6.7 4tPLZ 4.2 8.7 5.3 6.7 4UNIT fmax : MHz other : ns
CLK A or B MAX
OEBA or OEAB
A or B
A or B MAX
OEBA or OEAB MAX
tw Pulse duration
tsu Setup time
th Hold time
MIN
MIN
MIN
FUNCTION TABLE
INPUTS OUTPUTB
† A-to-B data flow is shown; B-to-A data flow is similar but uses CLKENBA, CLKBA, and OEBA.
‡ Level of B before the indicated steady-state input conditions were established.
X
HL
A
L
X Z
H
HL
L
H
CLKENAB OEABCLKAB
LXX
B0‡B0‡
LX
LLL→
→
H X
626
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1OE
1A1 1Y1
24
23 1
1A2 1Y222 3
1A3 1Y320 4
1A4 1Y419 6
2OE
2A1 2Y1
13
18 7
2A2 2Y217 9
2A3 2Y315 10
2A4 2Y414 12
2524425-Ω OCTAL BUS BUFFERS/DRIVERSWITH 3-STATE OUTPUTS
High Output Drive Current Distributed VCC and GND Pins Minimize Noise
Generated by the Simultaneous Switching ofOutputs
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN SN74BCT
SN64BCT UNIT
ICC MAX 119 119 mAIOH MAX -80 -80 mAIOL MAX 188 188 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN SN74BCT
SN64BCT
tPLH 5.5 5.5tPHL 6 6.3tPZH 9.3 9.7tPZL 10.2 10.4tPHZ 6.3 6.5tPLZ 8.4 9.5UNIT: ns
OE Y MAX
A Y MAX
OE Y MAX
FUNCTION TABLE(each buffer/driver)
INPUTS
HL
AH
X
OUTPUTYH
ZL L
OEL
627
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
2524525-Ω OCTAL BUS TRANSCEIVERSWITH 3-STATE OUTPUTS
High Output Drive Current Distributed VCC and GND Pins Minimize Noise
Generated by the Simultaneous Switching ofOutputs
DIR
OE
A1
B1
To Seven Other Channels
24
1
13
23
FUNCTION TABLE
INPUTS
LDIR OPERATION
LOE
H IsolationL H
X
B data to A busA data to B bus
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN SN74BCT ABTH UNIT
ICC MAX 125 20 mAIOH (A port) MAX -80 -80 mAIOH (B port) MAX -3 -32 mAIOL (A port) MAX 188 188 mAIOL (B port) MAX 24 64 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN SN74BCT ABTH
tPLH 5.7 3.9tPHL 7.2 4.3tPLH 5.5 3.9tPHL 6.2 4.3tPZH 9.6 6.5tPZL 10.3 6.8tPHZ 6.2 7.2tPLZ 8.3 6.4tPZH 8.9 6.5tPZL 9.7 6.8tPHZ 6.9 7.2tPLZ 7.5 6.4UNIT: ns
OE B MAX
B
A
OE MAX
OE MAX
A B MAX
OE A MAX
B A MAX
628
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
2564225-Ω OCTAL BUS TRANSCEIVER
High Output Drive Current Distributed VCC and GND Pins Minimize Noise
Generated by the Simultaneous Switching ofOutputs A1 B1
13
24
231
OE
DIR
To Seven Other Channels
FUNCTION TABLEINPUTS
OELLH
DIR
X
LH
OPERATION
B data to A busA data to B bus
Isolation
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN SN74BCT UNIT
ICC MAX 125 mAIOH (B port) MAX -3 mAIOL (A port) MAX 188 mAIOL (B port) MAX 24 mAVOH (A port) MAX 5.5 V
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN SN74BCT
tPLH 6.2tPHL 4tPLH 6.3tPHL 5.9tPLH 11.6tPHL 11.3tPZH 9.1tPZL 9.8tPHZ 7.3tPLZ 7.3UNIT: ns
A B MAX
B A MAX
A
OE MAX
OE MAX
OE B MAX
B
629
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
2982110-BIT BUS-INTERFACE FLIP-FLOPSWITH 3-STATE OUTPUTS
3-State Outputs Data Flow-Through Pinout
OE
CLK
1D1Q
1
13
223
To Nine Other Channels
C1
1D
FUNCTION TABLE(each fllp-flop)
INPUTS
H
L
DH
X
OUTPUTQH
Z
L L
OE
X
CLKL
XH or L Q0L
→→
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALS SN74BCT UNIT
ICC MAX 115 35 mAIOH MAX -24 -24 mAIOL MAX 48 48 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALS SN74BCT
fmax - 125tw Pulse duration CLK high or low MIN 7 7tsu Setup time Data before CLK MIN 4 7th Hold time Data after CLK MIN 2 1tPLH 10 12tPHL 10 10tPZH 14 12tPZL 14 13tPHZ 14 8tPLZ 12 8
UNIT fmax : MHz other : ns
MAX
MAX
MAX
Q
QOE
OE
QCLK
630
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
298258-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS
3-State Outputs Data Flow-Through Pinout
CLR
CLK1Q
To Seven Other Channels
OE1
OE2
OE3
CLKEN
C1
1D
R
1D
1
2
23
11
13
3
22
14
FUNCTION TABLE
INPUTS OUTPUTQ
LX
L
DCLK
L
ZH
HL
OE† CLKEN
X
L
XQ0L
→→
XH
LL H
CLR
X
HL
HH X
X
H or L
X L
† OE = H if any of the output-enable inputs is high.OE = L if all of the output-enable inputs are low.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN SN74BCT UNIT
ICC MAX 40 mAIOH MAX -24 mAIOL MAX 48 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN SN74BCT
fmax MIN 125
CLK low MIN 4CLK high or low MIN 4
Before CLK , data high MIN 6
Before CLK , data low MIN 3.5
CLR MIN 1
CLKEN before CLK MIN 8
After CLK , data high MIN 1.5
After CLK , data low MIN 0
CLKEN after CLK MIN 0.5tPLH 9tPHL 8.4tPHL CLR Q MAX 9.5tPZH 10.3tPZL 10.2tPHZ 9tPLZ 8.2
UNIT fmax : MHz other : ns
tsu Setup time
th Hold time
tw Pulse duration
CLK Q MAX
Q
OE
OE MAX
MAXQ
631
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
2982710-BIT BUFFERS AND BUS DRIVERSWITH 3-STATE OUTPUTS
pnp Inputs Reduce dc Loading 3-State Outputs Data Flow-Through Pinout
Y1
To Nine Other Channels
OE1
OE2
A12 23
13
1
FUNCTION TABLEINPUT
HL
AL
X
OUTPUT
L
Z
H H
OE1
†n = 1,2
X
OE2
HZ
X
LLL
LY
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALS SN74BCT UNIT
ICC MAX 40 40 mAIOH MAX -24 -24 mAIOL MAX 48 48 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALS SN74BCT
tPLH 7 5.5tPHL 7.5 7.5tPZH 15 9.1tPZL 15 12.8tPHZ 17 8.8tPLZ 12 8.4UNIT: ns
OE Y MAX
A Y MAX
OE Y MAX
632
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
To Nine Other Channels
OE2
OE1
A1
1
13
2 23Y1
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALS UNIT
ICC MAX 40 mAIOH MAX -24 mAIOL MAX 48 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALS
tPLH 7tPHL 7.5tPZH 15tPZL 15tPHZ 17tPLZ 12UNIT: ns
MAX
MAX
MAXOE
A
OE
Y
Y
Y
2982810-BIT BUFFERS AND BUS DRIVERSWITH 3-STATE OUTPUTS
pnp Inputs Reduce dc Loading 3-State Outputs Data Flow-Through Pinout
NOTICE : ALS IS NOT RECOMMENDED FOR NEW DESIGNS
633
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
2984110-BIT BUS INTERFACE D-TYPE LATCHESWITH 3-STATE OUTPUTS
3-State Outputs Data Flow-Through Pinout
1D
OE
2
1
13
1Q23
LE
1D
To Nine Other Channels
C1
FUNCTION TABLE
INPUTS
HL
DH
X
OUTPUT
H
Z
L L
OE
HL
LE
XQ0
X
LHL
Q
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALS SN74BCT UNIT
ICC MAX 85 35 mAIOH MAX -24 -24 mAIOL MAX 48 48 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALS SN74BCT
tw Pulse duration LE high or low MIN 6 4tsu Setup time Data beforeLE MIN 2.5 2
Data after LE , high MIN 4.5 1.5
Data after LE , low MIN 4.5 3.5tPLH 9.5 7.5tPHL 9.5 8.6tPLH 12 8.6tPHL 12 8.1tPZH 14 9.2tPZL 14 12.8tPHZ 15 6.9tPLZ 12 6.9UNIT: ns
OE
OE
QLE
MAX
MAX
MAX
Q
Q
th Hold time
D Q MAX
634
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
OE
LE
1D
1Q
1
13
223
To Eight Other Channels
PRE14
CLR11
S
C1
1D
R
298439-BIT BUS INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS
3-State Outputs Data Flow-Through Pinout
635PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
FUNCTION TABLE
INPUTS OUTPUTQ
X
L
DLE
L
ZL
H
HL
LX
Q0H
L
LH
CLR
X
HL
HH X
X
XL
OEPRE
X
X
H
HX
HX
HHH
LL
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN SN74BCT UNIT
ICC MAX 35 mAIOH MAX -24 mAIOL MAX 48 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN SN74BCT
PRE low 7
CLR low 5
LE high 4
Data before LE , high or low 1.5
PRE or CLR inactive 2th Hold time Data after LE , high or low MIN 3.5tPLH 8tPHL 9tPLH 10tPHL 10tPLH 12tPHL 12tPLH 12tPHL 12tPZH 15tPZL 15tPHZ 8tPLZ 8UNIT: ns
Q MAX
Q
OE
OE MAX
MAXQ
CLR
tsu Setup time
tw Pulse duration
D
LE
MIN
MIN
PRE
Q MAX
MAX
MAX
Q
Q
636: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
298548-BIT TO 9-BIT PARITY BUS TRANSCEIVER
Logic Diagram
8x
EN
A1–A8
OEA
OEB
LE
CLR
G1
1
1
1
1
MUX
2k
EN
8xB1–B8
PARITY
ERR
88
8
8
8
9P
637PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALS SN74BCT UNIT
ICC MAX 100 80 mAIOH MAX -24 -24 mAIOL MAX 48 48 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALS SN74BCT
LE high MIN 10 -
LE low MIN 10 10
CLR low MIN 10 10
Before LE , Bi and PARITY MIN 10 18
Before LE , CLR high MIN 15 -th Hold time Bi and PARITY after LE MIN 3 8tPLH 8 8tPHL 8 8tPLH 15 15tPHL 18 15tPZH 17 17tPZL 17 19tPHZ 15 15tPLZ 8 17tPHL LE ERR MAX 12 9tPLH CLR ERR MAX 12 15tPLH 17 15tPHL 19 16tPLH 20 20tPHL 20 15UNIT: ns
A or B MAX
OEA PARITY MAX
OEA or OEB
B or A MAX
PARITY MAX
tw Pulse duration
A or B
A
OEA or OEB
tsu Setup time
Bi / PARITY ERR MAX
A or B MAX
FUNCTION TABLE
INPUTS OUTPUT AND I/O
OEA
Even
Even
OPERATION
A data to B bus and generate parity
OEB
L H
H H Isolation§
B data to A bus and check parityH L
Store error flagH L
parityA data to B bus and generate invertedL L
Clear error-flag registerX X
CLR
X
LXX
H
X
H
X
L
LE
X
L
HHL
L
H
X
H
AiΣ of Hs
Odd
XL OddH Even
X
NA
NAX
Bi†Σ of Ls
NA
EvenOdd NA
X
Odd
XX
A
NA
NA
Z
B
XX
B
A
A
Z
NA
NANA
PARITY
LH
HL
Z
NA
NANA
L
ERR‡
NA
NA
HNC
LH
H
N-1H
NA = not applicable, NC = no change, X = don’t care† Summation of high-level inputs includes PARITY along with Bi inputs.‡ Output states Shown assume ERR was previously high.§ In this mode, ERR, when enabled, shows inverted parity of the A bus.
638
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
A1 B123
11OEBA1
1
2
14
13
OEBA2
OEAB1
OEAB2
To Eight Other Channels
298639-BIT BUS TRANSCEIVERSWITH 3-STATE OUTPUTS
True Outputs
FUNCTION TABLE
INPUTSOPERATION
L
H
OEBA2OEBA1
XH
B to AL
XX
LL
OEAB1
H
LL
HX L
H
IsolationHXH XHHX XXHX H
L
A to B
OEAB2L
X
Latch A and BH X
L
LL
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALS SN74BCT UNIT
ICC MAX 65 45 mAIOH MAX -24 -24 mAIOL MAX 48 48 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALS SN74BCT
tPLH 8 5tPHL 8 7.5tPZH 15 8.4tPZL 15 12.6tPHZ 17 8.8tPLZ 12 8.1UNIT: ns
OEAB or OEBA A or B MAX
A or B B or A MAX
OEAB or OEBA A or B MAX
639
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
298649-BIT BUS TRANSCEIVERSWITH 3-STATE OUTPUTS
Inverted OutputsA1 B1
23
11OEBA1
1
2
14
13
OEBA2
OEAB1
OEAB2
To Eight Other Channels
FUNCTION TABLE
INPUTSOPERATION
L
H
OEBA2OEBA1
XH
B to AL
XX
LL
OEAB1
H
LL
HX L
H
IsolationHXH XHHX XXHX H
L
A to B
OEAB2L
X
Latch A and BH X
L
LL
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN SN74BCT UNIT
ICC MAX 45 mAIOH MAX -24 mAIOL MAX 48 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN SN74BCT
tPLH 6.1tPHL 4.8tPZH 8.4tPZL 12.5tPHZ 8.4tPLZ 8.2UNIT: ns
OEAB or OEBA A or B MAX
A or B B or A MAX
OEAB or OEBA A or B MAX
640
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1OE
1A1
1A2
1A3
1A4
1Y1
1Y2
1Y3
1Y4
A3
A5
A6
B5
B6
A2
A1
B2
B1
2OE
2A1
2A2
2A3
2A4
2Y1
2Y2
2Y3
2Y4
A4
C5
C6
D5
D6
C2
C1
D2
D1
3OE
3A1
3A2
3A3
3A4
3Y1
3Y2
3Y3
3Y4
H4
E5
E6
F5
F6
E2
E1
F2
F1
4OE
4A1
4A2
4A3
4A4
4Y1
4Y2
4Y3
4Y4
H3
G5
G6
H6
H5
G2
G1
H1
H2
5OE
5A1
5A2
5A3
5A4
5Y1
5Y2
5Y3
5Y4
J3
J5
J6
K5
K6
J2
J1
K2
K1
6OE
6A1
6A2
6A3
6A4
6Y1
6Y2
6Y3
6Y4
J4
L5
L6
M5
M6
L2
L1
M2
M1
7OE
7A1
7A2
7A3
7A4
7Y1
7Y2
7Y3
7Y4
T4
N5
N6
P5
P6
N2
N1
P2
P1
8OE
8A1
8A2
8A3
8A4
8Y1
8Y2
8Y3
8Y4
T3
R5
R6
T6
T5
R2
R1
T1
T2
3224032-BIT BUFFER/DRIVER
641PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
INPUTS OUTPUTY
Z
OE
H
LL H
LA
X
HL
FUNCTION TABLE(each 4bit buffer/drirer)
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LVT UNIT
ICC MAX 10 mAIOH MAX -32 mAIOL MAX 64 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN LVT
tPLH MAX 3.5tPHL MAX 3.5tPZH MAX 4tPZL MAX 4.4tPHZ MAX 4.5tPLZ MAX 4.2UNIT:ns
Y
Y
Y
A
OE
OE
642
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1OE
1A1
1A2
1A3
1A4
1Y1
1Y2
1Y3
1Y4
A3
A5
A6
B5
B6
A2
A1
B2
B1
2OE
2A1
2A2
2A3
2A4
2Y1
2Y2
2Y3
2Y4
A4
C5
C6
D5
D6
C2
C1
D2
D1
3OE
3A1
3A2
3A3
3A4
3Y1
3Y2
3Y3
3Y4
H4
E5
E6
F5
F6
E2
E1
F2
F1
4OE
4A1
4A2
4A3
4A4
4Y1
4Y2
4Y3
4Y4
H3
G5
G6
H6
H5
G2
G1
H1
H2
5OE
5A1
5A2
5A3
5A4
5Y1
5Y2
5Y3
5Y4
J3
J5
J6
K5
K6
J2
J1
K2
K1
6OE
6A1
6A2
6A3
6A4
6Y1
6Y2
6Y3
6Y4
J4
L5
L6
M5
M6
L2
L1
M2
M1
7OE
7A1
7A2
7A3
7A4
7Y1
7Y2
7Y3
7Y4
T4
N5
N6
P5
P6
N2
N1
P2
P1
8OE
8A1
8A2
8A3
8A4
8Y1
8Y2
8Y3
8Y4
T3
R5
R6
T6
T5
R2
R1
T1
T2
3224436-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
643PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
INPUTS OUTPUTYOE
LLH
A
X
HHLZ
L
FUNCTION TABLE
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LVT3V
LVTH3V
ALVTH3V
LVC3V
LVCH3V
ALVCH3V UNIT
ICC MAX 10 10 5 0.02 0.02 0.04 mAIOH MAX -32 -32 -32 -24 -24 -24 mAIOL MAX 64 64 64 24 24 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN LVT3V
LVTH3V
ALVTH3V
LVC3V
LVCH3V
ALVCH3V
tPLH 3.2 3.2 2.4 4.1 4.1 3tPHL 3.2 3.2 2.5 4.1 4.1 3tPZH 4 4 3.8 4.6 4.6 4.4tPZL 4 4 2.9 4.6 4.6 4.4tPHZ 4.5 4.5 4.2 5.8 5.8 4.1tPLZ 4.2 4.2 3.6 5.8 5.8 4.1UNIT: ns
OE Y MAX
A Y MAX
OE Y MAX
644
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
3224536-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
To Seven Other Channels
1DIR
1A1
1B1
1OE
To Seven Other Channels
2DIR
2A1
2B1
2OE
A3
A5
H3
E5
A4
A2
H4
E2
To Seven Other Channels
3DIR
3A1
3B1
3OE
To Seven Other Channels
4DIR
4A1
4B1
4OE
J3
J5
T3
N5
J4
J2
T4
N2
645PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
FUNCTION TABLE(each 9-bit section)
INPUTS
LDIR OPERATION
LOE
H IsolationL H
X
B data to A busA data to B bus
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ABTH LVTH3V
LVC3V
LVCH3V
ALVCH3V UNIT
ICC MAX 20 10 0.04 0.02 0.04 mAIOH MAX -32 -32 -24 -24 -24 mAIOL MAX 64 64 24 24 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ABTH LVTH3V
LVC3V
LVCH3V
ALVCH3V
tPLH 5 3.3 4 4 3tPHL 5.2 3.3 4 4 3tPZH 7.3 4.5 5.5 5.5 4.4tPZL 8.1 4.6 5.5 5.5 4.4tPHZ 6.5 5.1 6.6 6.6 4.1tPLZ 6.9 5.1 6.6 6.6 4.1UNIT: ns
OE B or A MAX
A or B B or A MAX
OE B or A MAX
646
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
CLK
1 of 16 Channels
CE
C
OEA
SELA
CLKA
CLKENA
LEA
CLK
CE
C
OEB
SELB
CLKB
CLKENB
LEB
CLK
CE
C
OEC
SELC
CLKC
CLKENC
LEC
C1
B1
A1
77
76
74
73
75
52
24
25
27
28
26
32
78
79
22
21
23
80
3231616-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS
647PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ABTH UNIT
ICC MAX 40 mAIOH MAX -32 mAIOL MAX 64 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ABTH
fmax MIN 150LE high MIN 3.3CLK high or low MIN 3.3
A, B, or C before CLK MIN 2.4
A or B before LE MIN 2.1
CLKEN before CLK MIN 3.2
A, B, or C after CLK MIN 1.4
A or B after LE MIN 2.1
CLKEN after CLK MIN 1.1tPLH 6.1tPHL 6.6tPLH 6.5tPHL 6.5tPLH 7.5tPHL 6.9tPLH 7.5tPHL 6.7tPZH 6.4tPZL 6.8tPHZ 6tPLZ 6.1
UNIT fmax : MHz other : ns
MAX
MAX
MAX
OE A, B, or C MAX
OE A, B, or C MAX
MAXCLK A, B, or C
LE A, B, or C
tw Pulse duration
A, B, or C C, B, or A
SEL A, B, or C
tsu Setup time
th Hold time
FUNCTION TABLESTORAGE†
INPUTSOUTPUT
† A-port register shown, B and C ports are similar but use CLKENB, CLKENC, CLKB, CLKC, LEB, and LEC.
‡ Output level before the indicated steady-state input conditions were established.
X
HL
A
L
XH
HL
L
H
CLKENA LEACLKA
L
XX
Q0‡L
XL L
L
→→
X
XXX
X
HLH
HL
HLQ0‡Q0‡
A-PORT OUTPUT
INPUTS
L
SELA
H
OUTPUT AOEA
ZHOutput of C register
LL
X
Output of B register
B-PORT OUTPUT
INPUTS
L
SELB
H
OUTPUT BOEB
ZHOutput of A register
LL
X
Output of C register
C-PORT OUTPUT
INPUTS
L
SELC
H
OUTPUT COEC
ZHOutput of B register
LL
X
Output of A register
648
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
CLK
1 of 18 Channels
LE
OEA
SELA
CLKA
LEA
CLK
LE
OEB
SELB
CLKB
LEB
CLK
LE
OEC
SELC
CLKC
LEC
C1
B1
A1
77
76
74
75
52
24
25
27
26
28
78
79
22
23
80
D
Q
D
Q
D
Q
3231818-BIT TRI-PORT UNIVERSAL BUS EXCHANGERS
649PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ABTH UNIT
ICC MAX 45 mAIOH MAX -32 mAIOL MAX 64 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ABTH
fmax MIN 150LE high MIN 3.3CLK high or low MIN 3.3
A, B, or C before CLK MIN 2.4
A, B, or C before LE MIN 2.1
A, B, or C after CLK MIN 1.4
A, B, or C after LE MIN 2.1tPLH 6.1tPHL 6.6tPLH 6.5tPHL 6.5tPLH 7.5tPHL 6.9tPLH 7.4tPHL 6.7tPZH 6.8tPZL 7.1tPHZ 6.2tPLZ 6
UNIT fmax : MHz other : ns
tw Pulse duration
A, B, or C C, B, or A
SEL A, B, or C
tsu Setup time
th Hold time
CLK A, B, or C
LE A, B, or C
MAX
MAX
MAX
OE A, B, or C MAX
OE A, B, or C MAX
MAX
FUNCTION TABLESTORAGE†
INPUTSOUTPUT
† A-port register shown, B and C ports are similar but use CLKB, CLKC, LEB, and LEC.
‡ Outpu level befor the indicated steady-state input conditions were established.
HLA
L
HL
H
LEACLKA
XX
LLL
→→
XX
HLH
HL
HLQ0‡Q0‡
A-PORT OUTPUT
INPUTS
L
SELA
H
OUTPUT AOEA
ZHOutput of C register
LL
X
Output of B register
B-PORT OUTPUT
INPUTS
L
SELB
H
OUTPUT BOEB
ZHOutput of A register
LL
X
Output of C register
C-PORT OUTPUT
INPUTS
L
SELC
H
OUTPUT COEC
ZHOutput of B register
LL
X
Output of A register
650
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1OE
1LE
1D1
To Seven Other Channels
1Q1C1
1D
A3
A4
A5A2
2OE
2LE
2D1
To Seven Other Channels
2Q1C1
1D
H3
H4
E5E2
3OE
3LE
3D1
To Seven Other Channels
3Q1C1
1D
J3
J4
J5J2
4OE
4LE
4D1
To Seven Other Channels
4Q1C1
1D
T3
T4
N5N2
3237332-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
651PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LVTH3V
ALVTH3V
LVCH3V UNIT
ICC MAX 10 5 0.02 mAIOH MAX -32 -32 -24 mAIOL MAX 64 64 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN LVTH3V
ALVTH3V
LVCH3V
tw Pulse duration, LE high or low MIN 3 1.5 3.3
Data before LE , data high MIN 1 1.4 1.7
Data before LE , data low MIN 1 0.9 1.7
Data after LE , data high MIN 1 0.9 1.2
Data after LE , data low MIN 1 1.4 1.2tPLH 3.8 3.1 4.2tPHL 3.6 3.3 4.2tPLH 4.3 3.3 4.6tPHL 4 3.5 4.6tPZH 4.3 4 4.7tPZL 4.3 3.4 4.7tPHZ 5 4.9 5.9tPLZ 4.7 4.5 5.9UNIT: ns
OE Q MAX
OE Q MAX
th Hold time
tsu Setup time
MAX
MAX
D Q
QLE
INPUTS
LHHLE
OUTPUTQ
Z
OE
H
LLL
X
D
XX
HHLQ0
L
FUNCTION TABLE
652
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1OE
1CLK
1D1
To Seven Other Channels
1Q1C1
1D
A3
A4
A5A2
2OE
2CLK
2D1
To Seven Other Channels
2Q1C1
1D
H3
H4
E5E2
3OE
3CLK
3D1
To Seven Other Channels
3Q1C1
1D
J3
J4
J5J2
4OE
4CLK
4D1
To Seven Other Channels
4Q1C1
1D
T3
T4
N5N2
3237432-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
653PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LVTH3V
ALVTH3V
LVCH3V
ALVCH3V UNIT
ICC MAX 10 5 0.02 0.04 mAIOH MAX -32 -32 -24 -24 mAIOL MAX 64 64 24 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN LVTH3V
ALVTH3V
LVCH3V
ALVCH3V
fmax 160 250 150 150tw Pulse duration, CLK high or low MIN 3 1.5 3.3 3.3
Data before CLK , data high MIN 1.8 1 1.9 1.9
Data before CLK , data low MIN 1.8 1.5 1.9 1.9
Data after CLK , data high MIN 0.8 0.5 1.1 0.5
Data after CLK , data low MIN 0.8 1 1.1 0.5tPLH 4.5 3.2 4.5 4.2tPHL 4 3.2 4.5 4.2tPZH 4.5 3.8 4.6 4.8tPZL 4.4 3.3 4.6 4.8tPHZ 5 4.6 5.5 4.3tPLZ 4.6 4.2 5.5 4.3
UNIT fmax : MHz other : ns
th Hold time
tsu Setup time
MAXCLK Q
OE Q MAX
OE Q MAX
INPUTS
H or L
CLKOUTPUT
Q
Z
OE
H
LLL
X
D
XX
HHLQ0
L
→→
FUNCTION TABLE(each flip-flop)
654
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1DC1
CLK
1D
C1CLK
1B1
1OEAB
1CLKAB
1LEAB
1LEBA
1CLKBA
1OEBA
1A1
B3
A4
A3
K3
J4
J3
A2A5
To 17 Other Channels
1DC1
CLK
1D
C1CLK
2B1
2OEAB
2CLKAB
2LEAB
2LEBA
2CLKBA
2OEBA
2A1
L3
K5
K2
W3
V4
V3
L2L5
To 17 Other Channels
3250136-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
655PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ABTH ALVCH3V UNIT
ICC MAX 90 0.02 mAIOH MAX -32 -24 mAIOL MAX 64 24 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ABTH ALVCH3V
fmax MIN 150 150
LEAB or LEBA high MIN 3.3 3.3
CLKAB or CLKBA high or low MIN 3.3 3.3
A before CLKAB MIN 3.5 1.7
B before CLKBA MIN 3.5 1.7
A before LEAB or LEBA CLK high MIN 1.6 1.5
A before LEAB or LEBA CLK low MIN 1.6 1
A after CLKAB or B after CLKBA MIN 0 0.7
A after LEAB or B after LEBA MIN 1.6 1.4tPLH 4.8 3.9tPHL 5.4 3.9tPZH 5.3 4.6tPZL 5.5 4.6tPHZ 5.3 4.9tPLZ 5.4 4.9tPZH 5.6 4.6tPZL 6 4.6tPHZ 5.9 5tPLZ 5.6 5tPZH 5.6 5tPZL 6 5tPHZ 5.9 4.2tPLZ 5.6 4.2
UNIT fmax : MHz other : ns
tw Pulse duration
MAX
LEAB or LEBA MAX
tsu Setup time
th Hold time
CLKAB or CLKBA MAX
OEBA
B
MAX
B
MAX
MAX
OEBA A MAX
A or B B or A
B or A
B or A
A
OEAB
OEAB
FUNCTION TABLE†INPUTS
XH
ACLKAB
L
L
OUTPUTBZ
HH
OEABL
H
X
HXX
H
L
LEABX
LHH
HHL
XH
B0‡LL X B0§L
HH
→→
L
† A-to-B data flow is shown: B-to-A flow is similar but uses OEBA, LEBA, and CLKBA.
‡ Outoput level before the indicated steady-state input conditions were established
§ Output level before the indicated steady-state input conditions were established, provided that CLKAB was high before LEAB went low
656
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1OEBA
1CEBA
1LEBA
1OEAB
1CEAB
1LEAB
1A11B1
To 17 Other Channels
2OEBA
2CEBA
2LEBA
2OEAB
2CEAB
2LEAB
2A12B1
To 17 Other Channels
90
91
89
86
85
87
92
36
35
37
40
41
39
14
84
62
C1
1D
C1
1D
C1
1D
C1
1D
3254336-BIT REGISTERED BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
657PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ABTH UNIT
ICC MAX 20 mAIOH MAX -32 mAIOL MAX 64 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ABTH
tw Pulse duration, LEAB or LEBA low MIN 3.3
Data before LEAB or LEBA MIN 2.1
Data before CEAB or CEBA MIN 1.7
Data after LEAB or LEBA MIN 0.6
Data after CEAB or CEBA MIN 0.9tPLH 5.9tPHL 5.7tPLH 7.5tPHL 6.6tPZH 8tPZL 8.8tPHZ 7.1tPLZ 7.5tPZH 7.3tPZL 8.1tPHZ 6.5tPLZ 6.9UNIT: ns
MAX
MAXA or B B or A
LE A or B MAX
MAX
OE A or B MAX
OE A or B MAX
tsu Setup time
th Hold time
CE A or B
CE A or B
FUNCTION TABLE
INPUTS
XX
AOEAB
L
OUTPUTYZ
CEABH
L
X
LH
LEABX
LHL
LL
XB0‡L
LL
X
H
HX Z
† A-to-B data flow is shown: B-to-A flow conditions is the same that it uses CEBA, LEBA, and OEBA.
‡ Outoput level before the indicated steady-state input conditions were established
658
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
401038-STAGE SYNCHRONOUS DOWN COUNTERS
GN
D
VC
C
3
4
5
6
7
9
P7
P6
P5
P4
P3
P2
P1
P0
CP
10
11
12
13
1 215
MR
TE
PE
TC
PL
16 8
FUNCTION TABLECONTROL INPUTS
ACTIONPRESET MODESynchronous
AsynchronouslyPreset On Next Positive Clock TransitionCownt DownInhibit Counter
Preset AsychronouslyClear to Maximum Count
XX
PLMR
X H
PE
LL
XLXX
HH L
L H
LLL
TELL
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN CD74HC
CD74HCT UNIT
ICC MAX 0.16 0.16 mAIOH MAX -4 -4 mAIOL MAX 4 4 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN CD74HC
CD74HCT
tw 50 5338 6338 53
tsu 30 3622 3045 60
th 5 50 02 2
tPLH 90 90tPHL 90 90tPLH 90 95tPHL 90 95tPLH 60 75tPHL 60 75tPLH 83 102tPHL 83 102tPLH 83 83tPHL 83 83UNIT:ns
MR
P to CP
CP
P to CP
CP
CP
TE
PL
PE to CP
MAX
TC(Async Preset)
TC(Sync Preset)
TC
TC
TC
MAX
MAX
MAX
MAX
MIN
MIN
MIN
PE to CPTE to CP
TE to CP
PLMR
659PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
Logic Diagram
1622403.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SN74LVT162240, SN74LVTH162240: Output Ports Have Equivalent 22-Ω Series Resistors
1OE
1A1
1A2
1A3
1A4
1Y1
1Y2
1Y3
1Y4
1
47
46
44
43
2
3
5
6
2OE
2A1
2A2
2A3
2A4
2Y1
2Y2
2Y3
2Y4
48
41
40
38
37
8
9
11
12
3OE
3A1
3A2
3A3
3A4
3Y1
3Y2
3Y3
3Y4
25
36
35
33
32
13
14
16
17
4OE
4A1
4A2
4A3
4A4
4Y1
4Y2
4Y3
4Y4
24
30
29
27
26
19
20
22
23
OE
FUNCTION TABLE
INPUTS
L
A
X
H
OUTPUTYL
ZL
L
HH
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LVT3V
LVTH3V UNIT
ICC MAX 5 5 mAIOH MAX -12 -12 mAIOL MAX 12 12 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN LVT3V
LVTH3V
tPLH 4 4tPHL 4 4tPZH 4.8 4.8tPZL 4.7 4.7tPHZ 4.7 4.7tPLZ 4.5 4.5UNIT: ns
A
OE
OE
Y MAX
Y MAX
Y MAX
660
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1OE
1A1
1A2
1A3
1A4
1Y1
1Y2
1Y3
1Y4
1
47
46
44
43
2
3
5
6
2OE
2A1
2A2
2A3
2A4
2Y1
2Y2
2Y3
2Y4
48
41
40
38
37
8
9
11
12
3OE
3A1
3A2
3A3
3A4
3Y1
3Y2
3Y3
3Y4
25
36
35
33
32
13
14
16
17
4OE
4A1
4A2
4A3
4A4
4Y1
4Y2
4Y3
4Y4
24
30
29
27
26
19
20
22
23
1622413.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
FUNCTION TABLE
INPUTS
L1A, 4A1OE, 4OE
X
H
OUTPUT1Y, 4Y
LLHL
Z
H
INPUTS2A, 3A2OE, 3OE
X
H
OUTPUT2Y, 3Y
LLHH
L Z
H
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LVTH3V UNIT
ICC MAX 5 mAIOH MAX -12 mAIOL MAX 12 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN LVTH3V
tPLH 4.1tPHL 4.1tPZH 4.9tPZL 4.8tPHZ 5.3tPLZ 4.9UNIT: ns
OE or OE Y MAX
A Y MAX
OE or OE Y MAX
661
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
16224416-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SN74ABT162244: Output Ports Have Equivalent 25-Ω Series Resistors SN74LVT162244A, LVTH162244: Output Ports Have Equivalent 22-Ω Series Resistors SN74ALVTH162244: Output Ports Have Equivalent 30-Ω Series Resistors SN74LVC162244A: Output Ports Have Equivalent 26-Ω Series Resistors SN74LVCH162244A: Output Ports Have Equivalent 26-Ω Series Resistors SN74ALVCH162244: Output Ports Have Equivalent 26-Ω Series Resistors
1OE
1A1
1A2
1A3
1A4
1Y1
1Y2
1Y3
1Y4
1
47
46
44
43
2
3
5
6
2OE
2A1
2A2
2A3
2A4
2Y1
2Y2
2Y3
2Y4
48
41
40
38
37
8
9
11
12
3OE
3A1
3A2
3A3
3A4
3Y1
3Y2
3Y3
3Y4
25
36
35
33
32
13
14
16
17
4OE
4A1
4A2
4A3
4A4
4Y1
4Y2
4Y3
4Y4
24
30
29
27
26
19
20
22
23
FUNCTION TABLE(each 4-bit buffer)
INPUTS
HL
A
H
X
OUTPUTY
H
ZL L
OE
L
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ABT LVT3V
LVTH3V
ALVTH3V
LVC3V
LVCH3V
ALVCH3V UNIT
ICC MAX 30 5 5 5 0.02 0.02 0.04 mAIOH MAX -12 -12 -12 -12 -12 -12 -12 mAIOL MAX 12 12 12 12 12 12 12 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ABT LVT3V
LVTH3V
ALVTH3V
LVC3V
LVCH3V
ALVCH3V
tPLH 3.9 4 4 3.3 4.4 4.4 4.2tPHL 4.8 3.6 3.6 3.3 4.4 4.4 4.2tPZH 5.4 5.1 5.1 4.9 5.5 5.5 5.6tPZL 5.1 4.5 4.5 3.3 5.5 5.5 5.6tPHZ 4.6 5 5 4.9 6.3 6.3 5.5tPLZ 4.5 5 5 4.3 6.3 6.3 5.5UNIT: ns
OE Y MAX
A Y MAX
OE Y MAX
662
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
16224516-BIT TRANSCEIVER WITH 3-STATE OUTPUTS
SN74ABT162245, SN74ABTH162245: A-Port Outputs Have Equivalent 25-Ω Series Resistors SN74LVT162245A, SN74LVTH162245: A-Port Outputs Have Equivalent 22-Ω Series Resistors SN74ALVTH162245: A-Port Outputs Have Equivalent 30-Ω Series Resistors SN74LVCR162245: All Outputs Have Equivalent 26-Ω Series Resistors
To Seven Other Channels
1DIR
1A1
1B1
1OE
1
47
48
2
663PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
FUNCTION TABLE(each 8-bit section)
INPUTS
LDIR
OPERATION
LOE
H IsolationL H
X
B data to A busA data to B bus
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ABT ABTH LVT3V
LVTH3V
ALVTH3V
LVCR3V UNIT
ICC MAX 32 32 5 5 5 0.02 mAIOH (A port) MAX -12 -12 -12 -12 -12 -12 mAIOH (B port) MAX -32 -32 -32 -32 -32 -12 mAIOL (A port) MAX 12 12 12 12 12 12 mAIOL (B port) MAX 64 64 64 64 64 12 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ABT ABTH LVT3V
LVTH3V
ALVTH3V
LVC3V
tPLH 3.9 3.9 3.3 3.3 3.1 7.5tPHL 4.2 4.2 3.3 3.3 3 7.5tPLH 4.6 4.6 4 4 3.7 7.5tPHL 5.1 5.1 3.4 3.4 3.4 7.5tPZH 6.3 6.3 4.6 4.6 3.8 9tPZL 6.4 6.4 4.6 4.6 3.4 9tPHZ 6.3 6.3 5.2 5.2 4.7 7.5tPLZ 5.2 5.2 5.1 5.1 4.8 7.5tPZH 7.1 7.1 5.3 5.3 4.7 9tPZL 7 7 5.1 5.1 3.9 9tPHZ 6.6 6.6 5.6 5.6 5 7.5tPLZ 5.7 5.7 5.5 5.5 4.9 7.5UNIT: ns
OE A MAX
A B MAX
OE B MAX
B
AOE MAX
A MAX
OE B MAX
664
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
C1
1D
C1
1D
C1
1D
C1
1D
To 11 Other Channels
LE1B
LE2B
LEA1B
LEA2B
OE2B
OE1B
OEA
SEL
A1 1B1
2B1
27
2
30
55
56
29
1
28
8 23
6
G1
1
1
16226012-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS
SN74ABTH162260: B-Port Outputs Have Equivalent 25-Ω Series Resistors SN74ALVCH162260: B-Port Outputs Have Equivalent 26-Ω Series Resistors
665PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
OEA
INPUTS
LLLLLLL
L
L
H
HH
LL
OUTPUTS
1B01B01B0
H
H
L
LLLLL
L
2B1BH
XX
Z
Z
LHLHL
HXXX
HH
X
L
HH
L
LLL
XXX
HH
HH
XL
XXX
Active
Active
L
L2B02B0
2B0
ActiveActive
LH
LH
ZZ
A TO B (OEA = H)
INPUTS1B SELH
X
OUTPUTA
A0Z
L
H
X
XX
X
2B
H
XX
XX
L
X
L
X
H
L
H
X
LE1B
LHH X
LE2B
L
HH
L
L
H
H
L
L
X
X L
X
X L
X X
LH L
L
A0
FUNCTION TABLE
B TO A (OEB = H)
OE2BLEA1BA LEA2B OE1B
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ABTH ALVCH3V UNIT
ICC MAX 63 0.04 mAIOH (A port) MAX -32 -24 mAIOH (B port) MAX -32 -12 mAIOL (A port) MAX 64 24 mAIOL (B port) MAX 12 12 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ABTH ALVCH3V
fmax - 150tw Pulse duration, LE1B, LE2B, LEA1B, or LEA2B high MIN 3.3 3.3tsu Setup time, data before LE1B, LE2B, LEA1B, or LEA2B MIN 1.5 1.1th Hold time, data after LE1B, LE2B, LEA1B, or LEA2B MIN 1 1.5tPLH 6.1 4.9tPHL 7.1 4.9tPLH 6 4.3tPHL 6.2 4.3tPLH 6.3 4.4tPHL 5.8 4.4tPLH 6.1 5tPHL 7.1 5
SEL (1B) 5.6 5.6SEL (2B) 6.3 5.6SEL (1B) 5 5.6SEL (2B) 6.2 5.6
tPZH 6.3 5.4tPZL 6.5 5.4tPZH 6.3 6tPZL 8.2 6tPHZ 6.7 4.6tPLZ 5.2 4.6tPHZ 7.5 5.1tPLZ 6.2 5.1UNIT fmax : MHz other : ns
A
A
OE B MAX
OE B MAX
OE
MAX
MAX
tPLH
tPHL
AMAX
MAX
A B
B
MAX
MAX
B A MAX
LE A MAX
LE
OE
666
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
CLK
OEB
SEL
A1
1B1
2B1
CLKENA1
CLKENA2
1D 1D
CE
C1
1D
CE
C1
G1
1
1 1D
1D
CLKEN1B
C1
1D
1D
C1
CEOEA
1D
C1
C1
CLKEN2B
1 of 12 Channels
CE
CE
C1
2
27
30
55
56
28
1
29
8
23
6
C1
1D
16226812-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS
SN74ALVCH162268: B-Port Outputs Have Equivalent 26-Ω Series Resistors
667PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
FUNCTION TABLE
INPUTS OUTPUTSCLK
Z
H
L
HL H
L
OEA A 1B, 2BHL
OEB
OUTPUT ENABLE
Active
ZActiveZ
Active
Z
Active
→→
→→
1B0‡ 2B0‡
INPUTS OUTPUTSCLK
H
X
LL H
L
CLKENA1 1B 2B
LH†L†
HL
A
A-TO-B STORAGE (OEB = L)
→→
XXX
XX
XX
X XH
L
CLKENA2
LH
→→
† Two CLK edges are needed to propagate data.‡ Output level before the indicated steady-state input conditions
were established
H
X
LL
CLKEN1B
XX
XX
XH
L
CLKEN2B
L
A0‡
INPUTS OUTPUTACLK
XL
XHL
2B1BSEL
B-TO-A STORAGE (OEA = L)
→→
X XA0‡
HL
X X
H
HL
XX
XX
H
LL
HLH
→→
‡ Output level before the indicated steady-state input conditions were established
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALVCH3V UNIT
ICC MAX 0.04 mAIOH (A port) MAX -24 mAIOH (B port) MAX -12 mAIOL (A port) MAX 24 mAIOL (B port) MAX 12 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALVCH3V
fmax MIN 150tw Pulse duration, CLK high or low MIN 3.3
A data before CLK MIN 3.4B data before CLK MIN 1SEL before CLK MIN 1.3CLKENA1 or CLKENA2 before CLK MIN 2.8CLKENB1 or CLKENB2 before CLK MIN 2.5OE before CLK MIN 3.2
th Hold time A data after CLK MIN 0.2B data after CLK MIN 1.3SEL after CLK MIN 1CLKENA1 or CLKENA2 after CLK MIN 0.4CLKENB1 or CLKENB2 after CLK MIN 0.5OE after CLK MIN 0.2
B 5.4A (1B) 4.8A (2B) 4.8
A (SEL) 5.8B 6.1A 5.1B 5.9A 5
UNIT fmax : MHz other : ns
MAXCLK
CLK
tsu Setup time
tpd
MAX
CLKten MAX
tdis
668
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
C1
1D
C1
G1
1
1
C1
CE
1D
C1
CE
C1
CE
1D
1D
C1
CE
1D
1 of 16 Channels
39
40
42
41
29
19
18
CLK
SEL
OE
DIR
A1
1B1
2B1
1D
16228016-BIT TO 32-BIT REGISTERED BUS EXCHANGER WITH BYTE MASKS AND 3-STATE OUTPUTS
SN74ALVCHG162280: A-Port Outputs Have Equivalent 50-Ω Series Resistors B-Port Outputs Have Equivalent 20-Ω Series Resistors
669PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALVCHG3V UNIT
ICC MAX 0.04 mAIOH (A to B) MAX 8 mAIOH (B to A) MAX 6 mAIOL (A to B) MAX 8 mAIOL (B to A) MAX 6 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALVCHG3V
fmax MIN 160tw Pulse duration, CLK high or low MIN 2.3
A data before CLK , high or low MIN 1.4B data before CLK , high or low MIN 2C data before CLK , high or low MIN 1.3DIR before CLK , high or low MIN 2SEL before CLK , high or low MIN 2A data after CLK , high or low MIN 0.3B data after CLK , high or low MIN 0.3C data after CLK , high or low MIN 0.3DIR after CLK , high or low MIN 0.3SEL after CLK , high or low MIN 0.3
A 5B 7.4D 7.2A 6.2B 9.4A 6B 9.5D 7.9A 6.4B 7.8A 5B 7.6D 6.7
UNIT fmax : MHz other : ns
MAX
MAX
MAX
tsu Setup time
th Hold time
tpd CLK
OE MAXtdis
OEten
CLK MAX
CLK
FUNCTION TABLE
INPUTS
XA
HL
OUTPUTS
1B0†
H‡
CLK 2B1BH X
LL
↑↑
↑↑
↑
↑↑
↑↑
L‡2B0†
XX
A-TO-B STORAGE (OE = L, DIR = H)
SEL
† Output level before indicated steady-state input conditions were established
‡ Two CLK edges are needed to propagate the data.
OUTPUT ENABLE
INPUTS
XDIR
L
OEOUTPUT
H
LHL
Z
Active
1B, 2BA
ZZ
ZActive
1D, 2DZ
ActiveActive
CLK
INPUTS
XC
HL
OUTPUT
1B0†
H‡
CLK 2D1DH X
LL L‡
2B0†
HL
C-TO-D STORAGE (OE = L)
SEL
† Output level before indicated steady-state input conditions were established
‡ Two CLK edges are needed to propagate the data.
INPUTS1BSEL
H
OUTPUTA
HL
CLK
XX
2B
HXX
L
L
HH
L
L§H§L
§ Two CLK edges are needed to propagate the data. The data is loaded in the first register when SEL is low and propagates to the second register when SEL is high.
B-TO-A STORAGE (OE = L, DIR = L)
670
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
C1
1D
C1
1D
G1
1
1
C1
CE
1D
C1
CE
C1
CE
1D
1D
C1
CE
1D
1 of 18 Channels
39
40
42
41
27
25
24
CLK
SEL
OE
DIR
A1
1B1
2B1
16228218-BIT TO 36-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS
SN74ALVCHG162282: A-Port Outputs Have Equivalent 50-Ω Series Resistors B-Port Outputs Have Equivalent 20-Ω Series Resistors
671PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALVCHG3V UNIT
ICC MAX 0.04 mAIOH (A to B) MAX 8 mAIOH (B to A) MAX 6 mAIOL (A to B) MAX 8 mAIOL (B to A) MAX 6 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALVCHG3V
fmax MIN 160tw Pulse duration, CLK high or low MIN 2.3
A data before CLK MIN 1.5B data before CLK MIN 2DIR before CLK MIN 2SEL before CLK MIN 2A data after CLK MIN 0.3B data after CLK MIN 0.3DIR after CLK MIN 0.3SEL after CLK MIN 0.3
A 5B 7.4A 6.3B 9.4A 6B 9.5A 6.4B 7.8A 5B 7.6
UNIT fmax : MHz other : ns
MAXtpd
tsu Setup time
th Hold time
CLK
OE MAXtdis
ten
MAX
CLK MAX
OE MAX
CLK
FUNCTION TABLE
INPUTS
LL
HCLK
↑
X↑
OUTPUTS
1B0†L‡H‡ H
L2B0†2B1B
† Output level before indicated steady-state input conditions were established
‡ Two CLK edges are needed to propagate the data.
A-TO-B STORAGE(OE = L, DIR = H)
INPUTS
CLK
↑
↑↑↑
SELH
LL
H
OUTPUT
HL
L§H§
A
§ Two CLK edges are needed to propagate the data. The data is loaded in the first register when SEL is low and proparates to the second register when SEL is high.
B-TO-A STORAGE(OE = L, DIR = L)
INPUTS
CLK
↑
↑↑
OE
LLH
A
HLX
1B
HL
XX
2B
XX
LH
DIR
L
XH
OUTPUTS
ZZ
Active Z
ZActive
1B, 2BA
OUTPUT ENABLE
SEL
672
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
16233416-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
SN74ALVC162334: Output Ports Have Equivalent 26-Ω Series Resistors SN74ALVCH162334: Output Port Has Equivalent 26-Ω Series Resistors
1
48
25
471D
C1
CLK
2
To 15 Other Channels
OE
CLK
LE
A1
Y1
673PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
FUNCTION TABLE
INPUTS
XL
ACLK
L
L
OUTPUTYZ
HH
OEH
L
X
LXX
L or H
L
† Output level before the indicated steady-state input conditions were established
LEX
HHL HHXL Y0†H
LL
→→
L
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALVC3V
ALVCH3V UNIT
ICC MAX 0.04 0.04 mAIOH MAX -12 -12 mAIOL MAX 12 12 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALVC3V
ALVCH3V
fmax MIN 150 150LE low 3.3 3.3CLK high or low MIN 3.3 3.3Data before CLK MIN 1.5 1.5Data before LE CLK high MIN 1.3 1.3Data before LE CLK low MIN 1.2 1.2Data after CLK MIN 0.9 0.9Data after LE CLK high MIN 1.1 1.1Data after LE CLK low MIN 1.1 1.1
A MAX 3.9 3.9
LE 5 5
CLK MAX 4.9 4.9ten OE Y 5.4 5.4tdis OE Y MAX 5 5UNIT fmax : MHz other : ns
tpd Y
tw Pulse duration
tsu Setup time
th Hold time
674
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
56
29
28
1
21B1
31B2
51B3
61B4
8
OE4
OE3
OE2
OE1
1A
92B1
102B2
122B3
132B4
142A
163B1
173B2
193B3
203B4
153A
234B1
244B2
264B3
274B4
214A
345B1
335B2
315B3
305B4
365A
416B1
406B2
386B3
376B4
426A
487B1
477B2
457B3
447B4
437A
558B1
548B2
528B3
518B4
498A
1623441-BIT TO 4-BIT ADDRESS DRIVER WITH 3-STATE OUTPUTS
SN74ALVCH162344: Output Ports Have Equivalent 26-Ω Series Resistors
675PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
OE
FUNCTION TABLE
INPUTS
L
A
X
H
OUTPUTBnH
ZL
L
HL
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALVCH3V UNIT
ICC MAX 0.04 mAIOH MAX -12 mAIOL MAX 12 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALVCH3V
tPLH 4.4tPHL 4.4tPZH 5.7tPZL 5.7tPHZ 4.5tPLZ 4.5UNIT: ns
OE B MAX
A B MAX
OE B MAX
676
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1623733.3-V ABT 16-BIT TRANSPARENTD-TYPE LATCHESWITH 3-STATE OUTPUTS
SN74LVTH162373: Output Ports HaveEquivalent 22-Ω Series Resistors
1OE
1LE
1D1
To Seven Other Channels
1Q1
2OE
2LE
2D12Q1
To Seven Other Channels
1
48
47
24
25
36C1
1D13
2C1
1D
FUNCTION TABLE(each 8-bit section)
INPUTS
H
L
DH
X
OUTPUTQH
Z
L L
OE
X
LEL
X Q0L
HHL
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LVTH3V UNIT
ICC MAX 5 mAIOH MAX -12 mAIOL MAX 12 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN LVTH3V
tw Pulse duration, LE high or low MIN 3Data before LE , data high MIN 1Data before LE , data low MIN 1Data after LE , data high MIN 1Data after LE , data low MIN 1
tPLH 4.6tPHL 4tPLH 5.1tPHL 4.6tPZH 5.4tPZL 4.9tPHZ 5.4tPLZ 5.1UNIT: ns
th Hold time
tsu Setup time
MAX
MAX
D Q
QLE
OE Q MAX
OE Q MAX
677
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
1623743.3-V ABT 16-BIT EDGE-TRIGGEREDD-TYPE FLIP-FLOPSWITH 3-STATE OUTPUTS
SN74LVTH162374: Output Ports HaveEquivalent 22-Ω Series Resistors
SN74ALVCH162374: Output Ports HaveEquivalent 26-Ω Series Resistors
1OE
1CLK
1D1
To Seven Other Channels
1Q1
2OE
2CLK
2D12Q1
To Seven Other Channels
1
48
47
24
25
36C1
1D13
2C1
1D
FUNCTION TABLE(each fllp-flop)
INPUTS
H
L
D
H
X
OUTPUTQ
H
Z
L L
OE
X
CLK
L
X Q0L
→→
L
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LVTH3V
ALVCH3V UNIT
ICC MAX 5 0.04 mAIOH MAX -12 -12 mAIOL MAX 12 12 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN LVTH3V
ALVCH3V
fmax 160 150tw Pulse duration, CLK high or low MIN 3 3.3
Data before CLK , data high MIN 1.8 1.9Data before CLK , data low MIN 1.8 1.9Data after CLK , data high MIN 0.8 0.5Data after CLK , data low MIN 0.8 0.5
tPLH 5.3 4.6tPHL 4.9 4.6tPZH 5.6 5.2tPZL 4.9 5.2tPHZ 5.4 4.5tPLZ 5 4.5UNIT fmax : MHz other : ns
OE Q MAX
OE Q MAX
th Hold time
tsu Setup time
MAXCLK Q
678
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
LED
CLKCE
LED
CLKCE
CLKCE
DLE
CLKCE
DLE
LECLKCED
LECLKCED
LECLKCED
LECLKCED
MUX
CECLK
DLE
P
CE_SEL0
CE_SEL1
CLKENAB
1B1
1B2
1B3
1B4
CLKENAB Selector
One of FourChannels
CLKAB
OEA
1A
OEB
OEB4
OEB3
OEB2
OEB1
CLKENBA
CLKBA
LEBA
SEL0
SEL1
CLKENB
LEB1
LEB2
LEB3
LEB4 LEAB4
LEAB3
LEAB2
LEAB1
24
23
6
5
31
54
3
8
21
10
26
12
48
49
51
52
19
15
14
9
29
30
55
56
1
2
27
28
20
1624604-TO-1 MULTIPLEXED/DEMULTIPLEXED REGISTERED TRANSCEIVERSWITH 3-STATE OUTPUTS
SN74ABTH162460: B-Port Outputs Have Equivalent 25-Ω Series Resistors
679PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
SWITCHING CHARACTERISTICS
MAX or MIN ABTH
fmax MIN 160CLKAB high or low MIN 3.8CLKBA high or low MIN 4.5LEAB1, 2, 3 or 4 high MIN 2.8LEBA high MIN 2.8LEB1, 2, 3 or 4 high MIN 3
A bus MIN 2.5CE_SEL0/1 MIN 3.2CLKENAB MIN 3.2
Before LEAB1, 2, 3, or 4 A bus MIN 3.6B bus MIN 3.8CLKENB MIN 2.3CLKENBA MIN 2.5LEB1, 2, 3 or 4 MIN 4.3SEL0/1 MIN 4.5
Before LEB1, 2, 3, or 4 B bus MIN 3.2B bus MIN 4LEB1, 2, 3 or 4 MIN 4.4SEL0/1 MIN 4.3A bus MIN 0.5
CE_SEL0/1 MIN 1.1
CLKENAB MIN 0.5
after LEAB1, 2, 3, or 4 A bus MIN 1.2B bus MIN 1.3
CLKENB MIN 1
CLKENBA MIN 1SEL0/1 MIN 0
after LEB1, 2, 3, or 4 B bus MIN 1.5B bus MIN 0.4SEL0/1 MIN 0.1
PARAMETER
tw Pulse duration
Before CLKAB
Before CLKBA
Before CLKBA
th Hold time
after CLKAB
after CLKBA
after CLKBA
tsu Setup time
PARAMETER INPUT OUTPUT MAX or MIN ABTH
tPLH 6.5tPHL 6.5tPZH 5.6tPZL 5.5tPHZ 5.9tPLZ 6.5tPLH 6.2tPHL 6.5tPZH 6.8tPZL 6.3tPHZ 6.2tPLZ 5.8tPZH 6.6tPZL 6.2tPHZ 5.3tPLZ 4.9tPLH 7.4tPHL 7.7tPLH 6.5tPHL 6.5tPLH 5.8tPHL 5.8tPLH 6.2tPHL 6.2tPLH 7.2tPHL 6.8tPLH 7.5tPHL 6.9UNIT: ns
LEBA1, 2, 3, 4 A MAX
SEL A MAX
LEBA A MAX
LEAB1, 2, 3, 4 B MAX
CLKBA A MAX
CLKAB B MAX
OEB1, 2, 3, 4 B MAX
OEB1, 2, 3, 4 B MAX
OEB B MAX
OEB B MAX
OEA A MAX
A B MAX
B A MAX
OEA A MAX
FUNCTION TABLE
INPUTS
H
LH
L
OUTPUTBnOEB
H
HL
L
OEBn
ZZZ
A-TO-B OUTPUT ENABLE
INPUTS
HLLLLL
OUTPUTSCLKENAB
XX
A0A0A0
A0
H or LH or L
L
CLKAB
HLHL
CE_SEL0XXX
XH
LH
L
CE_SEL1XXX
X
H
LH
LL
LEAB1
HL
LEAB2
HL
L L
LEAB3LLLLLL
LEAB4 B1
A0A
A
B2
A0A
B3
A0A
AA
A
B4
A0
A0 A0 A0A0
A0 A0 A0A0
A0A0
A0A0A0A0
A0
A0
A
A-TO-B STORAGE(assuming OEB = L, OEBn = L)
Active
† Output level before the indicated steady-state input conditions were established
†n = 1, 2, 3, 4
→
L
L L
L
→
L
L L
L
→
L
L L
→ L LL L→
INPUTS
X
LLLH
OUTPUTACLKENBA
XX
XXXX
L
CLKBAX XHHLL
LEBAHL
OEA
HL
X
XHL
L
B
HL
A0†
HL
A0†
X
B-TO-A STORAGE(after point P)
L
L
→
L
L
→ LL
INPUTS
L
L
PCLKENBXX
XXXX
L
CLKBAH
L
LEB1
B1
B40†B30†B20†B10†
B1
B2
B2
B3
B3
B4
B4
B-TO-A STORAGE(after point P)
L
L
H
L
LEB2
L
L
HL
L LLL
L LLEB3
L
L
H
L
XL
XL
LEB4
L
L
H
H
H
LSEL1
L
L
H
H
H
HH
L
H
L
H
HH
L
SEL0
L
L
L
L
L
L
→
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ABTH UNIT
ICC MAX 32 mAIOH (A port) MAX -32 mAIOH (B port) MAX -12 mAIOL (A port) MAX 64 mAIOL (B port) MAX 12 mA
680
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1DC1
CLK
1D
C1CLK
B1
OEAB
CLKAB
LEAB
LEBA
CLKBA
OEBA
A1
1
55
2
28
30
27
354
To 17 Other Channels
16250018-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
SN74ABT162500: B-Port Outputs Have Equivalent 25-Ω Series Resistors
681PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
FUNCTION TABLE
INPUTS
H
OUTPUTB
H
B0‡
XL
LEAB
‡ Output level before the indicated steady-state input conditions were established.
§ Output level before the indicated steady-state input conditions were established, provided that CLKAB was low before LEAB went low.
LOEAB
H
X
HL
A
X
L
L LX
X Z
LL
HHHHHHH
HLX
X
B0§
HL
CLKAB
→→
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ABT UNIT
ICC MAX 36 mAIOH (A port) MAX -32 mAIOH (B port) MAX -12 mAIOL (A port) MAX 64 mAIOL (B port) MAX 12 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ABT
fmax MIN 150LEAB or LEBA high MIN 2.5CLKAB or CLKBA high or low MIN 3A before CLKAB MIN 3.3B before CLKBA MIN 3.3A before LEAB or LEBA CLK high MIN 1A before LEAB or LEBA CLK low MIN 2.5A after CLKAB or B after CLKBA MIN 0A after LEAB or B after LEBA MIN 2
tPLH 4.8tPHL 5.7tPZH 5.6tPZL 5.9tPHZ 5.9tPLZ 6tPZH 5.3tPZL 5.4tPHZ 6.5tPLZ 5.8tPZH 5.3tPZL 5.4tPHZ 6.5tPLZ 5.8UNIT fmax : MHz other : ns
tw Pulse duration
tsu Setup time
th Hold time
MAX
LEAB or LEBA MAX
CLKAB or CLKBA MAX
OEBA
B
MAX
B
MAX
MAX
OEBA A MAX
A or B B or A
B or A
B or A
A
OEAB
OEAB
682
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1DC1
CLK
1D
C1CLK
B1
OEAB
CLKAB
LEAB
LEBA
CLKBA
OEBA
A1
1
55
2
28
30
27
354
To 17 Other Channels
16250118-BIT UNIVERSAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SN74ABT162501: B-Port Outputs Have Equivalent 25-Ω Series Resistors
683PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
FUNCTION TABLE†INPUTS
XH
ACLKAB
L
L
OUTPUTYZ
HH
OEABL
H
X
HXX
H
L
LEABX
LHH
HHL
XH
B0‡LL X B0§L
HH
→→
L
† A-to-B data flow is shown: B-to-A flow is similar but uses OEBA, LEBA, and CLKBA.
‡ Output level before the indicated steady-state input conditions were established, provided that CLKAB was high before LEAB went low
§ Outoput level before the indicated steady-state input conditions were established
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ABT UNIT
ICC MAX 36 mAIOH (A port) MAX -32 mAIOH (B port) MAX -12 mAIOL (A port) MAX 64 mAIOL (B port) MAX 12 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ABT
fmax MIN 150LEAB or LEBA high MIN 3CLKAB or CLKBA high or low MIN 3.3A before CLKAB MIN 4.3B before CLKBA MIN 4.3A before LEAB or LEBA CLK high MIN 2.5A before LEAB or LEBA CLK low MIN 1A after CLKAB or B after CLKBA MIN 0A after LEAB or B after LEBA MIN 2
tPLH 4.8tPHL 5.7tPZH 5.6tPZL 5.9tPHZ 5.5tPLZ 5.3tPZH 5.3tPZL 5.4tPHZ 6.5tPLZ 5.8tPZH 5.3tPZL 5.4tPHZ 6.5tPLZ 5.8UNIT fmax : MHz other : ns
OEBA A MAX
A or B B or A
B or A
B or A
A
OEAB
OEAB
CLKAB or CLKBA MAX
OEBA
B
MAX
B
MAX
MAX
tw Pulse duration
MAX
LEAB or LEBA MAX
tsu Setup time
th Hold time
684
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
B1
CLKAB
CLK1BA
CLK2BA
CLKENBA
CLKENAB
OEAB
OEBA
SEL
CE
C1
1DA1
CE
C1
1D
CE
C11D
CE
C11D
CE
C11D
1
1
1 of 18 Channels
G1
55
30
29
28
1
2
27
56
3 54
16252518-BIT REGSTERED BUS TRANSCEIVER WITH 3-STATE OUTPUTS
SN74ALVCH162525: B-Port Outputs Have Equivalent 26-Ω Series Resistors
685PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
FUNCTION TABLE
INPUTS OUTPUTCLKNAB
XH
HLL
OLKAB BXL
A
A-TO-B STORAGE(OEAB=L)
L
A0†
B0†
H→→→
INPUTS OUTPUTCLK1BA
LL
LH HH
L
LHL
H‡L‡L
CLKENBA B ASEL
B-TO-A STORAGE (OEBA = L)
→
XX
CLK2BA
→→
→
H X X XX
L HL→→
† Output level before the indicated steady-state input conditions were established
‡ Three CLK1BA edges and one CLK2BA edge are needed to propagate data from B to A when SEL is low.
† Output level before the indicated steady-state input conditions were established
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALVCH3V UNIT
ICC MAX 0.04 mAIOH (A port) MAX -24 mAIOH (B port) MAX -12 mAIOL (A port) MAX 24 mAIOL (B port) MAX 12 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALVCH3V
fmax MIN 150tw Pulse duration, CLK high or low MIN 3
A data before CLKAB MIN 1.3B data before CLK2BA MIN 1.7B data before CLK1BA MIN 1.1SEL before CLK2BA MIN 3.3CLKENAB before CLKAB MIN 1.6CLKENBA before CLK1BA MIN 2.1CLKENBA before CLK2BA MIN 2.2A data after CLKAB MIN 0.9B data after CLK2BA MIN 0.6B data after CLK1BA MIN 1SEL after CLK2BA MIN 0.1CLKENAB after CLKAB MIN 0.3CLKENBA after CLK1BA MIN 0.1CLKENBA after CLK2BA MIN 0
CLKAB B 4.7
CLK2BA A 4.2
OEBA A 5.1
OEAB B 5.7
OEBA A 4.9
OEAB B 4.9UNIT fmax : MHz other : ns
tdis
MAX
MAX
tsu Setup time
th Hold time
tpd MAX
ten
686
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1625413.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SN74LVTH162541: Output Ports Have Equivalent 22-Ω Series Resistors
1OE1
1OE2
2OE1
2OE2
1A1 1Y1
2Y12A1
To Seven Other Channels
To Seven Other Channels
1
48
47
24
25
36
2
13
687PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
FUNCTION TABLE(each 8-bit section)
INPUTS
LA
X
L
OUTPUTY
HH
OE1
HX
LZ
OE2
ZX
XH
LL L
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LVTH3V UNIT
ICC MAX 5 mAIOH MAX -12 mAIOL MAX 12 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN LVTH3V
tPLH 4.1tPHL 4.1tPZH 5tPZL 4.8tPHZ 5.9tPLZ 5.4UNIT: ns
OE Y MAX
A Y MAX
OE Y MAX
688
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
CE
1DC1
CLK
CE
1D
C1CLK
B1
OEAB
CLKENAB
CLKAB
LEAB
LEBA
CLKBA
CLKENBA
OEBA
A1
1
56
55
2
28
30
29
27
354
To 17 Other Channels
16260118-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
SN74ABT162601: B-Port Outputs Have Equivalent 25-Ω Series Resistors SN74ALVCH162601: B-Port Outputs Have Equivalent 26-Ω Series Resistors
689PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
FUNCTION TABLE
INPUTS
H
OUTPUTB
H
B0‡
XL
† A-to-B data flow is shown: B-to-A flow is similar but uses OEBA, LEBA, CLKBA, and CLKENBA.
‡ Output level before the indicated steady-state input conditions were established.
§ Output level before the indicated steady-state input conditions were established, provided that CLKAB was low before LEAB went low.
H
X
HL
X
L
LL X
X Z
LL
HHH
HLX
X
B0§
HL
LH
CLKENAB OEABX
LXX
B0‡B0‡
L
XL
X
L
L
XL
X
L
L
L
LLLL
→→
LEAB CLKAB A
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ABT ALVCH3V UNIT
ICC MAX 36 0.04 mAIOH (A port) MAX -32 -24 mAIOH (B port) MAX -12 -12 mAIOL (A port) MAX 64 24 mAIOL (B port) MAX 12 12 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ABT ALVCH3V
fmax MIN 150 150LEAB or LEBA high MIN 2.5 3.3CLKAB or CLKBA high or low MIN 3 3.3Data before CLK MIN 4.3 2.1A before LEAB or B before LEBA , CLK high MIN 2.5 1.6A before LEAB or B before LEBA , CLK low MIN 1 1.1CLKEN before MIN 2.7 1.7Data after CLK MIN 0 0.8A after LEAB or B after LEBA , CLK high MIN 0.5 1.4A after LEAB or B after LEBA , CLK low MIN 0.5 1.7CLKEN after MIN 0 0.6
tPLH 4.8 4.5tPHL 5.7 4.5tPLH 4 4.1tPHL 4.9 4.1tPLH 5 4.7tPHL 5 4.7tPLH 5.6 5.1tPHL 5.9 5.1tPLH 5.3 5tPHL 5 5tPLH 5.5 5.5tPHL 5.3 5.5tPZH 5.1 5.2tPZL 5.4 5.2tPZH 6.1 5.7tPZL 5.7 5.7tPHZ 6.2 4.4tPLZ 5.4 4.4tPHZ 5.4 4.8tPLZ 5.2 4.8UNIT fmax : MHz other : ns
CLKBA A
B
MAX
CLKAB MAX
LEAB
A
B
MAX
MAX
tw Pulse duration
MAX
LEBA MAX
B A
tsu Setup time
th Hold time
B
MAX
MAX
A
OEAB B MAX
A B
OEBA
OEAB
OEBA
A
MAX
690
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
1627213.3-V 20-BIT FLIP-FLOPWITH 3-STATE OUTPUTS
SN74ALVCH162721: Output Ports Have Equivalent26-Ω Series Resistors
D1
CLK
CLKEN
To 19 Other Channels
C1
OE
Q1
1
56
29
552
CE
1D
FUNCTION TABLE
INPUTS
(each flip-flop)
OUTPUTQ
LX
L
DCLK
ZH
HL
OE CLKEN
L
XQ0
Q0
L
→→
X
LH
X
LH
LL XL or H
X
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALVCH3V UNIT
ICC MAX 0.04 mAIOH MAX -12 mAIOL MAX 12 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALVCH3V
fmax MIN 150tw Pulse duration CLK high or low MIN 3.3
Data before CLK MIN 3.1
CLKEN before CLK MIN 2.7
Data after CLK MIN 0
CLKEN after CLK MIN 0tPLH 5.3tPHL 5.3tPZH 5.8tPZL 5.8tPHZ 5tPLZ 5UNIT fmax : MHz other : ns
tsu Setup time
th Hold time
CLK
Q
OE
OE MAX
MAXQ
Q MAX
691
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
1628203.3-V 10-BIT FLIP-FLOP WITH DUAL OUTPUTSAND 3-STATE OUTPUTS
SN74ALVCH162820: Output Ports Have Equivalent26-Ω Series Resistors
C1
1D
1
28
56
55
2
3
To Nine Other Channels
1OE
2OE
CLK
D1
1Q1
1Q2
FUNCTION TABLE
INPUT
(each flip flop)
HL
DH
X
OUTPUT
H
Z
L L
OEn†
†n = 1,2
L
CLK
XQ0
X
L↑ ↑
LQ
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALVCH3V UNIT
ICC MAX 0.04 mAIOH MAX -12 mAIOL MAX 12 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALVCH3V
fmax MIN 150tw Pulse duration CLK high or low MIN 3.3tsu Setup time Data before CLK MIN 1.4th Hold time Data after CLK MIN 1tPLH 5.4tPHL 5.4tPZH 5.6tPZL 5.6tPHZ 5tPLZ 5UNIT fmax : MHz other : ns
CLK
Q
OE
OE MAX
MAXQ
Q MAX
692
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
16
17
15
7
CLK
D Q
18
To Six Other Channels
5
4
2
1
OE1
OE2
CLK
A1
SEL
1Y1
2Y1
3Y1
4Y1
16282318-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN74ABT162823A: Output Ports Have Equivalent 25-Ω Series Resistors
FUNCTION TABLE
INPUTS
XL
DCLENK CLK
L L
OUTPUTQL
L
X
OEL
L
X
LLL
X
CLRL
HHL
H ZH
X
Q0
X
X
HL
X
XX
Q0
HH →
→
H
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ABT UNIT
ICC MAX 80 mAIOH MAX -12 mAIOL MAX 12 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ABT
fmax MIN 150
CLR low MIN 3.3
CLK high or low MIN 3.3
CLR inactive MIN 1.6
Data before CLK MIN 2
CLKEN low before CLK MIN 2.8
Data after CLK MIN 1.2
CLKEN low after CLK MIN 0.6tPLH 7.5tPHL 6.7tPHL CLR Q MAX 7tPZH 5.9tPZL 7tPHZ 6.6tPLZ 9UNIT fmax : MHz other : ns
tw Pulse duration
CLK
tsu Setup time
th Hold time
Q MAX
Q
OE
OE MAX
MAXQ
693
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
1A1 1Y12
1
55
56
To Eight Other Channels
2A1 2Y116
28
41
29
To Eight Other Channels
1OE1
1OE2
2OE1
2OE2
16282518-BIT BUFFERS/DRIVERSWITH 3-STATE OUTPUTS
SN74ABT162825: Output Ports Have Equivalent25-Ω Series Resistors
FUNCTION TABLE
INPUTS
H
L
A
H
X
OUTPUTY
H
ZX
LOE2
HL
X
OE1L LL
X Z
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ABT UNIT
ICC MAX 32 mAIOH MAX -12 mAIOL MAX 12 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ABT
tPLH 3.9tPHL 4.7tPZH 6.9tPZL 6.3tPHZ 6.6tPLZ 6.3UNIT: ns
OE Y MAX
A Y MAX
OE Y MAX
694
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
16282720-BIT BUS BUFERS/DRIVERSWITH 3-STATE OUTPUTS
SN74ABT162827A: Output Ports Have Equivalent25-Ω Series Resistors
SN74ALVTH162827: Output Ports Have Equivalent30-Ω Series Resistors
SN74ALVCH162827: Output Ports Have Equivalent26-Ω Series Resistors
1Y12
1
55
1OE11OE2
56
2Y115
28
42
292OE12OE2
To Nine Other Channels
To Nine Other Channels
1A1
2A1
FUNCTION TABLE
INPUTS
(each flip flop)
XH
AL
X
OUTPUT
L
Z
H H
OE1
†n = 1,2
X
OE2
HZ
X
LLL
LY
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ABT ALVTH3V
ALVCH3V UNIT
ICC MAX 32 5.5 0.04 mAIOH MAX -12 -12 -12 mAIOL MAX 12 12 12 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ABT ALVTH3V
ALVCH3V
tPLH 3.9 3.9 3.8tPHL 4.7 3.7 3.8tPZH 6.9 5.6 5.1tPZL 6.3 4.1 5.1tPHZ 6.6 6.3 4.7tPLZ 6.3 5.1 4.7UNIT: ns
OE Y MAX
A Y MAX
OE Y MAX
695
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
1628301-BIT TO 2-BIT ADDRESS DRIVERWITH 3-STATE OUTPUTS
SN74ALVCH162830, SN74ALVCHS162830: OutputPorts Have Equivalent 26-Ω Series Resistors
To 17 Other Channels
1Y1
2Y1
A1
OE2
OE1
21
20
7
5
4
FUNCTION TABLE
INPUTS OUTPUTS
LA
L
LH
LH
HOE1
HH
L
L
HL
OE2
LX
1Yn
Z
LH
Z
LH
Z
2YnZ
LHZ
LH
ZH
LHH
LL
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALVCH3V
ALVCHS3V UNIT
ICC MAX 0.04 0.04 mAIOH MAX -12 -12 mAIOL MAX 12 12 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALVCH3V
ALVCHS3V
tPLH 3.5 3.5tPHL 3.5 3.5tPZH 4.8 4.8tPZL 4.8 4.8tPHZ 5.2 5.2tPLZ 5.2 5.2UNIT: ns
OE Y MAX
A Y MAX
OE Y MAX
696
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
20
21
19
8
CLK
D Q
22
To Eight Other Channels
5
4
2
1
OE1
OE2
CLK
A1
SEL
1Y1
2Y1
3Y1
4Y1
1628311-BIT TO 4-BIT ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS
SN74ALVC162831, SN74ALVCH162831: Output Ports Have Equivalent 26-Ω Series Resistors
FUNCTION TABLE
INPUTS
XHH
CLKSELOUTPUT
YZ
OEHLLLL
XXX
AX
LL
LH
LH
LH
LH
→→
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALVC3V
ALVCH3V UNIT
ICC MAX 0.04 0.04 mAIOH MAX -12 -12 mAIOL MAX 12 12 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALVC3V
ALVCH3V
fmax MIN 150 150tw Pulse duration CLK high or low MIN 3.3 3.3tsu Setup time A data before CLK MIN 1.6 1.6th Hold time A data after CLK MIN 1.1 1.1tPLH 4.3 4.3tPHL 4.3 4.3tPLH 4.7 4.7tPHL 4.7 4.7tPLH 4.8 4.8tPHL 4.8 4.8tPZH 5.1 5.1tPZL 5.1 5.1tPHZ 5.1 5.1tPLZ 5.1 5.1UNIT fmax : MHz other : ns
MAX
MAX
MAX
Y
OE
OE
Y
A Y MAX
SEL Y MAX
YCLK
Logic Diagram
16
17
15
7
CLK
D Q
18
To Six Other Channels
5
4
2
1
OE1
OE2
CLK
A1
SEL
1Y1
2Y1
3Y1
4Y1
697PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
1628321-BIT TO 4-BIT ADDRESS REGISTER/DRIVER WITH 3-STATE OUTPUTS
SN74ALVCH162832: Output Ports Have Equivalent 26-Ω Series Resistors
FUNCTION TABLE
INPUTS
XHH
CLKSELOUTPUT
YZ
OEHLLLL
XXX
AX
LL
LH
LH
LH
LH
→→
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALVCH3V UNIT
ICC MAX 0.04 mAIOH MAX -12 mAIOL MAX 12 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALVCH3V
fmax MIN 150tw Pulse duration CLK high or low MIN 3.3tsu Setup time A data before CLK MIN 1.6th Hold time A data after CLK MIN 1.1tPLH 4.3tPHL 4.3tPLH 4.7tPHL 4.7tPLH 4.8tPHL 4.8tPZH 5.1tPZL 5.1tPHZ 5.1tPLZ 5.1UNIT fmax : MHz other : ns
MAX
SEL Y MAX
YCLK
OE
OE
Y
A Y
MAX
MAX
MAX
Y
698
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
16283418-BIT UNIVERSAL BUS DRIVERWITH 3-STATE OUTPUTS
SN74ALVC162834: Outputs Have Equivalent26-Ω Series Resistors
OE
CLK
Y1
1D
C1
CLK
To 17 Other Channels
LE
A1
27
30
28
54
3
FUNCTION TABLE
INPUTS
XL
ACLK
L
L
OUTPUTYZ
HH
OEH
L
X
LXX
H
L
LEX
HHL
LHH
XL
Y0†HL X Y0‡H
LL
→→
L
† Output level before the indicated steady-state input conditions were established, provided that CLK is high before LE goes high
‡ Output level before the indicated steady-state input conditions were established
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALVC3V UNIT
ICC MAX 0.04 mAIOH MAX -12 mAIOL MAX 12 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALVC3V
fmax MIN 150
LE low MIN 3.3
CLK high or low MIN 3.3
Data before CLK MIN 1.7
Data before LE , CLK high MIN 1.9
Data before LE , CLK low MIN 1.5
A data after CLK MIN 0.7
Data after LE , CLK high MIN 0.9
Data after LE , CLK low MIN 0.9tPLH 4.2tPHL 4.2tPLH 5.8tPHL 5.8tPLH 5.4tPHL 5.4tPZH 5.9tPZL 5.9tPHZ 5tPLZ 5UNIT fmax : MHz other : ns
MAX
MAX
th Hold time
OE
tsu Setup time
tw Pulse duration
OE
Y
A Y
LE Y
YCLK
MAX
MAX
MAX
Y
699
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
16283518-BIT UNIVERSAL BUS DRIVERWITH 3-STATE OUTPUTS
SN74ALVC162835, SN74ALVCH162835: Output PortHas Equivalent 26-Ω Series Resistors
OE
CLK
Y1
1D
C1
CLK
To 17 Other Channels
LE
A1
27
30
28
54
3
FUNCTION TABLE
INPUTS
XL
ACLK
L
L
OUTPUTYZ
HH
OEH
L
X
LXX
L or H
L
† Output level before the indicated steady-state input conditions were established
LEX
LHL HLXL Y0†L
HH
→→
L
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALVC3V
ALVCH3V UNIT
ICC MAX 0.04 0.04 mAIOH MAX -12 -12 mAIOL MAX 12 12 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALVC3V
ALVCH3V
fmax MIN 150 150
LE low MIN 3.3 3.3
CLK high or low MIN 3.3 3.3
Data before CLK MIN 1.7 1.7
Data before LE , CLK high MIN 1.5 1.5
Data before LE , CLK low MIN 1 1
A data after CLK MIN 0.7 0.7
Data after LE , CLK high MIN 1.4 1.4
Data after LE , CLK low MIN 1.4 1.4tPLH 4.2 4.2tPHL 4.2 4.2tPLH 5.1 5.1tPHL 5.1 5.1tPLH 5.4 5.4tPHL 5.4 5.4tPZH 5.5 5.5tPZL 5.5 5.5tPHZ 4.5 4.5tPLZ 4.5 4.5UNIT fmax : MHz other : ns
tsu Setup time
tw Pulse duration
MAX
MAX
MAX
Y
OE
OE
Y
A
YCLK
th Hold time
MAXY
LE Y MAX
700
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
16283620-BIT UNIVERSAL BUS DRIVERWITH 3-STATE OUTPUTS
SN74ALVC162836, SN74ALVCH162836: Output PortHas Equivalent 26-Ω Series Resistors
1
56
29
551D
C1
CLK
2
To 19 Other Channels
OE
CLK
LE
A1
Y1
FUNCTION TABLE
INPUTS
XL
ACLK
L
L
OUTPUTYZ
HH
OEH
L
X
LXX
L or H
L
LEX
HHL
LHH
X Y0†H
LL
→→
L
† Output level before the indicated steady-state input conditions were established
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ALVC3V
ALVCH3V UNIT
ICC MAX 0.04 0.04 mAIOH MAX -12 -12 mAIOL MAX 12 12 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ALVC3V
ALVCH3V
fmax MIN 150 150
LE low MIN 3.3 3.3
CLK high or low MIN 3.3 3.3
Data before CLK MIN 1.5 1.5
Data before LE , CLK high MIN 1.3 1.3
Data before LE , CLK low MIN 1.2 1.2
A data after CLK MIN 0.9 0.9
Data after LE , CLK high MIN 1.1 1.1
Data after LE , CLK low MIN 1.1 1.1tPLH 4 4tPHL 4 4tPLH 5.1 5.1tPHL 5.1 5.1tPLH 5 5tPHL 5 5tPZH 5.5 5.5tPZL 5.5 5.5tPHZ 5.1 5.1tPLZ 5.1 5.1UNIT fmax : MHz other : ns
YCLK
th Hold time
MAXY
LE Y MAX
tsu Setup time
tw Pulse duration
MAX
MAX
MAX
Y
OE
OE
Y
A
701
Logic Diagram
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
16284120-BIT BUS-INTERFACE D-TYPE LATCHWITH 3-STATE OUTPUTS
SN74ABT162841: Output Ports Have Equivalent25-Ω Series Resistors
SN74ALVCH162841: Output Ports HaveEquivalent 26-Ω Series Resistors
1OE
To Nine Other Channels
1
56
552
1LE
1D1
C1
1D1Q1
2OE
To Nine Other Channels
28
29
4215
2LE
2D1
C1
1D2Q1
FUNCTION TABLE(each 10-bit latch)
INPUTS
LD
L
OUTPUTQ
Z
HHOE
HL
X
L L
LE
X
H
XHL Q0
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN ABT ALVCH3V UNIT
ICC MAX 89 0.04 mAIOH MAX -12 -12 mAIOL MAX 12 12 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN ABT ALVCH3V
tw Pulse duration LE high or low MIN 4 3.3tsu Setup time Data before LE MIN 0.8 1.1th Hold time Data after LE MIN 1.8 1.1tPLH 5.2 4.3tPHL 6 4.3tPLH 5.4 4.7tPHL 5.8 4.7tPZH 5.7 5.3tPZL 6.5 5.3tPHZ 6.5 4.4tPLZ 7.1 4.4UNIT: ns
MAX
MAX
Q
OE
OE
Q
D
LE MAX
MAX
Q
Q
702
Logic Diagram
: OBSOLETED or NOT RECOMMENDED NEW DESIGNS
16424516-BIT TRANSCEIVER AND 3.3-V TO 5-VSHIFTERWITH 3-STATE OUTPUTS
SN74ALVC164245:A port has VCCA, which is set to operate at 2.5 Vand 3.3 VB port has VCCB, which is set to operate at 3.3 Vand 5 V
SN74AVCB164245, SN74AVCBH164245: The A-port is designed to track VCCA, VCCA acceptsany supply voltage from 1.4 V to 3.6 VThe B-port is designed to track VCCB, VCCB acceptsany supply voltage from 1.4 V to 3.6 V
To Seven Other Channels
1DIR
1A1
1B1
1OE
To Seven Other Channels
2DIR
2A1
2B1
2OE
1
47
24
36
48
2
25
13FUNCTION TABLE(each 8-bit section)
INPUTS
L
DIR OPERATION
L
OE
H IsolationL H
X
B data to A busA data to B bus
RECOMMENDED OPERATING CONDITIONS
MAX or MIN AVCB AVCBH UNIT
MAX - - mAMAX 0.04 0.04 mAMAX - - mAMAX - - mAMAX -8 -8 mAMAX 8 8 mA
ALVC
0.040.02
12
-2424-12
PARAMETER
ICC (5V)
IOL (2.3V)IOH (2.3V)
ICC (3V)IOH (5V)IOL (5V)
SWITCHING CHARACTERISTICS
AVCB AVCBH
VCCB : 3VVCCA : 2.3V
VCCB : 5VVCCA : 3V
VCCB : 3VVCCA : 2.3V
VCCB : 3VVCCA : 2.3V
tPLH 7.6 5.8 3.4 3.4tPHL 7.6 5.8 3.4 3.4tPLH 7.6 5.8 3.7 3.7tPHL 7.6 5.8 3.7 3.7tPZL 11.5 8.9 5.1 5.1tPZH 11.5 8.9 5.1 5.1tPZL 12.3 9.1 4.2 4.2tPZH 12.3 9.1 4.2 4.2tPLZ 10.5 9.5 3.3 3.3tPHZ 10.5 9.5 3.3 3.3tPLZ 9.3 8.6 3 3tPHZ 9.3 8.6 3 3UNIT: ns
ALVCPARAMETER INPUT OUTPUT MAX or MIN
MAX
MAX
MAX
MAX
MAX
MAX
A B
OE B
B A
OE
OE
OE
A
B
A
703PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. See www.ti.com/sc/logic for the most current data sheets.
Logic Diagram
3223743.3-V ABT 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
Output Ports Have Equivalent 22-Ω Series Resistors
1OE
1CLK
1D1
To Seven Other Channels
1Q1
2OE
2CLK
2D12Q1
To Seven Other Channels
A3
A4
A5
H3
H4
E5C1
1DE2A2C1
1D
3OE
3CLK
3D1
To Seven Other Channels
3Q1
4OE
4CLK
4D14Q1
To Seven Other Channels
J3
J4
J5
T3
T4
N5C1
1DJ2C1
1D
N2
INPUTS
H or L
CLKOUTPUT
Q
Z
OE
H
LLL
X
D
XX
HHLQ0
L
FUNCTION TABLE(each 8bit flip-flop)
↑↑
RECOMMENDED OPERATING CONDITIONS
PARAMETER MAX or MIN LVTH3V UNIT
ICC MAX 10 mAIOH MAX -12 mAIOL MAX 12 mA
SWITCHING CHARACTERISTICS
PARAMETER INPUT OUTPUT MAX or MIN LVTH3V
fmax 160tw Pulse duration, CLK high or low MIN 3
Data before CLK , data high MIN 1.8Data before CLK , data low MIN 1.8Data after CLK , data high MIN 0.8Data after CLK , data low MIN 0.8
tPLH 5.3tPHL 4.9tPZH 5.6tPZL 4.9tPHZ 5.4tPLZ 5UNIT fmax : MHz other : ns
th Hold time
tsu Setup time
MAXCLK Q
OE Q MAX
OE Q MAX
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A070802
SCYD013Printed in Japan0103