Logic gatesFrom Wikipedia, the free encyclopedia

Contents

1 AND gate 11.1 Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 Implementations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.2.1 Alternatives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3 See also . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2 AND-OR-Invert 32.1 Logic operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32.2 Electronic implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42.3 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3 Booleo 63.1 The game . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63.2 Play . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63.3 Variations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73.4 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

4 C-element 84.1 Truth table and delay assumptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84.2 Implementations of the C-element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.2.1 Gate-level implementations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104.2.2 Static and semi-static embodiments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4.3 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114.4 External links . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5 C-ROT gate 135.1 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

6 Computer module 146.1 History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146.2 Benefits of Computer Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156.3 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

7 Controlled NOT gate 16

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7.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167.2 Behaviour of CNOT in the Hadamard basis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187.3 Details of the computation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207.4 Constructing the Bell State |Φ+⟩ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207.5 See also . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217.6 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217.7 External links . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217.8 Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

8 David E. Muller 228.1 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228.2 See also . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228.3 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

9 Diode-or circuit 24

10 Fan-in 2510.1 See also . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

11 Fan-out 2611.1 Logical practice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2611.2 Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

11.2.1 DC fan-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2711.2.2 AC fan-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

11.3 See also . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2811.4 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2811.5 External links . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

12 Fredkin gate 2912.1 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3012.2 Logic function with XOR and AND gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3012.3 Completeness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3012.4 Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3012.5 See also . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3012.6 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3112.7 Further reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

13 Gate equivalent 3213.1 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3213.2 See also . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

14 IMPLY gate 3314.1 Implementations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3314.2 See also . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

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14.3 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

15 NOT gate 3415.1 Electronic implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

15.1.1 Digital building block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3515.1.2 Alternatives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3515.1.3 Performance measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

15.2 See also . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3715.3 External links . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3715.4 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

16 Linear optical quantum computing 3816.1 Overview of linear optical quantum computation . . . . . . . . . . . . . . . . . . . . . . . . . . . 3816.2 Elements of LOQC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

16.2.1 Qubits and modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3916.2.2 State preparation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4016.2.3 State measurement/readout of KLM protocol . . . . . . . . . . . . . . . . . . . . . . . . 4016.2.4 Implementations of elementary quantum gates . . . . . . . . . . . . . . . . . . . . . . . . 4016.2.5 Implementation of nondeterministic conditional sign flip gate . . . . . . . . . . . . . . . . 4116.2.6 Gates teleportation and near-deterministic gates . . . . . . . . . . . . . . . . . . . . . . . 4216.2.7 Error detection and correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

16.3 Improvements of KLM protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4316.4 Integrated photonic circuits for LOQC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4316.5 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4316.6 External links . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

17 Logic gate 4617.1 Electronic gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4617.2 Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4717.3 Universal logic gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4817.4 De Morgan equivalent symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4817.5 Data storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5017.6 Three-state logic gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5017.7 History and development . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5017.8 Implementations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5117.9 See also . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5117.10References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5217.11Further reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

18 Logical equality 5318.1 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5418.2 Alternative descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5418.3 See also . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

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18.4 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5518.5 External links . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

19 Magnetic logic 5619.1 See also . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5619.2 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

20 Majority function 5720.1 Boolean circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5720.2 Monotone formulae for majority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5720.3 Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5820.4 Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5820.5 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5820.6 See also . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

21 Molecular logic gate 5921.1 See Also . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6521.2 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6521.3 External links . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

22 NAND gate 6722.1 Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6722.2 Hardware description and pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

22.2.1 CMOS version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6722.3 Implementations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

22.3.1 Alternatives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6922.4 See also . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6922.5 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7022.6 External links . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

23 NAND logic 7123.1 NAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7123.2 NOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7123.3 AND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7123.4 OR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7123.5 NOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7123.6 XOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7223.7 XNOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7223.8 See also . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7223.9 External links . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7223.10References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

24 NOR gate 7324.1 Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

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24.2 Hardware description and pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7324.2.1 Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

24.3 Implementations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7524.3.1 Alternatives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

24.4 See also . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7624.5 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7624.6 External links . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

25 NOR logic 7725.1 NOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7725.2 Making other gates by using NOR gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

25.2.1 NOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7725.2.2 OR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7825.2.3 AND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7825.2.4 NAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7825.2.5 XOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7825.2.6 XNOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

25.3 See also . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7825.4 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

26 NOT gate 7926.1 Electronic implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

26.1.1 Digital building block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8026.1.2 Alternatives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8026.1.3 Performance measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

26.2 See also . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8226.3 External links . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8226.4 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

27 OR gate 8327.1 Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8327.2 Hardware description and pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8327.3 Implementations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

27.3.1 Alternatives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8527.4 Wired-OR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8527.5 See also . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8527.6 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

28 Photochemical logic gate 8728.1 The OR gate electron–photon transfer chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8728.2 The ‘AND’ gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8728.3 Creating the NOT gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8828.4 See also . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

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28.5 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

29 Pulse transition detector 89

30 Quantum gate 9030.1 Commonly used gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

30.1.1 Hadamard gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9030.1.2 Pauli-X gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9130.1.3 Pauli-Y gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9130.1.4 Pauli-Z gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9130.1.5 Phase shift gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9230.1.6 Swap gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9230.1.7 Square root of Swap gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9230.1.8 Controlled gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9330.1.9 Toffoli gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9530.1.10 Fredkin gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

30.2 Universal quantum gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9630.3 History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9730.4 See also . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9730.5 Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9730.6 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

31 Race condition 9931.1 Electronics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

31.1.1 Critical and non-critical race conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 9931.1.2 Static, dynamic, and essential race conditions . . . . . . . . . . . . . . . . . . . . . . . . . 99

31.2 Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10131.2.1 Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10131.2.2 File systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10131.2.3 Networking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10131.2.4 Life-critical systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10231.2.5 Computer security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

31.3 Examples outside of Computing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10231.3.1 Biology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

31.4 See also . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10231.5 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10231.6 External links . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

32 Racetrack problem 10432.1 See also . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10432.2 External links . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

33 Reconvergent fan-out 105

CONTENTS vii

33.1 See also . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10533.2 External links . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

34 Sheffer stroke 10634.1 Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

34.1.1 Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10734.2 History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10734.3 Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10734.4 Introduction, elimination, and equivalencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10734.5 Formal system based on the Sheffer stroke . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

34.5.1 Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10734.5.2 Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10834.5.3 Calculus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10834.5.4 Simplification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

34.6 See also . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10934.7 Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10934.8 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11034.9 External links . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

35 Shift register lookup table 11135.1 See also . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11135.2 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

36 Standard cell 11336.1 Construction of a standard cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11436.2 Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11536.3 Application of standard cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

36.3.1 Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11536.3.2 Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

36.4 Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11636.4.1 DRC/LVS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

36.5 Other cell-based methodologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11736.6 Complexity measure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11736.7 See also . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11736.8 External links . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

37 Toffoli gate 11837.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11937.2 Universality and Toffoli gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11937.3 Related logic gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11937.4 Relation to quantum computing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12037.5 See also . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12037.6 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

viii CONTENTS

38 Transmission gate 12238.1 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12238.2 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12238.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

38.3.1 Electronic switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12338.3.2 Logic circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12438.3.3 Negative voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

38.4 See also . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12438.5 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

39 Tseitin transformation 12639.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12639.2 Approach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12639.3 Gate Sub-expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12639.4 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12739.5 Simple combinatorial logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12739.6 Derivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

39.6.1 OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12739.6.2 NOT Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12839.6.3 NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

39.7 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

40 Wired logic connection 12940.1 The wired AND connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12940.2 The wired OR connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13040.3 Reversed levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13040.4 Compatibility of wired AND OR using diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13240.5 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13240.6 External links . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

41 Wolfram axiom 13341.1 See also . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13341.2 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13341.3 External links . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

42 XNOR gate 13542.1 Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13542.2 Hardware description and pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13542.3 Alternatives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13642.4 See also . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13742.5 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

43 XOR gate 138

CONTENTS ix

43.1 Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13843.2 Alternatives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13843.3 More than two inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13943.4 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

43.4.1 Uses in addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14043.4.2 Pseudo-random number generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14043.4.3 Correlation and sequence detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

43.5 See also . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14143.6 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14143.7 External links . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14243.8 Text and image sources, contributors, and licenses . . . . . . . . . . . . . . . . . . . . . . . . . . 143

43.8.1 Text . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14343.8.2 Images . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14643.8.3 Content license . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Chapter 1

AND gate

The AND gate is a basic digital logic gate that implements logical conjunction - it behaves according to the truthtable to the right. A HIGH output (1) results only if both the inputs to the AND gate are HIGH (1). If neither or onlyone input to the AND gate is HIGH, a LOW output results. In another sense, the function of AND effectively findsthe minimum between two binary digits, just as the OR function finds the maximum. Therefore, the output is always0 except when all the inputs are 1s.

1.1 Symbols

There are three symbols for AND gates: the American (ANSI or 'military') symbol and the IEC ('European' or'rectangular') symbol, as well as the deprecated DIN symbol. For more information see Logic Gate Symbols.The AND gate with inputs A and B and output C implements the logical expression C = A ·B .

1.2 Implementations

An AND gate is usually designed using N-channel (pictured) or P-channel MOSFETs. The digital inputs a and bcause the output F to have the same result as the AND function.

1.2.1 Alternatives

If no specific AND gates are available, one can be made from NAND or NOR gates, because NAND and NOR gatesare considered the “universal gates,” [1] meaning that they can be used to make all the others.

1.3 See also• OR gate

• NOT gate

• NAND gate

• NOR gate

• XOR gate

• XNOR gate

• Boolean algebra

• Logic gate

1

2 CHAPTER 1. AND GATE

1.4 References[1] Mano, M. Morris and Charles R. Kime. Logic and Computer Design Fundamentals, Third Edition. Prentice Hall, 2004. p.

73.

Chapter 2

AND-OR-Invert

2-2 AOI Symbol

AND-OR-Invert (AOI) logic and AOI gates are two-level compound (or complex) logic functions constructed fromthe combination of one or more AND gates followed by a NOR gate. Construction of AOI cells is particularly efficientusing CMOS technology where the total number of transistor gates can be compared to the same construction usingNAND logic or NOR logic. The complement of AOI Logic is OR-AND-Invert (OAI) logic where the OR gatesprecede a NAND gate.

2.1 Logic operations

AOI gates perform one or more AND operations followed by an OR operation and then an inversion. For example,a 2-2 AOI gate can be represented by the boolean equation and truth table:F = (A ∧B) ∨ (C ∧D)

A 2-1 AOI gate can be represented by following the boolean equation and truth table:F = A ∨ (B ∧ C)

3

4 CHAPTER 2. AND-OR-INVERT

2-1 AOI Symbol

Larger AOI gates, such as 4-3 AOI or 3-3-3 AOI can also be used.

2.2 Electronic implementation

AOI and OAI gates can be readily implemented in CMOS circuitry. AOI gates are particularly advantaged in that thetotal number of transistors (or gates) is less than if the AND, NOT, and OR functions were implemented separately.This results in increased speed, reduced power, smaller area, and potentially lower fabrication cost. For example, a2-1 AOI gate can be constructed with 6 transistors in CMOS compared to 10 transistors using a 2-input NAND gate(4 transistors), an inverter (2 transistors), and a 2-input NOR gate (4 transistors).In NMOS logic, only the lower half of the CMOS circuit is used, in combination with a load device, or pull-uptransistor (typically a depletion load or a dynamic load).AOI gates are similarly efficient in transistor–transistor logic (TTL). The TTL 7400 line included a number of AOIgate parts, such as the 7451 dual 2-wide 2-input AND-OR-invert gate and the 7464 4-2-3-2-input AND-OR-invertgate.

2.3 References• Tinder, Richard F. (2000). Engineering digital design: Revised Second Edition. pp. 317–319. ISBN 0-12-691295-5. Retrieved 2008-07-04.

• John, Michael (1997). Application-Specific Integrated Circuits. Retrieved 2008-07-04.

2.3. REFERENCES 5

Vdd

A

B

A

B

Vss

Out

C

C

CMOS implementation of a 2-1 AOI gate

Chapter 3

Booleo

Booleo is a strategy card game using boolean logic gates. It was developed by Jonathan Brandt and Chris Kampfwith Sean P. Dennis in 2008, and it was first published by Tessera Games LLC in 2009.[1]

3.1 The game

The deck consists of 64 cards:

• 48 “Gate” cards using three Boolean operators AND, OR, and XOR

8 OR cards resolving to 18 OR cards resolving to 08 AND cards resolving to 18 AND cards resolving to 08 XOR cards resolving to 18 XOR cards resolving to 0

• 8 NOT cards

• 6 Initial Binary cards, each displaying a “0” and a “1” aligned to the two short ends of the card

• 2 Truth Tables (used for reference, not in play)

3.2 Play

Starting with up a line of Initial Binary cards laid perpendicular to two facing players, the object of the game is to bethe first to complete a logical pyramid whose final output equals that of the righmost Initial Binary card facing thatplayer.The game is played in “draw one play one” format. The pyramid consists of decreasing rows of gate cards, where theoutputs of any contiguous pair of cards comprise the input values to a single card in the following row. The pyramid,therefore, has Initial Binary values as its base and tapers to a single card closest to the player. By tracing the “flow”of values through any series of gate, every card placed in the pyramid must make “logical sense”, i.e. the inputs andoutput value of every gate card must conform to the rule of that gate card.The NOT cards are played against any of the Initial Binary cards in play, causing that card to be rotated 180 degrees,literally “flipping” the value of that card from 0 to 1 or vice versa.By changing the value of any Initial Binary, any and all gate cards which “flow” from it must be re-evaluated toensure its placement makes “logical sense”. If it does not, that gate card is removed from the player’s pyramid.

6

3.3. VARIATIONS 7

Since both player’s pyramids share the Initial Binary cards as a base, “flipping” an Initial Binary has an effect onboth player’s pyramids. A principal strategy during game play is to invalidate gate cards in the opponent’s logic pyramidwhile rendering as little damage to one’s own pyramid in the process.

Some logic gates are more robust than others to a change to their inputs. Therefore, not all logic gate cards have thesame strategic value.

3.3 Variations

The number of cards in bOOleO will comfortably support a match between two players whose logic pyramids are 6cards wide at their base. By combining decks, it is possible to construct larger pyramids or to have matches amongmore than 2 players. For example:

• Four players may play individually or as facing teams by arranging a cross of Initial Binary Cards,where four logic pyramids extend like compass points in four directions

• Four or more players may build partially overlapping pyramids from a long base of Initial BinaryCards

Tessera Games also published bOOleO-N Edition. This is identical to bOOleO with the exception that it uses theinverse set of logic gates: NAND, NOR, and XNOR. bOOleO-N Edition may be played on its own, or it may becombined with bOOleO.

3.4 References[1] http://boardgamegeek.com/boardgame/40943/booleo

Chapter 4

C-element

TheMullerC-element (C-gate or sometimes, Hysteresis flip-flop) is a commonly used asynchronous logic componentoriginally devised by David E. Muller.[1][2][3][4] The output of the C-element applies logical operations on the inputsand has state or logical hysteresis. When all the inputs go high, the output switches to high. It stays in this state until allthe inputs go low, at which time the output switches to low.[5][6][7] This behavior can be extended to the asymmetricC-element where some inputs only affect the operation in one of the transitions (positive or negative).

C4.1 Truth table and delay assumptions

For two input signals the C-element is defined by the equation cn = ab + (a + b)cn−1 , which corresponds to thefollowing truth table.This table can be turned into a circuit using the Karnaugh map. However, the obtained implementation is naïve, sincenothing is said about delay assumptions. To understand under what conditions the obtained circuit is workable, it isnecessary to do additional analysis, which reveals that

• delay1 is a propagation delay from node 1 via environment to node 3

• delay2 is a propagation delay from node 1 via internal feedback to node 3

• delay1 must be greater than delay2

Thus, the naïve implementation is correct only for slow environment.

8

4.2. IMPLEMENTATIONS OF THE C-ELEMENT 9

Delays in the naïve implementation and environment

4.2 Implementations of the C-element

C-element proposed in SU1081801

Depending on the ratio between the switching speed and power consumption, the C-element can be realized as acoarse- or fine-grain circuit.

10 CHAPTER 4. C-ELEMENT

4.2.1 Gate-level implementations

A C-element can be implemented at the gate-level in CMOS using only gates NAND, NOR and inverters. A numberof such implementations have been proposed in the former Soviet Union.[8][9][10][11][12] Note that so-called Maevsky’simplementation of the C-element[13][14] is loosely based on[15] and is an improved version of.[16] The C-elementsynthesized using Taxogram language is presented in .[17] Yet another version of the C-element built on two RSlatches has been derived in [18] using Petrify tool.

4.2.2 Static and semi-static embodiments

Vdd

Vss

A

B

C

B

A

A static 2-input Muller C-element. Note that transistors, branched in parallel, control the feedback signal.

The most known realization of a static C-element is a transistor circuit of majority gate with feedback. The majoritygate in turn, can be composed of AND-OR-Invert (AOI) gate and inverter.[19][20][21][22][23] One of themost commonlyused is the semi-static C-element, which stores its previous state with two cross-coupled inverters, similar to an SRAMcell. One of the inverters is weaker than the rest of the circuit, so it can be overpowered by the pull-up and pull-downnetworks. If both inputs are 0, then the pull-up network changes the latch's state, and the C-element outputs a 0. If

4.3. REFERENCES 11

both inputs are 1, then the pull-down network changes the latch’s state, making the C-element output a 1. Otherwise,the input of the latch is not connected to either V or ground, and so the weak inverter (drawn smaller in the diagram)dominates and the latch outputs its previous state.[24][25]

4.3 References[1] D. E. Muller, W. S. Bartky, “A theory of asynchronous circuits I,” Report no. 75, Digital Computer Laboratory, University

of Illinois at Urbana-Champaign, 1956.

[2] D. E.Muller, W. S. Bartky, “A theory of asynchronous circuits II,” Report no. 78, Digital Computer Laboratory, Universityof Illinois at Urbana-Champaign, 1957.

[3] W. S. Bartky, “A theory of asynchronous circuits III,” Report no. 96, Digital Computer Laboratory, University of Illinoisat Urbana-Champaign, 1960.

[4] W. D. Frazer, D. E.Muller, “Amethod for factoring the action of asynchronous circuits,” Report no. 104, Digital ComputerLaboratory, University of Illinois at Urbana-Champaign, 1960.

[5] W. Fleischhammer, “Improvements in or relating to asynchronous bistable trigger circuits,” UKpatent specificationGB1199698,Jul. 22, 1970

[6] M. Kuwako, T. Nanya, “Timing-reliability evaluation of asynchronous circuits based on different delay models,” IEEEInternational Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC) 1994, pp.22-31.

[7] J. Cortadella, M. Kishinevsky, Tutorial: Synthesis of control circuits from STG specifications. Summer school, Lyngby,1997

[8] B. S. Tsirlin, “H flip-flop,” USSR author’s certificate SU1096759, Jun. 7, 1984

12 CHAPTER 4. C-ELEMENT

[9] B. S. Tsirlin, “Multiple input H flip-flop,” USSR author’s certificate SU1162019, Jun. 15, 1985

[10] G. S. Brajlovskij, L. Ya. Rozenblyum, B. S. Tsirlin, “H flip-flop,” USSR author’s certificate SU1277385, Jan. 15, 1986

[11] B. S. Tsirlin, “H flip-flop,” USSR author’s certificate SU1324108, Jul. 15, 1987

[12] G. S. Brajlovskij, L. Ya. Rozenblyum, B. S. Tsirlin, “H flip-flop,” USSR author’s certificate SU1432733, Oct, 23, 1988

[13] J. A. Brzozowski, K. Raahemifar, “Testing C-elements is not elementary,” Working Conference on Asynchronous DesignMethodologies (ASYNC) 1995, pp. 150-159.

[14] S. Golubcovs, A. Alekseyev, A. Mokhov, A. Yakovlev, “Asynchronous circuit development with Workcraft,” TechnicalReport NCL-EECE-MSD-TR-2011-174, University of Newcastle upon Tyne, 2011

[15] V. I. Varshavskij, O. V. Maevskij, Yu. V. Mamrukov, B. S. Tsirlin, “H flip-flop,” USSR author’s certificate SU1081801,Mar. 23, 1984

[16] G. Brajlovskij, “H flip-flop,” USSR author’s certificate SU945960, Jul. 23, 1982

[17] N. A. Starodoubtsev, S. A. Bystrov, “Monotonic behavior refinement for synthesis of two-input-gate asynchronous circuits,”IEEE International Midwest Symposium on Circuits and Systems (MWSCAS) 2004, vol. I, pp. I-521-524.

[18] J. P. Murphy, “Design of latch-based C-element,” Electronics Letters, vol. 48, no. 19, 2012, pp. 1190-1191

[19] D. Hampel, K. Prost, and N. Scheingberg, “Threshold logic using complementary MOS device,” Patent US3900742, Aug.19, 1975.

[20] D. Doman, Engineering the CMOS Library: Enhancing Digital Design Kits for Competitive Silicon. Wiley, 2012, 327p.

[21] I. E. Sutherland, “Micropipelines,” Communications of the ACM, vol. 32, no. 6, pp. 720-738, 1989.

[22] C. H. van Berkel, “Beware the isochronic fork,” Report UR 003/91, Philips Research Laboratories, 1991.

[23] H. K. O. Berge, A. Hasanbegovic, S. Aunet, “Muller C-elements based on minority-3 functions for ultra low voltagesupplies,” 2011 IEEE 14th International Symposium onDesign and Diagnostics of Electronic Circuits & Systems (DDECS)2011, pp. 195-200.

[24] A. Morgenshtein, M. Moreinis, R. Ginosar, “Asynchronous gate-diffusion-input (GDI) circuits,” IEEE Transactions onVery Large Scale Integration (VLSI) Systems, vol.12, no.8, pp. 847-856, 2004

[25] S. M. Fairbanks, “Two-stage Muller C-element,” United States Patent US6281707, Aug. 28, 2001

4.4 External links• Muller C-Gate Simulation

• Workcraft tool: Synthesis and verification of C-element

Chapter 5

C-ROT gate

The C-ROT gate (controlled Rabi rotation) is equivalent to a C-NOT gate except for a π/2 rotation of the nuclearspin around the z axis.[1]

5.1 References[1] P. Chen, C. Piermarocchi, and L. J. Sham, Phys. Rev. Lett. 87, 067401 (2001), http://prola.aps.org/abstract/PRL/v87/

i6/e067401

13

Chapter 6

Computer module

This article is about computer hardware modules. For computer software and hardware modules, see Module (com-puting).A computer module is a selection of independent electronic circuits packaged onto a circuit board to provide a

DEC's original products were individual modules, like these System Building Blocks 1103 hex-inverter cards (both sides).

basic function within a computer. An example might be an inverter or flip-flop, which would require two or moretransistors and a small number of additional supporting devices. Modules would be inserted into a chassis and thenwired together to produce a larger logic unit, like an adder.

6.1 History

Modules were the basic building block of most early computer designs, until they started being replaced by integratedcircuits in the 1960s, which were essentially an entire module packaged onto a single computer chip. Modules withdiscrete components continued to be used in specialist roles into the 1970s, notably high-speed designs like the CDC8600, but advances in chip design led to the disappearance of the discrete-component module in the 1970s.In the 21st Century, computer modules more commonly refer to computer-on-module used in embedded computing.

14

6.2. BENEFITS OF COMPUTER MODULES 15

Contemporary computer modules look like this Colibri T30 manufactured by Toradex, Switzerland

An extension of the concept of System on Chip (SoC), COM lies between a full-up computer and a microcontrollerin nature. Today’s Computer On Modules (COM) are complete embedded computers built on a single circuit board.The design is centered on a microprocessor with RAM, input/output controllers and all other features needed to bea functional computer on the one board. However, unlike a single-board computer, the COM will usually lack thestandard connectors for any input/output peripherals to be attached directly to the board.The module will usually need to be mounted on a carrier board (or “baseboard”) which breaks the bus out to standardperipheral connectors. Some COMs also include peripheral connectors and/or can be used without a carrier.A COM solution offers a dense package computer system for use in small or specialized applications requiring lowpower consumption or small physical size as is needed in embedded systems. As a COM is very compact and highlyintegrated, even complex CPUs, including multi-core technology, can be realized on a COM.Using a carrier board is a benefit inmany cases, as it can implement special I/O interfaces, memory devices, connectorsor form factors. Separating the design of the carrier board and COMmakes design concepts more modular, if needed.A carrier tailored to a special application may involve high design overhead by itself. If the actual processor and mainI/O controllers are located on a COM, it is much easier, for example, to upgrade a CPU component to the nextgeneration, without having to redesign a very specialized carrier as well. This can save costs and shorten developmenttimes. On the other hand, this only works if the board-to-board connection between the COM and its carrier remainscompatible between upgrades.

6.2 Benefits of Computer Modules

There are many benefits to using COM products instead of ground-up development.[1] These benefits include increas-ing speed to market, reduction to risk, cost savings, choice of a variety of CPUs, reduced requirements and time forcustomer design, and an ability to conduct both hardware and software development at once.

6.3 References[1] Computer on Modules - Technical Reference Manuals

Chapter 7

Controlled NOT gate

x x

y yx

input

11

-1-1

1-1-11

x y x yx11

-1-1

1-11

-1

xx

yyXOR

0011

0110

x y x0011

0101

1 ~ 0-1 ~ 1

output input output

x

y x

(CNOT)F

The classical analog of the CNOT gate is a reversible XOR gate.

In computing science, the controlled NOT gate (also C-NOT or CNOT) is a quantum gate that is an essentialcomponent in the construction of a quantum computer. It can be used to entangle and disentangle EPR states. Anyquantum circuit can be simulated to an arbitrary degree of accuracy using a combination of CNOT gates and singlequbit rotations. The CNOT gate is the “quantization” of a classical gate.

7.1 Operation

The CNOT gate operates on a quantum register consisting of 2 qubits. The CNOT gate flips the second qubit (thetarget qubit) if and only if the first qubit (the control qubit) is |1⟩ .

16

7.1. OPERATION 17

How the CNOT gate can be used (with Hadamard gates) in a computation

If one allows only {|0⟩, |1⟩} as input values for both qubits, the TARGET output of the CNOT gate corresponds tothe result of a classical XOR gate. Fixing CONTROL as |1⟩ , the TARGET output of the CNOT gate yields theresult of a classical NOT gate.More generally, the inputs are allowed to be a linear superposition of {|0⟩, |1⟩} . The CNOT gate transforms thequantum state:a|00⟩+ b|01⟩+ c|10⟩+ d|11⟩into:a|00⟩+ b|01⟩+ c|11⟩+ d|10⟩The CNOT gate can be represented by the matrix (permutation matrix form):

CNOT =

1 0 0 00 1 0 00 0 0 10 0 1 0

.The first experimental realization of a CNOT gate was accomplished in 1995. Here, a single Beryllium ion in a trapwas used. The two qubits were encoded into an optical state and into the vibrational state of the ion within the trap.

18 CHAPTER 7. CONTROLLED NOT GATE

Representation of the CNOT gate

At the time of the experiment, the reliability of the CNOT-operation was measured to be on the order of 90%.In addition to a regular controlled NOT gate, one could construct a function-controlled NOT gate, which accepts anarbitrary number n+1 of qubits as input, where n+1 is greater than or equal to 2 (a quantum register). This gateflips the last qubit of the register if and only if a built-in function, with the first n qubits as input, returns a 1. Thefunction-controlled NOT gate is an essential element of the Deutsch-Jozsa algorithm.

7.2 Behaviour of CNOT in the Hadamard basis

When viewed only in the computational basis {|0⟩, |1⟩} , the behaviour of the CNOT appears to be like the equivalentclassical gate. However, the simplicity of labelling one qubit the control and the other the target does not reflect thecomplexity of what happens for most input values of both qubits.Insight can be won by expressing the CNOT gate with respect to a Hadamard basis {|+⟩, |−⟩} . The Hadamardbasis[lower-alpha 1] of a one-qubit register is given by

|+⟩ = 1√2(|0⟩+ |1⟩), |−⟩ = 1√

2(|0⟩ − |1⟩),

7.2. BEHAVIOUR OF CNOT IN THE HADAMARD BASIS 19

Answer on output depending on input and CNOT function

The first qubit flips only if the second qubit is 1.

20 CHAPTER 7. CONTROLLED NOT GATE

=CNOT gate in Hadamard Basis

and the corresponding basis of a 2-qubit register is

|++⟩ = |+⟩|+⟩ = 1

2(|0⟩+ |1⟩)(|0⟩+ |1⟩) = 1

2(|00⟩+ |01⟩+ |10⟩+ |11⟩)

etc. Viewing CNOT in this basis, the state of the second qubit remains unchanged, and the state of the first qubit isflipped, according to the state of the second bit. (For details see below.) “Thus, in this basis the sense of which bit isthe control bit and which the target bit has reversed. But we have not changed the transformation at all, only the waywe are thinking about it.”[1]

The “computational” basis {|0⟩, |1⟩} is the eigenbasis for the spin in the Z-direction, whereas the Hadamard basis{|+⟩, |−⟩} is the eigenbasis for spin in the X-direction. Switching X and Z and qubits 1 and 2, then, recovers theoriginal transformation.”[2] This expresses a fundamental symmetry of the CNOT gate.The observation that both qubits are (equally) affected in a CNOT interaction is of importance when consideringinformation flow in entangled quantum systems.[3]

7.3 Details of the computation

We now proceed to give the details of the computation. Working through each of the Hadamard basis states, the firstqubit flips between |+⟩ and |−⟩ when the second qubit is |−⟩ :A quantum circuit that performs a Hadamard transform followed by CNOT then another Hadamard transform canbe described in terms of matrix operators:(H1 ⊗ H1)−1 . CNOT . (H1 ⊗ H1)The single-qubit Hadamard transform, H1, is the negative of its own inverse. The tensor product of two Hadamardtransforms operating (independently) on two qubits is labelled H2. We can therefore write the matrices as:H2 . CNOT . H2

When multiplied out, this yields a matrix that swaps the |01⟩ and |11⟩ terms over, while leaving the |00⟩ and |10⟩terms alone. This is equivalent to a CNOT gate where qubit 2 is the control qubit and qubit 1 is the target qubit:

1

4

1 1 1 11 −1 1 −11 1 −1 −11 −1 −1 1

.

1 0 0 00 1 0 00 0 0 10 0 1 0

.

1 1 1 11 −1 1 −11 1 −1 −11 −1 −1 1

=

1 0 0 00 0 0 10 0 1 00 1 0 0

7.4 Constructing the Bell State |Φ+⟩

A common application of the CNOT gate is to maximally entangle two qubits into the |Φ+⟩ Bell state; this formspart of the setup of the superdense coding, quantum teleportation, and entangled quantum cryptography algorithms.To construct |Φ+⟩ , the inputs A (control) and B (target) to the CNOT gate are:1√2(|0⟩+ |1⟩)A and |0⟩B

7.5. SEE ALSO 21

After applying CNOT, the resulting Bell State 1√2(|00⟩ + |11⟩) has the property that the individual qubits can be

measured using any basis and will always present a 50/50 chance of resolving to each state. In effect, the individualqubits are in an undefined state. The correlation between the two qubits is the complete description of the state of thetwo qubits; if we choose the same basis to measure both qubits and compares notes, the measurements will perfectlycorrelate.When viewed in the computational basis, it appears that qubit A is affecting qubit B. Changing our viewpoint to theHadamard basis demonstrates that, in a symmetrical way, qubit B is affecting qubit A.The input state can alternately be viewed as:|+⟩A and 1√

2(|+⟩+ |−⟩)B

In the Hadamard view, the control and target qubits have conceptually swapped and qubit A is inverted when qubit Bis |−⟩B . The output state after applying the CNOT gate is 1√

2(|++⟩+ | − −⟩) which can be shown[lower-alpha 2] to

be exactly the same state as 1√2(|00⟩+ |11⟩) .

7.5 See also• C-ROT gate

7.6 References[1] Eleanor G. Rieffel; Wolfgang H. Polak (4 March 2011). Quantum Computing: A Gentle Introduction. MIT Press. p. 80.

ISBN 978-0-262-01506-6.

[2] Gottesman, Daniel (1998). “The Heisenberg Representation of Quantum Computers”. Group: Proceedings of the XXIIInternational Colloquium on Group Theoretical Methods in Physics, eds. S. P. Corney, R. Delbourgo, and P. D. Jarvis, pp.(Cambridge, MA, International Press, ) 22 (1999): 32–43. arXiv:quant-ph/9807006. Bibcode:1998quant.ph..7006G.

[3] Deutsch, David; Hayden, Patrick (1999). “Information Flow in Entangled Quantum Systems”. Proceedings of the Royal So-ciety A:Mathematical, Physical and Engineering Sciences 456 (1999): 1759–1774. arXiv:quant-ph/9906007. Bibcode:2000RSPSA.456.1759H.doi:10.1098/rspa.2000.0585.

• Nielsen, Michael A. & Chuang, Isaac L. (2000). Quantum Computation and Quantum Information. CambridgeUniversity Press. ISBN 0-521-63235-8.

• Monroe, C. & Meekhof, D. & King, B. & Itano, W. &Wineland, D. (1995). “Demonstration of a Fundamen-tal Quantum Logic Gate”. Physical Review Letters 75 (25): 4714–4717. Bibcode:1995PhRvL..75.4714M.doi:10.1103/PhysRevLett.75.4714. PMID 10059979.

7.7 External links• Michael Westmoreland: “Isolation and information flow in quantum dynamics” - discussion around the C ₒgate

7.8 Notes[1] Note that |+⟩ can be constructed by applying a Hadamard gate to a qubit set to |0⟩ , and similarly for |−⟩

[2] 1√2(|++⟩+|−−⟩) = 1√

2(|+⟩A|+⟩B+|−⟩A|−⟩B) = 1

2√

2((|0⟩A+|1⟩A)(|0⟩B+|1⟩B)+(|0⟩A−|1⟩A)(|0⟩B−|1⟩B))

= 1

2√

2((|00⟩+ |01⟩+ |10⟩+ |11⟩) + (|00⟩ − |01⟩ − |10⟩+ |11⟩)) = 1√

2(|00⟩+ |11⟩)

Chapter 8

David E. Muller

DavidEugeneMuller (November 2, 1924 –April 27, 2008) was anAmericanmathematician and computer scientist.He was a professor of mathematics and computer science at the University of Illinois (1953–92), when he became anemeritus professor, and was an adjunct professor of mathematics at the New Mexico State University (1995-2008).Muller received his BS in 1947 and his PhD in 1951 in physics from Caltech; an honorary PhD was conferred bythe University of Paris in 1989.[1] He was the inventor of the Muller C-element (or Muller C-gate), a device usedto implement asynchronous circuitry in electronic computers. He also co-invented the Reed–Muller codes. Hediscovered the codes, and Irving S. Reed proposed the majority logic decoding for the first time.

8.1 Family

David E. Muller was the son of Hermann Joseph Muller and Jessie Jacobs Muller Offermann (formerly Jesse MarieJacobs). He was born in Austin, Texas, when his parents taught at The University of Texas. His mother, who was oneof the earliest women who received a Ph.D. in mathematics in the United States,[2] lost her position as an instructorin pure mathematics at Texas because she became pregnant, and according to Hermann Joseph Muller’s biographer,“her colleagues felt that a mother could not give full attention to classroom duties and remain a good mother.”[3] Asa child he was with his parents in Berlin and Leningrad in 1933–34. His family was dissolved in the Soviet Union.He returned to Austin with his mother in July 1934. His mother obtained a divorce in Texas in the summer of 1935.Sometime between October 1935 and January 1936, Jessie Muller married Carlos Alberto Offermann, who had beenworking in Muller’s laboratory and was on a visit to Austin from the Soviet Union at that time.[2] Hermann JosephMuller left the Soviet Union in 1937 after the start of Stalin’s political persecutions. After a brief stay in Madrid andParis, in September 1937, Hermann moved to Edinburgh, where he married Dorothea Kantorowicz in May 1939.They had a daughter, Helen Juliette. Hermann Joseph Muller received the Nobel Prize in Physiology or Medicine in1946.David E. Muller died in 2008 in Las Cruces, New Mexico. He is survived by his children, Chandra L. Muller andKenneth J. Muller. His half-sister, Helen J. Muller, is a professor emerita at the University of New Mexico. He waspredeceased by his wife Alice Mimi Muller, who died in Urbana, IL, in 1989, and divorced (posthumously) in 2009from his second wife, Denise Impens Muller, in Las Cruces, NM.

8.2 See also

• Muller C-element

• Reed–Muller code

• Muller’s method (an established root finding method in numerical analysis)

22

8.3. REFERENCES 23

8.3 References[1] Marquis Who’s Who (2008). Who’s Who in the World 2007. Chicago, Ill: Marquis Who’s Who. p. 3002. ISBN 0-8379-

1137-0.

[2] Judy Green and Jeanne LaDuke, Pioneering Women in American Mathematics: The Pre-1940 PhD’s, American Mathemat-ical Society, 2008, 260–262.

[3] Elof Carlson, Genes, Radiation, and Society, Cornell University Press, 1982, 133.

Chapter 9

Diode-or circuit

A diode-OR circuit is used in electronics to isolate two or more voltage sources. There are two typical implemen-tations:When a DC supply voltage needs to be generated from one of a number of different sources, for example whenterminating a parallel SCSI bus, a very simple circuit like this can be used:

In digital electronics a diode-OR circuit is used to derive a simple Boolean logic function. This kind of circuit wasonce very common in Diode-transistor logic but has been largely replaced by CMOS in modern electronics:

24

Chapter 10

Fan-in

An AND gate with three inputs has a fan-in of 3.

Fan-in is the number of inputs a gate can handle. For instance the fan-in for the AND gate shown in the figureis 3. Physical logic gates with a large fan-in tend to be slower than those with a small fan-in. This is because thecomplexity of the input circuitry increases the input capacitance of the device. Using logic gates with higher fan-inwill help reducing the depth of a logic circuit.

10.1 See also• Fan-out, a related concept, which is the number of logic inputs that a given logic output drives.

25

Chapter 11

Fan-out

This article is about the concept in digital electronics. For software concept, see fan-out (software).

In digital electronics, the fan-out of a logic gate output is the number of gate inputs it can feed or connect to.In most designs, logic gates are connected to form more complex circuits. While no more than one logic gate outputis connected to any single input, it is common for one output to be connected to several inputs. The technologyused to implement logic gates usually allows a certain number of gate inputs to be wired directly together withoutadditional interfacing circuitry. The maximum fan-out of an output measures its load-driving capability: it is thegreatest number of inputs of gates of the same type to which the output can be safely connected.

11.1 Logical practice

Maximum limits on fan-out are usually stated for a given logic family or device in the manufacturer’s datasheets.These limits assume that the driven devices are members of the same family.More complex analysis than fan-in and fan-out is required when two different logic families are interconnected. Fan-out is ultimately determined by the maximum source and sink currents of an output and the maximum source andsink currents of the connected inputs; the driving device must be able to supply or sink at its output the sum ofthe currents needed or provided (depending on whether the output is a logic high or low voltage level) by all of theconnected inputs, while maintaining the output voltage specifications. For each logic family, typically a “standard”input is defined by the manufacturer with maximum input currents at each logic level, and the fan-out for an outputis computed as the number of these standard inputs that can be driven in the worst case. (Therefore, it is possiblethat an output can actually drive more inputs than specified by fan-out, even of devices within the same family, ifthe particular devices being driven sink and/or source less current, as reported on their data sheets, than a “standard”device of that family.) Ultimately, whether a device has the fan-out capability to drive (with guaranteed reliability) aset of inputs is determined by adding up all the input-low (max.) source currents specified on the datasheets of thedriven devices, adding up all the input-high (max.) sink currents of those same devices, and comparing those sumsto the driving device’s guaranteed maximum output-low sink current and output-high source current specifications,respectively. If both totals are within the driving device’s limits, then it has the DC fan-out capacity to drive thoseinputs on those devices as a group, and otherwise it doesn't, regardless of the manufacturer’s given fan-out number.However, for any reputable manufacturer, if this current analysis reveals that the device cannot drive the inputs, thefan-out number will agree.When high-speed signal switching is required, the AC impedance of the output, the inputs, and the conductorsbetween may significantly reduce the effective drive capacity of output, and this DC analysis may not be enough. SeeAC Fan-out below.

11.2 Theory

26

11.2. THEORY 27

11.2.1 DC fan-out

A perfect logic gate would have infinite input impedance and zero output impedance, allowing a gate output to driveany number of gate inputs. However, since real-world fabrication technologies exhibit less than perfect characteristics,a limit will be reached where a gate output cannot drive any more current into subsequent gate inputs - attempting todo so causes the voltage to fall below the level defined for the logic level on that wire, causing errors.The fan-out is simply the number of inputs that can be connected to an output before the current required by theinputs exceeds the current that can be delivered by the output while still maintaining correct logic levels. The currentfigures may be different for the logic zero and logic one states and in that case we must take the pair that give thelower fan-out. This can be expressed mathematically as

Fan-out DC = min(⌊

Ihigh outIhigh in

⌋,

⌊Ilow outIlow in

⌋)( ⌊ ⌋ is the floor function).Going on these figures alone TTL logic gates are limited to perhaps 2 to 10, depending on the type of gate, whileCMOS gates have DC fan-outs that are generally far higher than is likely to occur in practical circuits (e.g. usingNXP Semiconductor specifications for their HEF4000 series CMOS chips at 25 °C and 15 V gives a fan-out of 34thousand).

11.2.2 AC fan-out

However, inputs of real gates have capacitance as well as resistance to the power supply rails. This capacitance willslow the output transition of the previous gate and hence increase its propagation delay. As a result, rather than afixed fan-out the designer is faced with a trade off between fan-out and propagation delay (which affects the maximumspeed of the overall system). This effect is less marked for TTL systems, which is one reason why they maintained aspeed advantage over CMOS for many years.Often a single signal (as an extreme example, the clock signal) needs to drive far more than 10 things on a chip.Rather than simply wiring the output of a gate to 1000 different inputs, people who design such things have foundthat it runs much faster to have a tree (as an extreme example, a clock tree) – for example, have the output of thatgate drive 10 buffers (or equivalently a buffer scaled 10 times as big as the minimum-size buffer), those buffers drive100 other buffers (or equivalently a buffer scaled 100 times as big as the minimum-size buffer), and those final buffersto drive the 1000 desired inputs. During physical design (electronics), some VLSI design tools do buffer insertion aspart of signal integrity design closure.Likewise, rather than simply wiring all 64 output bits to a single 64-input NOR gate to generate the Z flag on a 64-bitALU, people who design such things have found that it runs much faster to have a tree – for example, have the Z flaggenerated by a 8-input NOR gate, and each of their inputs generated by a 8-input OR gate.Reminiscent of radix economy, one estimate for the total delay of such a tree -- the total number of stages by thedelay of each stage – gives an optimum (minimum delay) when each stage of the tree is scaled by e, approximately2.7. People who design digital integrated circuits typically insert trees whenever necessary such that the fan-in andfan-out of each and every gate on the chip is between 2 and 10.[1]

Dynamic or AC fan-out, not DC fan-out, is therefore the primary limiting factor in many practical cases, due tothe speed limitation. For example, suppose a microcontroller has 3 devices on its address and data lines, and themicrocontroller can drive 35 pF of bus capacitance at its maximum clock speed. If each device has 8 pF of inputcapacitance, then only 11 pF of trace capacitance is allowable. (Routing traces on printed circuit boards usuallyhave 1-2 pF per inch so the traces can be 5.5 inches long max.) If this trace length condition can't be met, thenthe microcontroller must be run at a slower bus speed for reliable operation, or a buffer chip with higher currentdrive must be added. Higher current drive increases speed since I= C*dV/dt; more simply, current is rate of flow ofcharge, so increased current charges the capacitance faster, and the voltage across a capacitor is equal to the chargeon it divided by the capacitance. So with more current, voltage changes faster, which allows faster signalling over thebus.Unfortunately, due to the higher speeds of modern devices, IBIS simulation may be required for exact determinationof the dynamic fan-out since dynamic fan-out is not clearly defined in most datasheets. (See the external link formore information.)

28 CHAPTER 11. FAN-OUT

11.3 See also• FO4 — fan-out of 4

• Fan-in — the number of inputs of a logic gate

• Reconvergent fan-out

11.4 References[1] Miles Murdocca, Apostolos Gerasoulis, and Saul Levy. “Novel Optical Computer Architecture Utilizing Reconfigurable

Interconnects”. 1991. p. 60-61.

11.5 External links• HIGH-SPEED DIGITAL DESIGN — online newsletter — Vol. 8 Issue 07

Chapter 12

Fredkin gate

Circuit representation of Fredkin gate

The Fredkin gate (also CSWAP gate) is a computational circuit suitable for reversible computing, invented by EdFredkin. It is universal, which means that any logical or arithmetic operation can be constructed entirely of Fredkingates. The Fredkin gate is the three-bit gate that swaps the last two bits if the first bit is 1.

29

30 CHAPTER 12. FREDKIN GATE

12.1 Definition

The basic Fredkin gate[1] is a controlled swap gate that maps three inputs (C, I1, I2) onto three outputs (C, O1, O2).The C input is mapped directly to the C output. If C = 0, no swap is performed; I1 maps to O1, and I2 maps to O2.Otherwise, the two outputs are swapped so that I1 maps to O2, and I2 maps to O1. It is easy to see that this circuitis reversible, i.e., “undoes” itself when run backwards. A generalized n×n Fredkin gate passes its first n−2 inputsunchanged to the corresponding outputs, and swaps its last two outputs if and only if the first n−2 inputs are all 1.The Fredkin gate is the reversible three-bit gate that swaps the last two bits if the first bit is 1.It has the useful property that the numbers of 0s and 1s are conserved throughout, which in the billiard ball modelmeans the same number of balls are output as input. This corresponds nicely to the conservation of mass in physics,and helps to show that the model is not wasteful.

12.2 Logic function with XOR and AND gatesO1 = I1 XOR S

O2 = I2 XOR S

with S = (I1 XOR I2) AND C

It can also be implemented by the following logic:

O1 = (NOT C AND I1) OR (C AND I2) = CI1+CI2O2 = (C AND I1) OR (NOT C AND I2) = CI1+CI2Cₒᵤ = Cᵢ

12.3 Completeness

One way to see that the Fredkin gate is universal is to observe that it can be used to implement AND and NOT:

If I2 = 0 , then O2 = C AND I1 .If I1 = 0 and I2 = 1 , then O2 = NOTC .

12.4 Example

Here is a diagram of a three-bit adder implemented using Fredkin gates. The three inputs are A, B and C, supple-mented by the constant T and F. In the diagram, the leftmost input (before the colon) swaps the two rightmost inputsif it is true.A:CB B:CFC:CAC:TFB:BA

XORcarry

12.5 See also• Quantum computing

• Quantum gate

12.6. REFERENCES 31

• Quantum programming

• Toffoli gate, which is a controlled-controlled-NOT gate.

12.6 References[1] Brown, Julian, The Quest for the Quantum Computer, New York : Touchstone, 2000.

12.7 Further reading• Fredkin, Edward; Toffoli, Tommaso (1982). “Conservative Logic” (PDF). International Journal of TheoreticalPhysics 21 (3-4): 219–253. doi:10.1007/BF01857727.

Chapter 13

Gate equivalent

A gate equivalent (GE) stands a unit of measure which allows to specify manufacturing-technology-independentcomplexity of digital electronic circuits. For today’s CMOS technologies, the silicon area of a two-input drive-strength-one NAND gate usually constitutes the technology-dependent unit area commonly referred to as gate equivalent. Aspecification in gate equivalents for a certain circuit reflects a complexity measure, from which a corresponding siliconarea can be deduced for a dedicated manufacturing technology.In digital circuit design, a dedicated standard cell library is employed for each manufacturing technology (e.g.,CMOS). The standard cell library comprises many different logic gates, for example a NAND gate. For each logicaltype of logic gate, e.g., a two-input NAND, there usually exist different physical realizations in the standard celllibrary, for instance with different output drive strengths.Basically, a two-input drive-strength-one NAND gate in CMOS technology consists of four transistors. If higheroutput drive strength is required, an additional output driver stage of four transistors is added.

13.1 References• Digital Integrated Circuit Design: From VLSI Architectures to CMOS Fabrication, Hubert Kaeslin, CambridgeUniversity Press, 2008

13.2 See also• Logic family

• NMOS logic

• MOSFET

• Fanout

• FO4

• Boolean logic

32

Chapter 14

IMPLY gate

The IMPLY gate is a digital logic gate that implements a logical conditional

14.1 Implementations

IMPLY gate can be implemented by 2 memristor. [1]

14.2 See also• AND gate

• NOT gate

• NAND gate

• NOR gate

• XOR gate

• XNOR gate

• Boolean algebra (logic)

• Logic gates

14.3 References[1] http://www.zigwap.com/digital/gates/imply_gate

33

Chapter 15

NOT gate

A out

Traditional NOT Gate (Inverter) symbol

1

International Electrotechnical Commission NOT Gate (Inverter) symbol

In digital logic, an inverter or NOT gate is a logic gate which implements logical negation. The truth table is shownon the right.

34

15.1. ELECTRONIC IMPLEMENTATION 35

15.1 Electronic implementation

• NMOS inverter

• PMOS inverter

• Static CMOS inverter

• NPN transistor–transistor logic inverter

• Depletion-load NMOS logic NAND

• Saturated-load NMOS inverter

• NPN resistor–transistor logic inverter

An inverter circuit outputs a voltage representing the opposite logic-level to its input. Inverters can be constructedusing a single NMOS transistor or a single PMOS transistor coupled with a resistor. Since this 'resistive-drain' ap-proach uses only a single type of transistor, it can be fabricated at low cost. However, because current flows throughthe resistor in one of the two states, the resistive-drain configuration is disadvantaged for power consumption andprocessing speed. Alternatively, inverters can be constructed using two complementary transistors in a CMOS con-figuration. This configuration greatly reduces power consumption since one of the transistors is always off in bothlogic states. Processing speed can also be improved due to the relatively low resistance compared to the NMOS-onlyor PMOS-only type devices. Inverters can also be constructed with bipolar junction transistors (BJT) in either aresistor–transistor logic (RTL) or a transistor–transistor logic (TTL) configuration.Digital electronics circuits operate at fixed voltage levels corresponding to a logical 0 or 1 (see binary). An invertercircuit serves as the basic logic gate to swap between those two voltage levels. Implementation determines the actualvoltage, but common levels include (0, +5V) for TTL circuits.

15.1.1 Digital building block

The inverter is a basic building block in digital electronics. Multiplexers, decoders, state machines, and other sophis-ticated digital devices may use inverters.The hex inverter is an integrated circuit that contains six (hexa-) inverters. For example, the 7404 TTL chip whichhas 14 pins and the 4049 CMOS chip which has 16 pins, 2 of which are used for power/referencing, and 12 of whichare used by the inputs and outputs of the six inverters (the 4049 has 2 pins with no connection).

15.1.2 Alternatives

If no specific NOT gates are available, one can be made from NAND or NOR gates, because NAND and NOR gatesare considered the “universal gates”,[1] meaning that they can be used to make all the others.

15.1.3 Performance measurement

Digital inverter quality is often measured using the voltage transfer curve (VTC), which is a plot of output vs. inputvoltage. From such a graph, device parameters including noise tolerance, gain, and operating logic levels can beobtained.Ideally, the VTC appears as an inverted step function – this would indicate precise switching between on and off –but in real devices, a gradual transition region exists. The VTC indicates that for low input voltage, the circuit outputshigh voltage; for high input, the output tapers off towards the low level. The slope of this transition region is a measureof quality – steep (close to infinity) slopes yield precise switching.The tolerance to noise can be measured by comparing the minimum input to the maximum output for each region ofoperation (on / off).

36 CHAPTER 15. NOT GATE

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

VDD

Q1

A1

Q2

A2

Q3

A3

VSS

NC

Q6

A6

NC

Q5

A5

Q4

A4

This schematic diagram shows the arrangement of NOT gates within a standard 4049 CMOS hex inverting buffer.

15.2. SEE ALSO 37

Voltage transfer curve for a 20 μm inverter constructed at North Carolina State University

15.2 See also• Controlled NOT gate

• AND gate

• OR gate

• NAND gate

• NOR gate

• XOR gate

• XNOR gate

• Boolean algebra

• Logic gate

15.3 External links• The Not Gate on All About Circuits

• CMOS Hex Inverting Buffer/Converter from Texas Instruments

• Datasheet: CMOS Hex Buffer/Converter

15.4 References[1] Mano, M. Morris and Charles R. Kime. Logic and Computer Design Fundamentals, Third Edition. Prentice Hall, 2004. p.

73.

Chapter 16

Linear optical quantum computing

Linear Optical Quantum Computing or Linear Optics Quantum Computation (LOQC) is a paradigm ofuniversal quantum computation. LOQC uses photons as information carriers, mainly uses linear optical elementsincluding beam splitters, phase shifters, and mirrors to process quantum information, and uses photon detectors andquantum memories to detect and store quantum information.[1][2][3]

16.1 Overview of linear optical quantum computation

Although there are many other implementations for quantum information processing (QIP) and computation,optical quantum systems are prominent candidates for QIP, since they link quantum computation and quantum com-munication in the same framework. Among the optical systems for quantum information processing, the unit of lightin a given mode—or photon—is used to represent a qubit. Superpositions of quantum states can be easily represented,encrypted, transmitted and detected using photons. Besides, linear optical elements of optical systems may be thesimplest building blocks to realize quantum operations and quantum gates. Each linear optical element equivalentlyapplies a unitary transformation on a finite number of qubits. The system of finite linear optical elements constructsa network of linear optics, which can realize any quantum circuit diagram or quantum network based on the quantumcircuit model. Quantum computing with continuous variables is also possible under the linear optics scheme.[4] Theuniversality of 1- and 2-bit gates to implement arbitrary quantum computation has been proven.[5][6][7][8] Up toN×Nunitary matrix ( U(N) ) operations can be realized by only using mirrors, beam splitters and phase shifters[9] (foot-note: it is also a starting point of Boson sampling and computational complexity analysis for LOQC). It points outthat each U(N) operator withN inputs andN outputs can be constructed viaO(N2) linear optical elements. Basedon the reason of universality and complexity, LOQC usually only uses mirrors, beam splitters, phase shifters and theircombinations such as Mach-Zehnder interferometers with phase shifts to implement arbitrary quantum operators. Ifusing a non-deterministic scheme, this fact also implies that LOQC could be resource-inefficient in the sense of thenumber of optical elements and time steps needed to implement a certain quantum gate or circuit, which is a majordrawback of LOQC.Operations via linear optics elements (beam splitters, mirrors and phase shifters, in this case) preserve the photonstatistics of input light. For example, a coherent (classical) light input produces a coherent light output; a superpositionof quantum states input yields a quantum light state output.[3] Due to this reason, people usually use single photonsource case to analyze the effect of linear optics elements and operators. Multi-photon cases can be implied throughsome statistical transformations.An intrinsic problem in using photons as information carriers is that photons hardly interact with each other. Thispotentially causes the scalability problem of LOQC, since nonlinear operations are hard to implement which canincrease the complexity of operators and hence can reduce the resources required to realize a given computationalfunction. There are basically two ways to solve this problem. One is to bring in nonlinear devices into the quantumnetwork. For instance, the Kerr effect can be applied into LOQC to make a single-photon controlled-NOT andother operations.[10][11] It was believed that adding nonlinearity to the linear optical network was sufficient to realizeefficient quantum computation.[12] However, to implement nonlinear optical effects is a difficult task. In 2000, Knill,Laflamme and Milburn proved that it is possible to create universal quantum computers solely with linear opticstools.[2] Their work has become known as the KLM scheme or KLM protocol, which uses linear optical elements,single photon sources and photon detectors as resources to construct a quantum computation scheme involving only

38

16.2. ELEMENTS OF LOQC 39

ancilla resources, quantum teleportations and error corrections. It uses another way of efficient quantum computationwith linear optical systems, and promotes nonlinear operations solely with linear optics elements.[3] The detaileddescriptions below will follow the KLM scheme and subsequent improvements upon the KLM scheme.At its root, the KLM scheme induces an effective interaction between photons by making projective measurementswith photodetectors, which falls into the category of non-deterministic quantum computation. It is based on a non-linear sign shift between two qubits that uses two ancilla photons and post-selection.[13] It is also based on the demon-strations that the probability of success of the quantum gates can be made close to one by using entangled statesprepared non-deterministically and quantum teleportation with single-qubit operations[14][15] Otherwise, without ahigh enough success rate of a single quantum gate unit, it may require an exponential amount of computing resources.Meanwhile, the KLM scheme is based on the fact that proper quantum coding can reduce the resources for obtainingaccurately encoded qubits efficiently with respect to the accuracy achieved, and can make LOQC fault-tolerant forphoton loss, detector inefficiency and phase decoherence. As a result, LOQC can be robustly implemented throughthe KLM scheme with a low enough resource requirement to suggest practical scalability, making it as promising atechnology for QIP as other known implementations.

16.2 Elements of LOQC

The basic building blocks for LOQC are introduced below. As discussed above, the KLM scheme will mainly befollowed at first, and the next section will introduce improvements for LOQC that have been studied after KLM’sproposal.DiVincenzo’s criteria for quantum computation and QIP[16][17] give that a system for QIP should satisfy at least thefollowing requirements:

1. a scalable physical system with well characterized qubits,

2. the ability to initialize the state of the qubits to a simple fiducial state, such as |000 · · · ⟩ ,

3. long relevant decoherence times, much longer than the gate operation time,

4. a “universal” set of quantum gates,

5. a qubit-specific measurement capability; if the system is also aiming for quantum communication, it shouldalso satisfy at least the following two requirements:

6. the ability to interconvert stationary and flying qubits, and

7. the ability faithfully to transmit flying qubits between specified location.

As a result of using photons and linear optical circuits, in general LOQC systems can easily satisfy conditions 3, 6and 7.[3] The following sections mainly focus on the implementations of quantum information preparation, readout,manipulation, scalability and error corrections, in order to show that LOQC is a good candidate for QIP.

16.2.1 Qubits and modes

A qubit is one of the fundamental QIP units. A qubit state which can be represented by α|0⟩+β|1⟩ is a superpositionstate with probability |α|2 of being in the |0⟩ state and probability |β|2 of being in the |1⟩ state, where |α|2+ |β|2 = 1is the normalization condition. The states |0⟩ and |1⟩ could correspond to 0-photon and 1-photon in a given modechannel. In general, there could be |n⟩, n = 0, 1, 2, · · · photon states for existing n -photon cases. An optical modeis a physically distinguishable optical communication channel, which is usually labeled by subscripts of a quantumstate. There are many ways to define distinguishable optical communication channels. For example, a set of modescould be different polarization channels of light which can be picked out with linear optics elements, various frequencychannels, or a combination of the two cases above.To avoid losing generality, the discussion below does not limit itselfto a particular instance of mode representation. A state written as |01⟩V H ≡ |0⟩V |1⟩H means a state with 0 photonin mode V (could be the “vertical” polarization channel) and 1 photon in the mode H (could be the “horizontal”polarization channel). This is a two-qubit case, as two independent modes are used.

40 CHAPTER 16. LINEAR OPTICAL QUANTUM COMPUTING

16.2.2 State preparation

To prepare a desired quantum state for LOQC, usually a single-photon state, single-photon generators and someoptical modules will be employed. For example, optical parametric down-conversion can be used to conditionallygenerate the |1⟩ state in the vertical polarization channel at time t (subscripts are ignored for this single qubit case).By using conditional single-photon source the output state is guaranteed, although there is a cost associated with thesuccess rate. A joint multi-qubit state can be prepared in a similar (possibly more sophisticated) way. In general, anarbitrary quantum state can be generated for QIP with a proper set of photon sources.A right-pointed triangle is used to represent the state preparation operator in circuit digrams in this article, followingKLM’s convention.[2]

16.2.3 State measurement/readout of KLM protocol

In the KLM protocol, a quantum state can be readout or measured using photon detectors along selected modes. Ifa photodetector detects a photon signal in a given mode, it means the corresponding mode state is a 1-photon statebefore measuring. As discussed in KLM’s proposal,[2] photon loss and detection efficiency dramatically influence thereliability of the measurement results. The corresponding failure issue and error correction methods will be describedlater.A left-pointed triangle will be used in circuit diagrams to represent the state readout operator in this article.[2]

16.2.4 Implementations of elementary quantum gates

To achieve universal quantum computing, LOQC should be capable of realizing a complete set of universal gates(please refer to the quantum gate article for the universality of quantum gates). The LOQC implementation of somebasic quantum gates are shown here.Ignoring error correction and other issues, implementations of elementary quantum gates using only mirrors, beamsplitters and phase shifters have been summarized in some early publications. See, for example, Ref.[1] The basicprinciple is that using these linear optics elements, one can construct an arbitrary (at least) 2-qubit unitary operationwhich links 2 or dual-rail qubits; in other words, those linear optical elements support a complete set of SU(2)operators. For example, the unitary matrix associated with a beam splitter Bθ,ϕ is

U(Bθ,ϕ) =

[cos θ −eiϕ sin θ

e−iϕ sin θ cos θ

],

where θ and ϕ are determined by the reflection amplitude r and the transmission amplitude t (relationship will begiven later for a simpler case). For a symmetric beam splitter, which has a phase shift ϕ = π

2 under the unitarytransformation condition |t|2 + |r|2 = 1 and t∗r + tr∗ = 0 , one can show that

U(Bθ,ϕ=π2) =

[t rr t

]=

[cos θ −i sin θ

−i sin θ cos θ

]= cos θI − i sin θσx = e−iθσx ,

which is a rotation of the dual-rail qubit about the x -axis by 2θ = 2 cos−1(|t|) in the Bloch sphere with Pauli operatorσx .A mirror is a special case that the reflecting rate is 1, so that the corresponding unitary operator is a rotation matrixgiven by

R(θ) =

[cos θ − sin θsin θ cos θ

].

For most cases of mirrors used in QIP, the incident angle θ = 45◦ . Similarly, a phase shifter operator Pϕ associateswith a unitary operator described by U(Pϕ) = eiϕ , or, if written in a 2-qubit format

U(Pϕ) =

[eiϕ 00 1

]=

[eiϕ/2 00 e−iϕ/2

]ignored) phase (global = ei

ϕ2 σz

16.2. ELEMENTS OF LOQC 41

which is equivalent to a rotation of−ϕ about the z -axis. Since any twoSU(2) rotations along orthogonal rotating axescan generate arbitrary rotations in the Bloch sphere, one can use a set of symmetric beam splitters and phase shiftersto realize an arbitrary SU(2) operators for QIP. The figures below are examples of making an equivalent H-gate andCNOT-gate using beam splitters (illustrated as rectangles connecting two sets of crossing lines with parameters θ andϕ ) and phase shifters (illustrated as rectangles on a line with parameter ϕ ).In the pictures showing the implementations of the quantum gates, each qubit is encoded using two mode channels(horizontal lines), such that |0⟩ represents a photon in the top mode, and |1⟩ represents the photon in the bottommode. The control line is not shown in the optical realization of the CNOT gate.In the KLM scheme, qubit manipulations are realized via a series of non-deterministic operations with increasingprobability of success. The first improvement to this implementation that will be discussed is the nondeterministicconditional sign flip gate.

16.2.5 Implementation of nondeterministic conditional sign flip gate

An important element of the KLM scheme is the conditional sign flip or nonlinear sign flip gate (NS-gate) as shownin the figure below on the right. It gives a nonlinear phase shift on one mode conditioned on two ancilla modes.

Linear optics implementation of NS-gate. The elements framed in the box with dashed border is the linear optics implementationwith three beam splitters and one phase shifter (see text for parameters). Modes 2 and 3 are ancilla modes.

In the picture on the right, the labels on the left of the bottom box indicate the modes. The output is accepted only ifthere is one photon in mode 2 and zero photons in mode 3 detected, where the ancilla modes 2 and 3 are prepared asthe |10⟩2,3 state. The subscript x is the phase shift of the output, and is determined by the parameters of inner opticalelements chosen.[2] For x = −1 case, the following parameters are used: θ1 = 22.5◦ , ϕ1 = 0◦ , θ2 = 65.5302◦

, ϕ2 = 0◦ , θ3 = −22.5◦ , ϕ3 = 0◦ , and ϕ4 = 180◦ . For the x = eiπ/2 case, the parameters can be chosen asθ1 = 36.53◦ , ϕ1 = 88.24◦ , θ2 = 62.25◦ , ϕ2 = −66.53◦ , θ3 = −36.53◦ , ϕ3 = −11.25◦ , and ϕ4 = 102.24◦ .Similarly, by changing the parameters of beam splitters and phase shifters, or by combining multiple NS gates, one

42 CHAPTER 16. LINEAR OPTICAL QUANTUM COMPUTING

can create various quantum gates. By sharing two ancilla modes, Knill invented the following controlled-Z gate (seethe figure on the right) with success rate of 2/27.[18]

Linear optics implementation of Controlled-Z Gate with ancilla modes labelled as 2 and 3. θ = 54.74◦ and θ′ = 17.63◦ .

The advantage of using NS gates is that the output can be guaranteed conditionally processed with some success ratewhich can be improved to nearly 1. Using the configuration as shown in the figure above on the right, the success rateof an x = −1 NS gate is 1/4 . To further improve successful rate and solve the scalability problem, one needs to usegate teleportation, described next.

16.2.6 Gates teleportation and near-deterministic gates

Given the use of non-deterministic quantum gates for LOQC, there may be only a very small probability pN thata circuit with N gates with a single-gate success possibility of p will work perfectly by running the circuit once.Therefore, the operations must on average be repeated on the order of p−N times or p−N such systems must berun in parallel. Either way, the required time or circuit resources scale exponentially. In 1999, Gottesman andChuang pointed out that one can prepare the probabilistic gates offline from the quantum circuit by using quantumteleportation.[15] The basic idea is that each probabilistic gate is prepared offline, and the successful event signal isteleported back to the quantum circuit. An illustration of quantum teleportation is given in the figure on the right.As can be seen, the quantum state in mode 1 is teleported to mode 3 through a Bell measurement and an entangledresource Bell state |Φ+⟩ , where the state 1 may be regarded as prepared offline.

Quantum circuit representation of quantum teleportation.

By using teleportation, many probabilistic gates may be prepared in parallel with n -photon entangled states, sending

16.3. IMPROVEMENTS OF KLM PROTOCOL 43

a control signal to the output mode. Through using n probabilistic gates in parallel offline, a success rate of n2

(n+1)2

can be obtained, which is close to 1 as n becomes large. The number of gates needed to realize a certain accuracyscales polynomially rather than exponentially. In this sense, the KLM protocol is resource-efficient. One experimentusing the KLM originally proposed controlled-NOT gate with four-photon input was demonstrated in 2011,[19] andgave an average fidelity of F = 0.82 ± 0.01 . This result shows that the KLM proposal is feasible for quantumcomputing tasks.

16.2.7 Error detection and correction

As discussed above, the success probability of teleportation gates can bemade arbitrarily close to 1 by preparing largerentangled states. However, the asymptotic approach to the probability of 1 is quite slow with respect to the photonnumber n . A more efficient approach is to encode against gate failure (error) based on the well-defined failure modeof the teleporters. In the KLM protocol, the teleporter’s failure can be diagnosed if zero or n+1 photons are detected.If the computing device can be encoded against accidental measurements of some certain number of photons, then itwill be possible to correct gate failures and the probability of eventually successfully applying the gate will increase.Many experimental trials using this idea has been carried out (see, for example, Refs[20][21][22]). However, a largenumber of operations are still needed to achieve a success probability very close to 1. In order to promote linearoptical quantum computing as a viable technology, more efficient quantum gates are needed. This is the subject ofthe next part.

16.3 Improvements of KLM protocol

There are many ways to improve the KLM protocol for LOQC and to make LOQCmore promising. Below are someproposals from the review article Ref.[3] and other subsequent articles:

• Using cluster states in optical quantum computing.• The Yoran-Reznik protocol.• The Nielsen protocol.• The Browne-Rudolph protocol.• Circuit-based optical quantum computing revisited.• Using one-step deterministic multipartite entanglement purification with linear optics to generate entangledphoton states.[23]

16.4 Integrated photonic circuits for LOQC

In reality, assembling a whole bunch (possibly on the order of 104 [21]) of beam splitters and phase shifters in an opticalexperimental table is challenging and unrealistic. To make LOQC functional, useful and compact, one solution is tominiaturize all linear optical elements, photon sources and photon detectors, and to integrate them onto a chip. If usinga semiconductor platform, single photon sources and photon detectors can be easily integrated. To separate modes,there have been integrated arrayed waveguide grating (AWG) which are commonly used as optical (de)multiplexersin wavelength division multiplexed (WDM). In principle, beam splitters and other linear optical elements can alsobe miniaturized or replaced by equivalent nanophotonics elements. Some progress in these endeavors can be foundin the literature, for example, Refs.[24][25][26] In 2013, the first integrated photonic circuit for quantum informationprocessing has been demonstrated using photonic crystal waveguide to realize the interaction between guided fieldand atoms.[27]

16.5 References[1] Adami, C.; Cerf, N. J. (1999). “Quantum computation with linear optics”. Quantum Computing and Quantum Com-

munications. Lecture Notes in Computer Science (Springer) 1509: 391–401. doi:10.1007/3-540-49208-9_36. ISBN978-3-540-65514-5.

44 CHAPTER 16. LINEAR OPTICAL QUANTUM COMPUTING

[2] Knill, E.; Laflamme, R.; Milburn, G. J. (2001). “A scheme for efficient quantum computation with linear optics”. Nature(Nature Publishing Group) 409 (6816): 46–52. Bibcode:2001Natur.409...46K. doi:10.1038/35051009. PMID 11343107.

[3] Kok, P.; Munro, W. J.; Nemoto, K.; Ralph, T. C.; Dowling, J. P.; Milburn, G. J. (2007). “Linear optical quantumcomputing with photonic qubits”. Rev. Mod. Phys. (American Physical Society) 79: 135–174. arXiv:quant-ph/0512071.Bibcode:2007RvMP...79..135K. doi:10.1103/RevModPhys.79.135.

[4] Lloyd, S.; Braunstein, S. L. (2003). “Quantum computation over continuous variables”. Quantum Information with Contin-uous Variables (Springer) 82 (8): 9–17. arXiv:quant-ph/9810082. Bibcode:1999PhRvL..82.1784L. doi:10.1103/PhysRevLett.82.1784.

[5] DiVincenzo, David P. (1995-02-01). “Two-bit gates are universal for quantum computation”. Physical Review A 51 (2):1015–1022. arXiv:cond-mat/9407022. Bibcode:1995PhRvA..51.1015D. doi:10.1103/PhysRevA.51.1015. Retrieved2014-01-25.

[6] Deutsch, David; Barenco, Adriano; Ekert, Artur (1995-06-08). “Universality in Quantum Computation”. Proceedings ofthe Royal Society of London. Series A: Mathematical and Physical Sciences 449 (1937): 669–677. arXiv:quant-ph/9505018.Bibcode:1995RSPSA.449..669D. doi:10.1098/rspa.1995.0065. ISSN 1471-2946. Retrieved 2014-01-25.

[7] Barenco, Adriano (1995-06-08). “A Universal Two-Bit Gate for Quantum Computation”. Proceedings of the Royal Societyof London. Series A:Mathematical and Physical Sciences 449 (1937): 679–683. arXiv:quant-ph/9505016. Bibcode:1995RSPSA.449..679B.doi:10.1098/rspa.1995.0066. ISSN 1471-2946. Retrieved 2014-01-25.

[8] Lloyd, Seth (1995-07-10). “Almost Any Quantum Logic Gate is Universal”. Physical Review Letters 75 (2): 346–349.Bibcode:1995PhRvL..75..346L. doi:10.1103/PhysRevLett.75.346. Retrieved 2014-01-25.

[9] Reck, Michael; Zeilinger, Anton; Bernstein, Herbert J.; Bertani, Philip (1994-07-04). “Experimental realization of any dis-crete unitary operator”. Physical Review Letters 73 (1): 58–61. Bibcode:1994PhRvL..73...58R. doi:10.1103/PhysRevLett.73.58.Retrieved 2014-01-25.

[10] Milburn, G. J. (1989-05-01). “Quantum optical Fredkin gate”. Physical Review Letters 62 (18): 2124–2127. Bibcode:1989PhRvL..62.2124M.doi:10.1103/PhysRevLett.62.2124. Retrieved 2014-01-25.

[11] Hutchinson, G. D.; Milburn, G. J. (2004). “Nonlinear quantum optical computing via measurement”. Journal of ModernOptics 51 (8): 1211–1222. arXiv:quant-ph/0409198. Bibcode:2004JMOp...51.1211H. doi:10.1080/09500340408230417.ISSN 0950-0340. Retrieved 2014-01-25.

[12] Lloyd, Seth (1992-07-20). “Any nonlinear gate, with linear gates, suffices for computation”. Physics Letters A 167 (3):255–260. Bibcode:1992PhLA..167..255L. doi:10.1016/0375-9601(92)90201-V. ISSN 0375-9601. Retrieved 2014-01-25.

[13] Adleman, Leonard M.; DeMarrais, Jonathan; Huang, Ming-Deh A. (1997-10). “Quantum Computability”. SIAM Journalon Computing 26 (5): 1524–1540. doi:10.1137/S0097539795293639. ISSN 0097-5397. Retrieved 2014-01-26. Checkdate values in: |date= (help)

[14] Bennett, Charles H.; Brassard, Gilles; Crépeau, Claude; Jozsa, Richard; Peres, Asher; Wootters, William K. (1993-03-29).“Teleporting an unknown quantum state via dual classical and Einstein-Podolsky-Rosen channels”. Physical Review Letters70 (13): 1895–1899. Bibcode:1993PhRvL..70.1895B. doi:10.1103/PhysRevLett.70.1895. Retrieved 2014-01-26.

[15] Gottesman, Daniel; Chuang, Isaac L. (1999-11-25). “Demonstrating the viability of universal quantum computation usingteleportation and single-qubit operations”. Nature 402 (6760): 390–393. arXiv:quant-ph/9908010. Bibcode:1999Natur.402..390G.doi:10.1038/46503. ISSN 0028-0836. Retrieved 2014-01-26.

[16] DiVincenzo, D.; Loss, D. (1998). “Quantum information is physical”. Superlattices and Microstructures 23 (3–4): 419–432. arXiv:cond-mat/9710259. Bibcode:1998SuMi...23..419D. doi:10.1006/spmi.1997.0520.

[17] Divincenzo, D. P. (2000). “The Physical Implementation of Quantum Computation”. Fortschritte der Physik 48 (9–11):771–783. arXiv:quant-ph/0002077. Bibcode:2000ForPh..48..771D. doi:10.1002/1521-3978(200009)48:9/11<771::AID-PROP771>3.0.CO;2-E.

[18] Knill, E. (2002-11-14). “Quantum gates using linear optics and postselection”. Physical Review A 66 (5): 052306.arXiv:quant-ph/0110144. Bibcode:2002PhRvA..66e2306K. doi:10.1103/PhysRevA.66.052306. Retrieved 2014-01-26.

[19] Okamoto, Ryo; O’Brien, Jeremy L.; Hofmann, Holger F.; Takeuchi, Shigeki (2011-06-21). “Realization of a Knill-Laflamme-Milburn controlled-NOT photonic quantum circuit combining effective optical nonlinearities”. Proceedingsof the National Academy of Sciences 108 (25): 10067–10071. arXiv:1006.4743. Bibcode:2011PNAS..10810067O.doi:10.1073/pnas.1018839108. ISSN 0027-8424. PMC 3121828. PMID 21646543. Retrieved 2014-01-26.

[20] O’Brien, J. L.; Pryde, G. J.; White, A. G.; Ralph, T. C. (2005-06-09). “High-fidelity Z-measurement error encoding ofoptical qubits”. Physical Review A (APS) 71 (6): 060303. arXiv:quant-ph/0408064. Bibcode:2005PhRvA..71f0303O.doi:10.1103/PhysRevA.71.060303. Retrieved 2014-01-26.

16.6. EXTERNAL LINKS 45

[21] Hayes, A. J. F.; Gilchrist, A.; Myers, C. R.; Ralph, T. C. (2004-12-01). “Utilizing encoding in scalable linear optics quan-tum computing”. Journal of Optics B: Quantum and Semiclassical Optics (IOP Publishing) 6 (12): 533–541. arXiv:quant-ph/0408098. Bibcode:2004JOptB...6..533H. doi:10.1088/1464-4266/6/12/008. ISSN 1464-4266. Retrieved 2014-01-26.

[22] Pittman, T. B.; Jacobs, B. C.; Franson, J. D. (2005-05-31). “Demonstration of quantum error correction using lin-ear optics”. Physical Review A (APS) 71 (5): 052332. arXiv:quant-ph/0502042. Bibcode:2005PhRvA..71e2332P.doi:10.1103/PhysRevA.71.052332. Retrieved 2014-01-26.

[23] Sheng, Y.-B.; Long, G. L.; Deng, F.-G. “One-step deterministic multipartite entanglement purification with linear optics”.Physics Letters A 2012 (376): 314–319. Bibcode:2012PhLA..376..314S. doi:10.1016/j.physleta.2011.09.056.

[24] Gevaux, D (2008). “Optical quantum circuits: To the quantum level”. Nature Photonics 2: 337–337. Bibcode:2008NaPho...2..337G.doi:10.1038/nphoton.2008.92.

[25] Politi, A.; Cryan, M. J.; Rarity, J. G.; Yu, S.; O'Brien, J. L. (2008). “Silica-on-silicon waveguide quantum circuits”. Science320: 646–649. arXiv:0802.0136. Bibcode:2008Sci...320..646P. doi:10.1126/science.1155441. PMID 18369104.

[26] Thompson, M. G.; Politi, A.; Matthews, J. C.; O'Brien, J. L. (2011). “Integrated waveguide circuits for optical quantumcomputing”. IET circuits, devices & systems 5: 94–102. doi:10.1049/iet-cds.2010.0108.

[27] Goban, A.; Hung, C. -L.; Yu, S. -P.; Hood, J. D.; Muniz, J. A.; Lee, J. H.; Martin, M. J.; McClung, A. C.; Choi, K.S.; Chang, D. E.; Painter, O.; Kimble, H. J. (2013). “Atom-Light Interactions in Photonic Crystals”. arXiv:1312.3446[physics.optics].

16.6 External links• “Optical chip allows for reprogramming quantum computer in seconds”. kurzweilai.net. August 14, 2015.

Chapter 17

Logic gate

“Discrete logic” redirects here. For discrete circuitry, see Discrete circuit.

In electronics, a logic gate is an idealized or physical device implementing a Boolean function; that is, it performs alogical operation on one or more logical inputs, and produces a single logical output. Depending on the context, theterm may refer to an ideal logic gate, one that has for instance zero rise time and unlimited fan-out, or it may referto a non-ideal physical device[1] (see Ideal and real op-amps for comparison).Logic gates are primarily implemented using diodes or transistors acting as electronic switches, but can also be con-structed using vacuum tubes, electromagnetic relays (relay logic), fluidic logic, pneumatic logic, optics, molecules, oreven mechanical elements. With amplification, logic gates can be cascaded in the same way that Boolean functionscan be composed, allowing the construction of a physical model of all of Boolean logic, and therefore, all of thealgorithms and mathematics that can be described with Boolean logic.Logic circuits include such devices as multiplexers, registers, arithmetic logic units (ALUs), and computer memory,all the way up through completemicroprocessors, whichmay containmore than 100million gates. Inmodern practice,most gates are made from field-effect transistors (FETs), particularly MOSFETs (metal–oxide–semiconductor field-effect transistors).Compound logic gates AND-OR-Invert (AOI) and OR-AND-Invert (OAI) are often employed in circuit design be-cause their construction using MOSFETs is simpler and more efficient than the sum of the individual gates.[2]

In reversible logic, Toffoli gates are used.

17.1 Electronic gates

Main article: Logic family

To build a functionally complete logic system, relays, valves (vacuum tubes), or transistors can be used. The simplestfamily of logic gates using bipolar transistors is called resistor-transistor logic (RTL). Unlike simple diode logicgates (which do not have a gain element), RTL gates can be cascaded indefinitely to produce more complex logicfunctions. RTL gates were used in early integrated circuits. For higher speed and better density, the resistors usedin RTL were replaced by diodes resulting in diode-transistor logic (DTL). Transistor-transistor logic (TTL) thensupplanted DTL. As integrated circuits became more complex, bipolar transistors were replaced with smaller field-effect transistors (MOSFETs); see PMOS andNMOS. To reduce power consumption still further, most contemporarychip implementations of digital systems now use CMOS logic. CMOS uses complementary (both n-channel and p-channel) MOSFET devices to achieve a high speed with low power dissipation.For small-scale logic, designers now use prefabricated logic gates from families of devices such as the TTL 7400series by Texas Instruments, the CMOS 4000 series by RCA, and their more recent descendants. Increasingly, thesefixed-function logic gates are being replaced by programmable logic devices, which allow designers to pack a largenumber of mixed logic gates into a single integrated circuit. The field-programmable nature of programmable logicdevices such as FPGAs has removed the 'hard' property of hardware; it is now possible to change the logic design ofa hardware system by reprogramming some of its components, thus allowing the features or function of a hardware

46

17.2. SYMBOLS 47

implementation of a logic system to be changed.Electronic logic gates differ significantly from their relay-and-switch equivalents. They are much faster, consumemuch less power, and aremuch smaller (all by a factor of amillion ormore inmost cases). Also, there is a fundamentalstructural difference. The switch circuit creates a continuous metallic path for current to flow (in either direction)between its input and its output. The semiconductor logic gate, on the other hand, acts as a high-gain voltage amplifier,which sinks a tiny current at its input and produces a low-impedance voltage at its output. It is not possible for currentto flow between the output and the input of a semiconductor logic gate.Another important advantage of standardized integrated circuit logic families, such as the 7400 and 4000 families, isthat they can be cascaded. This means that the output of one gate can be wired to the inputs of one or several othergates, and so on. Systems with varying degrees of complexity can be built without great concern of the designer forthe internal workings of the gates, provided the limitations of each integrated circuit are considered.The output of one gate can only drive a finite number of inputs to other gates, a number called the 'fanout limit'.Also, there is always a delay, called the 'propagation delay', from a change in input of a gate to the correspondingchange in its output. When gates are cascaded, the total propagation delay is approximately the sum of the individualdelays, an effect which can become a problem in high-speed circuits. Additional delay can be caused when a largenumber of inputs are connected to an output, due to the distributed capacitance of all the inputs and wiring and thefinite amount of current that each output can provide.

17.2 Symbols

A synchronous 4-bit up/down decade counter symbol (74LS192) in accordance with ANSI/IEEE Std. 91-1984 and IEC Publication60617-12.

There are two sets of symbols for elementary logic gates in common use, both defined in ANSI/IEEE Std 91-1984and its supplement ANSI/IEEE Std 91a-1991. The “distinctive shape” set, based on traditional schematics, is used

48 CHAPTER 17. LOGIC GATE

for simple drawings, and derives from MIL-STD-806 of the 1950s and 1960s. It is sometimes unofficially describedas “military”, reflecting its origin. The “rectangular shape” set, based on ANSI Y32.14 and other early industrystandards, as later refined by IEEE and IEC, has rectangular outlines for all types of gate and allows representationof a much wider range of devices than is possible with the traditional symbols.[3] The IEC standard, IEC 60617-12,has been adopted by other standards, such as EN 60617-12:1999 in Europe, BS EN 60617-12:1999 in the UnitedKingdom, and DIN EN 60617-12:1998 in Germany.The mutual goal of IEEE Std 91-1984 and IEC 60617-12 was to provide a uniformmethod of describing the complexlogic functions of digital circuits with schematic symbols. These functions were more complex than simple AND andOR gates. They could bemedium scale circuits such as a 4-bit counter to a large scale circuit such as a microprocessor.IEC 617-12 and its successor IEC 60617-12 do not explicitly show the “distinctive shape” symbols, but do not prohibitthem.[3] These are, however, shown in ANSI/IEEE 91 (and 91a) with this note: “The distinctive-shape symbol is,according to IEC Publication 617, Part 12, not preferred, but is not considered to be in contradiction to that standard.”IEC 60617-12 correspondingly contains the note (Section 2.1) “Although non-preferred, the use of other symbolsrecognized by official national standards, that is distinctive shapes in place of symbols [list of basic gates], shallnot be considered to be in contradiction with this standard. Usage of these other symbols in combination to formcomplex symbols (for example, use as embedded symbols) is discouraged.” This compromise was reached betweenthe respective IEEE and IEC working groups to permit the IEEE and IEC standards to be in mutual compliance withone another.A third style of symbols was in use in Europe and is still widely used in European academia. See the column “DIN40700” in the table in the German Wikipedia.In the 1980s, schematics were the predominant method to design both circuit boards and custom ICs known as gatearrays. Today custom ICs and the field-programmable gate array are typically designed with Hardware DescriptionLanguages (HDL) such as Verilog or VHDL.The two input exclusive-OR is true only when the two input values are different, false if they are equal, regardless ofthe value. If there are more than two inputs, the gate generates a true at its output if the number of trues at its inputis odd. In practice, these gates are built from combinations of simpler logic gates.

17.3 Universal logic gates

For more details on the theoretical basis, see functional completeness.Charles Sanders Peirce (winter of 1880–81) showed that NOR gates alone (or alternatively NAND gates alone)

can be used to reproduce the functions of all the other logic gates, but his work on it was unpublished until 1933.[4]The first published proof was by Henry M. Sheffer in 1913, so the NAND logical operation is sometimes calledSheffer stroke; the logical NOR is sometimes called Peirce’s arrow.[5] Consequently, these gates are sometimes calleduniversal logic gates.[6]

17.4 De Morgan equivalent symbols

By use ofDeMorgan’s laws, anAND function is identical to anOR functionwith negated inputs and outputs. Likewise,an OR function is identical to an AND function with negated inputs and outputs. A NAND gate is equivalent to anOR gate with negated inputs, and a NOR gate is equivalent to an AND gate with negated inputs.This leads to an alternative set of symbols for basic gates that use the opposite core symbol (AND or OR) but with theinputs and outputs negated. Use of these alternative symbols can make logic circuit diagrams much clearer and helpto show accidental connection of an active high output to an active low input or vice versa. Any connection that haslogic negations at both ends can be replaced by a negationless connection and a suitable change of gate or vice versa.Any connection that has a negation at one end and no negation at the other can be made easier to interpret by insteadusing the De Morgan equivalent symbol at either of the two ends. When negation or polarity indicators on both endsof a connection match, there is no logic negation in that path (effectively, bubbles “cancel”), making it easier to followlogic states from one symbol to the next. This is commonly seen in real logic diagrams - thus the reader must not getinto the habit of associating the shapes exclusively as OR or AND shapes, but also take into account the bubbles atboth inputs and outputs in order to determine the “true” logic function indicated.A De Morgan symbol can show more clearly a gate’s primary logical purpose and the polarity of its nodes that are

17.4. DE MORGAN EQUIVALENT SYMBOLS 49

The 7400 chip, containing four NANDs. The two additional pins supply power (+5 V) and connect the ground.

considered in the “signaled” (active, on) state. Consider the simplified case where a two-input NAND gate is usedto drive a motor when either of its inputs are brought low by a switch. The “signaled” state (motor on) occurs wheneither one OR the other switch is on. Unlike a regular NAND symbol, which suggests AND logic, the De Morganversion, a two negative-input OR gate, correctly shows that OR is of interest. The regular NAND symbol has a bubbleat the output and none at the inputs (the opposite of the states that will turn the motor on), but the De Morgan symbolshows both inputs and output in the polarity that will drive the motor.De Morgan’s theorem is most commonly used to implement logic gates as combinations of only NAND gates, or ascombinations of only NOR gates, for economic reasons.

50 CHAPTER 17. LOGIC GATE

17.5 Data storage

Main article: Sequential logic

Logic gates can also be used to store data. A storage element can be constructed by connecting several gates in a"latch" circuit. More complicated designs that use clock signals and that change only on a rising or falling edge of theclock are called edge-triggered "flip-flops". Formally, a flip-flop is called a bistable circuit, because it has two stablestates which it can maintain indefinitely. The combination of multiple flip-flops in parallel, to store a multiple-bitvalue, is known as a register. When using any of these gate setups the overall system has memory; it is then calleda sequential logic system since its output can be influenced by its previous state(s), i.e. by the sequence of inputstates. In contrast, the output from combinatorial logic is purely a combination of its present inputs, unaffected bythe previous input and output states.These logic circuits are known as computer memory. They vary in performance, based on factors of speed, complex-ity, and reliability of storage, and many different types of designs are used based on the application.

17.6 Three-state logic gates

A C

B

A CB

A tristate buffer can be thought of as a switch. If B is on, the switch is closed. If B is off, the switch is open.

Main article: Tri-state buffer

A three-state logic gate is a type of logic gate that can have three different outputs: high (H), low (L) and high-impedance (Z). The high-impedance state plays no role in the logic, which is strictly binary. These devices are usedon buses of the CPU to allow multiple chips to send data. A group of three-states driving a line with a suitable controlcircuit is basically equivalent to a multiplexer, which may be physically distributed over separate devices or plug-incards.In electronics, a high output would mean the output is sourcing current from the positive power terminal (positivevoltage). A low output would mean the output is sinking current to the negative power terminal (zero voltage). Highimpedance would mean that the output is effectively disconnected from the circuit.

17.7 History and development

The binary number system was refined by Gottfried Wilhelm Leibniz (published in 1705) and he also establishedthat by using the binary system, the principles of arithmetic and logic could be combined. In an 1886 letter, CharlesSanders Peirce described how logical operations could be carried out by electrical switching circuits.[7] Eventually,vacuum tubes replaced relays for logic operations. Lee De Forest's modification, in 1907, of the Fleming valve canbe used as an AND logic gate. Ludwig Wittgenstein introduced a version of the 16-row truth table as proposition5.101 of Tractatus Logico-Philosophicus (1921). Walther Bothe, inventor of the coincidence circuit, got part ofthe 1954 Nobel Prize in physics, for the first modern electronic AND gate in 1924. Konrad Zuse designed and builtelectromechanical logic gates for his computer Z1 (from 1935–38). Claude E. Shannon introduced the use of Booleanalgebra in the analysis and design of switching circuits in 1937. Active research is taking place in molecular logicgates.

17.8. IMPLEMENTATIONS 51

17.8 Implementations

Main article: Unconventional computing

Since the 1990s, most logic gates are made in CMOS technology (i.e. NMOS and PMOS transistors are used). Oftenmillions of logic gates are packaged in a single integrated circuit.There are several logic families with different characteristics (power consumption, speed, cost, size) such as: RDL(resistor-diode logic), RTL (resistor-transistor logic), DTL (diode-transistor logic), TTL (transistor-transistor logic)and CMOS (complementary metal oxide semiconductor). There are also sub-variants, e.g. standard CMOS logic vs.advanced types using still CMOS technology, but with some optimizations for avoiding loss of speed due to slowerPMOS transistors.Non-electronic implementations are varied, though few of them are used in practical applications. Many earlyelectromechanical digital computers, such as the Harvard Mark I, were built from relay logic gates, using electro-mechanical relays. Logic gates can be made using pneumatic devices, such as the Sorteberg relay or mechanical logicgates, including on a molecular scale.[8] Logic gates have been made out of DNA (see DNA nanotechnology)[9] andused to create a computer called MAYA (see MAYA II). Logic gates can be made from quantum mechanical ef-fects (though quantum computing usually diverges from boolean design). Photonic logic gates use non-linear opticaleffects.In principle any method that leads to a gate that is functionally complete (for example, either a NOR or a NANDgate) can be used to make any kind of digital logic circuit. Note that the use of 3-state logic for bus systems is notneeded, and can be replaced by digital multiplexers, which can be built using only simple logic gates (such as NANDgates, NOR gates, or AND and OR gates).

17.9 See also• And-inverter graph• Boolean algebra topics• Boolean function• Digital circuit• Espresso heuristic logic minimizer• Fanout• Flip-flop (electronics)• Functional completeness• Karnaugh map• Combinational logic• Logic family• Logical graph• NMOS logic• Programmable Logic Controller (PLC)• Programmable Logic Device (PLD)• Propositional calculus• Quantum gate• Race hazard• Reversible computing• Truth table

52 CHAPTER 17. LOGIC GATE

17.10 References[1] Jaeger, Microelectronic Circuit Design, McGraw-Hill 1997, ISBN 0-07-032482-4, pp. 226-233

[2] Tinder, Richard F. (2000). Engineering digital design: Revised Second Edition. pp. 317–319. ISBN 0-12-691295-5.Retrieved 2008-07-04.

[3] Overview of IEEE Standard 91-1984 Explanation of Logic Symbols, Doc. No. SDYZ001A, Texas Instruments Semicon-ductor Group, 1996

[4] Peirce, C. S. (manuscript winter of 1880–81), “A Boolean Algebra with One Constant”, published 1933 in Collected Papersv. 4, paragraphs 12–20. Reprinted 1989 inWritings of Charles S. Peirce v. 4, pp. 218-21, Google Preview. See Roberts,Don D. (2009), The Existential Graphs of Charles S. Peirce, p. 131.

[5] Hans Kleine Büning; Theodor Lettmann (1999). Propositional logic: deduction and algorithms. Cambridge UniversityPress. p. 2. ISBN 978-0-521-63017-7.

[6] John Bird (2007). Engineering mathematics. Newnes. p. 532. ISBN 978-0-7506-8555-9.

[7] Peirce, C. S., “Letter, Peirce to A. Marquand", dated 1886, Writings of Charles S. Peirce, v. 5, 1993, pp. 541–3. GooglePreview. See Burks, Arthur W., “Review: Charles S. Peirce, The new elements of mathematics", Bulletin of the AmericanMathematical Society v. 84, n. 5 (1978), pp. 913–18, see 917. PDF Eprint.

[8] Mechanical Logic gates (focused on molecular scale)

[9] DNA Logic gates

17.11 Further reading• Awschalom, D.D.; Loss, D.; Samarth, N. (5 August 2002). Semiconductor Spintronics and Quantum Compu-tation. Berlin, Germany: Springer-Verlag. ISBN 978-3-540-42176-4. Retrieved 28 November 2012.

• Bostock, Geoff (1988). Programmable logic devices: technology and applications. New York: McGraw-Hill.ISBN 978-0-07-006611-3. Retrieved 28 November 2012.

• Brown, Stephen D.; Francis, Robert J.; Rose, Jonathan; Vranesic, Zvonko G. (1992). Field ProgrammableGate Arrays. Boston, MA: Kluwer Academic Publishers. ISBN 978-0-7923-9248-4. Retrieved 28 November2012.

Chapter 18

Logical equality

For the corresponding concept in combinational logic, see XNOR gate.Logical equality is a logical operator that corresponds to equality in Boolean algebra and to the logical biconditional

AB

Q

XNOR Logic Gate Symbol

in propositional calculus. It gives the functional value true if both functional arguments have the same logical value,and false if they are different.It is customary practice in various applications, if not always technically precise, to indicate the operation of logicalequality on the logical operands x and y by any of the following forms:x ↔ y x ⇔ y Exyx EQ y x = y

Some logicians, however, draw a firm distinction between a functional form, like those in the lefthand column, whichthey interpret as an application of a function to a pair of arguments — and thus a mere indication that the value ofthe compound expression depends on the values of the component expressions — and an equational form, like thosein the righthand column, which they interpret as an assertion that the arguments have equal values, in other words,that the functional value of the compound expression is true.In mathematics, the plus sign "+" almost invariably indicates an operation that satisfies the axioms assigned to additionin the type of algebraic structure that is known as a field. For boolean algebra, this means that the logical operationsignified by "+" is not the same as the inclusive disjunction signified by "∨" but is actually equivalent to the logicalinequality operator signified by "≠", or what amounts to the same thing, the exclusive disjunction signified by “XOR”.Naturally, these variations in usage have caused some failures to communicate between mathematicians and switchingengineers over the years. At any rate, one has the following array of corresponding forms for the symbols associatedwith logical inequality:

53

54 CHAPTER 18. LOGICAL EQUALITY

x+ y x ≡ y Jxyx XOR y x = y

This explains why “EQ” is often called "XNOR" in the combinational logic of circuit engineers, since it is the Nega-tion of the XOR operation; NXOR is a less commonly used alternative.[1] Another rationalization of the admittedlycircuitous name “XNOR” is that one begins with the “both false” operator NOR and then adds the eXception, “orboth true”.

18.1 Definition

Logical equality is an operation on two logical values, typically the values of two propositions, that produces a valueof true if and only if both operands are false or both operands are true.The truth table of p EQ q (also written as p = q, p ↔ q, or p ≡ q, or p == q) is as follows:

The Venn diagram of A EQ B (red part is true)

18.2 Alternative descriptions

The form (x = y) is equivalent to the form (x ∧ y) ∨ (¬x ∧ ¬y).(x = y) = ¬(x⊕ y) = ¬x⊕ y = x⊕ ¬y = (x ∧ y) ∨ (¬x ∧ ¬y) = (¬x ∨ y) ∧ (x ∨ ¬y)For the operands x and y, the truth table of the logical equality operator is as follows:

18.3 See also• Boolean function

18.4. REFERENCES 55

• If and only if

• Logical equivalence

• Logical biconditional

• Propositional calculus

18.4 References[1] Keeton, Brian; Cavaness, Chuck; Friesen, Geoff (2001), Using Java 2, Que Publishing, p. 112, ISBN 9780789724687.

18.5 External links• Mathworld, XNOR

Chapter 19

Magnetic logic

Magnetic logic is digital logic made using the non linear properties of wound ferrite cores.[1] Magnetic logic repre-sents 0 and 1 by magnetising cores clockwise or anticlockwise.[2]

Examples of magnetic logic include core memory. Also, AND, OR, NOT and clocked shift logic gates can beconstructed using appropriate windings, and the use of diodes.A complete computer called the ALWAC 800 was constructed using magnetic logic, but it was not commerciallysuccessful. The Elliott 803 computer used a combination of magnetic cores (for logic function) and germaniumtransistors (as pulse amplifiers) for its CPU. It was a commercial success.Magnetic logic was able to achieve switching speeds of about 1Mhz but was overtaken by semiconductor basedelectronics which was able to switch much faster.Magnetic logic has advantages in that it is non volatile, it may be powered down without losing its state, and in theform of core memory was used for over two decades.[1]

19.1 See also• Electropermanent magnet

• Magnetic amplifier

• Parametron

19.2 References[1] “All-Magnetic Logic”. Timeline of Innovations. SRI International. Retrieved 2013-07-01.

[2] MAGNETIC CORES - PART I - PROPERTIES - Department of Defense 1962 - PIN 28374 - PROPERTIES OFMAGNETIC CORES AND THEIR APPLICATION IN DATA PROCESSING SYSTEM; HOW INFORMATION ISSTORED AND TRANSFERRED FROM ONE CORE TO ANOTHER.

56

Chapter 20

Majority function

In Boolean logic, the majority function (also called the median operator) is a function from n inputs to one out-put. The value of the operation is false when n/2 or more arguments are false, and true otherwise. Alternatively,representing true values as 1 and false values as 0, we may use the formula

Majority (p1, . . . , pn) =⌊1

2+

(∑n

i=1 pi)− 1/2

n

⌋.

The "−1/2” in the formula serves to break ties in favor of zeros when n is even. If the term "−1/2” is omitted, theformula can be used for a function that breaks ties in favor of ones.

20.1 Boolean circuits

A majority gate is a logical gate used in circuit complexity and other applications of Boolean circuits. A majority gatereturns true if and only if more than 50% of its inputs are true.For instance, in a full adder, the carry output is found by applying a majority function to the three inputs, althoughfrequently this part of the adder is broken down into several simpler logical gates.Many systems have triple modular redundancy; they use the majority function for majority logic decoding to imple-ment error correction.A major result in circuit complexity asserts that the majority function cannot be computed by AC0 circuits of subex-ponential size.

20.2 Monotone formulae for majority

For n = 1 the median operator is just the unary identity operation x. For n = 3 the ternary median operator can beexpressed using conjunction and disjunction as xy + yz + zx. Remarkably this expression denotes the same operationindependently of whether the symbol + is interpreted as inclusive or or exclusive or.For an arbitrary n there exists a monotone formula for majority of size O(n5.3).[1] This is proved using probabilisticmethod. Thus, this formula is non-constructive. However, one can obtain an explicit formula for majority of poly-nomial size using a sorting network of Ajtai, Komlós, and Szemerédi.The majority function produces “1” when more than half of the inputs are 1; it produces “0” when more than halfthe inputs are 0. Most applications deliberately force an odd number of inputs so they don't have to deal with thequestion of what happens when exactly half the inputs are 0 and exactly half the inputs are 1. The few systems thatcalculate the majority function on an even number of inputs are often biased towards “0”—they produce “0” whenexactly half the inputs are 0 -- for example, a 4-input majority gate has a 0 output only when two or more 0’s appearat its inputs.[2] In a few systems, a 4-input majority network randomly chooses “1” or “0” when exactly two 0’s appearat its inputs.[3]

57

58 CHAPTER 20. MAJORITY FUNCTION

20.3 Properties

For any x, y, and z, the ternary median operator ⟨x, y, z⟩ satisfies the following equations.

• ⟨x, y, y⟩ = y

• ⟨x, y, z⟩ = ⟨z, x, y⟩

• ⟨x, y, z⟩ = ⟨x, z, y⟩

• ⟨⟨x, w, y⟩, w, z⟩ = ⟨x, w, ⟨y, w, z⟩⟩

An abstract system satisfying these as axioms is a median algebra.

20.4 Notes[1] Valiant, Leslie (1984). “Short monotone formulae for the majority function”. Journal of Algorithms 5 (3): 363–366.

doi:10.1016/0196-6774(84)90016-6.

[2] Peterson, William Wesley; Weldon, E.J. (1972). Error-correcting Codes. MIT Press. ISBN 9780262160391.

[3] Chaouiya, Claudine; Ourrad, Ouerdia; Lima, Ricardo (July 2013). “Majority Rules with Random Tie-Breaking in BooleanGene Regulatory Networks”. PLoS ONE 8 (7) (Public Library of Science). doi:10.1371/journal.pone.0069626.

20.5 References• Knuth, Donald E. (2008). Introduction to combinatorial algorithms and Boolean functions. The Art of Com-puter Programming 4a. Upper Saddle River, NJ: Addison-Wesley. pp. 64–74. ISBN 0-321-53496-4.

20.6 See also

Media related to Majority functions at Wikimedia Commons

• Boolean algebra (structure)

• Boolean algebras canonically defined

• Majority problem (cellular automaton)

Chapter 21

Molecular logic gate

A molecular logic gate is a molecule that performs a logical operation based on one or more physical or chemicalinputs and a single output. The field has advanced from simple logic systems based on a single chemical or physicalinput to molecules capable of combinatorial and sequential operations such as arithmetic operations i.e. moleculatorsand memory storage algorithms.For logic gates with a single input, there are four possible output patterns. When the input is 0, the output can beeither a 0 or 1. When the input is 1, the output can again be 0 or 1. The four output bit patterns that can arisecorresponds to a specific logic type: PASS 0, YES, NOT and PASS 1. PASS 0 always outputs 0, whatever the input.PASS 1 always outputs 1, whatever the input. YES outputs a 1 when the input is 1 and NOT is the inverse YES - itoutputs a 0 when the input is 1. An example of a YES logic gate is the molecular structure shown below. A ‘1’ outputis given only when sodium ions are present in solution (‘1’ input).Molecular logic gates workwith input signals based on chemical processes andwith output signals based on spectroscopy.One of the earlier water solution-based systems exploits the chemical behavior of compounds A and B in scheme 1 .Compound A is a push-pull olefin with the top receptor containing four carboxylic acid anion groups (and non-disclosed counter cations) capable of binding to calcium. The bottom part is a quinoline molecule which is a receptorfor hydrogen ions. The logic gate operates as follows. Without any chemical input of Ca2+ or H+, the chromophoreshows a maximum absorbance in UV/VIS spectroscopy at 390 nm. When calcium is introduced a blue shift takesplace and the absorbance at 390 nm decreases. Likewise addition of protons causes a red shift and when both cationsare in the water the net result is absorption at the original 390 nm. This system represents a XNOR logic gate inabsorption and a XOR logic gate in transmittance.In compound B the bottom section now contains a tertiary amino group also capable of binding to protons. In thissystem fluorescence only takes place when both cations available. The presence of both cations hinders photoinducedelectron transfer (PET) allowing compound B to fluoresce. In the absence of both or either ion, fluorescence isquenched by PET, which involves an electron transfer from either the nitrogen atom or the oxygen atoms, or both tothe anthracenyl group. When both receptors are bound to calcium ions and protons respectively, both PET channelsare shut off. The overall result of Compound B is AND logic, since an output of “1” (fluorescence) occurs onlywhen both Ca2+ and H+ are present in solution, that is, have values as “1”. With both systems run in parallel andwith monitoring of transmittance for system A and fluorescence for system B the result is a half-adder capable ofreproducing the equation 1+1=2.In a modification of system B not two but three chemical inputs are simultaneously processed in an AND logic gate. An enhanced fluorescence signal is observed only in the presence of excess protons, zinc and sodium ions throughinteractions with their respective amine, phenyldiaminocarboxylate and crown ether receptors. The processing modeoperates similarly as discussed above - fluorescence is observed due to the prevention of competing photoinducedelectron transfer reactions from the receptors to the excited anthracene fluorophore. The absence of one, two or allthree ion inputs results in a low fluorescence output. Each receptor is selective for its specific ion as an increase inthe concentration of the other ions does not yield a high fluorescence. The specific concentration threshold of eachinput must be reached to achieve a fluorescent output in accordance with combinatorial AND logic. This prototypecould potentially be extended to point-of-care medical diagnostics application for disease screening in the future.In a similar set-up, the molecular logic gate illustrated below demonstrates the advancement from redox-fluorescentswitches to multi-input logic gates with an electrochemical switch. This two-input AND logic gate incorporates a

59

60 CHAPTER 21. MOLECULAR LOGIC GATE

A YES molecular logic gate receptive to sodium ions

Scheme 1. Molecular logic gates de Silva 2000

61

A three-input AND logic gate

tertiary amine proton receptor and a tetrathiafulvelene redox donor. These groups, when attached to anthracene cansimultaneously process information concerning acid concentration and oxidizing ability of the solution.

A two-input AND molecular logic gate sensor for protons and electrons

The INHIBIT logic gate illustrated below as provided by Gunnlaugsson et al. incorporates a Tb3+ ion in a chelatecomplex. This two-input logic gate is the first of its kind and displays non-commutative behaviour with chemicalinputs and a phosphorescence output. Whenever dioxygen (input 1) is present, the system is quenched and nophosphorescence is observed (output 0). The second input, H+, must also be present for an output “1” to be ob-served. This is understood from a two-input INHIBIT truth table.In another XOR logic gate system the chemistry is based on the pseudorotaxane depicted in scheme 3. In organicsolution the electron deficient diazapyrenium salt (rod) and the electron rich 2,3-dioxynaphthalene units of the crownether (ring) self-assemble by formation of a charge transfer complex.

62 CHAPTER 21. MOLECULAR LOGIC GATE

Two-input INHIBIT logic gate

An added tertiary amine like tributylamine forms a 1:2 adduct with the diazapyrene and the complex gets dethreaded.This process is accompanied by an increase in emission intensity at 343 nm resulting from freed crown ether. Addedtrifluoromethanesulfonic acid reacts with the amine and the process is reverted. Excess acid locks the crown ether byprotonation and again the complex is dethreaded.A full adder system based on fluorescein is able to compute 1+1+1=3.

63

Scheme 3. Pseudorotaxane logic gate

Molecular sequential logic is exemplified by D. Margulies et al., were they demonstrate a molecular keypad lockresembling the processing capabilities of an electronic security device which is equivalent to incorporates severalinterconnected AND logic gates in parallel. Themoleculemimics an electronic keypad of an automated teller machine(ATM). The output signals are dependent not only on the combination of inputs but also on the correct order ofinputs: in other words the correct password must be entered. The molecule was designed using pyrene and fluoresceinfluorophores connected by a siderophore, which binds to Fe(III), and the acidic of the solution changes the fluorescenceproperties of the fluorescein fluorophore.Further development in this field might also see molecular logic gates replace semiconductors in the IT industry. Suchmolecular systems can theoretically overcome the problems arising when semiconductors approach nano-dimensions.Molecular logic gates are more versatile than their silicon counterparts, with phenomena such as superposed logicunavailable to semiconductor electronics. Drymolecular gates such as the one demonstrated byAvouris and colleaguesprove to be possible substitutes for semiconductor devices due to their small size, similar infrastructure and dataprocessing abilities. Avouris revealed a NOT logic gate composed of a bundle of carbon nanotubes. The nanotubesare doped differently in adjoining regions creating two complementary field effect transistors. The bundle operates asa NOT logic gate only when satisfactory conditions are met.New potential applications of chemical logic gates continue to be explored. A recent study illustrates the applicationof a logic gate for photodynamic therapy. A bodipy dye attached to a crown-ether and two pyridyl groups separatedby spacers (as shown below) works according to an AND logic gate. The molecule works as a photodynamic agentupon irradiation at 660 nm under conditions of relatively high sodium and proton ion concentrations by convertingtriplet oxygen to cytotoxic singlet oxygen. This prototypical example would take advantage of the higher sodiumlevels and lower pH in tumor tissue compared to the levels in normal cells. When these two cancer-related cellularparameters are satisfied, a change is observed in the absorbance spectrum. This technique could be useful for thetreatment of malignant tumors as it is non-invasive and specific.A molecular logic gate can processes modulators much like the set up seen in de Silva’s ‘Proof-of-principle’ butincorporating different logic gates on the same molecule. Such a function is called integrated logic and is exemplifiedby the BODIPY-based, half-subtractor logic gate illustrated by A. Coskun, E. U. Akkaya and their colleagues (as

64 CHAPTER 21. MOLECULAR LOGIC GATE

Two-input AND logic gate by Ozlem and Akkaya with photodynamic therapeutic applications

shown below). When monitored at two different wavelengths, 565 and 660 nm, XOR and INHIBIT logic gates areobtained at the respective wavelengths. Optical studies of this compound in THF reveal an absorbance peak at 565nm and an emission peak at 660 nm. Addition of an acid results in a hypsochromic shift of both peaks as protonationof the tertiary amine results in an internal charge transfer. The colour of the emission observed is yellow. Upon

21.1. SEE ALSO 65

addition of a strong base, the phenolic hydroxyl group is rendered deprotonated, resulting in a photoinduced electrontransfer, which in turn renders the molecule non-emissive. Upon addition of both an acid and a base, the emissionof the molecule is observed as red, as the tertiary amine would not be protonated while the hydroxyl group wouldremain protonated resulting in the absence of both PET and ICT. Due to the great difference in emission intensity,this single molecule is capable of carrying out an arithmetic operation; subtraction at a nanoscale level.

Two-input integrated logic gate

21.1 See Also

• Chemical computer

• Quantum Computer

21.2 References

1. ^ A. Prasanna de Silva and Nathan D. McClenaghan. Proof-of-Principle of Molecular-Scale Arithmetic J. Am.Chem. Soc. 2000, 122, 16, 3965–3966. Abstract

2. ^ David C. Magri, Gareth J. Brown, Gareth D. McClean and A. Prasanna de Silva. Communicating ChemicalCongregation: A Molecular AND Logic Gate with Three Chemical Inputs as a “Lab-on-a-Molecule” Prototype J.Am. Chem. Soc. 2006, 128, 4950–4951. (Communication) Abstract

3. ^ David C. Magri. A fluorescent AND logic gate driven by electrons and protons. New J. Chem. 2009, 33,457–461.

4. ^ T. Gunnlaugsson, D.A. MacDonail and D. Parker, Chem. Commun. 2000, 93.

5. ^ Alberto Credi, Vincenzo Balzani, Steven J. Langford, and J. Fraser Stoddart. Logic Operations at the Molec-ular Level. An XOR Gate Based on a Molecular Machine J. Am. Chem. Soc. 1997,119, 2679–2681.(Article)Abstract

6. ^ David Margulies, Galina Melman, and Abraham Shanzer. A Molecular Full-Adder and Full-Subtractor, anAdditional Step toward aMoleculator J. Am. Chem. Soc. 2006, 128, 4865–4871. (Article) doi:10.1021/ja058564w

66 CHAPTER 21. MOLECULAR LOGIC GATE

7. ^ David Margulies, Galina Melman, and Abraham Shanzer. A molecular keypad lock: A photochemical devicecapable of authorizing password entries. J. Am. Chem. Soc. 2007, 129, 347–354.

8. ^ S. Oslem and E.U. Akkaya. Thinking outside the silicon box: molecular AND logic as an additional layer ofselectivity in singlet oxygen generation for photodynamic therapy. J. Am. Chem. Soc. 2009, 131, 48–49.

9. ^ A. Coskun, E. Deniz and E.U. Akkaya. Effective PET and ICT switching of boradiazaindacene emission:A unimolecular, emission-mode, molecular half-subtractor with reconfigurable logic gates. Org. Lett. 20055187–5189.

21.3 External links• A Molecular Photoionic AND Gate Based on Fluorescent Signaling

• The 3rd International Conference on Molecular Sensors &Molecular Logic Gates (MSMLG) was held on July8–11, 2012 at Korea University in Seoul, Korea.

Chapter 22

NAND gate

In digital electronics, a NAND gate (negative-AND) is a logic gate which produces an output that is false only if allits inputs are true; thus its output is complement to that of the AND gate. A LOW (0) output results only if boththe inputs to the gate are HIGH (1); if one or both inputs are LOW (0), a HIGH (1) output results. It is made usingtransistors. By De Morgan’s theorem, AB=A+B, a NAND gate is equivalent to inverters followed by an OR gate.The NAND gate is significant because any boolean function can be implemented by using a combination of NANDgates. This property is called functional completeness.Digital systems employing certain logic circuits take advantage of NAND’s functional completeness.The function NAND(a1, a2, ..., an) is logically equivalent to NOT(a1 AND a2 AND ... AND an).

22.1 Symbols

There are three symbols for NAND gates: the MIL/ANSI symbol, the IEC symbol and the deprecated DIN symbolsometimes found on old schematics. For more information see logic gate symbols. The ANSI symbol for the NANDgate is a standard AND gate with an inversion bubble connected.

22.2 Hardware description and pinout

NAND gates are basic logic gates, and as such they are recognised in TTL and CMOS ICs.

22.2.1 CMOS version

The standard, 4000 series, CMOS IC is the 4011, which includes four independent, two-input, NAND gates.

Availability

These devices are available from most semiconductor manufacturers such as Fairchild Semiconductor, Philips orTexas Instruments. These are usually available in both through-hole DIL and SOIC format. Datasheets are readilyavailable in most datasheet databases.The standard 2-, 3-, 4- and 8-input NAND gates are available:

• CMOS

• 4011: Quad 2-input NAND gate• 4023: Triple 3-input NAND gate• 4012: Dual 4-input NAND gate

67

68 CHAPTER 22. NAND GATE

The TTL 7400 chip, containing four NANDs. The two additional pins supply power (+5 V) and connect the ground

• 4068: Mono 8-input NAND gate

• TTL

• 7400: Quad 2-input NAND gate

• 7410: Triple 3-input NAND gate

• 7420: Dual 4-input NAND gate

• 7430: Mono 8-input NAND gate

22.3. IMPLEMENTATIONS 69

1

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7

14

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9

VDD

GND4011

8

B4

A4

Q4

Q3

B3

A1

B1

Q1

Q2

A2

B2

A3

This schematic diagram shows the arrangement of NAND gates within a standard 4011 CMOS integrated circuit.

22.3 Implementations

The NAND gate has the property of functional completeness. That is, any other logic function (AND, OR, etc.) canbe implemented using only NAND gates.[1] An entire processor can be created using NAND gates alone. In TTLICs using multiple-emitter transistors, it also requires fewer transistors than a NOR gate.

22.3.1 Alternatives

If no specific NAND gates are available, one can be made from NOR gates, because NAND and NOR gates areconsidered the “universal gates”, meaning that they can be used to make all the others.[1]

22.4 See also

• AND gate

• OR gate

70 CHAPTER 22. NAND GATE

• NOT gate

• NOR gate

• XOR gate

• XNOR gate

• Boolean algebra

• Logic gate

• NAND logic

• Digital electronics

22.5 References[1] Mano, M. Morris and Charles R. Kime. Logic and Computer Design Fundamentals, Third Edition. Prentice Hall, 2004. p.

73.

22.6 External links• TTL NAND and AND gates - All About Circuits

Chapter 23

NAND logic

This article is about NANDLogic in the sense of building other logic gates using just NAND gates. For NANDGates,see NAND gate. For NAND in the purely logical sense, see Logical NAND. For logic gates generally, see Logic gate.

Because the NAND function has functional completeness all logic systems can be converted into NAND gates. Thisis also true of NOR gates. In principle, any combinatorial logic function can be realized with enough NAND gates.

23.1 NAND

A NAND gate is an inverted AND gate. It has the following truth table:

23.2 NOT

A NOT gate is made by joining the inputs of a NAND gate together. Since a NAND gate is equivalent to an ANDgate followed by a NOT gate, joining the inputs of a NAND gate leaves only the NOT gate.

23.3 AND

An AND gate is made by following a NAND gate with a NOT gate as shown below. This gives a NOT NAND, i.e.AND.

23.4 OR

If the truth table for a NAND gate is examined or by applying De Morgan’s Laws, it can be seen that if any of theinputs are 0, then the output will be 1. To be an OR gate, however, the output must be 1 if any input is 1. Therefore,if the inputs are inverted, any high input will trigger a high output.

23.5 NOR

A NOR gate is simply an inverted OR gate. Output is high when neither input A nor input B is high:

71

72 CHAPTER 23. NAND LOGIC

23.6 XOR

An XOR gate is constructed similarly to an OR gate, except with an additional NAND gate inserted such that if bothinputs are high, the inputs to the final NAND gate will also be high, and the output will be low.

23.7 XNOR

An XNOR gate is simply an XOR gate with an inverted output:

23.8 See also• NOR logic. Like NAND gates, NOR gates are also universal gates.

• Functional Completeness

23.9 External links• TTL NAND and AND gates - All About Circuits

• Steps to Derive XOR from NAND gate.

• NAND Gate, Demonstrate an interactive simulation of the NAND Gate circuit created with Teahlab’s simu-lator.

23.10 References

Lancaster, Don (1974). TTL Cookbook (1st ed.). Indianapolis, IN: Howard W Sams. pp. 126–135. ISBN 0-672-21035-5.

Chapter 24

NOR gate

This article is about NOR in the sense of an electronic logic gate (e.g. CMOS 4001). For NOR in the purely logicalsense, see Logical NOR. For other uses of NOR or Nor, see Nor (disambiguation).“4001” redirects here. For the year, see 5th millennium.

The NOR gate is a digital logic gate that implements logical NOR - it behaves according to the truth table to theright. A HIGH output (1) results if both the inputs to the gate are LOW (0); if one or both input is HIGH (1), a LOWoutput (0) results. NOR is the result of the negation of the OR operator. It can also be seen as an AND gate with allthe inputs inverted. NOR is a functionally complete operation—NOR gates can be combined to generate any otherlogical function. By contrast, the OR operator is monotonic as it can only change LOW to HIGH but not vice versa.In most, but not all, circuit implementations, the negation comes for free—including CMOS and TTL. In such logicfamilies, OR is the more complicated operation; it may use a NOR followed by a NOT. A significant exception issome forms of the domino logic family.The original Apollo Guidance Computer used 4,100 ICs, each one containing only a single 3-input NOR gate.

24.1 Symbols

There are three symbols for NOR gates: the American (ANSI or 'military') symbol and the IEC ('European' or'rectangular') symbol, as well as the deprecated DIN symbol. For more information see Logic Gate Symbols. TheANSI symbol for the NOR gate is a standard OR gate with an inversion bubble connected.

24.2 Hardware description and pinout

NOR Gates are basic logic gates, and as such they are recognised in TTL and CMOS ICs. The standard, 4000 series,CMOS IC is the 4001, which includes four independent, two-input, NOR gates. The pinout diagram is as follows:

24.2.1 Availability

These devices are available from most semiconductor manufacturers such as Fairchild Semiconductor, Philips orTexas Instruments. These are usually available in both through-hole DIP and SOIC format. Datasheets are readilyavailable in most datasheet databases.In the popular CMOS and TTL logic families, NOR gates with up to 8 inputs are available:

• CMOS

• 4001: Quad 2-input NOR gate• 4025: Triple 3-input NOR gate

73

74 CHAPTER 24. NOR GATE

A = f0

03

0c

B = cc

30 11

C = aa

55

1c

e8 = CARRY

e2 8a

0815

61

96 = SUM

NOR Full adder

• 4002: Dual 4-input NOR gate• 4078: Single 8-input NOR gate

• TTL

• 7402: Quad 2-input NOR gate

24.3. IMPLEMENTATIONS 75

• 7427: Triple 3-input NOR gate

• 7425: Dual 4-input NOR gate (with strobe, obsolete)

• 74260: Dual 5-Input NOR Gate

• 744078: Single 8-input NOR Gate

In the older RTL and ECL families, NOR gates were efficient and most commonly used.

24.3 Implementations

The diagrams above show the construction of a 2-input NOR gate using NMOS logic circuitry. If either of the inputsare high, the corresponding N-channel MOSFET is turned on and the output is pulled low; otherwise the output ispulled high through the pull-up resistor.The diagram below shows a 2-input NOR gate using CMOS technology. The diodes and resistors on the inputs areto protect the CMOS components from damage due to electrostatic discharge (ESD) and play no part in the logicalfunction of the circuit.

Unbuffered CMOS two input NOR gate

76 CHAPTER 24. NOR GATE

24.3.1 Alternatives

If no specific NOR gates are available, one can be made from NAND gates, because NAND and NOR gates areconsidered the “universal gates”, meaning that they can be used to make all the others.[1]

24.4 See also• AND gate

• OR gate

• NOT gate

• NAND gate

• XOR gate

• XNOR gate

• Boolean algebra (logic)

• Logic gates

• NOR logic

24.5 References[1] Mano, M. Morris and Charles R. Kime. Logic and Computer Design Fundamentals, Third Edition. Prentice Hall, 2004. p.

73.

24.6 External links• Interactive NOR gate, Displays the logic simulation of the NOR Gate.

Chapter 25

NOR logic

This article is about NOR Logic in the sense of building other logic gates using just NOR gates. For NOR gates, seeNOR gate. For NOR in the purely logical sense, see Logical NOR. For logic gates in general, see Logic Gate.Like NAND gates, NOR gates are so-called “universal gates” that can be combined to form any other kind of logic

AB

Q

A single NOR gate

gate. For example, the first embedded system, Apollo Guidance Computer, was built exclusively from NOR gates,about 5,600 in total for the later versions. Today, integrated circuits are not constructed exclusively from a singletype of gate. Instead, EDA tools are used to convert the description of a logical circuit to a netlist of complex gates(standard cells) or transistors (full custom approach).

25.1 NOR

A NOR gate is logically an inverted OR gate. By itself has the following truth table:

25.2 Making other gates by using NOR gates

A NOR gate is a universal gate, meaning that any other gate can be represented as a combination of NOR gates.

25.2.1 NOT

This is made by joining the inputs of a NOR gate. As a NOR gate is equivalent to an OR gate leading to NOT gate,this automatically sees to the “OR” part of the NOR gate, eliminating it from consideration and leaving only the NOT

77

78 CHAPTER 25. NOR LOGIC

part.output= NOT(A+A)

25.2.2 OR

The OR gate is simply a NOR gate followed by another NOR gate.Output= NOT[NOT(A+B)+NOT(A+B)]

25.2.3 AND

An AND gate gives a 1 output when both inputs are 1; a NOR gate gives a 1 output only when both inputs are 0.Therefore, an AND gate is made by inverting the inputs to a NOR gate.

25.2.4 NAND

A NAND gate is made using an AND gate in series with a NOR gate:

25.2.5 XOR

An XOR gate is made by connecting the output of 3 NOR gates (connected as an AND gate) and the output of aNOR gate to the respective inputs of a NOR gate. This expresses the logical fomula (A AND B) NOR (A NOR B).This construction entails a propagation delay three times that of a single NOR gate.

25.2.6 XNOR

An XNOR gate can be constructed from four NOR gates implementing the expression "(A NOR N) NOR (B NORN) where N = A NOR B”.This construction has a propagation delay three times that of a single NOR gate, and usesmore gates.

25.3 See also• NAND Logic. Like NOR gates, NAND gates are also universal gates.

• Functional Completeness

25.4 References

Chapter 26

NOT gate

A out

Traditional NOT Gate (Inverter) symbol

1

International Electrotechnical Commission NOT Gate (Inverter) symbol

In digital logic, an inverter or NOT gate is a logic gate which implements logical negation. The truth table is shownon the right.

79

80 CHAPTER 26. NOT GATE

26.1 Electronic implementation

• NMOS inverter

• PMOS inverter

• Static CMOS inverter

• NPN transistor–transistor logic inverter

• Depletion-load NMOS logic NAND

• Saturated-load NMOS inverter

• NPN resistor–transistor logic inverter

An inverter circuit outputs a voltage representing the opposite logic-level to its input. Inverters can be constructedusing a single NMOS transistor or a single PMOS transistor coupled with a resistor. Since this 'resistive-drain' ap-proach uses only a single type of transistor, it can be fabricated at low cost. However, because current flows throughthe resistor in one of the two states, the resistive-drain configuration is disadvantaged for power consumption andprocessing speed. Alternatively, inverters can be constructed using two complementary transistors in a CMOS con-figuration. This configuration greatly reduces power consumption since one of the transistors is always off in bothlogic states. Processing speed can also be improved due to the relatively low resistance compared to the NMOS-onlyor PMOS-only type devices. Inverters can also be constructed with bipolar junction transistors (BJT) in either aresistor–transistor logic (RTL) or a transistor–transistor logic (TTL) configuration.Digital electronics circuits operate at fixed voltage levels corresponding to a logical 0 or 1 (see binary). An invertercircuit serves as the basic logic gate to swap between those two voltage levels. Implementation determines the actualvoltage, but common levels include (0, +5V) for TTL circuits.

26.1.1 Digital building block

The inverter is a basic building block in digital electronics. Multiplexers, decoders, state machines, and other sophis-ticated digital devices may use inverters.The hex inverter is an integrated circuit that contains six (hexa-) inverters. For example, the 7404 TTL chip whichhas 14 pins and the 4049 CMOS chip which has 16 pins, 2 of which are used for power/referencing, and 12 of whichare used by the inputs and outputs of the six inverters (the 4049 has 2 pins with no connection).

26.1.2 Alternatives

If no specific NOT gates are available, one can be made from NAND or NOR gates, because NAND and NOR gatesare considered the “universal gates”,[1] meaning that they can be used to make all the others.

26.1.3 Performance measurement

Digital inverter quality is often measured using the voltage transfer curve (VTC), which is a plot of output vs. inputvoltage. From such a graph, device parameters including noise tolerance, gain, and operating logic levels can beobtained.Ideally, the VTC appears as an inverted step function – this would indicate precise switching between on and off –but in real devices, a gradual transition region exists. The VTC indicates that for low input voltage, the circuit outputshigh voltage; for high input, the output tapers off towards the low level. The slope of this transition region is a measureof quality – steep (close to infinity) slopes yield precise switching.The tolerance to noise can be measured by comparing the minimum input to the maximum output for each region ofoperation (on / off).

26.1. ELECTRONIC IMPLEMENTATION 81

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2

3

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This schematic diagram shows the arrangement of NOT gates within a standard 4049 CMOS hex inverting buffer.

82 CHAPTER 26. NOT GATE

Voltage transfer curve for a 20 μm inverter constructed at North Carolina State University

26.2 See also• Controlled NOT gate

• AND gate

• OR gate

• NAND gate

• NOR gate

• XOR gate

• XNOR gate

• Boolean algebra

• Logic gate

26.3 External links• The Not Gate on All About Circuits

• CMOS Hex Inverting Buffer/Converter from Texas Instruments

• Datasheet: CMOS Hex Buffer/Converter

26.4 References[1] Mano, M. Morris and Charles R. Kime. Logic and Computer Design Fundamentals, Third Edition. Prentice Hall, 2004. p.

73.

Chapter 27

OR gate

This article is about OR in the sense of an electronic logic gate (e.g. CMOS 4071). For OR in the purely logicalsense, see Logical disjunction.

The OR gate is a digital logic gate that implements logical disjunction - it behaves according to the truth table to theright. A HIGH output (1) results if one or both the inputs to the gate are HIGH (1). If neither input is high, a LOWoutput (0) results. In another sense, the function of OR effectively finds the maximum between two binary digits, justas the complementary AND function finds the minimum.[1]

27.1 Symbols

There are two symbols of OR gates: the American (ANSI or 'military') symbol and the IEC ('European' or 'rectan-gular') symbol, as well as the deprecated DIN symbol.[2][3] For more information see Logic Gate Symbols.

27.2 Hardware description and pinout

OR Gates are basic logic gates, and as such they are available in TTL and CMOS ICs logic families. The standard4000 series CMOS IC is the 4071, which includes four independent two-input OR gates. The traditional TTL versionis the 7432. There are many offshoots of the original 7432 OR gate. All have the same pinout but different internalarchitecture, allowing them to operate in different voltage ranges and/or at higher speeds. In addition to the standard2-Input OR Gate, 3- and 4-Input OR Gates are also available. In the CMOS series, these are:

• 4075: Triple 3-Input OR Gate

• 4072: Dual 4-Input OR Gate

TTL variations include:

• 74LS32: Quad 2-input OR gate (Low power Schottky version)

• 74HC32: Quad 2-input OR gate (High Speed CMOS version) - has lower current consumption/wider Voltagerange

• 74LVC32: Low voltage CMOS version of the same.

83

84 CHAPTER 27. OR GATE

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This schematic diagram shows the arrangement of OR gates within a standard 4071 CMOS integrated circuit.

27.3. IMPLEMENTATIONS 85

27.3 Implementations

27.3.1 Alternatives

If no specific OR gates are available, one can be made from NAND or NOR gates in the configuration shown in theimage below. Any logic gate can be made from a combination of NAND or NOR gates.

27.4 Wired-OR

Wired OR gate using open-collector NOR gates

With active low open collector logic outputs, as used for control signals in many circuits, an OR function can beproduced by wiring together several outputs. This arrangement is called a wired OR. This implementation of an ORfunction typically is also found in integrated circuits of N or P-type only transistor processes.

27.5 See also• AND gate

• NOT gate

• NAND gate

• NOR gate

86 CHAPTER 27. OR GATE

• XOR gate

• XNOR gate

• Boolean algebra

• Logic gate

27.6 References[1] “OR Gate”. Hyperphysics.phy-astr.gsu.edu. Retrieved 2012-09-24.

[2] Harris, David Harris, Sarah (2007). Digital design and computer architecture (1st ed.). San Francisco,Calif.: MorganKaufmann. p. 21. ISBN 9780123704979.

[3] Brumbach, Michael E. Industrial electricity (8th ed.). Clifton Park, N.Y.: Delmar. p. 546. ISBN 9781435483743.

Chapter 28

Photochemical logic gate

A photochemical logic gate is based on the photochemical intersystem crossing and molecular electronic transitionbetween photochemically active molecules, leading to logic gates that can be produced.[1]

28.1 The OR gate electron–photon transfer chain

_A* A* = excited state of molecule A_B*_C*_A _B _CThe OR gate is based on the activation of molecule A, and thus pass electron / photon to molecule C’s excited stateorbitals ( C*). The electron from molecule A inter system crosses to C* via the excited state orbitals of B, eventuallyutilised as a signal in the C* h υc emission. The ‘OR’ gate uses two inputs of light (photons) to molecule A in twoseparate electron transfer chains, both of which are capable of transferring to C* and thus producing the output ofan OR gate. Therefore, if either electron transfer chain is activated, molecule C’s excitation produces a valid/ outputemission.Input InputA D↘↙B E↘↙Coutput

28.2 The ‘AND’ gate

_C** Second excited state of molecule C_A*_B*_C*_A _B _CExcitation A → A* by h υa photon, whereby the promoted electron is passed down to the C* molecular orbital. Asecond photon applied to the system (h υc2 ) causes the excitation of the electron in the C* molecular orbital to theC** molecular orbital -analogous pump probe spectroscopy._* * Second excited state of molecule C↑ h υc2_*

87

88 CHAPTER 28. PHOTOCHEMICAL LOGIC GATE

↑ h υc_CAbove, the energy level diagram illustrating the principle of pump probe spectroscopy –the excitation of an excitedstate. The AND gate is produced by the necessity of both A→A* and the C**→C excitations occurring at the sametime -input h υ and h υ , are simultaneously required. To prevent erroneous emissions of light from a single inputto the AND gate, it would be necessary to have an electron transfer series with ability accept any electrons (energy)from C* energy level. The electron transfer series would terminate with a low (non-radiative decay) of the energyThe alternatives for producing an AND gate, using molecular photphysics, are two. (1) The emission produced bythe electron drop from C*→ C (h υc ) is not a valid output frequency. The emission from the C** (h υc + h υc2 , hυc3 ) molecular orbital is a valid output signal;. to be used in subsequent logic gates -arranged to respond to the C**→c2 C emission. The second input of photon(s) to trigger the rapid conversion of a molecule used to complete theelectron transfer chain. A very complex molecule like a protein can be engineered to possess high strain energies, sothat in the absence of the second light frequency molecule B is inactive (B). The second photon input triggers B →B' where the forward rate constant is much smaller than the reverse. If such a molecule is used as molecule B, thetransfer chain can be switched on and off.

28.3 Creating the NOT gate

To stop the electron transfer chain completing, producing output signals, the input of a photon, h υc2 , is used toproduce a ‘pump probe spectroscopy’ effect by promoting an electron in an electron transfer chain. The fall of thepump probe promoted electron produces an output that is quenched down an electron transfer chain.An alternative is similar to the AND gate alternative; an input causes a change in molecule structure breaking theelectron transfer chain by not allowing the smooth energy transfer of electrons.

28.4 See also• Photohydrogen

• Artificial photosynthesis

• Photocatalysis

• Photodissociation

• Photoelectrolysis

• Photosynthesis

• Photochemical reaction

• Photochemistry

28.5 References[1] Karlin, Kenneth D. (2009). Progress in Inorganic Chemistry. Wiley-Interscience. p. 458. ISBN 0-470-39547-8.

Chapter 29

Pulse transition detector

A Pulse transition detector is used in flip flops in order to achieve edge triggering in the circuit. It merely convertsthe clock signal's rising edge to a very narrow pulse.The PTD consists of a delay gate (which delays the clock signal) and the clock signal itself passed through a NANDgate and then inverted.The benefit of edge triggering is that it removes the problems of zeroes and ones catching associated with pulsetriggered flipflops (e.g. master slave flip flops).

89

Chapter 30

Quantum gate

For the game, see Quantum Gate (video game).

In quantum computing and specifically the quantum circuit model of computation, a quantum gate (or quantumlogic gate) is a basic quantum circuit operating on a small number of qubits. They are the building blocks of quantumcircuits, like classical logic gates are for conventional digital circuits.Unlike many classical logic gates, quantum logic gates are reversible. However, it is possible to perform classicalcomputing using only reversible gates. For example, the reversible Toffoli gate can implement all Boolean functions.This gate has a direct quantum equivalent, showing that quantum circuits can perform all operations performed byclassical circuits.Quantum logic gates are represented by unitary matrices. The most common quantum gates operate on spaces ofone or two qubits, just like the common classical logic gates operate on one or two bits. This means that as matrices,quantum gates can be described by 2 × 2 or 4 × 4 unitary matrices.

30.1 Commonly used gates

Quantum gates are usually represented as matrices. A gate which acts on k qubits is represented by a 2k x 2k unitarymatrix. The number of qubits in the input and output of the gate have to be equal. The action of the quantum gateis found by multiplying the matrix representing the gate with the vector which represents the quantum state. In thefollowing, the vector representation of a single qubit is:

v0|0⟩+ v1|1⟩ →[v0v1

]and the vector representation of two qubits is:

v00|00⟩+ v01|01⟩+ v10|10⟩+ v11|11⟩ →

v00v01v10v11

where |ab⟩ is the state where the first qubit has value a and the second qubit b.

30.1.1 Hadamard gate

The Hadamard gate acts on a single qubit. It maps the basis state |0⟩ to |0⟩+|1⟩√2

and |1⟩ to |0⟩−|1⟩√2

and represents arotation of π about the axis (x+ z)/

√2 . It is represented by the Hadamard matrix:

90

30.1. COMMONLY USED GATES 91

Circuit representation of Hadamard gate

H =1√2

[1 11 −1

]SinceHH∗ = I where I is the identity matrix, H is indeed a unitary matrix.

30.1.2 Pauli-X gate

The Pauli-X gate acts on a single qubit. It is the quantum equivalent of a NOT gate (with respect to the standardbasis |0⟩ , |1⟩ , which privileges the Z-direction) . It equates to a rotation of the Bloch Sphere around the X-axis byπ radians. It maps |0⟩ to |1⟩ and |1⟩ to |0⟩ . It is represented by the Pauli matrix:

X =

[0 11 0

]

30.1.3 Pauli-Y gate

The Pauli-Y gate acts on a single qubit. It equates to a rotation around the Y-axis of the Bloch Sphere by π radians.It maps |0⟩ to i|1⟩ and |1⟩ to −i|0⟩ . It is represented by the Pauli Y matrix:

Y =

[0 −ii 0

]

30.1.4 Pauli-Z gate

The Pauli-Z gate acts on a single qubit. It equates to a rotation around the Z-axis of the Bloch Sphere by π radians.Thus, it is a special case of a phase shift gate (next) with θ=π. It leaves the basis state |0⟩ unchanged and maps |1⟩ to−|1⟩ . It is represented by the Pauli Z matrix:

Z =

[1 00 −1

]

92 CHAPTER 30. QUANTUM GATE

30.1.5 Phase shift gates

This is a family of single-qubit gates that leave the basis state |0⟩ unchanged and map |1⟩ to eiϕ|1⟩ . The probabilityof measuring a |0⟩ or |1⟩ is unchanged after applying this gate, however it modifies the phase of the quantum state.This is equivalent to tracing a horizontal circle (a line of latitude) on the Bloch Sphere by ϕ radians.

Rϕ =

[1 00 eiϕ

]where φ is the phase shift. Some common examples are the π

8 gate where φ = π4 , the phase gate where φ = π

2 andthe Pauli-Z gate where φ = π.

30.1.6 Swap gate

Circuit representation of SWAP gate

The swap gate swaps two qubits. With respect to the basis |00⟩ , |01⟩ , |10⟩ , |11⟩ , it is represented by the matrix:

SWAP =

1 0 0 00 0 1 00 1 0 00 0 0 1

30.1.7 Square root of Swap gate

The sqrt(swap) gate performs half-way of a two-qubit swap. It is universal such that any quantum many qubit gatecan be constructed from only sqrt(swap) and single qubit gates.

√SWAP =

1 0 0 00 1

2 (1 + i) 12 (1− i) 0

0 12 (1− i) 1

2 (1 + i) 00 0 0 1

30.1. COMMONLY USED GATES 93

Circuit representation of√SWAP gate

30.1.8 Controlled gates

Controlled gates act on 2 or more qubits, where one or more qubits act as a control for some operation. For example,the controlled NOT gate (or CNOT) acts on 2 qubits, and performs the NOT operation on the second qubit only whenthe first qubit is |1⟩ , and otherwise leaves it unchanged. It is represented by the matrix

CNOT =

1 0 0 00 1 0 00 0 0 10 0 1 0

More generally if U is a gate that operates on single qubits with matrix representation

U =

[x00 x01

x10 x11

]then the controlled-U gate is a gate that operates on two qubits in such a way that the first qubit serves as a control. Itmaps the basis states as follows.

|00⟩ 7→ |00⟩

|01⟩ 7→ |01⟩

|10⟩ 7→ |1⟩U |0⟩ = |1⟩ (x00|0⟩+ x10|1⟩)

94 CHAPTER 30. QUANTUM GATE

Circuit representation of controlled NOT gate

Circuit representation of controlled-U gate

|11⟩ 7→ |1⟩U |1⟩ = |1⟩ (x01|0⟩+ x11|1⟩)

The matrix representing the controlled U is

30.1. COMMONLY USED GATES 95

C(U) =

1 0 0 00 1 0 00 0 x00 x01

0 0 x10 x11

controlled X-, Y- and Z- gates

controlled-X gate

controlled-Y gate

controlled-Z gate

WhenU is one of the Pauli matrices, σₓ, σ , or σ , the respective terms “controlled-X", “controlled-Y", or “controlled-Z" are sometimes used.[1]

30.1.9 Toffoli gate

Main article: Toffoli gateThe Toffoli gate, also CCNOT gate, is a 3-bit gate, which is universal for classical computation. The quantum Toffoligate is the same gate, defined for 3 qubits. If the first two bits are in the state |1⟩ , it applies a Pauli-X on the thirdbit, else it does nothing. It is an example of a controlled gate. Since it is the quantum analog of a classical gate, it iscompletely specified by its truth table.It can be also described as the gate which maps |a, b, c⟩ to |a, b, c⊕ ab⟩ .

30.1.10 Fredkin gate

Main article: Fredkin gateThe Fredkin gate (also CSWAP gate) is a 3-bit gate that performs a controlled swap. It is universal for classicalcomputation. It has the useful property that the numbers of 0s and 1s are conserved throughout, which in the billiardball model means the same number of balls are output as input.

96 CHAPTER 30. QUANTUM GATE

Circuit representation of Toffoli gate

30.2 Universal quantum gates

Informally, a set of universal quantum gates is any set of gates to which any operation possible on a quantumcomputer can be reduced, that is, any other unitary operation can be expressed as a finite sequence of gates from theset. Technically, this is impossible since the number of possible quantum gates is uncountable, whereas the number offinite sequences from a finite set is countable. To solve this problem, we only require that any quantum operation canbe approximated by a sequence of gates from this finite set. Moreover, for the specific case of single qubit unitariesthe Solovay–Kitaev theorem guarantees that this can be done efficiently.One simple set of two-qubit universal quantum gates is the Hadamard gate ( H ), the π/8 gate R(π/4) , and thecontrolled NOT gate.A single-gate set of universal quantum gates can also be formulated using the three-qubit Deutsch gateD(θ) , whichperforms the transformation[2]

|a, b, c⟩ 7→

{i cos(θ)|a, b, c⟩+ sin(θ)|a, b, 1− c⟩ for a = b = 1

|a, b, c⟩ otherwise.

The universal classical logic gate, the Toffoli gate, is reducible to the Deutsch gate, D(π2 ) , thus showing that allclassical logic operations can be performed on a universal quantum computer.

30.3. HISTORY 97

Circuit representation of Fredkin gate

30.3 History

The current notation for quantum gates was developed by Barenco et al.,[3] building on notation introduced byFeynman.[4]

30.4 See also• Pauli matrices

30.5 Notes[1] M. Nielsen and I. Chuang, Quantum Computation and Quantum Information, Cambridge University Press, 2000

[2] Deutsch, David (September 8, 1989), “Quantum computational networks” (PDF), Proc. R. Soc. Lond. A 425 (1968):73–90, Bibcode:1989RSPSA.425...73D, doi:10.1098/rspa.1989.0099

[3] Phys. Rev. A 52 3457–3467 (1995), DOI:10.1103/PhysRevA.52.3457; e-print arXiv:quant-ph/9503016

98 CHAPTER 30. QUANTUM GATE

[4] R. P. Feynman, “Quantum mechanical computers”, Optics News, February 1985, 11, p. 11; reprinted in Foundations ofPhysics 16(6) 507–531

30.6 References• M. Nielsen and I. Chuang, Quantum Computation and Quantum Information, Cambridge University Press,2000

Chapter 31

Race condition

A race condition or race hazard is the behavior of an electronic, software or other system where the output isdependent on the sequence or timing of other uncontrollable events. It becomes a bug when events do not happen inthe order the programmer intended. The term originates with the idea of two signals racing each other to influencethe output first.Race conditions can occur in electronics systems, especially logic circuits, and in computer software, especiallymultithreaded or distributed programs.

31.1 Electronics

A typical example of a race condition may occur in a system of logic gates, where inputs vary. If a particular outputdepends on the state of the inputs, it may only be defined for steady-state signals. As the inputs change state, a smalldelay will occur before the output changes, due to the physical nature of the electronic system. For a brief period,the output may change to an unwanted state before settling back to the designed state. Certain systems can toleratesuch glitches, but if, for example, this output functions as a clock signal for further systems that contain memory, thesystem can rapidly depart from its designed behaviour (in effect, the temporary glitch becomes a permanent glitch).For example, consider a two input AND gate fed with a logic signal A on one input and its negation, NOT A, onanother input. In theory, the output (A AND NOT A) should never be true. However, if changes in the value of Atake longer to propagate to the second input than the first when A changes from false to true, a brief period will ensueduring which both inputs are true, and so the gate’s output will also be true.[1]

Design techniques such as Karnaugh maps encourage designers to recognize and eliminate race conditions beforethey cause problems. Often logic redundancy can be added to eliminate some kinds of races.As well as these problems, some logic elements can enter metastable states, which create further problems for circuitdesigners.

31.1.1 Critical and non-critical race conditions

A critical race occurs when the order in which internal variables are changed determines the eventual state that thestate machine will end up in.A non-critical race occurs when the order in which internal variables are changed does not alter the eventual state.In other words, a non-critical race occurs when moving to a desired state means that more than one internal statevariable must be changed at once, but no matter in what order these internal state variables change, the resultant statewill be the same.

31.1.2 Static, dynamic, and essential race conditions

Static race conditions These are caused when a signal and its complement are combined together.

99

100 CHAPTER 31. RACE CONDITION

Race condition in a logic circuit. Here, ∆t1 and ∆t2 represent the propagation delays of the logic elements. When the input value (A)changes from low to high, the circuit outputs a short spike of duration (∆t1+∆t2) - ∆t2 = ∆t1.

Dynamic race conditions These result in multiple transitions when only one is intended. They are due to interactionbetween gates (Dynamic race conditions can be eliminated by using no more than two levels of gating).

Essential race conditions These are caused when an input has two transitions in less than the total feedback prop-agation time. Sometimes they are cured using inductive delay-line elements to effectively increase the timeduration of an input signal.

31.2. SOFTWARE 101

31.2 Software

Race conditions arise in software when an application depends on the sequence or timing of processes or threads forit to operate properly. As with electronics, there are critical race conditions that result in invalid execution and bugs aswell as non-critical race-conditions that result in unanticipated behavior. Critical race conditions often happen whenthe processes or threads depend on some shared state. Operations upon shared states are critical sections that mustbe mutually exclusive. Failure to obey this rule opens up the possibility of corrupting the shared state.Race conditions have a reputation of being difficult to reproduce and debug, since the end result is nondeterministic anddepends on the relative timing between interfering threads. Problems occurring in production systems can thereforedisappear when running in debugmode, when additional logging is added, or when attaching a debugger, often referredto as a "Heisenbug". It is therefore better to avoid race conditions by careful software design rather than attemptingto fix them afterwards.

31.2.1 Example

As a simple example let us assume that two threads each want to increment the value of a global integer variable byone. Ideally, the following sequence of operations would take place:In the case shown above, the final value is 2, as expected. However, if the two threads run simultaneously withoutlocking or synchronization, the outcome of the operation could be wrong. The alternative sequence of operationsbelow demonstrates this scenario:The final value is 1 instead of the expected result of 2. This occurs because the increment operations of the secondcase are not mutually exclusive. Mutually exclusive operations are those that cannot be interrupted while accessingsome resource such as a memory location.

31.2.2 File systems

In file systems, two or more programs may “collide” in their attempts to modify or access a file, which could result indata corruption. File locking provides a commonly used solution. A more cumbersome remedy involves organizingthe system in such a way that one unique process (running a daemon or the like) has exclusive access to the file, andall other processes that need to access the data in that file do so only via interprocess communication with that oneprocess (which of course requires synchronization at the process level).A different form of race condition exists in file systems where unrelated programs may affect each other by suddenlyusing up available resources such as disk space (or memory, or processor cycles). Software not carefully designedto anticipate and handle this race situation may then become quite fragile and unpredictable. Such a risk may beoverlooked for a long time in a system that seems very reliable. But eventually enough data may accumulate or enoughother software may be added to critically destabilize many parts of a system. Probably the best known example ofthis occurred with the near loss of the Mars Rover “Spirit” not long after landing, but this is a commonly overlookedhazard in many computer systems. A solution is for software to request and reserve all the resources it will needbefore beginning a task; if this request fails then the task is postponed, avoiding the many points where failure couldhave occurred. (Alternatively, each of those points can be equipped with error handling, or the success of the entiretask can be verified afterwards, before continuing.) A more common but incorrect approach is to simply verify thatenough disk space (for example) is available before starting a task; this is not adequate because in complex systemsthe actions of other running programs can be unpredictable.

31.2.3 Networking

In networking, consider a distributed chat network like IRC, where a user who starts a channel automatically acquireschannel-operator privileges. If two users on different servers, on different ends of the same network, try to start thesame-named channel at the same time, each user’s respective server will grant channel-operator privileges to eachuser, since neither server will yet have received the other server’s signal that it has allocated that channel. (Note thatthis problem has been largely solved by various IRC server implementations.)In this case of a race condition, the concept of the “shared resource" covers the state of the network (what channelsexist, as well as what users started them and therefore have what privileges), which each server can freely change as

102 CHAPTER 31. RACE CONDITION

long as it signals the other servers on the network about the changes so that they can update their conception of the stateof the network. However, the latency across the network makes possible the kind of race condition described. In thiscase, heading off race conditions by imposing a form of control over access to the shared resource—say, appointingone server to control who holds what privileges—would mean turning the distributed network into a centralized one(at least for that one part of the network operation).Race conditions can also exist when a computer program is written with non-blocking sockets, in which case theperformance of the program can be dependent on the speed of the network link.

31.2.4 Life-critical systems

Software flaws in life-critical systems can be disastrous. Race conditions were among the flaws in the Therac-25radiation therapy machine, which led to the death of at least three patients and injuries to several more.[2]

Another example is the Energy Management System provided by GE Energy and used by Ohio-based FirstEnergyCorp (among other power facilities). A race condition existed in the alarm subsystem; when three sagging power lineswere tripped simultaneously, the condition prevented alerts from being raised to the monitoring technicians, delayingtheir awareness of the problem. This software flaw eventually led to the North American Blackout of 2003.[3] GEEnergy later developed a software patch to correct the previously undiscovered error.

31.2.5 Computer security

A specific kind of race condition involves checking for a predicate (e.g. for authentication), then acting on thepredicate, while the state can change between the time of check and the time of use. When this kind of bug exists insecurity-conscious code, a security vulnerability called a time-of-check-to-time-of-use (TOCTTOU) bug is created.

31.3 Examples outside of Computing

31.3.1 Biology

Neuroscience is demonstrating that race conditions can occur in mammal (rat) brains as well.[4][5]

31.4 See also

• Concurrency control

• Deadlock

• Synchronization (computer science)

• Linearizability

• Racetrack problem

• Call collision

31.5 References[1] Unger, S.H. (June 1995). “Hazards, Critical Races, and Metastability”. IEEE Transactions on Computers 44 (6): 754–768.

doi:10.1109/12.391185.

[2] “An Investigation of Therac-25 Accidents — I”. Courses.cs.vt.edu. Retrieved 2011-09-19.

[3] Kevin Poulsen (2004-04-07). “Tracking the blackout bug”. Securityfocus.com. Retrieved 2011-09-19.

[4] “How Brains Race to Cancel Errant Movements”. Discover Magazine blogs. 2013-08-03.

31.6. EXTERNAL LINKS 103

[5] Schmidt, Robert; Leventhal, Daniel K; Mallet, Nicolas; Chen, Fujun; Berke, Joshua D (2013). “Canceling actions involvesa race between basal ganglia pathways”. Nature Neuroscience 16 (8): 1118–24. doi:10.1038/nn.3456. PMC 3733500.PMID 23852117.

31.6 External links• Karam, G.M.; Buhr, R.J.A. (August 1990). “Starvation and Critical Race Analyzers for Ada”. IEEE Transac-tions on Software Engineering 16 (8): 829–843. doi:10.1109/32.57622.

• Fuhrer, R.M.; Lin, B.; Nowick, S.M. (27–29 Mar 1995). “Algorithms for the optimal state assignment ofasynchronous state machines”. Advanced Research in VLSI, 1995. Proceedings., 16th Conference on. pp.59–75. doi:10.1109/ARVLSI.1995.515611. ISBN 0-8186-7047-9. as PDF

• Paper "A Novel Framework for Solving the State Assignment Problem for Event-Based Specifications" byLuciano Lavagno, Cho W. Moon, Robert K. Brayton and Alberto Sangiovanni-Vincentelli

• Wheeler, David A. (7 October 2004). “Secure programmer: Prevent race conditions—Resource contentioncan be used against you”. IBM developerWorks.

• Chapter "Avoid Race Conditions" (Secure Programming for Linux and Unix HOWTO)

• Race conditions, security, and immutability in Java, with sample source code and comparison to C code, byChiral Software

• Karpov, Andrey (11 April 2009). “Interview with Dmitriy Vyukov — the author of Relacy Race Detector(RRD)". Intel Software Library Articles.

• Microsoft Support description

Chapter 32

Racetrack problem

A racetrack problem is a specific instance of a type of race condition. A racetrack problem is a flaw in a systemor process whereby the output and/or result of the process is unexpectedly and critically dependent on the sequenceor timing of other events that run in a circular pattern. Note that this problem is semantically different from a racecondition because of the circular nature of the problem.The term originates with the idea of two signals racing each other in a circular motion to influence the output first.Racetrack problems can occur in electronics systems, especially logic circuits, and in computer software, especiallymultithreaded or distributed programs.The term “Racetrack problem” was coined by a Research Engineer at Penn State University. This engineer noticedthat the problem seemed to involve a racetrack, instead of just any kind of race.

32.1 See also• Race Condition

• Concurrency control

• Deadlock

• Synchronization

• Therac-25

32.2 External links• Starvation and Critical Race Analyzers for Ada

• Paper "Algorithms for the Optimal State Assignment of Asynchronous State Machines" by Robert M. Fuhrer,Bill Lin and Steven M. Nowick

• Paper "A Novel Framework for Solving the State Assignment Problem for Event-Based Specifications" byLuciano Lavagno, Cho W. Moon, Robert K. Brayton and Alberto Sangiovanni-Vincentelli

• Article "Secure programmer: Prevent race conditions—Resource contention can be used against you" by DavidA. Wheeler

• Chapter "Avoid Race Conditions" (Secure Programming for Linux and Unix HOWTO)

• Race conditions, security, and immutability in Java, with sample source code and comparison to C code, byChiral Software

104

Chapter 33

Reconvergent fan-out

Reconvergent fan-out is a technique to make VLSI logic simulation less pessimistic.Static timing analysis tries to figure out the best and worst case time estimate for each signal as they pass through anelectronic device. Whenever a signal passes through a node, a bit of uncertainty must be added to the time required forthe signal to transit that device. These uncertain delays add up so, after passing through many devices, the worst-casetiming for a signal will could be unreasonably pessimistic.It is common for two signals to share an identical path, branch and follow different paths for a while, then convergeback to the same point to produce a result. When this happens, you can remove a fair amount of uncertainty from thetotal delay because you know that they shared a common path for a while. Even though each signal has an uncertaindelay, because their delays were identical for part of the journey (because they were in fact the same signal) the totaluncertainty can be reduced. This tightens up the worst-case estimation for the signal delay, and usually allows a smallbut important speedup of the overall device.This term is starting to be used in a more generic sense as well. Any time a signal splits into two and then reconverges,certain optimizations can be made. The term reconvergent fan-out has been used to describe similar optimizationsin graph theory and static code analysis.

33.1 See also• Fan-out

• Fan-in

33.2 External links• An example of reconvergent fan-out

105

Chapter 34

Sheffer stroke

Venn diagram of A ↑ B

In Boolean functions and propositional calculus, the Sheffer stroke, named after Henry M. Sheffer, written "|" (seevertical bar, not to be confused with "||" which is often used to represent disjunction), “Dpq", or "↑" (an upwardsarrow), denotes a logical operation that is equivalent to the negation of the conjunction operation, expressed in ordinarylanguage as “not both”. It is also called nand (“not and”) or the alternative denial, since it says in effect that at leastone of its operands is false. In Boolean algebra and digital electronics it is known as the NAND operation.Like its dual, the NOR operator (also known as the Peirce arrow or Quine dagger), NAND can be used by itself,without any other logical operator, to constitute a logical formal system (making NAND functionally complete). Thisproperty makes the NAND gate crucial to modern digital electronics, including its use in NAND flash memory andcomputer processor design.

106

34.1. DEFINITION 107

34.1 Definition

The NAND operation is a logical operation on two logical values. It produces a value of true, if — and only if — atleast one of the propositions is false.

34.1.1 Truth table

The truth table of A NAND B (also written as A | B, Dpq, or A ↑ B) is as follows:

34.2 History

The stroke is named after Henry M. Sheffer, who in 1913 published a paper in the Transactions of the AmericanMathematical Society (Sheffer 1913) providing an axiomatization of Boolean algebras using the stroke, and provedits equivalence to a standard formulation thereof by Huntington employing the familiar operators of propositionallogic (and, or, not). Because of self-duality of Boolean algebras, Sheffer’s axioms are equally valid for either of theNAND or NOR operations in place of the stroke. Sheffer interpreted the stroke as a sign for non-disjunction (NOR)in his paper, mentioning non-conjunction only in a footnote and without a special sign for it. It was Jean Nicod whofirst used the stroke as a sign for non-conjunction (NAND) in a paper of 1917 and which has since become currentpractice.[1] Russell and Whitehead used the Sheffer stroke in the 1927 second edition of Principia Mathematica andsuggested it as a replacement for the “or” and “not” operations of the first edition.Charles Sanders Peirce (1880) had discovered the functional completeness of NAND or NOR more than 30 yearsearlier, using the term ampheck (for 'cutting both ways’), but he never published his finding.

34.3 Properties

NAND does not possess any of the following five properties, each of which is required to be absent from, and theabsence of all of which is sufficient for, at least one member of a set of functionally complete operators: truth-preservation, falsity-preservation, linearity, monotonicity, self-duality. (An operator is truth- (falsity-) preservingif its value is truth (falsity) whenever all of its arguments are truth (falsity).) Therefore {NAND} is a functionallycomplete set.This can also be realized as follows: All three elements of the functionally complete set {AND, OR, NOT} can beconstructed using only NAND. Thus the set {NAND} must be functionally complete as well.

34.4 Introduction, elimination, and equivalencies

The Sheffer stroke ↑ is the negation of the conjunction:Expressed in terms of NAND ↑ , the usual operators of propositional logic are:

34.5 Formal system based on the Sheffer stroke

The following is an example of a formal system based entirely on the Sheffer stroke, yet having the functional ex-pressiveness of the propositional logic:

34.5.1 Symbols

pn for natural numbers n( | )The Sheffer stroke commutes but does not associate (e.g., (T|T)|F = T, but T|(T|F) = F). Hence any formal systemincluding the Sheffer stroke must also include a means of indicating grouping. We shall employ '(' and ')' to this effect.

108 CHAPTER 34. SHEFFER STROKE

We also write p, q, r, … instead of p0, p1, p2.

34.5.2 Syntax

Construction Rule I: For each natural number n, the symbol pn is a well-formed formula (wff), called an atom.Construction Rule II: If X and Y are wffs, then (X|Y) is a wff.Closure Rule: Any formulae which cannot be constructed by means of the first two Construction Rules are not wffs.The letters U, V,W, X, and Y are metavariables standing for wffs.A decision procedure for determining whether a formula is well-formed goes as follows: “deconstruct” the formulaby applying the Construction Rules backwards, thereby breaking the formula into smaller subformulae. Then repeatthis recursive deconstruction process to each of the subformulae. Eventually the formula should be reduced to itsatoms, but if some subformula cannot be so reduced, then the formula is not a wff.

34.5.3 Calculus

All wffs of the form

((U |(V |W))|((Y |(Y |Y))|((X|V)|((U |X)|(U |X)))))

are axioms. Instances of

(U |(V |W)), U ⊢W

are inference rules.

34.5.4 Simplification

Since the only connective of this logic is |, the symbol | could be discarded altogether, leaving only the parentheses togroup the letters. A pair of parentheses must always enclose a pair of wffs. Examples of theorems in this simplifiednotation are

(p(p(q(q((pq)(pq)))))),

(p(p((qq)(pp)))).

The notation can be simplified further, by letting

(U) := (UU)((U)) ≡ U

for any U. This simplification causes the need to change some rules:

1. More than two letters are allowed within parentheses.

2. Letters or wffs within parentheses are allowed to commute.

3. Repeated letters or wffs within a same set of parentheses can be eliminated.

The result is a parenthetical version of the Peirce existential graphs.Another way to simplify the notation is to eliminate parenthesis by using Polish Notation. For example, the earlierexamples with only parenthesis could be rewritten using only strokes as follows

34.6. SEE ALSO 109

(p(p(q(q((pq)(pq)))))) becomes|p|p|q|q||pq|pq, and

(p(p((qq)(pp)))) becomes,

: |p|p||qq|pp.This follows the same rules as the parenthesis version, with opening parenthesis replaced with a Sheffer stroke andthe (redundant) closing parenthesis removed.

34.6 See also

• List of logic symbols

• AND gate

• Boolean domain

• CMOS

• Gate equivalent (GE)

• Laws of Form

• Logic gate

• Logical graph

• NAND Flash Memory

• NAND logic

• NAND gate

• NOR gate

• NOT gate

• OR gate

• Peirce’s law

• Peirce arrow = NOR

• Propositional logic

• Sole sufficient operator

• XOR gate

• Peirce arrow

34.7 Notes

[1] Church (1956:134)

110 CHAPTER 34. SHEFFER STROKE

34.8 References• Bocheński, Józef Maria (1960), Précis of Mathematical Logic, translated from the French and German editionsby Otto Bird, Dordrecht, South Holland: D. Reidel.

• Church, Alonzo, (1956) Introduction to mathematical logic, Vol. 1, Princeton: Princeton University Press.

• Nicod, Jean G. P. (1917). “A Reduction in the Number of Primitive Propositions of Logic”. Proceedings ofthe Cambridge Philosophical Society 19: 32–41.

• Charles Sanders Peirce, 1880, “A Boolian[sic] Algebra with One Constant”, in Hartshorne, C. and Weiss, P.,eds., (1931–35) Collected Papers of Charles Sanders Peirce, Vol. 4: 12–20, Cambridge: Harvard UniversityPress.

• Sheffer, H. M. (1913), “A set of five independent postulates for Boolean algebras, with application to logicalconstants”, Transactions of the American Mathematical Society 14: 481–488, doi:10.2307/1988701, JSTOR1988701

34.9 External links• http://hyperphysics.phy-astr.gsu.edu/hbase/electronic/nand.html

• implementations of 2 and 4-input NAND gates

• Proofs of some axioms by Stroke function by Yasuo Setô @ Project Euclid

Chapter 35

Shift register lookup table

A shift register lookup table, also shift register LUT or SRL, refers to a component in digital circuitry. It isessentially a shift register of variable length. The length of SRL is set by driving address pins high or low and can bechanged dynamically, if necessary.[1]

The SRL component is used in FPGA devices. The SRL can be used as a programmable delay element.

35.1 See also• Lookup table

• Shift register

35.2 References[2]

[1] 16-Bit Shift Register Look-Up-Table (LUT)

[2] Application note from Xilinx http://www.xilinx.com/support/documentation/application_notes/xapp465.pdf

111

112 CHAPTER 35. SHIFT REGISTER LOOKUP TABLE

QD

A0A1A2A3

CLK

Shift register lookup table.

Chapter 36

Standard cell

A rendering of a small standard cell with three metal layers (dielectric has been removed). The sand-colored structures are metalinterconnect, with the vertical pillars being contacts, typically plugs of tungsten. The reddish structures are polysilicon gates, and thesolid at the bottom is the crystalline silicon bulk.

113

114 CHAPTER 36. STANDARD CELL

For the batteries used as a voltage reference (laboratory standard), see Weston cell and Clark cell.

In semiconductor design, standard cellmethodology is a method of designing application-specific integrated circuits(ASICs) with mostly digital-logic features. Standard cell methodology is an example of design abstraction, wherebya low-level very-large-scale integration (VLSI) layout is encapsulated into an abstract logic representation (such as aNAND gate). Cell-based methodology — the general class to which standard cells belong — makes it possible forone designer to focus on the high-level (logical function) aspect of digital design, while another designer focuses on theimplementation (physical) aspect. Along with semiconductor manufacturing advances, standard cell methodology hashelped designers scale ASICs from comparatively simple single-function ICs (of several thousand gates), to complexmulti-million gate system-on-a-chip (SoC) devices.

36.1 Construction of a standard cell

A standard cell is a group of transistor and interconnect structures that provides a boolean logic function (e.g., AND,OR, XOR, XNOR, inverters) or a storage function (flipflop or latch). The simplest cells are direct representations ofthe elemental NAND, NOR, and XOR boolean function, although cells of much greater complexity are commonlyused (such as a 2-bit full-adder, or muxed D-input flipflop.) The cell’s boolean logic function is called its logical view:functional behavior is captured in the form of a truth table or Boolean algebra equation (for combinational logic), ora state transition table (for sequential logic).Usually, the initial design of a standard cell is developed at the transistor level, in the form of a transistor netlist orschematic view. The netlist is a nodal description of transistors, of their connections to each other, and of their termi-nals (ports) to the external environment. A schematic view may be generated with a number of different ComputerAided Design (CAD) or Electronic Design Automation(EDA) programs that provide a Graphical User Interface(GUI) for this netlist generation process. Designers use additional CAD programs such as SPICE or Spectre tosimulate the electronic behavior of the netlist, by declaring input stimulus (voltage or current waveforms) and thencalculating the circuit’s time domain (analogue) response. The simulations verify whether the netlist implements thedesired function and predict other pertinent parameters, such as power consumption or signal propagation delay.Since the logical and netlist views are only useful for abstract (algebraic) simulation, and not device fabrication, thephysical representation of the standard cell must be designed too. Also called the layout view, this is the lowest levelof design abstraction in common design practice. From a manufacturing perspective, the standard cell’s VLSI layoutis the most important view, as it is closest to an actual “manufacturing blueprint” of the standard cell. The layoutis organized into base layers, which correspond to the different structures of the transistor devices, and interconnectwiring layers and via layers, which join together the terminals of the transistor formations. The interconnect wiringlayers are usually numbered and have specific via layers representing specific connections between each sequentiallayer. Non-manufacturing layers may be also be present in a layout for purposes of Design Automation, but manylayers used explicitly for Place and route (PNR) CAD programs are often included in a separate but similar abstractview. The abstract view often contains much less information than the layout and may be recognizable as a LayoutExtraction Format (LEF) file or an equivalent.After a layout is created, additional CAD tools are often used to perform a number of common validations. ADesign Rule Check (DRC) is done to verify that the design meets foundry and other layout requirements. A ParasiticEXtraction (PEX) then is performed to generate a PEX-netlist with parasitic properties from the layout. The nodalconnections of that netlist are then compared to those of the schematic netlist with a Layout Vs Schematic (LVS)procedure to verify that the connectivity models are equivalent.The PEX-netlist may then be simulated again (since it contains parasitic properties) to achieve more accurate timing,power, and noise models. These models are often characterized (contained) in a Synopsys Liberty format, but otherVerilog formats may be used as well.Finally, powerful Place and Route (PNR) tools may be used to pull everything together and synthesize (generate) VeryLarge Scale Integration (VLSI) layouts, in an automated fashion, from higher level design netlists and floor-plans.Additionally, a number of other CAD tools may be used to validate other aspects of the cell views and models. Andother files may be created to support various tools that utilize the standard cells for a plethora of other reasons. All ofthese files that are created to support the use of all of the standard cell variations are collectively known as a standardcell library.For a typical Boolean function, there are many different functionally equivalent transistor netlists. Likewise, for a

36.2. LIBRARY 115

typical netlist, there are many different layouts that fit the netlist’s performance parameters. The designer’s challengeis to minimize the manufacturing cost of the standard cell’s layout (generally by minimizing the circuit’s die area),while still meeting the cell’s speed and power performance requirements. Consequently, integrated circuit layout is ahighly labor-intensive job, despite the existence of design tools to aid this process.

36.2 Library

A standard cell library is a collection of low-level electronic logic functions such as AND, OR, INVERT, flip-flops,latches, and buffers. These cells are realized as fixed-height, variable-width full-custom cells. The key aspect withthese libraries is that they are of a fixed height, which enables them to be placed in rows, easing the process ofautomated digital layout. The cells are typically optimized full-custom layouts, which minimize delays and area.A typical standard-cell library contains two main components:

1. Library Database - Consists of a number of views often including layout, schematic, symbol, abstract, and otherlogical or simulation views. From this, various information may be captured in a number of formats includingthe Cadence LEF format, and the Synopsys Milkyway format, which contain reduced information about thecell layouts, sufficient for automated “Place and Route” tools.

2. Timing Abstract - Generally in Liberty format, to provide functional definitions, timing, power, and noiseinformation for each cell.

A standard-cell library may also contain the following additional components:

• A full layout of the cells

• Spice models of the cells

• Verilog models or VHDL-VITAL models

• Parasitic Extraction models

• DRC rule decks

An example is a simple XOR logic gate, which can be formed from OR, INVERT and AND gates.

36.3 Application of standard cell

Strictly speaking, a 2-input NAND or NOR function is sufficient to form any arbitrary Boolean function set. Butin modern ASIC design, standard-cell methodology is practiced with a sizable library (or libraries) of cells. Thelibrary usually contains multiple implementations of the same logic function, differing in area and speed. This varietyenhances the efficiency of automated synthesis, place, and route (SPR) tools. Indirectly, it also gives the designergreater freedom to perform implementation trade-offs (area vs. speed vs. power consumption). A complete groupof standard-cell descriptions is commonly called a technology library.Commercially available Electronic DesignAutomation (EDA) tools use the technology libraries to automate synthesis,placement, and routing of a digital ASIC. The technology library is developed and distributed by the foundry operator.The library (along with a design netlist format) is the basis for exchanging design information between different phasesof the SPR process.

36.3.1 Synthesis

Using the technology library’s cell logical view, the Logic Synthesis tool performs the process of mathematicallytransforming the ASIC’s register-transfer level (RTL) description into a technology-dependent netlist. This processis analogous to a software compiler converting a high-level C-program listing into a processor-dependent assembly-language listing.

116 CHAPTER 36. STANDARD CELL

The netlist is the standard-cell representation of the ASIC design, at the logical view level. It consists of instances ofthe standard-cell library gates, and port connectivity between gates. Proper synthesis techniques ensure mathematicalequivalency between the synthesized netlist and original RTL description. The netlist contains no unmapped RTLstatements and declarations.The high-level synthesis tool performs the process of transforming the C-level models (SystemC, ANSI C/C++)description into a technology-dependent netlist.

36.3.2 Placement

The placement tool starts the physical implementation of the ASIC. With a 2-D floorplan provided by the ASICdesigner, the placer tool assigns locations for each gate in the netlist. The resulting placed gates netlist contains thephysical location of each of the netlist’s standard-cells, but retains an abstract description of how the gates’ terminalsare wired to each other.Typically the standard cells have a constant size in at least one dimension that allows them to be lined up in rows onthe integrated circuit. The chip will consist of a huge number of rows (with power and ground running next to eachrow) with each row filled with the various cells making up the actual design. Placers obey certain rules: Each gate isassigned a unique (exclusive) location on the die map. A given gate is placed once, and may not occupy or overlapthe location of any other gate.

36.4 Routing

Using the placed-gates netlist and the layout view of the library, the router adds both signal connect lines and powersupply lines. The fully routed physical netlist contains the listing of gates from synthesis, the placement of each gatefrom placement, and the drawn interconnects from routing.

36.4.1 DRC/LVS

Simulated lithographic and other fabrication defects visible in a small standard cell.

Design Rule Check (DRC) and Layout Versus Schematic (LVS) are verification processes. Reliable device fabricationat modern deep-submicrometer (0.13 µm and below) requires strict observance of transistor spacing, metal layerthickness, and power density rules. DRC exhaustively compares the physical netlist against a set of “foundry designrules” (from the foundry operator), then flags any observed violations.

36.5. OTHER CELL-BASED METHODOLOGIES 117

The LVS process confirms that the layout has the same structure as the associated schematic; this is typically the finalstep in the layout process. The LVS tool takes as an input a schematic diagram and the extracted view from a layout.It then generates a netlist from each one and compares them. Nodes, ports, and device sizing are all compared. Ifthey are the same, LVS passes and the designer can continue. LVS tends to consider transistor fingers to be the sameas an extra-wide transistor. Thus, 4 transistors (each 1 μm wide) in parallel, a 4-finger 1 μm transistor, or a 4 μmtransistor are viewed the same by the LVS tool. Functionality of .lib files will be taken from SPICE models and addedas an attribute to the .lib file.

36.5 Other cell-based methodologies

“Standard cell” falls into a more general class of design automation flows called cell-based design. Structured ASICs,FPGAs, and CPLDs are variations on cell-based design. From the designer’s standpoint, all share the same inputfront end: an RTL description of the design. The three techniques, however, differ substantially in the details of theSPR flow (Synthesize, Place-and-Route) and physical implementation.

36.6 Complexity measure

For digital standard cell designs, for instance in CMOS, a common technology-independent metric for complexitymeasure is gate equivalents (GE).

36.7 See also• Integrated Circuits

• Circuit Design

• Semiconductor

• Very-large-scale integration (VLSI)

36.8 External links• VLSI Technology— This site contains support material for a book that Graham Petley is writing, The Art ofStandard Cell Library Design

• Oklahoma State University— This site contains support material for a complete System on Chip standard celllibrary that utilizes public-domain and Mentor Graphics/Synopsys/Cadence Design System tools

The standard cell areas in a CBIC are build-up of rows of standard cells, like a wall built-up of bricks

• Virginia Tech— This is a standard cell library developed by the Virginia Technology VLSI for Telecommuni-cations (VTVT)

• ChipX - Interesting overview of Standard Cell as well as metal layer configurable chip options.

Low Power Standard Cell Design

Chapter 37

Toffoli gate

Circuit representation of Toffoli gate

In logic circuits, the Toffoli gate (also CCNOT gate), invented by Tommaso Toffoli, is a universal reversible logicgate, which means that any reversible circuit can be constructed from Toffoli gates. It is also known as the “controlled-controlled-not” gate, which describes its action. It has 3-bit inputs and outputs; if the first two bits are set, it invertsthe third bit, otherwise all bits stay the same.

118

37.1. BACKGROUND 119

37.1 Background

A logic gate L is reversible if, for any output y, there is a unique input x such that applying L(x) = y. If a gate Lis reversible, there is an inverse gate L′ which maps y to x for which L′(y) = x. From common logic gates, NOT isreversible, as can be seen from its truthtable below.The common AND gate is not reversible however. The inputs 00, 01 and 10 are all mapped to the output 0.Reversible gates have been studied since the 1960s. The original motivation was that reversible gates dissipate lessheat (or, in principle, no heat). In a normal gate, input states are lost, since less information is present in the outputthan was present at the input. This loss of information loses energy to the surrounding area as heat, because ofthermodynamic entropy. Another way to understand this is that charges on a circuit are grounded and thus flow away,taking a small quantity of energy with them when they change state. A reversible gate only moves the states around,and since no information is lost, energy is conserved.More recent motivation comes from quantum computing. Quantum mechanics requires the transformations to bereversible but allows more general states of the computation (superpositions). Thus, the reversible gates form asubset of gates allowed by quantum mechanics and, if we can compute something reversibly, we can also compute iton a quantum computer.

37.2 Universality and Toffoli gate

Any reversible gate must have the same number of input and output bits, by the pigeonhole principle. For one inputbit, there are two possible reversible gates. One of them is NOT. The other is the identity gate which maps its inputto the output unchanged. For two input bits, the only non-trivial gate is the controlled NOT gate which XORs thefirst bit to the second bit and leaves the first bit unchanged.Unfortunately, there are reversible functions that cannot be computed using just those gates. In other words, the setconsisting of NOT and XOR gates is not universal. If we want to compute an arbitrary function using reversible gates,we need another gate. One possibility is the Toffoli gate, proposed in 1980 by Toffoli.[1]

This gate has 3-bit inputs and outputs. If the first two bits are set, it flips the third bit. The following is a table of theinput and output bits:It can be also described as mapping bits a, b and c to a, b and c XOR (a AND b).The Toffoli gate is universal; this means that for any Boolean function f(x1, x2, ..., xm), there is a circuit consistingof Toffoli gates which takes x1, x2, ..., xm and some extra bits set to 0 or 1 and outputs x1, x2, ..., xm, f(x1, x2, ...,xm), and some extra bits (called garbage). Essentially, this means that one can use Toffoli gates to build systems thatwill perform any desired Boolean function computation in a reversible manner.

37.3 Related logic gates

• The Fredkin gate is a reversible 3-bit gate that swaps the last two bits if the first bit is 1; a controlled-swapoperation.

• The n-bit Toffoli gate is a generalization of Toffoli gate. It takes n bits x1, x2, ..., xn as inputs and outputs nbits. The first n−1 output bits are just x1, ..., xn₋₁. The last output bit is (x1 AND ... AND xn₋₁) XOR xn.

• The Toffoli gate can be realized by five two-qubit quantum gates.[2]

• This gate is one of the reversible-gate cases that can be modeled with billiard balls (see Billiard-ball computer).The billiard ball modeling was introduced by Fredkin and Toffoli.[3] An example of how the collisions are usedto model an electronic gate is shown in the figure.

120 CHAPTER 37. TOFFOLI GATE

Fredkin & Toffoli billiard ball model for gates

37.4 Relation to quantum computing

Any reversible gate can be implemented on a quantum computer, and hence the Toffoli gate is also a quantum operator.However, the Toffoli gate can not be used for universal quantum computation, though it does mean that a quantumcomputer can implement all possible classical computations. The Toffoli gate has to be implemented along with someinherently quantum gate(s) in order to be universal for quantum computation. In fact, any single-qubit gate with realcoefficients that can create a nontrivial quantum state suffices.[4] A quantum mechanics-based Toffoli gate has beensuccessfully realized in January 2009 at the University of Innsbruck, Austria.[5]

37.5 See also• Fredkin gate

• Reversible computing

• Quantum computing

• Quantum gate

• Quantum programming

37.6 References[1] Technical Report MIT/LCS/TM-151 (1980) and an adapted and condensed version: Toffoli, Tommaso (1980). J. W. de

Bakker and J. van Leeuwen, ed. Reversible computing (PDF). Automata, Languages and Programming, Seventh Collo-quium. Noordwijkerhout, Netherlands: Springer Verlag. pp. 632–644. doi:10.1007/3-540-10003-2_104. ISBN 3-540-10003-2.

[2] Barenco, Adriano; Bennett, Charles H.; Cleve, Richard; DiVincenzo, David P.; Margolus, Norman; Shor, Peter; Sleator,Tycho; Smolin, John A.; Weinfurter, Harald (Nov 1995). “Elementary gates for quantum computation”. Phys. Rev. A(American Physical Society) 52 (5): 3457–3467. arXiv:quant-ph/9503016. Bibcode:1995PhRvA..52.3457B. doi:10.1103/PhysRevA.52.3457.PMID 9912645.

[3] Fredkin, Edward; Toffoli, Tommaso (April 1982). “Conservative logic” (PDF). International Journal of Theoretical Physics(Springer Netherlands) 21 (3): 219–253. Bibcode:1982IJTP...21..219F. doi:10.1007/BF01857727. ISSN 0020-7748.

[4] Shi, Yaoyun (Jan 2003). Quantum Information & Computation 3 (1): 84–92. arXiv:quant-ph/0205115. Missing or empty|title= (help)

37.6. REFERENCES 121

[5] Monz, T.; Kim, K.; Hänsel, W.; Riebe, M.; Villar, A. S.; Schindler, P.; Chwalla, M.; Hennrich, M.; Blatt, R. (Jan2009). “Realization of the Quantum Toffoli Gate with Trapped Ions”. R. (American Physical Society) 102 (4): 040501.arXiv:0804.0082. Bibcode:2009PhRvL.102d0501M. doi:10.1103/PhysRevLett.102.040501.

Chapter 38

Transmission gate

A transmission gate is similar to a relay that can conduct in both directions or block by a control signal with almostany voltage potential.

38.1 Structure

In principle, a transmission gate made up of two field effect transistors, in which - in contrast to traditional discretefield effect transistors - the substrate terminal (Bulk) is not connected internally to the source terminal. The twotransistors, an n-channel MOSFET and a p-channel MOSFET are connected in parallel with this, however, only thedrain and source terminals of the two transistors are connected together. Their gate terminals are connected to eachother via a NOT gate (inverter), to form the control terminal.As with discrete transistors, the substrate terminal is connected to the source connection, so there is a transistorto the parallel diode (body diode), whereby the transistor passes backwards. However, since a transmission gatemust block flow in either direction, the substrate terminals are connected to the respective supply voltage potentialin order to ensure that the substrate diode is always operated in the reverse direction. The substrate terminal ofthe p-channel MOSFET is thus connected to the positive supply voltage potential and the substrate terminal of then-channel MOSFET connected to the negative supply voltage potential.

38.2 Function

When the control input is a logic zero (negative power supply potential), the gate of the n-channel MOSFET is alsoat a negative supply voltage potential. The gate terminal of the p-channel MOSFET is caused by the inverter, tothe positive supply voltage potential. Regardless of on which switching terminal of the transmission gate (A or B)a voltage is applied (within the permissible range), the gate-source voltage of the n-channel MOSFETs is alwaysnegative, and the p-channel MOSFETs is always positive. Accordingly, neither of the two transistors will conductand the transmission gate turns off.When the control input is a logic one, so the gate terminal of the n-channel MOSFETs is located at a positive supplyvoltage potential. By the inverter, the gate terminal of the p-channel MOSFETs is now at a negative supply voltagepotential. As the substrate terminal of the transistors is not connected to the source terminal, the drain and sourceterminals are almost equal and the transistors start at a voltage difference between the gate terminal and one of theseconducts.One of the switching terminals of the transmission gate is raised to a voltage near the negative supply voltage, apositive gate-source voltage (gate-to-drain voltage) will occur at the N-channel MOSFET, and the transistor beginsto conduct, and the transmission gate conducts. The voltage at one of the switching terminals of the transmission gateis now raised continuously up to the positive supply voltage potential, so the gate-source voltage is reduced (gate-drain voltage) on the n-channel MOSFET, and this begins to turn off. At the same time, the p-channel MOSFEThas a negative gate-source voltage (gate-to-drain voltage) builds up, whereby this transistor starts to conduct and thetransmission gate switches.Thereby it is achieved that the transmission gate passes over the entire voltage range. The transition resistance of

122

38.3. APPLICATIONS 123

UA UB

Vneg

ST

Vpos

QN

QP

Principle diagram of a transmission gate. The control input ST must be able to take to control depending on the supply voltage andswitching voltage different logic levels.

the transmission gate varies depending upon the voltage to be switched, and corresponds to a superposition of theresistance curves of the two transistors.

38.3 Applications

38.3.1 Electronic switch

Main article: Electronic switch

Transmission gates are used in order to realize electronic switches and analog multiplexers. If a signal is connectedto different outputs (changeover switches, multiplexers), multiple transmission gates can be used as a transmissiongate to either conduct or block (simple switch). A typical example is known as the 4066 4-way analog switch whichis available from various manufacturers.[1]

analog multiplexer

Many mixed-signal systems use an analog multiplexer to route several analog input channels to a single ADC. [2][3][4]

124 CHAPTER 38. TRANSMISSION GATE

U1,VDDVTHNVTHPVSS

r ON

r ON Gesamt

r ON p-Kanal

r ON n-Kanal

U2

Resistance characteristic of a transmission gate. VTHN and VTHP denote those positions at which the voltage to be switched hasreached a potential, where the threshold voltage of the respective transistor is reached.

38.3.2 Logic circuits

Main article: pass transistor logic

Logic circuits are constructed with the aid of transmission gates. Usually can be smaller in comparison to traditionaltransistorised logic circuits, and thus saves space on the silicon.

38.3.3 Negative voltages

By using a transmission gate to switch alternating voltages (e.g.: audio signal), the negative power supply potentialmust be lower than the lowest signal potential. This ensures that the substrate diode will remain locked even atnegative voltages. Although the transmission gate can still switch to logic voltage levels, there are special versionswith integrated level shifters.

38.4 See also

Tri-state logic

38.5 References

Article Google-Translated from German Wikipedia. English article was deleted 2013 due to copyright.

• Ulrich Tietze, Christoph Schenk: Halbleiter-Schaltungstechnik. 12. Auflage, Springer, Berlin/Heidelberg/NewYork 2002, ISBN 3-540-42849-6.

• Erwin Böhmer: Elemente der angewandten Elektronik. 15. Auflage, Vieweg & Sohn Verlag | GWV Fachver-lage GmbH, Wiesbaden 2007, ISBN 978-3-8348-0124-1.

• Klaus Fricke: Digitaltechnik. 6. Auflage, Vieweg & Sohn Verlag | GWV Fachverlage GmbH, Wiesbaden2009, ISBN 978-3-8348-0459-4.

[1] 4066 Datenblätter

38.5. REFERENCES 125

[2] Franco Zappa. “Electronic Systems”. Section 6.9: Analog Multiplexers.

[3] John G. Webster. “Electrical Measurement, Signal Processing, and Displays”. 2003. p. 36-12.

[4] Robert A. Pease. “Troubleshooting Analog Circuits”. 2013. p. 132.

Chapter 39

Tseitin transformation

The Tseitin transformation takes as input an arbitrary combinatorial logic circuit and produces a boolean formulain conjunctive normal form (CNF), which can be solved by a CNF-SAT solver. The length of the formula is linear inthe size of the circuit. Input vectors that make the circuit output “true” are in 1-to-1 correspondence with assignmentsthat satisfy the formula. This reduces the problem of circuit satisfiability on any circuit (including any formula) tothe satisfiability problem on 3-CNF formulas.

39.1 Motivation

The naive approach is to write the circuit as a Boolean expression, and use De Morgan’s law and the distributiveproperty to convert it to CNF. However, this can result in an exponential increase in equation size. The Tseitintransformation outputs a formula whose size has grown linearly relative to the input circuit’s.

39.2 Approach

The output equation is the constant 1 set equal to an expression. This expression is a conjunction of sub-expressions,where the satisfaction of each sub-expression enforces the proper operation of a single gate in the input circuit. Thesatisfaction of the entire output expression thus enforces that the entire input circuit is operating properly.For each gate, a new variable representing its output is introduced. A small pre-calculated CNF expression that relatesthe inputs and outputs is appended (via the “and” operation) to the output expression. Note that inputs to these gatescan be either the original literals or the introduced variables representing outputs of sub-gates.Though the output expression contains more variables than the input, it remains equisatisfiable, meaning that it issatisfiable if, and only if, the original input equation is satisfiable. When a satisfying assignment of variables is found,those assignments for the introduced variables can simply be discarded.A final clause is appended with a single literal: the final gate’s output variable. If this literal is complemented, thenthe satisfaction of this clause enforces the output expression’s to false; otherwise the expression is forced true.

39.3 Gate Sub-expressions

Listed is some of the possible sub-expressions that can be created for various logic gates.

126

39.4. EXAMPLES 127

39.4 Examples

39.5 Simple combinatorial logic

The following circuit returns true when at least some of its inputs are true, but not more than two at a time. Itimplements the equation y = x1 · x2+ x1 · x2+ x2 · x3 . A variable is introduced for each gates’ output; here eachis marked in red:

Notice that the output of the inverter with x2 as an input has two variables introduced. While this is redundant, itdoes not affect the equisatisfiability of the resulting equation. Now substitute each gate with its appropriate CNFsub-expression:

The final output variable is gate8 so to enforce that the output of this circuit be true, one final simple clause is ap-pended: (gate8) . Combining these equations results in the final instance of SAT:

One possible satisfying assignment of these variables is:The values of the introduced values are usually discarded, but they can be used to trace the logic path in the originalcircuit. Here, (x1, x2, x3) = (0, 0, 1) indeed meets the criteria for the original circuit to output true. To find adifferent answer, the clause (x1 ∨ x2 ∨ x3) can be appended and the SAT solver executed again.

39.6 Derivation

Presented is one possible derivation of the CNF sub-expression for some chosen gates:

39.6.1 OR Gate

The OR gate is operating properly when the following conditions hold:

1. if the output C is true, then one (or both) of its inputs A, B is true

2. if the output C is false, then both its inputs A, B are false

express these conditions as an expression that must be satisfied:(C → (A ∨B)) ∧ (C → (A ∧B))convert the implications to AND’s and OR’s(C ∨ (A ∨B)) ∧ (C ∨ (A ∧B))it’s nearly CNF already; distribute the rightmost clause twice(C ∨A ∨B) ∧ ((C ∨A) ∧ (C ∨B))associativity of conjunction(C ∨A ∨B) ∧ (C ∨A) ∧ (C ∨B)

128 CHAPTER 39. TSEITIN TRANSFORMATION

39.6.2 NOT Gate

The NOT gate is operating properly when its input and output oppose each other. That is:

1. if the output C is true, the input A is false

2. if the output C is false, the input A is true

express these conditions as an expression that must be satisfied:(C → A) ∧ (C → A)(C ∨A) ∧ (C ∨A)

39.6.3 NOR Gate

The NOR gate is operating properly when the following conditions hold:

1. if the output C is true, then neither A or B are true

2. if the output C is false, then at least one of A and B were true

express these conditions as an expression that must be satisfied:(C → (A ∨B)) ∧ (C → (A ∨B))

(C ∨ (A ∧B)) ∧ (C ∨A ∨B))(C ∧ (A ∨B)) ∧ (C ∨A ∨B))(A ∧ C) ∨ (A ∨B) ∧ (C ∨A ∨B))(A ∨ C) ∧ (A ∧B) ∧ (C ∨A ∨B))

39.7 References• G.S. Tseitin: On the complexity of derivation in propositional calculus. In: Slisenko, A.O. (ed.) Studies inConstructive Mathematics and Mathematical Logic, Part II, Seminars in Mathematics, pp. 115–125. SteklovMathematical Institute (1970). Translated from Russian: Zapiski Nauchnykh Seminarov LOMI 8 (1968), pp.234–259.

Chapter 40

Wired logic connection

VIL

VIL

COMMONINTERCONNECTION

MODE

V

TOLOAD

RL

ION

Open Collector AND gate

Awired logic connection is a logic gate that implements boolean algebra (logic) using only passive components suchas diodes and resistors. A wired logic connection can create an AND or an OR gate. The limitations are the inabilityto create a NOT gate and the lack of level restoration.

40.1 The wired AND connection

The wired AND connection is a form of AND gate. It uses a pull up resistor and one diode per input to create thisfunction.The positive voltage from the source is directed away from the output C and towards A and B via the diodes connecteddirected towards the inputs. When positive logic that is equal to or greater than that of the source is applied to allinputs the source voltage is directed to the output. The AND gate is capable of an arbitrary number of inputs.The wiredAND function can be achieved by simply tying gate outputs together to a common-collector pull-up resistor.The wired AND function below is achieved by using open collector TTL gates. This is commonly called Dot OR.The output C is determined by the inputs at A and B according to the truth table (right).[1]

129

130 CHAPTER 40. WIRED LOGIC CONNECTION

CA

B

+5V

Wired AND connection using diodes and a resistor

40.2 The wired OR connection

The wired OR connection electrically performs the Boolean logic operation of an OR gate, using a pull down resistorand one diode per input.Voltage from any input is directed through its corresponding diode directly to the output C. If no voltage/logic existson any input there will be no output. The positive voltage source that is present in the AND connection is replaced bya ground in the OR connection. Also, notice the positioning of the diodes as compared to the AND gate. Similarly,the OR connection is capable of an arbitrary number of inputs and only one output.The output C is determined by the inputs at A and B according to the truth table (not shown) and square wave (below).

40.3 Reversed levels

A wired AND can be converted into a wired OR, and vice versa, by using signals with reversed levels. Commonexamples are signals like INT or RST.

40.3. REVERSED LEVELS 131

Truth table for two input AND

Wired OR connection using diodes and a resistor

132 CHAPTER 40. WIRED LOGIC CONNECTION

Logical OR of two signals A and B

40.4 Compatibility of wired AND OR using diodes

With the wired AND or OR using diodes it should be cautioned that the output voltage will be shifted positive ornegative by a diode drop so that it is likely not compatible with the primary logic family.

40.5 References[1] M. Morris Mano, Digital Logic and Computer Design, Prentice-Hall, 1979 ISBN 0-13-214510-3, page 571

• Digital Techniques, Heathkit Educational Systems,1990

• Fundamental Physics, K.L Gomber and K.L Gogia,Pradeep Publications, 2005

40.6 External links• Introduction to Wired-OR Outputs and Open-Collector Circuits

Chapter 41

Wolfram axiom

TheWolfram axiom is the result of a computer exploration undertaken by StephenWolfram[1] in his A New Kind ofScience looking for the shortest single axiom equivalent to the axioms of Boolean algebra (or propositional calculus).The result[2] of his search was an axiom with six Nand’s and three variables equivalent to Boolean algebra:

((a|b) | c) | (a | ((a|c) | a)) = c

With the dot representing the Nand logical operation (also known as the Sheffer stroke), with the following meaning:p Nand q is true if and only if not both p and q are true. It is named for Henry M. Sheffer, who proved that all theusual operators of Boolean algebra (Not, And, Or, Implies) could be expressed in terms of Nand. This means thatlogic can be set up using a single operator.Wolfram’s 25 candidates are precisely the set of Sheffer identities of length less or equal to 15 elements (excludingmirror images) that have no noncommutative models of size less or equal to 4 (variables).[3]

Researchers have known for some time that single equational axioms (i.e., 1-bases) exist for Boolean algebra, includ-ing representation in terms of disjunction and negation and in terms of the Sheffer stroke. Wolfram proved that therewere no smaller 1-bases candidates than the axiom he found using the techniques described in his NKS book. Theproof is given in two pages (in 4-point type) in Wolfram’s book. Wolfram’s axiom is therefore the single simplestaxiom by number of operators and variables needed to reproduce Boolean algebra.Sheffer identities were independently obtained by different means and reported in a technical memorandum[4] in June2000 acknowledging correspondence with Wolfram in February 2000 in which Wolfram discloses to have found theaxiom in 1999 while preparing his book. In[5] is also shown that a pair of equations (conjectured by StephenWolfram)are equivalent to Boolean algebra.

41.1 See also

• Boolean algebra

41.2 References[1] Stephen Wolfram, A New Kind of Science, 2002, p. 808–811 and 1174.

[2] Rudy Rucker, A review of NKS, The Mathematical Association of America, Monthly 110, 2003.

[3] William Mccune, Robert Veroff, Branden Fitelson, Kenneth Harris, Andrew Feist and Larry Wos, Short Single Axiomsfor Boolean algebra, J. Automated Reasoning, 2002.

[4] Robert Veroff and William McCune, A Short Sheffer Axiom for Boolean algebra, Technical Memorandum No. 244

[5] Robert Veroff, Short 2-Bases for Boolean algebra in Terms of the Sheffer stroke. Tech. Report TR-CS-2000-25, ComputerScience Department, University of New Mexico, Albuquerque, NM

133

134 CHAPTER 41. WOLFRAM AXIOM

41.3 External links• Stephen Wolfram, 2002, "A New Kind of Science, online”.

• Weisstein, Eric W., “Wolfram Axiom”, MathWorld.

• http://hyperphysics.phy-astr.gsu.edu/hbase/electronic/nand.html

• Weisstein, Eric W., “Boolean algebra”, MathWorld.

• Weisstein, Eric W., “Robbins Axiom”, MathWorld.

• Weisstein, Eric W., “Huntington Axiom”, MathWorld.

Chapter 42

XNOR gate

TheXNORgate (sometimes spelled “exnor” or “enor” and rarely written NXOR) is a digital logic gate whose functionis the logical complement of the exclusive OR (XOR) gate. The two-input version implements logical equality,behaving according to the truth table to the right. A HIGH output (1) results if both of the inputs to the gate are thesame. If one but not both inputs are HIGH (1), a LOW output (0) results.

42.1 Symbols

There are 2 symbols for XNOR gates: the 'distinctive' symbol and the 'rectangular' symbol. For more informationsee Logic Gate Symbols. The ANSI symbol for the XNOR gate is a standard XOR gate with an inversion bubbleconnected.

AB

out

“Distinctive” XNOR symbol

=1

“Rectangular” XNOR Symbol

The XNOR gate with inputs A and B implements the logical expression A ·B +A ·B .

42.2 Hardware description and pinout

XNOR gates are represented in most TTL and CMOS IC families. The standard 4000 series CMOS IC is the 4077and the TTL IC is the 74266. Both include four independent, two-input, XNOR gates. The pinout diagram is asfollows:This device is available from most semiconductor manufacturers such as NXP. It is usually available in both through-hole DIP and SOIC format. Datasheets are readily available in most datasheet databases. DIL is a Dual In Linepackage, and SIL is a Single In Line package.

135

136 CHAPTER 42. XNOR GATE

42.3 Alternatives

If no specific XNOR gates are available, one can be made from four NOR gates or five NAND gates in the config-urations shown below. In fact, any logic gate can be made from combinations of only NAND gates or only NORgates.

XNOR gate constructed using only NOR gates

XNOR gate constructed using only NAND gates

XNOR gate can be made with 3 gates (1x OR & 2x NAND gates)

XNOR Gate made up of 3 gates

42.4. SEE ALSO 137

42.4 See also• AND gate

• OR gate

• NOT gate

• NAND gate

• NOR gate

• XOR gate

• Kronecker delta function

• Logical biconditional

42.5 References• Texas Instruments© CD4077 Datasheet

Chapter 43

XOR gate

This article is about XOR in the sense of an electronic logic gate (e.g. CMOS 4030). For XOR in the purely logicalsense, see Exclusive disjunction. For other uses, see XOR (disambiguation).

The XOR gate (sometimes EOR gate, or EXOR gate and pronounced as Exclusive OR gate) is a digital logic gatethat implements an exclusive or; that is, a true output (1/HIGH) results if one, and only one, of the inputs to thegate is true. If both inputs are false (0/LOW) or both are true, a false output results. XOR represents the inequalityfunction, i.e., the output is true if the inputs are not alike otherwise the output is false. A way to remember XOR is“one or the other but not both”.XOR can also be viewed as addition modulo 2. As a result, XOR gates are used to implement binary addition incomputers. A Half adder consists of an XOR gate and an AND gate. Other uses include substractors, comparators,and controlled inverters.[1]

The algebraic expressions A ·B +A ·B and (A+B)· ( A+B ) both represent the XOR gate with inputs A and B.The behavior of XOR is summarized in the truth table shown on the right.

43.1 Symbols

There are two symbols for XOR gates: the traditional symbol and the IEEE symbol. For more information see LogicGate Symbols.The logic symbols ⊕ and ⊻ can be used to denote XOR in algebraic expressions.C-like languages use the caret symbol ^ to denote bitwise XOR. (Note that the caret does not denote logical con-junction (AND) in these languages, despite the similarity of symbol.)

43.2 Alternatives

If a specific type of gate is not available, a circuit that implements the same function can be constructed from otheravailable gates. A circuit implementing an XOR function can be trivially constructed from an XNOR gate followedby a NOT gate. If we consider the expression A · B + A · B , we can construct an XOR gate circuit directly usingAND, OR and NOT gates. However, this approach requires five gates of three different kinds.An XOR gate circuit can be made from four NAND or five NOR gates in the configurations shown below . In fact,both NAND and NOR gates are so-called “universal gates,” and any logical function can be constructed from eitherNAND logic or NOR logic alone.As an alternative, if different gates are available we can apply Boolean algebra to transformA ·B+A ·B ≡ (A+B)·( A + B ) as stated above, and apply de Morgan’s Law to the last term to get (A + B)· (A ·B) which can beimplemented using only three gates as shown below.

138

43.3. MORE THAN TWO INPUTS 139

A

¬B

¬A

¬BB

A

B

¬A

A xor B

Vss

Vdd

CMOS XOR gate

Traditional XOR Symbol

43.3 More than two inputs

Strict reading of the definition of exclusive or, or observation of the IEC rectangular symbol, raises the question ofcorrect behaviour with additional inputs. If a logic gate were to accept three or more inputs and produce a true outputif exactly one of those inputs were true, then it would in effect be a one-hot detector (and indeed this is the case foronly two inputs). However, it is rarely implemented this way in practice.It is most common to regard subsequent inputs as being applied through a cascade of binary exclusive-or operations:the first two signals are fed into an XOR gate, then the output of that gate is fed into a second XOR gate together

140 CHAPTER 43. XOR GATE

1

IEEE XOR Symbol

with the third signal, and so on for any remaining signals. The result is a circuit that outputs a 1 when the number of1s at its inputs is odd, and a 0 when the number of incoming 1s is even. This makes it practically useful as a paritygenerator or a modulo-2 adder.For example, the 74LVC1G386microchip is advertised as a three-input logic gate, and implements a parity generator.[2]

43.4 Applications

43.4.1 Uses in addition

The XOR logic gate can be used as a one-bit adder that adds any two bits together to output one bit. For example, ifwe add 1 plus 1 in binary, we expect a two-bit answer, 10 (i.e. 2 in decimal). Since the trailing sum bit in this outputis achieved with XOR, the preceding carry bit is calculated with an AND gate. This is the main principle in HalfAdders and the combined AND-XOR circuit may be chained together in order to add ever longer binary numbers.

43.4.2 Pseudo-random number generation

Pseudo-random number (PRN) generators, specifically Linear feedback shift registers, are defined in terms of theexclusive-or operation. Hence, a suitable setup of XOR gates can model a linear feedback shift register, in order togenerate random numbers.

43.4.3 Correlation and sequence detection

XOR gates produce a 0 when both inputs match. When searching for a specific bit pattern or PRN sequence in a verylong data sequence, a series of XOR gates can be used to compare a string of bits from the data sequence against thetarget sequence in parallel. The number of 0 outputs can then be counted to determine how well the data sequencematches the target sequence. Correlators are used in many communications devices such as CDMA receivers anddecoders for error correction and channel codes. In a CDMA receiver, correlators are used to extract the polarity ofa specific PRN sequence out of a combined collection of PRN sequences.A correlator looking for 11010 in the data sequence 1110100101 would compare the incoming data bits against thetarget sequence at every possible offset while counting the number of matches (zeros):1110100101 (data) 11010 (target) 00111 (XOR) 2 zero bits 1110100101 11010 00000 5 zero bits 111010010111010 01110 2 zero bits 1110100101 11010 10011 2 zero bits 1110100101 11010 01000 4 zero bits 1110100101

43.5. SEE ALSO 141

AB

S

C

Example half adder circuit diagram

11010 11111 0 zero bits Matches by offset: . : : : : : : : ----------- 0 1 2 3 4 5In this example, the best match occurs when the target sequence is offset by 1 bit and all five bits match. When offsetby 5 bits, the sequence exactly matches its inverse. By looking at the difference between the number of ones andzeros that come out of the bank of XOR gates, it is easy to see where the sequence occurs and whether or not it isinverted. Longer sequences are easier to detect than short sequences.

43.5 See also

• Exclusive or

• AND gate

• OR gate

• Inverter (NOT gate)

• NAND gate

• NOR gate

• XNOR gate

• Boolean algebra

• Logic gate

43.6 References

[1] Fletcher, William (1980). An engineering approach to digital design. Prentice-Hall. p. 98. ISBN 0-13-277699-5.

[2] 74LVC1G386 data sheet

142 CHAPTER 43. XOR GATE

43.7 External links• Interactive XOR Gate, Demonstrate the logic flow of the XOR Gate circuit created with Teahlab’s simulator.

43.8. TEXT AND IMAGE SOURCES, CONTRIBUTORS, AND LICENSES 143

43.8 Text and image sources, contributors, and licenses

43.8.1 Text• AND gate Source: https://en.wikipedia.org/wiki/AND_gate?oldid=675123761 Contributors: SimonP, Michael Hardy, Booyabazooka,

Ixfd64, Robbot, Dbroadwell, Zigger, Phe, Alperen, Slambo, Hooperbloob, Wtshymanski, Cburnett, Ademkader, DoubleBlue, Freshe-neesz, Crotalus horridus, Toffile, Trovatore, Nutiketaiel, Nick C, Gadget850, Wknight94, Jecowa, MattieTK, InverseHypercube, Anwarsaadat, MalafayaBot, Colonies Chris, Jjbeard~enwiki, Somnlaut, Dicklyon, Saxbryn, Dl2000, CmdrObot, PamD, JimmE, Leuqarte,Kruckenberg.1, Carlwev, Tedickey, Sodabottle, R'n'B, KCinDC, KylieTastic, Remember the dot, CardinalDan, TXiKiBoT, Oshwah,Janahan, Anna Lincoln, Jackfork, Jamelan, Inductiveload, Kehrbykid, SieBot, Joshua Griisser, I Like Cheeseburgers, CultureDrone,Pinkadelica, Yohanesyuen, Orthoepy, Excirial, Watchduck, Kalmz98, Alejandrocaro35, SoxBot III, Karanvirh, Manfi, Paul Vernaza, Ad-dbot, Download, OlEnglish, Luckas-bot, Yobot, Grebaldar, Luizdl, Objix, Materialscientist, Xqbot, GrouchoBot, Wikipe-tan, Redrose64,Robert A. Maxwell, Ezhuttukari, Robert.Baruch, PiRSquared17, ,دالبا Ripchip Bot, Destrucules, EmausBot, Wikipelli, ZéroBot, NG-Priest,Wayne Slam, Eda eng, RaptureBot, Mora714, ChuispastonBot, DASHBotAV, F457fede, ClueBotNG,MelbourneStar, O.Koslowski,EBatlleP, Jobin RV, Mchivetta, Roshan220195, Murughendra, Ajv39 and Anonymous: 97

• AND-OR-Invert Source: https://en.wikipedia.org/wiki/AND-OR-Invert?oldid=651048835Contributors: Jeandré du Toit, Toffile, Smack-Bot, Chris the speller, Dicklyon, Edward Vielmetti, Gregbard, Ktalon, Dspark76, RjwilmsiBot, John of Reading, Widr, Helpful Pixie Botand Anonymous: 7

• Booleo Source: https://en.wikipedia.org/wiki/Booleo?oldid=593540061 Contributors: 2005, Mindmatrix, Gregbard, ImageRemovalBot,Yobot, AnomieBOT, Nemesis63, LilHelpa, Jesse V., Wcherowi, Jranbrandt, Ducknish, MrNiceGuy1113, Shevek1981 and Anonymous:1

• C-element Source: https://en.wikipedia.org/wiki/C-element?oldid=677266269Contributors: Wesley, SeventyThree, SystemBuilder, Brejc8,Allens, SmackBot, Glrx, KylieTastic, Reinderien, ImageRemovalBot, ClueBot, Quercus basaseachicensis, Qwfp, MystBot, Addbot,Sketerpot, Jesse V., RjwilmsiBot, Topeil, ClueBot NG, Jkwchui, BG19bot, MatthewIreland, Tyywoody, Thealik and Anonymous: 8

• C-ROT gate Source: https://en.wikipedia.org/wiki/C-ROT_gate?oldid=624562457 Contributors: Malcolma, SmackBot, Latch.r, Head-bomb, Addbot, Yobot, K6ka, Wbm1058 and Anonymous: 2

• Computer module Source: https://en.wikipedia.org/wiki/Computer_module?oldid=651885302 Contributors: Maury Markowitz, Jni,Bearcat, Dawynn, Jarble, AnomieBOT, Alvin Seville, 10metreh, BG19bot, Pippab3, Mattarthur, Matthewdoo, Suniltx and Anonymous:1

• Controlled NOT gate Source: https://en.wikipedia.org/wiki/Controlled_NOT_gate?oldid=665267258 Contributors: Mrwojo, DiegoMoya, RJFJR, Rjwilmsi, Koavf, Revolving Bugbear, Conscious, Archelon, SmackBot, InverseHypercube, Colonies Chris, Frap, WenD House, DavidBoden, A5b, Ligulembot, Flipperinu, Vikesh, Cryptonaut, King Mir, Falcor84, Leyo, Idioma-bot, LokiClock, Jediknil,Cnot~enwiki, Cnotgate, StewartMH, Alksentrs, Asf107, Addbot, DOI bot, Adinrivera, LaaknorBot, Cesiumfrog, Rubinbot, Citation bot,QBenni, Soccerdude 13, John of Reading, ZéroBot, Wbm1058, Bibcode Bot, BG19bot, Anubhab91, Gronk Oz and Anonymous: 26

• DavidE.Muller Source: https://en.wikipedia.org/wiki/David_E._Muller?oldid=618511537Contributors: Michael Hardy, Bearcat, Lock-ley, Waacstats, David Eppstein, Ponyo, Yobot, Alvin Seville, RjwilmsiBot, Marcuszengl, Suslindisambiguator, Poppopsun, Dynahub andAnonymous: 2

• Diode-or circuit Source: https://en.wikipedia.org/wiki/Diode-or_circuit?oldid=532068572Contributors: Neilm, Gurch,Malcolma, Smack-Bot, Amalas, 718 Bot, Addbot, Erik9bot and Anonymous: 1

• Fan-in Source: https://en.wikipedia.org/wiki/Fan-in?oldid=656914944 Contributors: Heron, RTC, Clubjuggle, Richwales, Jidan, Toffile,Pegship, Tevildo, SmackBot, DMacks, Mystic Pixel, JoshuaZ, IronGargoyle, Dicklyon, Amalas, Revolus, Thijs!bot, Widefox, TXiKiBoT,Inductiveload, Sunjay03, Uncle Milty, KALYAN T.V., Addbot, ^musaz, Erik9bot, Ripchip Bot, AndyHe829, WikitanvirBot, Donner60,Rakeshkprasad and Anonymous: 25

• Fan-out Source: https://en.wikipedia.org/wiki/Fan-out?oldid=667601268 Contributors: Heron, RTC, GRAHAMUK, Zoicon5, Omega-tron, DavidCary, Chowbok, McCart42, Abdull, Perey, Alistair1978, Plugwash, Zr40, Anthony Appleyard, Kolbasz, Karch, Toffile,TeeEmCee, Herostratus, Gilliam, Bluebot, Oli Filth, Joeylawn, Dicklyon, Jaredtritz, Thijs!bot,Widefox, Jdclevenger, 28421u2232nfenfcenc,Genuineleather, TXiKiBoT, Ckrich 99, Mild Bill Hiccup, Hans Adler, Addbot, ,ماني Legobot, Luckas-bot, Yobot, Ptbotgourou, Ched,Wikipelli, Naseem Awan, ClueBot NG, Fahrettinkoc, Mrramazani, BG19bot, Arjunazadi, JYBot, Panzer ele, K0zka and Anonymous:36

• Fredkin gate Source: https://en.wikipedia.org/wiki/Fredkin_gate?oldid=645550922Contributors: PaulMurray, Pengo, DavidCary, Quackor,Hooperbloob, Wikiklrsc, Koavf, Toffile, robot, Stepa, Bluebot, FrankBuss, WinBot, J.delanoy, Jamelan, Int21h, ClueBot, Alk-sentrs, Bender2k14, DumZiBoT, Addbot, Balabiot, Ywaz, Ched, Prari, Fealrviiss, Fredkinfollower, RjwilmsiBot, Wbm1058 and Anony-mous: 11

• Gate equivalent Source: https://en.wikipedia.org/wiki/Gate_equivalent?oldid=639315398Contributors: Richwales, LOL, Luethi, Smack-Bot, Doodle77, Nick Number and Anonymous: 6

• IMPLY gate Source: https://en.wikipedia.org/wiki/IMPLY_gate?oldid=667427318 Contributors: User-000 and Anonymous: 1• Inverter (logic gate) Source: https://en.wikipedia.org/wiki/Inverter_(logic_gate)?oldid=674635507 Contributors: Butik, Glenn, Alaric,

Hydnjo, Robbot, DavidCary, Hugh Mason, TedPavlic, Pjacobi, Hooperbloob, Philthecow, BD2412, Eubot, Nimur, George Leung, Russ-Bot, Toffile, NawlinWiki, Deville, StealthFox, Audriusa, Dicklyon, Dl2000, KX36, Circuit dreamer, Cbmeeks, Thijs!bot, JAnDbot,MER-C, Sodabottle, STBot, Glrx, Kloisiie, Jamelan, SieBot, JL-Bot, DragonBot, Dspark76, AlanM1, MystBot, Addbot, !Silent, Gre-baldar, Mike1975, ^musaz, Climber22, Jmundo, Nasa-verve, GrouchoBot, RibotBOT, Prari, Redrose64, Yahia.barie, Robert.Baruch,CobraBot, ,دالبا EmausBot, RaptureBot, ClueBot NG, CocuBot, Wbm1058, GKFX, L888Y5, Ajv39, Jamesx12345, Sriharsh1234,Ali.Zeineddine93, Crystallizedcarbon and Anonymous: 37

• Linear optical quantum computing Source: https://en.wikipedia.org/wiki/Linear_optical_quantum_computing?oldid=676287763Con-tributors: Wtmitchell, Rjwilmsi, Azaghal of Belegost, Citation bot, GoingBatty, Bibcode Bot, ChrisGualtieri, Faizan, Anne Delong,I2000s, Phleg1 and Anonymous: 3

144 CHAPTER 43. XOR GATE

• Logic gate Source: https://en.wikipedia.org/wiki/Logic_gate?oldid=675310778Contributors: AxelBoldt, MagnusManske, PeterWinnberg,Derek Ross, MarXidad, The Anome, BenBaker, Jkominek, Mudlock, Heron, Stevertigo, Frecklefoot, RTC, Michael Hardy, Booy-abazooka, Mahjongg, Dominus, SGBailey, Ixfd64, Karada, Mac, Glenn, Netsnipe, GRAHAMUK, Arteitle, Reddi, Dysprosia, ColinMarquardt, Maximus Rex, Mrand, Omegatron, Jni, Sjorford, Robbot, Lord Kelvin, Pingveno, Bkell, Ianml, Paul Murray, Mushroom, An-chetaWis, Centrx, Giftlite, Andy, DavidCary, Peruvianllama, Everyking, Pashute, AJim, Andris, Espetkov, Vadmium, LucasVB, Kaldari,CSTAR, Creidieki, Jlang, Kineox~enwiki, Mormegil, Discospinster, Rich Farmbrough, Luzian~enwiki, Roo72, LindsayH, SocratesJedi,ESkog, ZeroOne, Plugwash, Nabla, CanisRufus, Aecis, Diomidis Spinellis, Smalljim, La goutte de pluie, Hooperbloob, Jumbuck, GuyHarris, Arthena, Blues-harp, Lectonar, Pion, Bantman, N313t3~enwiki, BRW, Wtshymanski, Rick Sidwell, Cburnett, Deadworm222,Bonzo, Alai, Axeman89, LunaticFringe, Bookandcoffee, Dan100, Cipherswarm, Smark33021, Boothy443, Mindmatrix, Jonathan deBoyne Pollard, Bkkbrad, VanFowler, Kglavin, Karmosin, The Nameless, V8rik, BD2412, Syndicate, ZanderSchubert, GOD, Bruce1ee,Ademkader, DoubleBlue, Firebug, Mirror Vax, Latka, Ewlyahoocom, Swtpc6800, Fresheneesz, Vonkje, DVdm, Bgwhite, The Ram-bling Man, YurikBot, Adam1213, RussBot, Akamad, Stephenb, Yyy, Robchurch, FreelanceWizard, Zwobot, Rohanmittal, StuRat, Reyk,Urocyon, HereToHelp, Anclation~enwiki, Easter Monkey, SorryGuy, AMbroodEY, JDspeeder1, Adam outler, Crystallina, SmackBot,Eveningmist, Jcbarr, Frymaster, Canthusus, Folajimi, Andy M. Wang, Lindosland, JoeKearney, SynergyBlades, Oli Filth, MovGP0,Lightspeedchick, Jjbeard~enwiki, Audriusa, Ian Burnet~enwiki, Can't sleep, clown will eat me, Nick Levine, KevM, Atilme, Epachamo,Hgilbert, Jon Awbrey, Shadow148, SashatoBot, Lambiam, Kuru, MagnaMopus, Athernar, Igor Markov, Mgiganteus1, JHunterJ, Van-ished user 8ij3r8jwefi, Robert Bond, Dicklyon, Mets501, Dacium, JYi, J Di, Aeons, Rangi42, Marysunshine, Eassin, Tawkerbot2, Don-keyKong64, Drinibot, Circuit dreamer, Skoch3, Arnavion, Gregbard, Rajiv Beharie, Mblumber, Abhignarigala, Mello newf, Dancter,Tawkerbot4, DumbBOT,Omicronpersei8, Lordhatrus, Thijs!bot, Epbr123, N5iln, Al Lemos, Marek69, DmitTrix, James086, Towopedia,Izyt, Eleuther, Stannered, AntiVandalBot, USPatent, MER-C, Wasell, Massimiliano Lincetto, Bongwarrior, VoABot II, JNW, Yandman,Rhdv, M 3bdelqader, Robin S, Rickterp, MartinBot, Rettetast, Glrx, J.delanoy, Jonpro, Feis-Kontrol, Zen-in, Jeepday, Eibx, Bigdumb-dinosaur, FreddieRic, Hanacy, Sunderland06, Cometstyles, Tiggerjay, Tygrrr, DorganBot, Alex:D, Barber32, Idioma-bot, VolkovBot,Hersfold, AlnoktaBOT, Lear’s Fool, Philip Trueman, PNG crusade bot, TXiKiBoT, GLPeterson, Mamidanna, Murugango, Djkrajnik,Salvar, The Tetrast, Corvus cornix, Jackfork, Inductiveload, Dirkbb, Updatebjarni, STEDMUNDS07, Logan, Neparis, SieBot, Niv.sarig,I Like Cheeseburgers, ToePeu.bot, Gerakibot, Teh Naab, Flyer22, Berserkerus, Evaluist, Oxymoron83, Steven Crossin, WimdeValk,ClueBot, The Thing That Should Not Be, Rilak, Boing! said Zebedee, CounterVandalismBot, Namazu-tron, Alexbot, Ftbhrygvn, Ed-dyJ07, Dspark76, Hans Adler, The Red, Abhishek Jacob, Horselover Frost, Versus22, Egmontaz, DumZiBoT, XLinkBot, Marylee23,MystBot, Iranway, Addbot, Willking1979, Melab-1, A0602336, Chef Super-Hot, Ashton1983, Vishnava, Fluffernutter, Rchard2scout,Hmorris94, Tyw7, Tide rolls, Lightbot, OlEnglish, Legobot, PlankBot, Luckas-bot, Ptbotgourou, THENWHOWAS PHONE?, Knownot,Alienskull, AnomieBOT, 0x38I9J*, Jim1138, JackieBot, Piano non troppo, Keithbob, Materialscientist, Spirit469, Citation bot, Bean49,Xqbot, RMSfromFtC, Sketchmoose, Big angry doggy, Capricorn42, Coretheapple, RibotBOT, Elep2009, XPEHOPE3, Joaquin008,Vdsharma12, FrescoBot, Roman12345, Machine Elf 1735, Cannolis, Pinethicket, Jschnur, RedBot, MastiBot, SpaceFlight89, ForwardUnto Dawn, Cnwilliams, Wikitikitaka, Blackenblue, Vrenator, Zvn, Clarkcj12, MrX, Meistro god, Galloping Moses, EmausBot, John ofReading, Trinibones, Wikipelli, Draconicfire, GOVIND SANGLI, Wayne Slam, Dmitry123456, Ontyx, Carmichael, Tijfo098, GrayFull-buster, Protoborg, Stevenglowa, ClueBot NG, Jack Greenmaven, Morgankevinj huggle, VladikVP, Marechal Ney, Masssly, Vibhijain,Jk2q3jrklse, Helpful Pixie Bot, Wbm1058, Lowercase sigmabot, Mark Arsten, CitationCleanerBot, Snow Blizzard, Husigeza, Rscprint-erBot, Safeskiboydunknoe, FrederickE, Teammm, Mrt3366, Rsmary, Sha-256, Harsh 2580, Lugia2453, Itsmeshiva, Red-eyed demon,Jamesmcmahon0, Tentinator, SelfishSeahorse, Lilbonanza, Mz bankie, Jianhui67, Abhinav dw6, Cdouglas32, Trax support, TerryAlex,Gfdsfgfgfg, Areyoureadylouie, Charliegirl321, Bobbbbbbbbvvvvvcvcv, KasparBot and Anonymous: 552

• Logical equality Source: https://en.wikipedia.org/wiki/Logical_equality?oldid=641602683 Contributors: Toby Bartels, Patrick, Ixfd64,Lethe, Peruvianllama, Paul August, AzaToth, Oleg Alexandrov, Mindmatrix, BD2412, Canderson7, FlaBot, YurikBot, Daverocks, Dijx-tra, Trovatore, Arthur Rubin, SmackBot, Melchoir, Bluebot, Jerome Charles Potts, Jjbeard~enwiki, Radagast83, Jon Awbrey, Gregbard,Cydebot, Julian Mendez, Letranova, Thijs!bot, Escarbot, David Eppstein, Infovarius, MartinBot, Santiago Saint James, R'n'B, SieBot,BotMultichill, Aeoza, Sitush, Francvs, Rumping, Hans Adler, Addbot, AnomieBOT, 2ndjpeg, Gamewizard71, Kuzmaka, Wcherowi,Masssly, MerlIwBot, Faus, Trinitresque, MikeShafe and Anonymous: 22

• Magnetic logic Source: https://en.wikipedia.org/wiki/Magnetic_logic?oldid=671571665 Contributors: Maury Markowitz, PeterO, Disa-vian, GliderMaven, Forgot to put name and Sfkevfjf

• Majority function Source: https://en.wikipedia.org/wiki/Majority_function?oldid=673370318 Contributors: Tobias Hoevekamp, Jz-cool, Michael Hardy, Ckape, Robbot, DavidCary, ABCD, Bluebot, Radagast83, Lambiam, J. Finkelstein, Gregbard, Pascal.Tesson, Al-phachimpbot, Magioladitis, Vanish2, David Eppstein, Ilyaraz, Alexei Kopylov, TFCforever, DOI bot, Balabiot, Legobot, Luckas-bot,Yobot, Rubinbot, Citation bot, Citation bot 1, Андрей Куликов, Jesse V., Monkbot and Anonymous: 7

• Molecular logic gate Source: https://en.wikipedia.org/wiki/Molecular_logic_gate?oldid=668578299Contributors: DocWatson42, V8rik,Ketiltrout, Rjwilmsi, Angusmclellan, Toffile, SmackBot, Edgar181, M stone, Myasuda, Cydebot, Antony-22, ImageRemovalBot, Arun-singh16, Mbcudmore, Qwfp, Addbot, Yobot, WikiDan61, AnomieBOT, Carlog3, GoingBatty, Mcfdcm0510 and Anonymous: 8

• NAND gate Source: https://en.wikipedia.org/wiki/NAND_gate?oldid=660912804 Contributors: Booyabazooka, DopefishJustin, Rob-bot, M1ss1ontomars2k4, Abdull, Mattisgoo, EmilJ, Hooperbloob, Wtshymanski, Cburnett, Linas, M412k, Holek, FlaBot, Fresheneesz,Crotalus horridus, RussBot, Member, Donbert, Jecowa, Whaa?, SmackBot, Nscheffey, SlimJim, Thumperward, Jjbeard~enwiki, UU,Cybercobra, Dl2000, Tawkerbot2, Gregbard, Mblumber, Optimist on the run, Royas, Magioladitis, Sodabottle, JJ Harrison, JoshuaDavis, Ghostwo, R'n'B, Kloisiie, Wbrito, WhiteOak2006, Jamelan, Aby.india, Tonyhawkwiz, SieBot, Joshua Griisser, Bentogoa, Ale-jandrocaro35, AlanM1, Addbot, Jafeluv, Unibond, Wikimono111, Luckas-bot, Yobot, AndrooUK, LilHelpa, Kierkkadon, ListenerX,Redrose64, Chas.owens, Edderso, Robert.Baruch, Rx5674, ,دالبا Alph Bot, EmausBot, F457fede, ClueBot NG, Murughendra, TheIllusive Man, Rarkenin, Ajv39, Dhx1, Jcherman, EthicalBreakdown and Anonymous: 50

• NAND logic Source: https://en.wikipedia.org/wiki/NAND_logic?oldid=674359112Contributors: Perey, Adam850, Smalljim, Hooperbloob,Wtshymanski, Qwertyus, Melesse, Miserlou, Swtpc6800, Toffile, Archelon, Rsrikanth05, Bobbo, Onionjake, Jecowa, SmackBot, Can-thusus, Andy M. Wang, Thumperward, Morte, Colonies Chris, Jjbeard~enwiki, Rrburke, Felipe.sanches~enwiki, Saxbryn, Chj9183,Sakurambo, Jesse Viviano, Mblumber, Ivant, PamD, Malcolmst, Tholly, Johnl1479, KylieTastic, Olmsfam, Inductiveload, Denisarona,ClueBot, Capitocapito, Rilak, Adrianwn, Michael2695, 718 Bot, Excirial, Rishidigital1055, Addbot, RPHv, AceOfJesters, Yobot, Demo-craticLuntz, Piano non troppo, Ipatrol, Erik9bot, MinimanDragon32, Dmbaturin, LawBot, DARTH SIDIOUS 2, ,دالبا RjwilmsiBot,WikitanvirBot, Elee, Darsh3799, ZéroBot, Érico Júnior Wouters, A930913, ClueBot NG, Widr, Pratyya Ghosh, The Illusive Man, Bajs-fisk, Young scientists (Mansoor), Asdeefa Tahniath, Skadmz, Feadnation20, Lightrace, Brianlen, Quenhitran, PLayLP, Shyy Xiryx andAnonymous: 113

43.8. TEXT AND IMAGE SOURCES, CONTRIBUTORS, AND LICENSES 145

• NOR gate Source: https://en.wikipedia.org/wiki/NOR_gate?oldid=667331982 Contributors: Michael Hardy, Booyabazooka, Cherkash,HPA, Bkell, Paul Murray, Dbroadwell, Hugh Mason, Rich Farmbrough, Andros 1337, Bender235, Smalljim, Hooperbloob, Wtmitchell,Velella, Wtshymanski, Cburnett, Matevzk, JVz, Ademkader, Fresheneesz, Korg, YurikBot, Dmharvey, RussBot, Jengelh, Toffile, Trova-tore, Nkendrick, Anclation~enwiki, SmackBot, InverseHypercube, Gilliam, Colonies Chris, Jjbeard~enwiki, Can't sleep, clown will eatme, Lambiam, Saxbryn, Dl2000, Tenbergen, Stannered, Anoop anooprs, Sodabottle, Cscade, RockMFR, GandalfDaGraay, NewEng-landYankee, Kloisiie, Jamelan, Inductiveload, Aby.india, Joshua Griisser, Keilana, CultureDrone, Adrianwn, Lampak, Auntof6, 718Bot, Watchduck, Alejandrocaro35, AlanM1, Addbot, Elfix, Erik9bot, Prari, Redrose64, Meaghan, Robert.Baruch, ,دالبا Tommy2010,Thecheesykid, Jaredjeya, Alpha Quadrant, F457fede, ClueBot NG, Frietjes, Jcherman, Lightrace, YiFeiBot, Jrgsampaio, Jamieddd andAnonymous: 41

• NOR logic Source: https://en.wikipedia.org/wiki/NOR_logic?oldid=667742638 Contributors: Bkell, Antandrus, Perey, Triona, Interiot,Ketiltrout, Sceptre, Siker, SmackBot, Veggies, Dro Kulix, S Roper, Dragonix, CarrotMan, Nick Number, Malcolmst, Inductiveload,DaYZman, Andrew1~enwiki, ClueBot, Adrianwn, Addbot, Download, Maslen, Yobot, Evaders99, GrouchoBot, Erik9bot, LawBot, Su-per48paul, Moswento, Scrlk95, Donner60, ClueBot NG, Rarkenin, Forgot to put name, Acagastya and Anonymous: 63

• NOT gate Source: https://en.wikipedia.org/wiki/Inverter_(logic_gate)?oldid=674635507 Contributors: Butik, Glenn, Alaric, Hydnjo,Robbot, DavidCary, Hugh Mason, TedPavlic, Pjacobi, Hooperbloob, Philthecow, BD2412, Eubot, Nimur, George Leung, RussBot, Tof-file, NawlinWiki, Deville, StealthFox, Audriusa, Dicklyon, Dl2000, KX36, Circuit dreamer, Cbmeeks, Thijs!bot, JAnDbot, MER-C, Sod-abottle, STBot, Glrx, Kloisiie, Jamelan, SieBot, JL-Bot, DragonBot, Dspark76, AlanM1, MystBot, Addbot, !Silent, Grebaldar, Mike1975,^musaz, Climber22, Jmundo, Nasa-verve, GrouchoBot, RibotBOT, Prari, Redrose64, Yahia.barie, Robert.Baruch, CobraBot, ,دالباEmausBot, RaptureBot, ClueBot NG, CocuBot, Wbm1058, GKFX, L888Y5, Ajv39, Jamesx12345, Sriharsh1234, Ali.Zeineddine93,Crystallizedcarbon and Anonymous: 37

• OR gate Source: https://en.wikipedia.org/wiki/OR_gate?oldid=674748969 Contributors: Heron, Michael Hardy, Bewildebeast, Zigger,Everyking, LucasVB, Phe, Discospinster, Rich Farmbrough, Hooperbloob, Andrewpmk, Sligocki, Wtshymanski, Cburnett, PoccilScript,Palica, Fresheneesz, Toffile, Trovatore, SmackBot, Gilliam, Anwar saadat, Colonies Chris, Jjbeard~enwiki, RProgrammer, Lambiam, Fe-lipe.sanches~enwiki, Saxbryn, Dl2000, Christian75, Thijs!bot, Escarbot, Stannered, Mentifisto, Sodabottle, Jaakobou, SuperMarioMan,Jamelan, SieBot, Joshua Griisser, Gupta sreenath, COBot, CultureDrone, ClueBot, Rumping, Watchduck, Tonkawa68, ChardonnayN-imeque, Alejandrocaro35, Dspark76, AlanM1, Koumz, WikHead, SilvonenBot, MystBot, Addbot, !Silent, Luckas-bot, Yobot, Gre-baldar, THEN WHO WAS PHONE?, Materialscientist, LilHelpa, Xqbot, Psabbala, Nasa-verve, Erik9bot, Redrose64, Ezhuttukari,Robert.Baruch, Knoppson, PiRSquared17, EmausBot, RaptureBot, F457fede, Kasirbot, EBatlleP, Mchivetta, Roshan220195, BattyBot,Comatmebro, Mllyjn, Ajv39, Stuner0, Crystallizedcarbon, Saurabh Chatterjee 2 and Anonymous: 47

• Photochemical logic gate Source: https://en.wikipedia.org/wiki/Photochemical_logic_gate?oldid=491629916 Contributors: Kingturtle,Pearle, Hooperbloob, V8rik, Toffile, Shaddack, SmackBot, Dicklyon, Garethjhughes, CmdrObot, Brad101, MarshBot, Jeepday, HelpfulPixie Bot and Anonymous: 1

• Pulse transition detector Source: https://en.wikipedia.org/wiki/Pulse_transition_detector?oldid=473839543 Contributors: Towel401,Toffile, Malcolma, SmackBot, Alaibot, MarshBot, R'n'B, Katharineamy, EnOreg, OlEnglish, Erik9bot, GoingBatty, Autoerrant, ClueBotNG and Anonymous: 5

• Quantum gate Source: https://en.wikipedia.org/wiki/Quantum_gate?oldid=676601750 Contributors: Michael Hardy, AugPi, CharlesMatthews, Sanders muc, Hadal, Alan Liefting, CSTAR, V79, Cedders, One-dimensional Tangent, Cortonin, Linas, Ruud Koot, Rjwilmsi,Phillip Jordan, Marozols, Vyroglyph, Stepa, Dave Kielpinski, Njerseyguy, Samharrison, Mct mht, Cryptonaut, Jhansonxi, SalvNaut, Loki-Clock, WereSpielChequers, Bender2k14, Justin545, Addbot, Zahd, LaaknorBot, Verbal, Luckas-bot, Yobot, AnomieBOT, GrouchoBot,Meieram, RobinK, Kodus, Ssposts, Mattedia, Vincent Russo, Wbm1058, Bibcode Bot, Cardinal Direction, W. P. Uzer, M. M. Eshom,Geek3 and Anonymous: 31

• Race condition Source: https://en.wikipedia.org/wiki/Race_condition?oldid=659492166 Contributors: Aldie, SimonP, Patrick, RTC,Michael Hardy, Karada, Mr100percent, GRAHAMUK, Dysprosia, Colin Marquardt, Pedant17, Furrykef, Joy, Bloodshedder, Ben-wing, Razi~enwiki, Nurg, Nilmerg, Mdrejhon, Tobias Bergemann, ManuelGR, DavidCary, Gracefool, Elmindreda, Gadfium, Quarl,Simoneau, McCart42, Freakofnurture, Rich Farmbrough, Drano, Smyth, David Schaich, Neko-chan, Aaronbrick, Cuervo, R. S. Shaw,Kamyar~enwiki, Daf, Pearle, Hooperbloob, Tom Yates, Walter Görlitz, Ynhockey, Alai, Forderud, Kenyon, Crosbiesmith, Daira Hop-wood, Mido, Cbdorsett, Male1979, Marudubshinki, E090, FlaBot, Bubbleboys, Intgr, Pinecar, YurikBot, Bhny, Barefootguru, Carl-Hewitt, Yahya Abdal-Aziz, Zwobot, Square87~enwiki, Lt-wiki-bot, Curpsbot-unicodify, Erik Sandberg, SmackBot, Slamb, Unyoyega,Dbnull, Commander Keane bot, PJTraill, RDBrown, Thumperward, Nbarth, Tsca.bot, JonHarder, Allan McInnes, Pcgomes, Soar-head77, Kuru, Moabdave, MTSbot~enwiki, Sakurambo, Cydebot, Mblumber, Jamesjiao, Barticus88, Michagal, Pietrodn, Parsiferon,Jirka6, HarmonicFeather, Greensburger, .anacondabot, Andrewdolby, Stijn Vermeeren, Madanmus, Japo, Hbent, R'n'B, Wiki Raja,Erkan Yilmaz, Szeder, Uncle Dick, AngryBear, Kyle the bot, TXiKiBoT, Softtest123, Sashman, Forlornturtle, ToePeu.bot, Jimmythe Snout, Psychless, JCLately, Chillum, PerryTachett, The Thing That Should Not Be, RFST, DumZiBoT, Addbot, Ghettoblaster,Some jerk on the Internet, Olli Niemitalo, Tothwolf, Leszek Jańczuk, Wikomidia, Numbo3-bot, Tide rolls, Luckas-bot, Yobot, PM-Lawrence, Rubinbot, Darolew, Xqbot, Miym, Erik9, Abed pacino, Winterst, Vrenator, Msghani, Alph Bot, ToneDaBass, Lambdatypes,Moswento, ZéroBot, AManWithNoPlan, Music Sorter, Eda eng, Ego White Tray, Ipsign, ChuispastonBot, ClueBot NG, Naveenmouni,Snotbot, Zakblade2000, JagexSucks, Jorgenev, Uwadb, Wbm1058, BG19bot, PhnomPencil, ElphiBot, Pleet, AllenZh, Musicologyman,Mr.goodbyte42, Hari.raghu, Eric Corbett, Kernosky, Mmpozulp, Godugu jaya, Scrabbler94, Bin927 and Anonymous: 135

• Racetrack problem Source: https://en.wikipedia.org/wiki/Racetrack_problem?oldid=596904454Contributors: Walter Görlitz, RomanSpa,HelloAnnyong, Cydebot, DanielPharos, Salamangkero, Addbot, Erik9, Ekhule, ArwinJ, Wbm1058 and Anonymous: 2

• Reconvergent fan-out Source: https://en.wikipedia.org/wiki/Reconvergent_fan-out?oldid=532645707Contributors: Avalon, SmackBot,Sabron, Bluebot, Oli Filth, Widefox, King Mir, The Kinslayer and Anonymous: 3

• Sheffer stroke Source: https://en.wikipedia.org/wiki/Sheffer_stroke?oldid=675431460 Contributors: AxelBoldt, Fubar Obfusco, Davidspector, Vik-Thor, Michael Hardy, AugPi, Jouster, Dcoetzee, Dysprosia, Markhurd, Hyacinth, Cameronc, Johnleemk, Robbot, Saaska,Rorro, Paul Murray, Snobot, Giftlite, DocWatson42, Brouhaha, Zigger, Gubbubu, Halo, Sam, Urhixidur, Ratiocinate, Rich Farmbrough,Leibniz, Pie4all88, TheJames, SocratesJedi, Paul August, Chalst, EmilJ, Nortexoid, Redfarmer, Emvee~enwiki, Dominic, Bookand-coffee, Drakferion, Woohookitty, Mindmatrix, Steven Luo, Ruud Koot, Wayward, BD2412, Qwertyus, Kbdank71, Rjwilmsi, R.e.b.,Ademkader, FlaBot, Mathbot, George Leung, Algebraist, RobotE, Sceptre, Imagist, Archelon, Ksyrie, NormalAsylum, Dijxtra, Trova-tore, Nad, Yahya Abdal-Aziz, Prolineserver, JMRyan, Rohanmittal, Luethi, JoanneB, SmackBot, Melchoir, Mhss, Chris the speller,

146 CHAPTER 43. XOR GATE

Bluebot, Thumperward, UU, Cybercobra, Jon Awbrey, Lambiam, Loadmaster, Yoderj, CBM, Ezrakilty, Gregbard, Nilfanion, Rotiro,Cydebot, Julian Mendez, Asenine, SpK, Royas, MER-C, Magioladitis, VoABot II, Vujke, Seba5618, Santiago Saint James, Kloisiie,Olmsfam, Somejan, Josephholsten, The Tetrast, Philogo, Manusharma, Jamelan, Inductiveload, Dogah, CultureDrone, Francvs, Clue-Bot, Plastikspork, Achlaug, Watchduck, Dspark76, Hans Adler, Addbot, Meisam, Bunnyhop11, TaBOT-zerem, Erud, M&M987, DanteCardoso Pinto de Almeida, LittleWink, Dhanyavaada, Omerta-ve, Dega180, Gamewizard71, RjwilmsiBot, Arielkoiman, Set theorist,Zahnradzacken, Hpvpp, SporkBot, ClueBot NG, Masssly, Jones11235813, MerlIwBot, SOFooBah, Yamaha5, Brianlen, SarahRMadden,Sofia Koutsouveli and Anonymous: 65

• Shift register lookup table Source: https://en.wikipedia.org/wiki/Shift_register_lookup_table?oldid=643839870 Contributors: Sky-smith, SMcCandlish, SmackBot, David Ashley, Amalas, Leolaursen, Addbot, Yobot, AnomieBOT, Armandas j and Anonymous: 7

• Standard cell Source: https://en.wikipedia.org/wiki/Standard_cell?oldid=658833099 Contributors: AxelBoldt, Michael Hardy, Alten-mann, Mboverload, Abdull, Dyl, Atlant, Wtshymanski, Pol098, BD2412, Ketiltrout, Chobot, Trovatore, Yahya Abdal-Aziz, Simon80,Luethi, RupertMillard, Bluebot, Craig t moore, Royboycrashfan, Radagast83, Dicklyon, Dgranda, David Carron, Afyoung, Branclem,PamD, Northumbrian, Amazake, Prolog, Nelziq, Wabernat, Wsuverkropp, Netspin, Jstine, Damiankaelgreen, Iveney, Jlstine, Editore99,TubularWorld, WimdeValk, Doseiai2, Krispykrem, Addbot, AnomieBOT, Agasta, Br77rino, FrescoBot, LucienBOT, Jc3s5h, DASHBot,Ruchir.verma.200, Wbm1058, Muendelezaji, Tabatha dora, Armintaj, Faizan, Hammerfrog, Jiten.meena and Anonymous: 40

• Toffoli gate Source: https://en.wikipedia.org/wiki/Toffoli_gate?oldid=646611233 Contributors: Heron, Michael Hardy, Cyp, GRA-HAMUK, Robbot, Paul Murray, Pengo, DavidCary, Andris, Quackor, CSTAR, Kulp, Hooperbloob, Woohookitty, Wikiklrsc, Rjwilmsi,Vary, John Baez, Imnotminkus, Mpfrank, R.e.s., robot, InverseHypercube, Torzsmokus, Kingdon, Llafnwod, JimStyle61093475,Neoromeo, Conrad.Irwin, Headbomb, Thumble, WinBot, Klapi, David Eppstein, LokiClock, Steven130793, Newcomp, Phrenophobia,Int21h, Bender2k14, SchreiberBike, Addbot, Lightbot, Francesco Betti Sorbelli, JackieBot, Quebec99, Tomdo08, Erik9, Fredkinfol-lower, Trappist the monk, RjwilmsiBot, Calcyman, ZéroBot, Helpful Pixie Bot, Wbm1058, Bibcode Bot, Anubhab91, Isarra (HG), YuvalFilmus, Monkbot, Vieque, Trax support and Anonymous: 29

• Transmission gate Source: https://en.wikipedia.org/wiki/Transmission_gate?oldid=669797246Contributors: Bearcat, DavidCary, Yobot,RevelationDirect, Charlieb000, John of Reading, Solarra, Guy Adler, Andrewright, MicroPaLeo and Anonymous: 4

• Tseitin transformation Source: https://en.wikipedia.org/wiki/Tseitin_transformation?oldid=669333494 Contributors: Bearcat, Cek,EmilJ, Eclecticos, Mblumber, Addbot, Yobot, Alamoureux, RileyBot, Rseba and Anonymous: 6

• Wired logic connection Source: https://en.wikipedia.org/wiki/Wired_logic_connection?oldid=622117861 Contributors: Schneelocke,Abdull, Wtshymanski, Rjwilmsi, Schultkl, SmackBot, O keyes, OrphanBot, Circuit dreamer, Alaibot, PamD, Esowteric, Stannered,Faizhaider, R'n'B, Zen-in, Philip Trueman, ImageRemovalBot, Treystewart333, Jzuteck, Addbot, Yobot, Raffamaiden, DrilBot, Cdwn,Thingmaker and Anonymous: 11

• Wolfram axiom Source: https://en.wikipedia.org/wiki/Wolfram_axiom?oldid=676853435 Contributors: Michael Hardy, Bearcat, Greg-bard, Nick Number, Magioladitis, Addbot, FrescoBot, EmausBot, Bourbaki78, BG19bot, G McGurk and Anonymous: 4

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• XOR gate Source: https://en.wikipedia.org/wiki/XOR_gate?oldid=668031873 Contributors: Heron, Twilsonb, Michael Hardy, Booy-abazooka, Ianml, Jorend, Alexf, Phe, Mysidia, Discospinster, Rich Farmbrough, ArnoldReinhold, Southen, Hooperbloob, DanielLC,Doopokko, Mrholybrain, Cburnett, Grenavitar, SCEhardt, Mandarax, Golem Unity, Fresheneesz, Toffile, Trovatore, Dogcow, Icedwa-ter, David Biddulph, Aforencich, SmackBot, Emj, Oli Filth, Lodev, Colonies Chris, ToobMug, Jjbeard~enwiki, Phaedriel, Jon Aw-brey, Lambiam, Saxbryn, Dl2000, Gregbard, DumbBOT, Ladyneka, Stannered, Mentifisto, Storkk, JAnDbot, Bongwarrior, Sodabot-tle, SU Linguist, Biglovinb, Alpvax, VolkovBot, Gmoose1, Jfrascencio, PNG crusade bot, Jamelan, Inductiveload, Falcon8765, JoshuaGriisser, Alexbook, Zacatecnik, CultureDrone, Watchduck, Alejandrocaro35, Abhishek Jacob, Addbot, Melab-1, CanadianLinuxUser,OlEnglish, Luckas-bot, Yobot, Crispmuncher, Seth.merritt, LilHelpa, Wikidood123456789, Maddie!, GrouchoBot, RibotBOT, Prari,Koltar1237, Redrose64, Robert A. Maxwell, Ashutosh diwakar, DARTH SIDIOUS 2, ,دالبا Calcyman, EmausBot, Mega Gamer05,Tinogomes, Wikipelli, Mjaked, LoremIpsumDolorSitAsmet, Fæ, WilloftheD, Mburdis, ClueBot NG, CocuBot, Lowercase sigmabot,Wiki13, MusikAnimal, Software11, Goldenshimmer, Bortingo, Ea91b3dd, BRYCErBryceee, Frommaddie2u, Jodiblomdahl1234, Flo-rek2, Ajv39, Webclient101, Matty.007, Lightrace, Icensnow42, Ricochet Bunny, Nigam Bhattarai, Crystallizedcarbon and Anonymous:115

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43.8. TEXT AND IMAGE SOURCES, CONTRIBUTORS, AND LICENSES 151

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152 CHAPTER 43. XOR GATE

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43.8.3 Content license• Creative Commons Attribution-Share Alike 3.0