Logic Families

CSET 4650 Field Programmable Logic Devices

Dan SolarekDan SolarekDan SolarekDan Solarek

Logic FamiliesLogic FamiliesIntroduction & OverviewIntroduction & Overview

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Logic FamiliesLogic FamiliesLogic Family : A collection of different IC’s that Logic Family : A collection of different IC’s that have similar circuit characteristicshave similar circuit characteristicsThe circuit design of the basic gate of each logic The circuit design of the basic gate of each logic family is the samefamily is the sameThe most important parameters for evaluating and The most important parameters for evaluating and comparing logic families include :comparing logic families include :

Logic Levels Logic Levels Power Dissipation Power Dissipation Propagation delayPropagation delayNoise margin Noise margin Fan-out ( loading )Fan-out ( loading )

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Example Logic FamiliesExample Logic FamiliesGeneral comparison or three commonly available logic General comparison or three commonly available logic families.families.

the most important to understand

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Implementing Logic CircuitsImplementing Logic Circuits

There are several varieties of transistors – the There are several varieties of transistors – the building blocks of logic gates – the most building blocks of logic gates – the most important are:important are:

BJT (bipolar junction transistors)BJT (bipolar junction transistors)one of the first to be inventedone of the first to be invented

FET (field effect transistors)FET (field effect transistors)especially Metal-Oxide Semiconductor types (MOSFET’s)especially Metal-Oxide Semiconductor types (MOSFET’s)

MOSFET’s are of two types: NMOS and PMOSMOSFET’s are of two types: NMOS and PMOS

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Transistor Size ScalingTransistor Size ScalingPerformance improves as size is decreased: shorter switching time, lower power consumption.

2 orders of magnitude reduction in transistor size in 30 years.

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Moore’s LawMoore’s Law

In 1965, Gordon Moore predicted that the number of In 1965, Gordon Moore predicted that the number of transistors that can be integrated on a die would transistors that can be integrated on a die would double every 18 to 14 monthsdouble every 18 to 14 months

i.e., grow exponentially with timei.e., grow exponentially with time

Considered a visionary – million transistor/chip Considered a visionary – million transistor/chip barrier was crossed in the 1980’sbarrier was crossed in the 1980’s

2300 transistors, 1 MHz clock (Intel 4004/4040) - 19712300 transistors, 1 MHz clock (Intel 4004/4040) - 1971

42 Million transistors, 2 GHz clock (Intel P4) - 200142 Million transistors, 2 GHz clock (Intel P4) - 2001

140 Million transistors, (HP PA-8500)140 Million transistors, (HP PA-8500)

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Moore’s Law and IntelMoore’s Law and Intel

From Intel’s 4040 (2300 transistors) to Pentium II (7,500,000 transistors) and beyond

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TTL and CMOSTTL and CMOSConnecting BJT’s together gives rise to a family of logic gates Connecting BJT’s together gives rise to a family of logic gates known as TTLknown as TTL

Connecting NMOS and PMOS transistors together gives rise Connecting NMOS and PMOS transistors together gives rise to the CMOS family of logic gatesto the CMOS family of logic gates

BJTMOSFET

(NMOS, PMOS)

TTL CMOS

transistor types

logic gate families

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Electrical Parameters And Electrical Parameters And Interpretation Of Data SheetsInterpretation Of Data Sheets

Voltages and CurrentsVoltages and Currents

Noise MarginNoise Margin

Power DissipationPower Dissipation

Propagation DelayPropagation Delay

Speed-Power ProductSpeed-Power Product

Fan-In, Fan-OutFan-In, Fan-Out

Comparison of Logic FamiliesComparison of Logic Families

Interpretation of Data SheetsInterpretation of Data Sheets

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Electrical CharacteristicsElectrical Characteristics

TTL TTL faster (some versions)faster (some versions)

strong drive capabilitystrong drive capability

ruggedrugged

CMOSCMOSlower power consumptionlower power consumption

simpler to makesimpler to make

greater packing densitygreater packing density

better noise immunitybetter noise immunity

• Complex IC’s contain many millions of transistors• If constructed entirely from TTL type gates would melt• A combination of technologies (families) may be used• CMOS has become most popular and has had greatest development

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For a High-state gate driving a second gate, we define:For a High-state gate driving a second gate, we define:VVOHOH (min), high-level output voltage, the minimum voltage level that a logic (min), high-level output voltage, the minimum voltage level that a logic

gate will gate will produce as a logic 1 outputproduce as a logic 1 output..

VVIHIH (min), high-level input voltage, the minimum voltage level that a logic (min), high-level input voltage, the minimum voltage level that a logic

gate will gate will recognize as a logic 1 inputrecognize as a logic 1 input. Voltage below this level will not be . Voltage below this level will not be accepted as high.accepted as high.

IIOHOH, high-level output current, current that flows from an output in the logic , high-level output current, current that flows from an output in the logic

1 state under specified load conditions.1 state under specified load conditions.

IIIHIH, high-level input current, current that flows into an input when a logic 1 , high-level input current, current that flows into an input when a logic 1

voltage is applied to that input.voltage is applied to that input.

Voltage & CurrentVoltage & Current

Ground

VIHVOH

I OH I IHTest setup for measuring values

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For a Low-state gate driving a second gate, we For a Low-state gate driving a second gate, we define:define:

VVOLOL (max), low-level output voltage, the maximum voltage level (max), low-level output voltage, the maximum voltage level that a logic gate will that a logic gate will produce as a logic 0 outputproduce as a logic 0 output..VVILIL (max), low-level input voltage, the maximum voltage level (max), low-level input voltage, the maximum voltage level that a logic gate will that a logic gate will recognize as a logic 0 inputrecognize as a logic 0 input. Voltage above . Voltage above this value will not be accepted as low.this value will not be accepted as low.IIOL OL , low-level output current, current that flows from an output in , low-level output current, current that flows from an output in the logic 0 state under specified load conditions.the logic 0 state under specified load conditions.IIIL IL , low-level input current, current that flows into an input when , low-level input current, current that flows into an input when a logic 0 voltage is applied to that input.a logic 0 voltage is applied to that input.

Voltage & CurrentVoltage & Current

Inputs are connected to Vcc instead of Ground

Ground

V ILV OL

I OL I IL

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Electrical CharacteristicsElectrical Characteristics

Important characteristics are:Important characteristics are:

VVOHminOHmin min value of output recognized as a ‘1’ min value of output recognized as a ‘1’

VVIHminIHmin min value input recognized as a ‘1’ min value input recognized as a ‘1’

VVILmaxILmax max value of input recognized as a ‘0’ max value of input recognized as a ‘0’

VVOLmax OLmax max value of output recognized as a ‘0’max value of output recognized as a ‘0’

Values outside the given range are not allowed.Values outside the given range are not allowed.logic 0logic 0

logic 1logic 1

indeterminateindeterminate

input voltageinput voltage

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Typical acceptable voltage ranges for positive logic 1 and logic 0 Typical acceptable voltage ranges for positive logic 1 and logic 0 are shown beloware shown below

A logic gate with an input at a voltage level within the A logic gate with an input at a voltage level within the ‘indeterminate’ range will produce an unpredictable output level.‘indeterminate’ range will produce an unpredictable output level.

Logic Level & Voltage RangeLogic Level & Voltage Range

Logic 1

Logic 0

5.0V

0V

2.5V

Indeterminate

0.8V

TTL

Logic 1

Logic 0

5.0V

Indeterminate

0V

1.5V

CMOS

3.5V

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Noise MarginNoise MarginManufacturers specify voltage limits to represent the logical 0 or 1. These limits are not the same at the input and output sides.

For example, a particular Gate A may output a voltage of 4.8V when it is supposed to output a HIGH but, at its input side, it can take a voltage of 3V as HIGH.

In this way, if any noise should corrupt the signal, there is some margin for error.

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If noise in the circuit is high enough If noise in the circuit is high enough it can push a logic 0 up or drop a it can push a logic 0 up or drop a logic 1 down into the indeterminate logic 1 down into the indeterminate or “illegal” regionor “illegal” regionThe magnitude of the voltage The magnitude of the voltage required to reach this level is the required to reach this level is the noise marginnoise marginNoise margin for logic high is:Noise margin for logic high is:

NNMHMH = V = VOHminOHmin – V – VIHminIHmin

VOHmin

VIHmin

VILmax

VOLmax

logic 0logic 0

logic 1logic 1

indeterminateindeterminate

input voltageinput voltage

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Difference between the worst case output voltage of Difference between the worst case output voltage of one stage and worst case input voltage of next stage one stage and worst case input voltage of next stage

Greater the difference, the more unwanted signal that Greater the difference, the more unwanted signal that can be added without causing incorrect gate can be added without causing incorrect gate operationoperation

NMNMhighhigh = V = VOHminOHmin - V - VIHminIHmin

NMNMlowlow = V = VILmaxILmax - V - VOLmaxOLmax

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Given the following parameters, calculate the Given the following parameters, calculate the noise margin of 74LS series.noise margin of 74LS series.

Parameter 74LSVIH(min) 2V

VIL(max) 0.8V

VOH(min) 2.7V

VOL(max) 0.4V

Solution:High Level Noise Margin, VNH = VOH (min) - VIH (min)=2.7V-2.0V=0.7V

Low Level Noise Margin, VNL = VIL (max) - VOL (max)=0.8V-0.4V=0.4V

Worked ExampleWorked Example

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Noise immunity of a logic circuit refers to the circuit’s ability to Noise immunity of a logic circuit refers to the circuit’s ability to tolerate noise voltages on its inputs. tolerate noise voltages on its inputs. A quantitative measure of noise immunity is called A quantitative measure of noise immunity is called noise noise marginmarginHigh Level Noise Margin, VHigh Level Noise Margin, VNHNH = V = VOHOH (min) - V (min) - VIHIH (min) (min)

Low Level Noise Margin, VLow Level Noise Margin, VNLNL = V = VILIL (max) - V (max) - VOLOL (max) (max)

Noise Margin & Noise ImmunityNoise Margin & Noise Immunity

Logic 1

Logic 0Logic 0

Logic 1VOH (min)

VOL (max)

VIH (min)

VIL (max)

VNH

VNL

Output Voltage Ranges Input Voltage Ranges

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Further Important CharacteristicsFurther Important Characteristics

The The propagation delay propagation delay (t(tpdpd) which is the time ) which is the time

taken for a change at the input to appear at the taken for a change at the input to appear at the outputoutput

The The fan-outfan-out, which is the maximum number of , which is the maximum number of inputs that can be driven successfully to either inputs that can be driven successfully to either logic level before the output becomes invalidlogic level before the output becomes invalid

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Speed: Rise & Fall TimesSpeed: Rise & Fall Times

Rise TimeRise TimeTime from 10% to 90% of signal, Low to HighTime from 10% to 90% of signal, Low to High

Fall TimeFall TimeTime from 90% to 10% of signal, High to LowTime from 90% to 10% of signal, High to Low

rise time

10% 90% 90% 10%

fall time

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A logic gate always takes some time to change statesA logic gate always takes some time to change statesttPLHPLH is the delay time before output changes from low to high is the delay time before output changes from low to high

ttPHLPHL is the delay time before output changes from high to low is the delay time before output changes from high to low

both both ttPLHPLH & & ttPHLPHL are measured between the 50% points on the are measured between the 50% points on the input and output transitionsinput and output transitions

Speed: Propagation DelaySpeed: Propagation Delay

50%Input

Output

0

0tPHL tPLH

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Power DissipationPower Dissipation

StaticStaticII22R losses due to passive components, no input signalR losses due to passive components, no input signal

DynamicDynamicII22R losses due to charging and discharging capacitances R losses due to charging and discharging capacitances through resistances, due to input signalthrough resistances, due to input signal

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Speed (propagation delay) and power consumption Speed (propagation delay) and power consumption are the two most important performance parameters are the two most important performance parameters of a digital IC.of a digital IC.A simple means for measuring and comparing the A simple means for measuring and comparing the overall performance of an IC family is the speed-overall performance of an IC family is the speed-power product (the smaller, the better).power product (the smaller, the better).For example, an IC has For example, an IC has

an average propagation delay of 10 ns an average propagation delay of 10 ns an average power dissipation of 5 mW an average power dissipation of 5 mW the speed-power product = (10 ns) x (5 mW)the speed-power product = (10 ns) x (5 mW)

= 50 picoJoules (pJ)= 50 picoJoules (pJ)

Speed-Power ProductSpeed-Power Product

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Logic Family TradeoffsLogic Family Tradeoffs

Looking for the best Looking for the best speed/power productspeed/power product

ttpp and Pd are normally and Pd are normally

included in the data included in the data sheet for each devicesheet for each device

Older logic families Older logic families are the worstare the worst

CMOS is one of the CMOS is one of the bestbest

FPGAs use CMOSFPGAs use CMOS

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TTL - TTL - ExampleExample SN74LS00 SN74LS00

Recommended operating conditionsRecommended operating conditionsVVcccc supply voltage supply voltage 5V ± 0.5 V5V ± 0.5 V

input voltages input voltages VVIHIH = 2V = 2VVVILIL = 0.8V = 0.8V

Electrical CharacteristicsElectrical Characteristicsoutput voltage output voltage VVOHOH = 2.7V = 2.7V (worst case) (worst case) VVOLOL = 0.5V = 0.5V

max input currentsmax input currents IIIHIH = 20µA = 20µAIIILIL = -0.4mA = -0.4mA

propagation delay propagation delay ttpdpd = 15 nS = 15 nS

noise margins noise margins for a logic 0 = 0.3Vfor a logic 0 = 0.3Vfor a logic 1 = 0.7Vfor a logic 1 = 0.7V

Fan-outFan-out 20 TTL loads20 TTL loads

5 Volt

0 Volt

0.80.5

2.02.7

InputRangefor 1

InputRangefor 0

OutputRangefor 0

OutputRangefor 1

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Fan-InFan-In

Number of input signals to a gateNumber of input signals to a gateNot an electrical propertyNot an electrical property

Function of the manufacturing processFunction of the manufacturing process

NAND gate with a Fan-in of 8

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Fan-OutFan-OutA measure of the ability of the output of one gate to A measure of the ability of the output of one gate to drive the input(s) of subsequent gatesdrive the input(s) of subsequent gatesUsually specified as standard loads within a single Usually specified as standard loads within a single familyfamily

e.g., an input to an inverter in the same familye.g., an input to an inverter in the same family

May have to compute based on current drive May have to compute based on current drive requirements when mixing familiesrequirements when mixing families

Although mixing families is not usually recommendedAlthough mixing families is not usually recommended

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VOH

IIH

Low

VOL

IIL

High

Current Sourcing and SinkingCurrent Sourcing and Sinking

Current-source : the driving gate produces a Current-source : the driving gate produces a outgoing currentoutgoing current

Current-sinking : the driving gate receives an incoming current

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Fan-OutFan-OutAn illustration of fan-out and the associated source An illustration of fan-out and the associated source and sink currentsand sink currents

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How many 74LS00 NAND gate inputs can be driven How many 74LS00 NAND gate inputs can be driven by a 74LS00 NAND gate outputs ?by a 74LS00 NAND gate outputs ?

Solution:Solution:

Refer to data sheet of 74LS00, the maximum values ofRefer to data sheet of 74LS00, the maximum values of

IIOH OH = 0.4mA, = 0.4mA, IIOLOL = 8mA= 8mA, I, IIHIH = 20uA, and = 20uA, and IIILIL = 0.4mA= 0.4mA

Hence,Hence,

fan-out(high) = fan-out(high) = IIOHOH(max) / (max) / IIIHIH (max)=0.4mA/20uA=20(max)=0.4mA/20uA=20

fan-out(low) = fan-out(low) = IIOLOL(max) / (max) / IIILIL(max)=8mA/0.4mA=20,(max)=8mA/0.4mA=20,

the overall fan-out = fan-out(high) or fan-out(low) whichever is lower. the overall fan-out = fan-out(high) or fan-out(low) whichever is lower.

Hence, overall fan-out = 20Hence, overall fan-out = 20

Worked ExampleWorked Example

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A logic gate can supply a maximum A logic gate can supply a maximum outputoutput current currentIIOHOH(max), in the high state or(max), in the high state or

IIOLOL(max), in the low state(max), in the low state

A logic gate requires a maximum A logic gate requires a maximum inputinput current currentIIIHIH(max), in the high state or(max), in the high state or

IIILIL(max), in the low state(max), in the low state

Ratio of output and input current decide how many logic Ratio of output and input current decide how many logic gates can be driven by a logic gategates can be driven by a logic gate

fan-out(high) = Ifan-out(high) = IOHOH(max) / I(max) / IIH IH (max)(max)

fan-out(low) = Ifan-out(low) = IOLOL(max) / I(max) / IILIL(max)(max)overall fan-out = fan-out(high) or fan-out(low) whichever is loweroverall fan-out = fan-out(high) or fan-out(low) whichever is lower

A typical figure of fan-out is ten (10)A typical figure of fan-out is ten (10)

Gate Drive Capability: Fan-OutGate Drive Capability: Fan-Out

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Wired-ANDWired-ANDOpen collector outputs connected together to a common pull-Open collector outputs connected together to a common pull-up resistorup resistor

Any collector can pull the signal line lowAny collector can pull the signal line low

Logically an AND gateLogically an AND gate

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Tri-State LogicTri-State Logic

Both output transistors of totem-pole output are turned off Both output transistors of totem-pole output are turned off

Usually used to bus multiple signals on the same wireUsually used to bus multiple signals on the same wire

Gates not enabled present high-Z to bus and therefore do Gates not enabled present high-Z to bus and therefore do not interfere with other gates putting signals on the busnot interfere with other gates putting signals on the bus

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Tri-State LogicTri-State Logic

Tri-state logic includes a switch at the outputTri-state logic includes a switch at the output

In the figure below, the three states are illustrated:In the figure below, the three states are illustrated:a)a) Logic High outputLogic High output

b)b) Logic Low outputLogic Low output

c)c) High impedance (Hi-Z) outputHigh impedance (Hi-Z) output

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Electronic Combinational LogicElectronic Combinational LogicWithin each of these families there is a large variety of different devicesWithin each of these families there is a large variety of different devices

We can break these into groups based on the number gates per deviceWe can break these into groups based on the number gates per device

AcronymAcronym DescriptionDescription No GatesNo Gates ExampleExample

SSISSI Small-scale integrationSmall-scale integration <12<12 4 NAND gates4 NAND gates

MSIMSI Medium-scale integrationMedium-scale integration 12 – 10012 – 100 AdderAdder

LSILSI Large-scale integrationLarge-scale integration 100 – 1000100 – 1000 68006800

VLSIVLSI Very large-scale integrationVery large-scale integration 1000 – 1M1000 – 1M 6800068000

ULSIULSI Ultra large scale integrationUltra large scale integration > 1M> 1M 80486/8058680486/80586

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SSI DevicesSSI Devices

Each package contains a code identifying the packageEach package contains a code identifying the package

N74LS00

Manufacturers Code

N = National SemiconductorsSN = Signetics

Specification

FamilyLLSH

Member00 = Quad 2 input NAND02 = Quad 2 input Nor04 = Hex Invertors20 = Dual 4 Input NAND

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7400 Series History7400 Series History

1960s space program drove 1960s space program drove development of 7400 seriesdevelopment of 7400 series

Consumed all available devices for Consumed all available devices for internal flight computerinternal flight computer

$1000 / device (1960 dollars)$1000 / device (1960 dollars)

10:1 integration improvement over 10:1 integration improvement over discrete transistorsdiscrete transistors

1963 Minuteman missile forced 1963 Minuteman missile forced 7400 into mass production7400 into mass production

Drove pricing down to $25 / circuit Drove pricing down to $25 / circuit (1963 dollars)(1963 dollars)

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7400 Series Evolution7400 Series EvolutionBJT storage time reduction by using a BC Schottky diode.

Schottky diode has a Vfw=0.25V. When BC junction becomes forward biased Schottky diode will bypass base current.

B

C

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Too Much of a Good Thing?Too Much of a Good Thing?FamiliesFamilies

PackagesPackages

Reliability optionsReliability options

Speed gradesSpeed grades

FeaturesFeatures

FunctionsFunctions

An availability nightmare! >> 500K unique devices

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Different Families Don’t all Speak Different Families Don’t all Speak the Same Languagethe Same Language

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Sometimes Things Get Lost or Sometimes Things Get Lost or Added in the Translation*Added in the Translation*

Different families aren’t always on speaking terms with one another

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The World of TTLThe World of TTL

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Success Drives ProliferationSuccess Drives Proliferation

New families introduced based on New families introduced based on Higher performanceHigher performanceLower powerLower powerNew featuresNew featuresNew signaling thresholdNew signaling threshold

Spawned over 32 unique families!Spawned over 32 unique families!

19602003

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Success Drives ProliferationSuccess Drives ProliferationProducts introduced in the 1960 Products introduced in the 1960 are near the end of their life are near the end of their life cyclecycle

Decreasing supplier baseDecreasing supplier baseIncreasing pricesIncreasing pricesNot recommended for new Not recommended for new designsdesigns

Products considered to be Products considered to be “mature” are about 2 decades “mature” are about 2 decades into their life cycleinto their life cycle

High-volume productionHigh-volume productionMultiple suppliersMultiple suppliersLow pricesLow prices

Newer products are only a few Newer products are only a few years into their life cycleyears into their life cycle

High performanceHigh performanceHigh level of vendor and High level of vendor and supplier supportsupplier supportNewest technologiesNewest technologiesHigher pricesHigher prices

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Characteristics: TTL and MOSCharacteristics: TTL and MOS

TTL stands for Transistor-Transistor LogicTTL stands for Transistor-Transistor Logicuses BJTsuses BJTs

MOS stands for Metal Oxide SemiconductorMOS stands for Metal Oxide Semiconductoruses FETsuses FETs

MOS can be classified into three sub-families:MOS can be classified into three sub-families: PMOS (P-channel)PMOS (P-channel)

NMOS (N-channel)NMOS (N-channel)

CMOS (Complementary MOS, most common)CMOS (Complementary MOS, most common)

Remember:Remember:

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AB Y O/P

+Vcc

Q1

Q 2

Q3

Q4

4K 1.6K 130R1 R2

R3

R4

1K

I CQ1

D 3

D1 D2

A B ICQ1 Q1 Q2 Q3 Q4 Y O/P

0 0 + ON OFF OFF ON 1



1 1 － OFF ON ON OFF 0

A standard TTL NAND gate circuit

Table explaining the operation of the TTL NAND gate circuit

TTL Circuit OperationTTL Circuit Operation

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Transistor-Transistor Logic FamiliesTransistor-Transistor Logic Families

TTransistor-ransistor-TTransistor ransistor LLogic Families:ogic Families:

74L74L LLow powerow power

74H74H HHigh speedigh speed

74S74S SSchottkychottky

74LS74LS LLow power ow power SSchottkychottky

74AS74AS AAdvanced dvanced SSchottkychottky

74ALS 74ALS AAdvance dvance LLow power ow power SSchottkychottky

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+VDD

O/P

I/P

S

D

D

S

Q

Q

1

2

I / P Q1 Q2 O / P

0 O N O F F 1

1 O F F O N 0

Table explaining the operation of the CMOS inverter circuit

A CMOS inverter circuit

MOS Circuit OperationMOS Circuit Operation

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CMOS Logic FamiliesCMOS Logic Families

CMOS Logic FamiliesCMOS Logic Families4040xx/45xxxx/45xx Metal-gate CMOSMetal-gate CMOS

74C74C TTL-compatible TTL-compatible CCMOSMOS

74HC74HC HHigh speed igh speed CCMOSMOS

74ACT74ACT AAdvanced dvanced CCMOS -MOS -TTTL TL compatiblecompatible

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CMOS Family EvolutionCMOS Family Evolution

CMOS Logic Trend: Reduction of dynamic losses (cross-conduction, capacitive charge/discharge cycles) by decreasing supply voltages:

12V→5V →3.3V →2.5V → 1.8V → 1.5V …

Reduction of IC power dissipation is the key to:lower cost (packaging)

higher integration

improved reliability

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vi

vo

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Comparison Logic FamiliesComparison Logic Families

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speed power product = a constant

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Logic Families