Question 1iii)module mux (y, a, b ,c ,d, s0, s1);

input a,b,c,d,s0,s1;output y;assign y = (s1)? ((s0)? d:c):((s0)? b:a);

endmodule

iv)library IEEE;use IEEE.std_logic_1164.all;

entity mux4 is port(a,b,c,d,s1,s0: in std_logic;y: out std_logic

);end mux4;

architecture sequential of mux4 isbegin

process (a,b,c,d,s1,s0) isbegin

if(s1 = '1') thenif (s0 = '1') then

y

y: out std_logic); end component;

signal temp : std_logic_vector (3 downto 0);begin

stage1_mux1 : mux4 port map (a => x[0], b=> x[1], c => x[2], d=>x[3], s1=>s[1], s0=>s[0], y => temp[0]);

stage1_mux2 : mux4 port map (a => x[4], b=> x[5], c => x[6], d=>x[7], s1=>s[1], s0=>s[0] y => temp[1]);

stage1_mux3 : mux4 port map (a => x[8], b=> x[9], c => x[10], d=>x[11], s1=>s[1], s0=>s[0], y => temp[2]);

stage1_mux4 : mux4 port map (a => x[12], b=> x[13], c => x[14], d=>x[15], s1=>s[1], s0=>s[0], y => temp[3]);

stage2 : mux4 port map (a => temp[0], b=> temp[1], c => temp[2], d=>temp[3], s1=>s[3], s0=>s[2]);

end structural;

Note: Also draw the block digram using 5 4-1 muxes

b)iii)module decoder2 (x,en,y)

input en;input [1:0] x;output reg [3:0] y;

wire [2:0] select;

assign select = {en,x};always@(*)

case (select)3'b100: y = 4'b0001;3'b101: y = 4'b0010;3'b110: y = 4'b0100;3'b111: y = 4'b1000;default:y = 4'b0000;

endcaseendmodule

iv) draw the block diagram following code

v) module decoder4 (x,en,y)input en;input [3:0] x;output [15:0] y;

wire [3:0 ]temp;

decoder2 stage1_decoder (.x(x[3:2]),.en(en),.y(temp)

);

decoder2 stage2_decoder1 (.x(x[1:0]),.en(temp[0]),.y(y[3:0])

);

decoder2 stage2_decoder2 (.x(x[1:0]),.en(temp[1]),.y(y[7:4])

);

decoder2 stage1_decoder3 (.x(x[1:0]),.en(temp[2]),.y(y[11:8])

);

decoder2 stage1_decoder4 (.x(x[1:0]),.en(temp[3]),.y(y[15:12])

);

endmodule

Question 2:b) Any combination circuit can be described using when else. Which can be implemented using multipliers arranged by the priority of the input. Give a code example too with a block diagram of any circuit.

e)i) 4'b1001 & (5'b10010 | 5'b11010) = 4'b1001 & (5'b11010) = 5'b01000ii) ~(5'b10010) = 5'b01101iii) (4'b1001

Question 3

a) entity dff is port (

d,clk,reset: in std_logic;q: out std_logic

);end dff;architecture behavioral of dff isbegin

process (clk,reset) begin

if (reset = '1') thenq

tcu

process(state)begin

case state iswhen s0 =>

z

z

z