9
Rise and rise again until lambs become lions 授授授授 授授授 授授授授 授授授授 授授授 :、

Logic Design LAB 9

Embed Size (px)

DESCRIPTION

Logic Design LAB 9. 授課老師:伍紹勳 課程助教:邱麟凱、江長庭. Outline. Generate clock by IC 555 oscillator Implement count up counter by JK flip-flop 7476 JK flip-flop count up counter. Requirement. - PowerPoint PPT Presentation

Citation preview

Page 1: Logic Design LAB 9

Rise and rise again until lambs become lions

授課老師:伍紹勳課程助教:邱麟凱、江長庭

Page 2: Logic Design LAB 9

Rise and rise again until lambs become lions

Outline

Generate clock by IC 555 oscillatorImplement count up counter by JK flip-flop– 7476 JK flip-flop– count up counter

Page 3: Logic Design LAB 9

Rise and rise again until lambs become lions

Requirement

220Ω電阻 x 4 、 7476 x 2 、 7400(NAND) x 1(buffer) 、 LED x 4 、 7476 x 2 、 555x1 、電阻470KΩx2( 黃紫黃 )、電解電容 1μF x1

Page 4: Logic Design LAB 9

Rise and rise again until lambs become lions

555 oscillator

Refer to exp.11 555 Calculator (Website)

Frequency=1:44

(R1+2£ R2) £ C

Page 5: Logic Design LAB 9

Rise and rise again until lambs become lions

555 oscillator

You can connect output of 555 to a buffer– Oscillator would be more stable– E.g. connect output of 555 to an inverter or AND output

of 555 with signal 1

Electrolytic capacitor( 電解電容 )– With polarity (long pin should connect to VCC)

+

-

Page 6: Logic Design LAB 9

Rise and rise again until lambs become lions

7476 Dual Master-Slave J-K Flip-Flops with Clear, Preset, and Complementary Outputs

Falling-edge Trigger JK Flip-Flop

Reset

Preset

Toggle

Page 7: Logic Design LAB 9

Rise and rise again until lambs become lions

Count up counter

0000

0001

0010

0011

0100

20: 0->1 (Toggle)

20: 1->0 (Toggle), carry to next digit

20: 0->1 (Toggle)

20: 1->0 (Toggle), carry to next digit

21: 0->1 (Toggle)

21: 1->0 (Toggle), carry to next digit22: 0->1 (Toggle)

Page 8: Logic Design LAB 9

Rise and rise again until lambs become lions

4-bits output– output=input+1 at falling edge

Count up counter

0000 0001

1111

0010 0011 0100

1100 1011 1010 1001 1000

0101

0110

0111

1110

1101

+1

Page 9: Logic Design LAB 9

Rise and rise again until lambs become lions

Count up counter

題外話 : 在設計電路時,應盡可能遵守只用 ”單一時脈”及”不要把時脈拿來做邏輯運算”二個原則,以免產生不必要的 Bug 。 ( 除非很有把握電路不會出錯 )