Logic Circuits II ECE 2411

Thursday 4:45pm-7:20pm

Lecture 4

Lecture 4

• Topics:

– HW1

– Schedule

– Chapter 5

HW1 • 1.10 Convert the following binary number to hex and decimal:

(a) 1.100102 = 0001.10012 = 1.916 = 1 + 9/16 = 1.56310

(b) 110.0102 = 0110.01002 = 6.416 = 6 + 4/16 = 6.2510

• 1.14 Obtain the 1’s and 2’ complements of the following binary numbers:

• 1.18 Preform subtraction on the given unsigned binary numbers using 2’s complement of the subtrahend. Where the results should be negative, find

the 2’s complement and affix a minus sign.

HW1 • 1.35 By means of the timing diagram similar to fig. 1.5, show the signals of the outputs of f and g in fig. p1.35 as func. Of the three inputs a, b, and c.

Use all eight possible combinations of a, b, and c.

• 2.11) List the truth table of the functions:

• a) F = xy + xy’ + y’z

• b) F = bc = a’c’

• 2.19) Express the following func as a sum of minterms

and as a product of sums: F(A, B, C, D) = B’D + A’D + BD

HW1 • 2.27) Write the Boolean eq. and draw the logic diagram of the circuit whose outputs are defined by the following truth table:

f1 f2 a b c

1 1 0 0 0

0 1 0 0 1

1 0 0 1 0

1 1 0 1 1

1 0 1 0 0

0 1 1 0 1

1 0 1 1 1

HW1

HW1

HW1 • 3.32) Using continuous assignment statements, write a Verilog description of the circuit shown in:

a) fig. 3.20(a)

b) fig. 3.20(b)

c) fig. 3.21(a)

d) fig 3.21(b)

e) fig. 3.24

f) fig. 3.25

HW1

• Convert 6.425 to IEEE754 format

Definitions

• Instantiate

– To instantiate is to create an instance of an object

– Each instance created by instantiation will be unique

– The module is the basic unit of hierarchy in Verilog

– Lower level modules can be instantiated within the upper one

Section 5.5 • 0-detector

– Asserts output when 0 is detected in a stream of 1’s.

Section 5.5 • A(t+1) = A’Bx + AB’x + ABx

= x(A’B + AB’ + AB)

= x(A’B + AB’ + AB + AB) Theorem 1a: x = x + x

= x((A’B + AB) + (AB’ + AB))

= x(B(A’+ A) + A(B’ + B)) Postulate 5a: 1 = x + x’

= x(B + A)

• B(t+1) = A’Bx + A’Bx

= x(A’B’ + A’B)

= x(A’(B’ + B))

= xA’

• y(t) = A’Bx’ + AB’x’ + ABx’

= x’(A’B + AB’ + AB + AB)) Theorem 1a: x = x + x

= x’((A’B + AB) + (AB’ + AB))

= x’(B(A’+ A) + A(B’ + B)) Postulate 5a: 1 = x + x’

= x’(B + A)

Section 5.5 • From previous page:

• A(t+1) = x(B + A) = xB + xA

• B(t+1) = xA’

• y(t) = x’(B + A)

Not sure what this y is for

module figure5p15_book(input x, Clock, output y_seq, y_comb); reg A, B; wire DA, DB; assign y_comb = (A||B) && !x; assign y_seq = A || B || !x; assign DA = (A && x) || (x && B); assign DB = !A && x; always @(posedge Clock) begin A <= DA; B <= DB; end endmodule // figure5p15_book

Section 5.5

Section 5.5 module figure5p16(input x, Clock, output reg y_sd); reg [1:0] current_state = 2'b00, next_state = 2'b00; always @(posedge Clock) current_state <= next_state; always @(*) begin case({current_state[1:0], x}) 3'b000: begin next_state = 2'b00; y_sd = 0; end 3'b001: begin next_state = 2'b01; y_sd = 0; end 3'b010: begin next_state = 2'b00; y_sd = 1; end 3'b011: begin next_state = 2'b11; y_sd = 0; end 3'b100: begin next_state = 2'b00; y_sd = 1; end 3'b101: begin next_state = 2'b10; y_sd = 0; end 3'b110: begin next_state = 2'b00; y_sd = 1; end 3'b111: begin next_state = 2'b10; y_sd = 0; end endcase // case (current_state[1:0], x) end // always @ (*) endmodule // figure5p16

Section 5.5

Finite State Machines • Mealy FSM:

– The output is a function of both the present state and the input

• Moore FSM:

– The output is a function of the present state only

Mealy FSM

Moore FSM

State Reduction • State Reduction Algorithm:

– Two states are said to be equivalent if, for each member of the set of inputs, they give the exactly the same output and send the circuit either to the same state or to an equivalent state

– When two state are equivalent, one of them can be removed without altering the input-output relationship

State Reduction

State Reduction

State Assignment

# of FFs 3 3 5

State Assignment

Other assignment options

– One Cold

• Assign a single “0” for each state 1110, 1101, 1011, 0111

– Almost One Hot encoding (zero-idle)

• Use no-hot (000…0) for the initial/reset state

– Johnson

State Assignment // Binary Encoding parameter definitions parameter [1:0] IDLE = 2’b00, S1 = 2’b01, S2 = 2’b10, S3 = 2’b11;

// One Hot Encoding parameter definitions parameter [3:0] IDLE = 4’b0001, S1 = 4’b0010, S2 = 4’b0100, S3 = 4’b1000;

// One Cold Encoding parameter definitions parameter [3:0] IDLE = 4’b1110, S1 = 4’b1101, S2 = 4’b1011, S3 = 4’b0111;

// Gray Code Encoding parameter definitions parameter [1:0] IDLE = 2’b00, S1 = 2’b01, S2 = 2’b11, S3 = 2’b10;

FSM coding styles

• Many ways are possible

• Two common ways are:

– Two always blocks

• One for sequential logic

• One for combinational logic

– One always block

• Two always block is easiest to implement and understand and will be discuss here.

Two always blocks • Sequential always block

• Combinational always block // Next State Case always @(*) begin next_state = 2’b00; case (state) IDLE: begin if (!in1) next = IDLE; if (in1 & in2) next = S1; if (in1 & !in2 & in3) next = S2; end S1: …

// State Register always @(posedge clk or posedge reset) if (reset) state <= IDLE; else state <= next_state;

FSM Output Generation

• Code the output logic as either a separate block of continuous assignments or within the combinational always block

// Mealy Outputs assign y = ((state == S1) || (state == S2) || (state == S3)) && !x;

always @(*) begin case({current_state[1:0], x}) 3'b000: begin next_state = 2'b00; y_sd = 0; end 3'b001: begin next_state = 2'b01; y_sd = 0; end 3'b010: begin next_state = 2'b00; y_sd = 1; end 3'b011: begin next_state = 2'b11; y_sd = 0; end … endcase // case (current_state[1:0], x) end // always @ (*)