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Logic Circuits and Computer Architecture. Appendix A Digital Logic Circuits Part 2:Combinational and Sequential Circuits. Combinational circuits. Each of the m outputs can be expressed as function of n input variables Truth table has: n input columns m output columns - PowerPoint PPT Presentation
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RLAC (2008-09) by Luciano Gualà 1A -
Logic Circuits and Computer Architecture
Appendix ADigital Logic Circuits
Part 2: Combinational andSequential Circuits
RLAC (2008-09) by Luciano Gualà 2A -
Combinational circuits
• Each of the m outputs can be expressed as function of n input variables
• Truth table has: n input columns m output columns 2n rows (all possible input combinations)
RLAC (2008-09) by Luciano Gualà 3A -
Binary Adder
Combinational Circuit
a3 a2 a1 a0b3 b2 b1 b0
c3 c2 c1 c0c4
A=a3a2a1a0
B=b3b2b1b0
C=c4c3c2c1c0 : the sum of A and B
RLAC (2008-09) by Luciano Gualà 4A -
Seven-segment decoder
abcdefg
a
b
c
d
e
fg
ABCD
A=0 B=0 C=0 D=0
A=0 B=1 C=1 D=1
CombinationalCircuit
It converts a 4-bit binary-coded decimal (BCD) value into the code required to drive a seven-segment display
RLAC (2008-09) by Luciano Gualà 5A -
The truth table
RLAC (2008-09) by Luciano Gualà 6A -
Design Procedure
1. Specification Write a specification for the circuit if one is not
already available
2. Formulation Derive a truth table or initial Boolean equations that
define the required relationships between the inputs and outputs, if not in the specification
Apply hierarchical design if appropriate
3. Optimization Apply 2-level and multiple-level optimization Draw a logic diagram or provide a netlist for the
resulting circuit using ANDs, ORs, and inverters
RLAC (2008-09) by Luciano Gualà 7A -
Design Procedure
4. Technology Mapping Map the logic diagram or netlist to the
implementation technology selected
5. Verification Verify the correctness of the final design
manually or using simulation
RLAC (2008-09) by Luciano Gualà 8A -
Design Example
1. Specification BCD to Excess-3 code converter Transforms BCD code for the decimal digits to
Excess-3 code for the decimal digits BCD code words for digits 0 through 9: 4-bit
patterns 0000 to 1001, respectively Excess-3 code words for digits 0 through 9: 4-
bit patterns consisting of 3 (binary 0011) added to each BCD code word
Implementation: • multiple-level circuit
RLAC (2008-09) by Luciano Gualà 9A -
Design Example (continued)
2. Formulation Conversion of 4-bit codes can be most easily
formulated by a truth table Variables
- BCD: A,B,C,D
Variables- Excess-3 W,X,Y,Z
Don’t Cares- BCD 1010 to 1111
Input BCD A B C D
Output Excess-3 WXYZ
0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 0 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 0 0 1 1 1 0 1 0 1 1 0 0 0 0 1 1 0 1 0 0 1 0 1 1 1 1 0 1 0 1 0 0 0 1 0 1 1 1 0 0 1 1 1 0 0
RLAC (2008-09) by Luciano Gualà 10A -
Design Example (continued)
3. Optimizationa. 2-level using
K-mapsW = A + BC + BD
X = B’C + B’D + BC’D’
Y = CD + C’D’
Z = D’
B
C
D
A
0 1 3 2
4 5 7 6
12 13 15 14
8 9 11 10
1
11
1
X X X
X X
X
1
B
C
D
A
0 1 3 2
4 5 7 6
12 13 15 14
8 9 11 10
1
11
1
X X X
X X
X
1
B
C
D
A
0 1 3 2
4 5 7 6
12 13 15 14
8 9 11 10
1 1
1
1
X X X
X X
X
1
B
C
D
A
0 1 3 2
4 5 7 6
12 13 15 14
8 9 11 10
1 1
1
X X X
X X
X
1
1
w
z y
x
RLAC (2008-09) by Luciano Gualà 11A -
Design Example (continued)
3. Optimization (continued)b. Multiple-level optimization: we start from
W = A + BC + BDX = C + D + BY = CD + Z = G = 7 + 10 + 6 + 0 = 23
…and we obtain:W = A + BT
X = B’T + BC’D’ where T = C + D
Y = CD + C’D’
Z = D’ G = 19
B CDBCD
D
RLAC (2008-09) by Luciano Gualà 12A -
Design Example (continued)
A
B
CD
W
X
Y
Z
RLAC (2008-09) by Luciano Gualà 13A -
Beginning Hierarchical Design
• To control the complexity of the function mapping inputs to outputs: Decompose the function into smaller pieces called blocks Decompose each block’s function into smaller blocks,
repeating as necessary until all blocks are small enough Any block not decomposed is called a primitive block The collection of all blocks including the decomposed ones
is a hierarchy• Example: comparison circuit for 4-bit words
Specification: Input: vectors A(3:0) and B(3:0); Ai Bi: i-th element of A and
B, respectively Output: a variable E; E=1 if and only if A=B Formulation: is it convenient to derive the truth table?
RLAC (2008-09) by Luciano Gualà 14A -
E
A0A1A2A3
B0
B2B3
B1
Ni=0 iff Ai=Bi
RLAC (2008-09) by Luciano Gualà 15A -
Reusable Functions
• Whenever possible, we try to decompose a complex design into common, reusable function blocks
• These blocks are verified and well-documented placed in libraries for future use
RLAC (2008-09) by Luciano Gualà 16A -
Top-Down versus Bottom-Up
• A top-down design proceeds from an abstract, high-level specification to a more and more detailed design by decomposition and successive refinement
• A bottom-up design starts with detailed primitive blocks and combines them into larger and more complex functional blocks
RLAC (2008-09) by Luciano Gualà 17A -
Functions and Functional Blocks
• The functions considered are those found to be very useful in design
• Corresponding to each of the functions is a combinational circuit implementation called a functional block
• In the past, functional blocks were packaged as small-scale-integrated (SSI), medium-scale integrated (MSI), and large-scale-integrated (LSI) circuits.
• Today, they are often simply implemented within a very-large-scale-integrated (VLSI) circuit.
RLAC (2008-09) by Luciano Gualà 18A -
Real circuits
74LS00 - has four 2-input NAND gates Small scale integration (SSI)
RLAC (2008-09) by Luciano Gualà 19A -
Integrated circuits
• Scales of integration
• (Small) SSI: 1-10 gates• (Medium) MSI: 10-100 gates• (Large) LSI: 100-100.000 gates• (Very Large) VLSI: > 100.000 gates
RLAC (2008-09) by Luciano Gualà 20A -
Decoder (n-to-2n)
• Convert n inputs to exactly one of 2n outputsi.e., given an n-bit value i in input the decoder activates only the i-th output line
decoder2-to-4
20
21
0123
A0
A1
D0
D1
D3
D2
An example
RLAC (2008-09) by Luciano Gualà 21A -
Decoder Examples
A1
0
0
1
1
A0
0
1
0
1
D0
1
0
0
0
D1
0
1
0
0
D2
0
0
1
0
D3
0
0
0
1
(a)
D0 A1 A0
D1 A1 A0
D2 A1 A0
D3 A1 A0
(b)
A1
A0
1-to-2 decoder
2-to-4 decoder
A D0 D1
0 1 01 0 1 D1 AA
D0 A
RLAC (2008-09) by Luciano Gualà 22A -
A 3-to-8 decoder
RLAC (2008-09) by Luciano Gualà 23A -
abcd
equivalent toa b c d
Inpu
ts
A2
A1
A0
D0 D1 D7
3-to-8 decoder
abcd
equivalent toa b c d
…
RLAC (2008-09) by Luciano Gualà 24A -
A different circuit for a 3-to-8 decoder
3-to-8 Line decoder
1-to-2-Line decoders
4 2-input ANDs 8 2-input ANDs
2-to-4-Linedecoder
D0A 0
A 1
A 2
D1
D2
D3
D4
D5
D6
D7
RLAC (2008-09) by Luciano Gualà 25A -
Decoder Expansion
• General procedure for building a decoder with n inputs and 2n outputs
• This procedure builds a decoder backward from the outputs
• We take 2n 2-input AND gates (output AND gates)• The output AND gates are driven by two decoders
with their numbers of inputs either equal or differing by 1
• These decoders are then designed using the same procedure until 1-to-2-line decoders are reached
RLAC (2008-09) by Luciano Gualà 26A -
Decoder Expansion - Example 1
• 3-to-8-line decoder Number of output ANDs = 8 Number of inputs to decoders driving output ANDs = 3 Closest possible split to equal
• 2-to-4-line decoder• 1-to-2-line decoder
2-to-4-line decoder• Number of output ANDs = 4• Number of inputs to decoders driving output ANDs = 2• Closest possible split to equal
Two 1-to-2-line decoders
RLAC (2008-09) by Luciano Gualà 27A -
Decoder Expansion - Example 2
• 6-to-64-line decoder Number of output ANDs = 64 Number of inputs to decoders driving output ANDs =
6 Closest possible split to equal
• two 3-to-8-line decoders 3-to-8-line decoder
• Number of output ANDs = 8• Number of inputs to decoders driving output ANDs = 3• Closest possible split to equal
2-to-4-line decoder 1-to-2-line decoder
…
RLAC (2008-09) by Luciano Gualà 28A - G= 0 + 16 + 32 + 128 = 176
cost of a 2-level circuit: G= 64 * 6= 384
RLAC (2008-09) by Luciano Gualà 29A -
• See truth table below for function Note use of X’s to denote both 0 and 1 Combination containing two X’s represent four binary
combinations
Decoder with Enable
EN A1 A0 D0 D1 D2 D3
01111
X0011
X0101
01000
00100
00010
00001
RLAC (2008-09) by Luciano Gualà 30A -
S1
S0
E
RLAC (2008-09) by Luciano Gualà 31A -
3-to-8 decoder from two 2-to-4 decoders with enable
decoder2-to-4
20
21
0123
Enable
decoder2-to-4
20
21
0123
Enable
A0
A1
A2
D0
D1
D3
D2
D4
D5
D7
D6
RLAC (2008-09) by Luciano Gualà 32A -
Combinational Logic Implementation- Decoder and OR Gates
• Implement m functions of n variables with: Sum-of-minterms expressions One n-to-2n-line decoder m OR gates, one for each output
• Approach 1: Find the truth table for the functions Make a connection to the corresponding OR
from the corresponding decoder output wherever a 1 appears in the truth table
• Approach 2 Find the minterms for each output function OR the minterms together
RLAC (2008-09) by Luciano Gualà 33A -
Decoder and OR Gates Example
0 1 2 3 4 5 6 7 8 9101112131415
A0
A1
A2
A3
F1
F3
F2
Finding sum ofminterms expressions
F1 = m (1,2,5,6,8,11,12,15)F2 = m (1,3,4,6,8,10,13,15)F3 = m (2,3,4,5,8,9,14,15)
RLAC (2008-09) by Luciano Gualà 34A -
Exercise
• Use a decoder and or gates to build a combinatorial circuit with INPUT: 3 boolean variables OUTPUT: the number of 1s in the input
(expressed in binary)
RLAC (2008-09) by Luciano Gualà 35A -
Solution: Truth Table
A0 A1 A2 D1 D0
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
RLAC (2008-09) by Luciano Gualà 36A -
Solution: the implementation
D1 D0
A0
A1
A2
OR Gates
RLAC (2008-09) by Luciano Gualà 37A -
Encoding
• Encoding - the opposite of decoding - the conversion of an m-bit input code to a n-bit output code with n m 2n such that each valid code word produces a unique output code
• Circuits that perform encoding are called encoders• An encoder has 2n (or fewer) input lines and n output
lines which generate the binary code corresponding to the input values
• Typically, an encoder converts a code containing exactly one bit that is 1 to a binary code corresponding to the position in which the 1 appears.
RLAC (2008-09) by Luciano Gualà 38A -
a truth table for a 8-to-3 encoder
A2 = D4 + D5 + D6 + D7
A1 = D2 + D3 + D6 + D7
A0 = D1 + D3 + D5 + D7
RLAC (2008-09) by Luciano Gualà 39A -
Encoder Example
• A decimal-to-BCD encoder Inputs: 10 bits corresponding to decimal
digits 0 through 9, (D0, …, D9) Outputs: 4 bits with BCD codes Function: If input bit Di = 1, then the output
(A3, A2, A1, A0) is the BCD code for i
• Exercise: design and realize it
RLAC (2008-09) by Luciano Gualà 40A -
Priority Encoder
• An encoder has two drawbacks: If more than one input value is 1, then the
encoder just designed does not work if all inputs are 0, the encoder responds as
when D0=1
• Priority encorder Among the 1s that appear, it selects the
most significant input position (or the least significant input position) containing a 1 and responds with the corresponding binary code for that position
RLAC (2008-09) by Luciano Gualà 41A -
Priority encoder with 4 inputs
V=1 iff at least one input is 1
Xs in input part of table represent 0 or 1; thus table entries correspond to product terms instead of minterms
RLAC (2008-09) by Luciano Gualà 42A -
RLAC (2008-09) by Luciano Gualà 43A -
• Selecting of data or information is a critical function in digital systems and computers
• Circuits that perform selecting have: A set of information inputs from which the
selection is made A single output A set of control lines for making the
selection
• Logic circuits that perform selecting are called multiplexers
Selecting
RLAC (2008-09) by Luciano Gualà 44A -
Multiplexer (Mux) 2n-to-1
• 2n data inputs -- 1 output• n controls, to select one of the inputs to
be “sent” to the outputExample: 4-to-1 mux Truth table
Logic symbol
S1 S0 F
0 0 D0
0 1 D1
1 0 D2
1 1 D3
RLAC (2008-09) by Luciano Gualà 45A -
Logic circuit for a 4-to-1 Mux
RLAC (2008-09) by Luciano Gualà 46A -
Example: 4-to-1-line Multiplexer
S1Decoder
S0
Y
S1Decoder
S0
Y
Enabling circuits
S1Decoder
S0
F
2
3
1
D0
D
D
D
RLAC (2008-09) by Luciano Gualà 47A -
Exercise
• Consider a 2-to-1 multiplexer: 2 data inputs: D0 and D1
1 control input: S0
1 data output: F
• Write Truth table Logic circuits which implements it
• Extend it to deal with 4 bits at a time
RLAC (2008-09) by Luciano Gualà 48A -
2-to-1 mux
S
D0
1
F
D
S F
0 D0
1 D1
D0
D1
S
F
RLAC (2008-09) by Luciano Gualà 49A -
Quadruple 2-to-1 mux (with enable)
RLAC (2008-09) by Luciano Gualà 50A -
How to use multiplexers to implement functions
• 2n-to-1 mux for a n-variable function
A B C F
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1
0
A
F
BC
1100011
RLAC (2008-09) by Luciano Gualà 51A -
How to use multiplexers to implement functions
• 2n-1-to-1 mux for a n-variable function
A B C F
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1A
F
B
C
0
1
F=C
F=C’
F=0
F=1
C’
RLAC (2008-09) by Luciano Gualà 52A -
De-multiplexer (Demux)
• 1 input -- 2n data outputs --• n controls, to select exactly one of the
outputs to “receive” the inputExample: 1-to-4 demux
input: E, controls: S0 , S1
outputs: D0 , D1 , D2 , D3
Truth table
S0 S1 D0
D1
D2
D3
0 0 E
1 0 E
0 1 E
1 1 E
RLAC (2008-09) by Luciano Gualà 53A -
Logic circuit for a 1-to-4 Demux
It is equal to a decoder with enableSometimes it is called decoder/demultiplexer
RLAC (2008-09) by Luciano Gualà 54A -
Programmable Logic Device (PLD)
• What is a PLD? A circuit that can be “programmed” after the
manufacturing process
• Why PLD? A PLD can be:
• made in large volumes• programmed to implement large numbers of
different low-volume designs
RLAC (2008-09) by Luciano Gualà 55A -
How to program a PLD
• Different programming technologies are used to control connections
• Some technologies: Mask programming Fuse Antifuse Single-bit storage element Stored charge on a floating transistor gate
• We will see two PLDs: ROM: read only memory PLA: Programmable Logic Array
RLAC (2008-09) by Luciano Gualà 56A -
Read Only Memories (ROMs)
• They are just a combinational circuits with n inputs and m output!
• It can be viewed as a memory with the inputs as addresses of data (output values)
• data are embedded into the circuit
• 2n words of m bits
A0 A1 A2
D3 D2 D1 D0
0 0 0 1 0 0 0
0 0 1 0 0 0 1
0 1 0 0 0 0 1
0 1 1 0 0 1 1
1 0 0 0 0 0 1
1 0 1 0 0 1 1
1 1 0 1 0 1 1
1 1 1 0 1 0 1
RLAC (2008-09) by Luciano Gualà 57A -
ROM: the circuit
• A ROM is made by a decoder followed by a second module combining minterms to give the desired functions (matrix of OR gates)
• First module: a decoder Fixed AND array with 2n outputs implementing
all n-literal minterms.
• Second module: Programmable OR Array with m outputs lines to
form up to m sum of minterm expressions
RLAC (2008-09) by Luciano Gualà 58A -
The implementation
D0D1D2
A0
A1
A2
programmable OR array
D3
RLAC (2008-09) by Luciano Gualà 59A -
…a ROM not yet programmed…
D0D1D2
A0
A1
A2
programmable OR array
D3
RLAC (2008-09) by Luciano Gualà 60A -
Programmable Logic Array (PLA)
• A PLA for sum of products is made by a first module combining inputs to form
products (programmable array of AND gates), followed by
a second module combining products to give the desired functions (programmable array of OR gates)
• A PLA having a decoder as first module is a ROM
RLAC (2008-09) by Luciano Gualà 61A -
An example
A B C X Y
0 0 0 1 0
0 0 1 1 0
0 1 0 0 0
0 1 1 0 1
1 0 0 0 0
1 0 1 0 1
1 1 0 1 1
1 1 1 1 1
X=AB+A’B’
Y=AB+BC+AC
RLAC (2008-09) by Luciano Gualà 62A -
The PLA implementation
AND Gates
OR Gates
Inpu
ts
Out
puts
X
Y
A
B
C
AB BC AC A’B’
RLAC (2008-09) by Luciano Gualà 63A -
Programmable Configurations
• ROM: a fixed array of AND gates and a programmable array of OR gates
• PLA: a programmable array of AND gates feeding a programmable array of OR gates
PLA
InputsProgrammable
OR array OutputsProgrammableConnections
ProgrammableConnections
ProgrammableAND array
ROM
InputsFixed
AND array(decoder)
ProgrammableOR array Outputs
ProgrammableConnections
RLAC (2008-09) by Luciano Gualà 64A -
Binary Addition
CarriesAddend-1 1 0 1 1 0Addend-2 1 0 1 1 1Sum
+
=
101101
001101
RLAC (2008-09) by Luciano Gualà 65A -
Functional Blocks: Addition
• Binary addition used frequently• Functional Blocks:
Half-Adder (HA), a 2-input bit-wise addition functional block,
Full-Adder (FA), a 3-input bit-wise addition functional block,
Ripple Carry Adder, a circuit performing binary addition, and
Carry-Look-Ahead Adder (CLA), a hierarchical structure to improve performance.
RLAC (2008-09) by Luciano Gualà 66A -
• It’s just a 2-input, 2-output circuit that performs the following computations:
• A half adder adds two bits to produce a two-bit sum
• The sum is expressed as a sum bit , S and a carry bit, C
X 0 0 1 1
+ Y + 0 + 1 + 0 + 1
C S 0 0 0 1 0 1 1 0
Half-Adder
RLAC (2008-09) by Luciano Gualà 67A -
The half adder
• Sum two binary inputs without the carry-inTruth table Logic Circuit
X Y S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
RLAC (2008-09) by Luciano Gualà 68A -
Full-Adder
• A full adder is similar to a half adder, but includes a carry-in bit from lower stages. Like the half-adder, it computes a sum bit, S and a carry bit, C.
For a carry-in (Z) of 0, it is the same as the half-adder:
For a carry- in(Z) of 1:
Z 0 0 0 0
X 0 0 1 1
+ Y + 0 + 1 + 0 + 1
C S 0 0 0 1 0 1 1 0
Z 1 1 1 1
X 0 0 1 1
+ Y + 0 + 1 + 0 + 1
C S 0 1 1 0 1 0 1 1
RLAC (2008-09) by Luciano Gualà 69A -
Full-adder
• Has to be able to deal Truth tablewith the carry-in
Z represents the carry-in
X Y Z S C
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
RLAC (2008-09) by Luciano Gualà 70A -
Karnaugh’s maps for full adder
S = X’Y’Z+X’YZ’+XY’Z’+XYZ C = XY + XZ + YZ = X Y Z = XY + XY’Z + X’YZ
= XY + Z.(XY’+X’Y) = XY + Z.(X Y)
RLAC (2008-09) by Luciano Gualà 71A -
The logic circuit of a full adder
RLAC (2008-09) by Luciano Gualà 72A -
Binary adder
• Has to be able to deal with more bits• An n-bit adder can be built chaining n full
adders• It’s called ripple-carry adder
RLAC (2008-09) by Luciano Gualà 73A -
Ideal behaviour of circuits
• Consider an inverter (NOT gate)
RLAC (2008-09) by Luciano Gualà 74A -
The real behaviour
• Propagation delay: time needed for a change in the input to affect the output (gate delay)
• Fall time: time taken for the signal to fall from high level to low level
• Rise time: time taken to rise from low to high
RLAC (2008-09) by Luciano Gualà 75A -
Carry Propagation
• Signals must propagate from inputs for output to be valid
• Carry and sum outputs of a single full-adder are valid c “gate-delays” after inputs are stable
• Value of c depends on the used technology• In a binary adder of n bits the last carry is
valid cn “gate-delays” after inputs are stable• For n large it may be unacceptable !
RLAC (2008-09) by Luciano Gualà 76A -
Carry look-ahead adder
• each carry is a function of the inputs (A and B)
• Hence, each carry can be computed by a two-level circuit
• Idea: pre-computing all carries by means of a (two-level) combinatorial circuit
RLAC (2008-09) by Luciano Gualà 77A -
Solution
• Write a general expression for a carry When is a carry
generated in the output? When does an input
carry propagates to the output?
ai bi ci si ci+1
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
RLAC (2008-09) by Luciano Gualà 78A -
General expression
• General expression for the (i+1)-th carry ci+1 = aibi + ci (ai + bi) = gi +cipi
gi = aibi generate carry
pi = ai+bi propagate carry
Iterate the expression for ci
RLAC (2008-09) by Luciano Gualà 79A -
General expression (2)
ci+1 = gi + pici
= gi + pi(gi-1+ci-1pi-1) = gi+pigi-1+pipi-1ci-1 =
= gi+pigi-1+pipi-1(gi-2+ci-2pi-2)
= gi+pigi-1+pipi-1gi-2+pipi-1pi-2ci-2
= gi+pigi-1+pipi-1gi-2+pipi-1pi-2gi-3+pipi-1pi-
2pi-3gi-4+...
• It could be developed until the least significant input bits
• Every ci depends only on c0, pj, gj (j<i)
RLAC (2008-09) by Luciano Gualà 80A -
Carry expressions for a 4-bit adder
• c1= g0 + p0c0
• c2= g1 + p1g0 + p1p0c0
• c3= g2 + p2g1 + p2p1g0 + p2p1p0c0
• c4= g3 + p3g2 + p3p2g1 + p3p2p1g0 + p3p2p1p0c0
RLAC (2008-09) by Luciano Gualà 81A -
Carry Look-Ahead: the architecture
FA FA FA FA
generation/propagation
carry look-ahead
s3 s2 s1 s0
a3 a2 a1 a0b3 b2 b1 b0
a3 a2 a1 a0b3 b2 b1 b0
g3 g2 g1 g0p3 p2 p1 p0
c3 c2 c1 c0
c4
c0
RLAC (2008-09) by Luciano Gualà 82A -
A practical problem
• c1= g0 + p0c0
• c2= g1 + p1g0 + p1p0c0
• c3= g2 + p2g1 + p2p1g0 + p2p1p0c0
• c4= g3 + p3g2 + p3p2g1 + p3p2p1g0 + p3p2p1p0c0
there is a limit due to circuit fan-in: the maximum number of inputs
RLAC (2008-09) by Luciano Gualà 83A -
Practical solution for n bits
• Use carry look-ahead adders for just m consecutive bits (4-8 is typical)
• Each of these is a stage• Use n/m stages connected by means of
the ripple-carry technique• The overall delay is now (more or less)
only cn/m “gate delays”
RLAC (2008-09) by Luciano Gualà 84A -
A mixed solution
CLA4 CLA4 CLA4 CLA4
s[15..12]
a[3..0]b[3…0]
c12 c8 c4 c0
c16
a[7..4]b[7…4]a[11..8]b[11…8]a[15..12]b[15…12]
s[11..8] s[7..4] s[3..0]
RLAC (2008-09) by Luciano Gualà 85A -
Sequential circuits
• More difficult to analyze since there is feedback: output is fed back to input
• Need to introduce a concept of state Current state and next state
• Asynchronous: change of state of an element is fed into other elements without any coordination
• Synchronous: change of state of each element is fed into other elements only at a given instant, the same for all elements
RLAC (2008-09) by Luciano Gualà 86A -
Introduction to Sequential Circuits
• A Sequential circuit contains: Storage elements:
• Latches or Flip-Flops
Combinational Logic:• Implements a multiple-output
boolean function• Inputs are signals from the outside• Outputs are signals to the outside• Other inputs, State or Present State, are
signals from storage elements• The remaining outputs, Next State are
inputs to storage elements
Combina-tionalLogic
Storage Elements
Inputs Outputs
StateNextState
RLAC (2008-09) by Luciano Gualà 87A -
Initial examples
• What does this circuit do ?
• Replace inverters with NOR gates
RLAC (2008-09) by Luciano Gualà 88A -
SR-Latch
• Intuition: it is a storage element that can store one bit Q is the bit stored into the SR-Latch two states:
• set: Q=1 (Q’=0)• reset: Q=0 (Q’=1)
inputs S and R can be used to write the bit (i.e. to change state)
RLAC (2008-09) by Luciano Gualà 89A -
Analysis of SR-Latch
• Two kinds of analysis• COMBINATIONAL
Consider all possible configurations of S,R,Q and check their feasibility
i.e. check which cofigurations are stable
• SEQUENTIAL Consider all possible configurations of S,R,Q at a generic
step k and check what happens for Q at step k+1 i.e. consider all configurations and check if a stable
configuration is reached
RLAC (2008-09) by Luciano Gualà 90A -
SR-Latch Truth Table:Combinational View
Q’ Q S R
1 0 0 0 stable
1 0 0 1 stable
1 0 1 0 unstable
1 0 1 1 unstable
0 1 0 0 stable
0 1 0 1 unstable
0 1 1 0 stable
0 1 1 1 unstable
• 8 possible combinations (Q= NOT Q’)
RLAC (2008-09) by Luciano Gualà 91A -
SR-Latch: sequential View
• Next state as a function of current state
S R Q(k) Q(k+1) Q’(k+1)
0 0 0 0 1 reset (stable)
0 0 1 1 0 set (stable)
0 1 0 0 1 reset (stable)
0 1 1 0 1 reset (transient)
1 0 0 1 0 Set (transient)
1 0 1 1 0 Set (stable)
1 1 0 0 0 unacceptable!
1 1 1 0 0 unacceptable!
RLAC (2008-09) by Luciano Gualà 92A -
Q’
RLAC (2008-09) by Luciano Gualà 93A -
First reason to avoid S=R=1
• When both inputs go from 1 to 0: a race condition happens
• Both outputs are driven from 0 to 1• Due to unpredictable physical differences
one of the NOR gates may commute earlier from 0 to 1
• Then it will prevent the commutation of the other gate
• Conclusion: output value is unpredictable !
RLAC (2008-09) by Luciano Gualà 94A -
Second reason to avoid S=R=1
• When both inputs go from 1 to 0: a race condition happens
• Both outputs are driven from 0 to 1• Both the NOR gates commute from 0 to 1
almost at the same time This drives both outputs from 1 to 0 Both gates are again forced to commute This repeats again and again
• Conclusion: output values oscillate !
RLAC (2008-09) by Luciano Gualà 95A -
Temporal evolution of SR-latch
Time ->
SRQQ’
RLAC (2008-09) by Luciano Gualà 96A -
Transition table for SR-Latch
S R Qn+1
0 0 Qn
0 1 0
1 0 1
1 1 ---
A synthetic description
RLAC (2008-09) by Luciano Gualà 97A -
Adding a clock to SR-latch
• An additional input (the clock) is used to ensure the latch commutes only when required
pulses of a clock
• The latch senses S and R only when Clock=1
clock cycle
RLAC (2008-09) by Luciano Gualà 98A -
The role of the clock
• A clock ensures commutation is propagated from the input to the output only when required
• But the general system clock is running continuously: how can it be used to control a circuit only when needed?
Enable Clock for the specific circuitSystem Clock
RLAC (2008-09) by Luciano Gualà 99A -
Circuit clock from system clock
System Clock
Circuit Enable
Circuit Clock
Enable Clock for the specific circuit
System Clock
RLAC (2008-09) by Luciano Gualà 100A -
A more subtle problem: the latch timing problem
while clock=1, outputs of the latch change whenever the inputs
change during the same clock cycle
Q’
RLAC (2008-09) by Luciano Gualà 101A -
…as a consequence…
• In a commutation from (S=1,R=0) to (S=0,R=1) or from (S=0,R=1) to (S=1,R=0) the SR-latch outputs may be (for some time) in the unacceptable state where both outputs are 0
• If Q and Q’ are in input to a further circuit, this receives wrong input values, hence its computed output may differ from the required one
Initial
state
Input chang
e
Transient state
Stable state
S 1 0 0 0
R 0 1 1 1
Q 1 1 0 0
Q’ 0 0 0 1
RLAC (2008-09) by Luciano Gualà 102A -
…one more consequence…
• Consider the following circuit and suppose that initially Q = 0
• As long as C = 1, the value of Q continues to change!
Clock Q
S
R
Desired behavior: Q changes only once
per clock pulse
RLAC (2008-09) by Luciano Gualà 103A -
The solution: master-slave Flip-Flop circuit
• it consists of two SR Latches (master and slave) the master (connected to circuit’s inputs only) can change
its state (flip) when clock=1 The slave (connected to circuit’s outputs only) can changes
its state (flop) when clock=0
• Hence: the slave reads master’s outputs after they have stabilized the next circuit reads slave’s outputs in the next clock
commutation to 1, when they have stabilized
• In a chain of circuits this allows to control exactly when the (commuted) output of the i-th circuit acts on the input of the (i+1)-th circuit
RLAC (2008-09) by Luciano Gualà 104A -
The solution: master-slave Flip-Flop circuit
RLAC (2008-09) by Luciano Gualà 105A -
SR flip-flop: execution example
0
0
0
1
10
0
1
1
0
1
0
0
1
1
0
1
RLAC (2008-09) by Luciano Gualà 106A -
D flip-flop: a secure SR flip-flop
• Forcing R to always be NOT(S) the critical condition S=R=1 is avoided
S
R
C
Q
Q
D
SR flip-flop
RLAC (2008-09) by Luciano Gualà 107A -
Use of D flip-flop
• A D flip-flop is a memory cell, since it stores what is presented at its input Symbol Truth table
D Qn+1
0 0
1 1
RLAC (2008-09) by Luciano Gualà 108A -
JK flip-flop: using also S=R=1
RLAC (2008-09) by Luciano Gualà 109A -
Tabular description for JK-FF
• Input: J, K; State: Q; Output: Q
J K Qn Qn+1
0 0 0 0
0 1 0 0
1 0 0 1
1 1 0 1
0 0 1 1
0 1 1 0
1 0 1 1
1 1 1 0
RLAC (2008-09) by Luciano Gualà 110A -
Transition Tables
• Synthetic description of flip-flop dynamics
S R Qn+1
0 0 Qn
0 1 0
1 0 1
1 1 ---
J K Qn+1
0 0 Qn
0 1 0
1 0 1
1 1 Q’n
D Qn+1
0 0
1 1
RLAC (2008-09) by Luciano Gualà 111A -
Use of D-FF:4 bit register
WE
RE
WE.Pr
X0 X1 X2 X3
Y0 Y1Y2
Y3
WE.Ck
DQ
Ck
DQ
Ck
DQ
Ck
DQ
Ck
RE: Read-EnableWE: Write-EnablePr: Preset - signals to prepare the gate
writes all 1s
RLAC (2008-09) by Luciano Gualà 112A -
Use of D flip-flop (2)
• A D flip-flop is a delay unit, since it replicates at the output - one propagation delay later - what is presented at its input (delay flip-flop)
• A chain of n D flip-flops can be used to delay a bit value for n clock pulses
RLAC (2008-09) by Luciano Gualà 113A -
4 bit delay unit
RE
SE
Y0 Y1Y2
Y3
DoutDin
SE.Ck
DQ
Ck
D Q
Ck
DQ
Ck
DQ
Ck
RE: Read-EnableSE: Shift-Enable
RLAC (2008-09) by Luciano Gualà 114A -
4 bit shift register
WE
RE
SE
X0 X1 X2 X3
Y0 Y1Y2
Y3
DoutDin
(SE.Ck)+(WE.Ck)
DQ
Ck
DQ
Ck
DQ
Ck
DQ
Ck
RLAC (2008-09) by Luciano Gualà 115A -
Register Control Signals
• WE (Write Enable): needed since many registers are attached to (i.e., receive data from) the same data bus
• SE (Shift Enable): allows a register output to drive next register input
• RE (Read Enable): needed since many registers are attached to (i.e., put data on) the same data bus
RLAC (2008-09) by Luciano Gualà 116A -
Counters
• It counts the number of clock cycles in which I=1
• IDEA: A single JK-FF with a periodic input commutes its output with twice the period of its input
• Use a chain of JK-FF each time doubling the period of the input
• A counter modulo 24 is shown
I
D0
D1
D2
D3
COUT
I.D0
I.D0.D1
I.D0.D1.D2
Ck
RLAC (2008-09) by Luciano Gualà 117A -
Temporal behaviour (1)
0 1 2 3 4 5 6 7 8 9 10
11
12
13
14
15
16I=Ck
D0
RLAC (2008-09) by Luciano Gualà 118A -
Temporal behaviour (2)
0 1 2 3 4 5 6 7 8 9 10
11
12
13
14
15
16
D0
D1
I=Ck
RLAC (2008-09) by Luciano Gualà 119A -
Temporal behaviour (3)
0 1 2 3 4 5 6 7 8 9 10
11
12
13
14
15
16
D0
D1
I=Ck
D2
RLAC (2008-09) by Luciano Gualà 120A -
Temporal behaviour (4)
0 1 2 3 4 5 6 7 8 9 10
11
12
13
14
15
16
D0
D1
I=Ck
D2
D3
RLAC (2008-09) by Luciano Gualà 121A -
Temporal behaviour (5)
0 1 2 3 4 5 6 7 8 9 10
11
12
13
14
15
16
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0
0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0
D0
D1
I=Ck
D2
D3
COUT
RLAC (2008-09) by Luciano Gualà 122A -
Finite State Machines (FSM)
• Called also Finite State Automata (FSA)• Formal model useful to describe a sequential circuit• Described by a table of transitions between states
as a consequence of inputs• If an input is true in a given state, a transition
changes the state and may produce an output• Two formal models exist:
Moore Model: outputs are a function only of states Mealy Model: outputs are a function of inputs and states
RLAC (2008-09) by Luciano Gualà 123A -
Graphical representation
• States are circles, transition are arrows, input are arrow labels, output are arrow (Mealy) or state (Moore) labels:
Currentstate
Nextstate
Input / OutputMealy model
Currentstate/Output
Nextstate/output
Input
Moore model
RLAC (2008-09) by Luciano Gualà 124A -
A very simple example of FSM
• A FSM with a binary input x, and a binary output z. The output z=1 iff the number of 1s in the input sequence is even
even odd
1/0
0/1
1/1
0/0
initial state
RLAC (2008-09) by Luciano Gualà 125A -
Tabular description for this FSM
• Next state as a function of current state and input
• Output as a function of current state and input
Current state
Input Next state
even 0 even
even 1 odd
odd 0 odd
odd 1 even
Current state
Input Output
even 0 1
even 1 0
odd 0 0
odd 1 1
RLAC (2008-09) by Luciano Gualà 126A -
Abstraction process
• FSM describes a sequential network (SN)• SN realizes Finite State Machine
• The analysis of a SN allows to write the corresponding FSM• From a FSM a SN is obtain through a synthesis process
• Similar to boolean functions and logical circuits Boolean Functions (BF) describe logical circuits (LC) LC realize Boolean Functions
The analisys of a LC produces a BF LC are combinational networks (memoryless) synthesizing BF
RLAC (2008-09) by Luciano Gualà 127A -
FSA for D flip-flop
0 1
1/0
1/10/0
0/1
• Use Q as state descriptor (state variable)
• Use D as input• Use Q as output • Check for completeness
RLAC (2008-09) by Luciano Gualà 128A -
Its tabular description
• Output values as a function of input and current state values
• Next state values as a function of input and state value D flip-flop
Output: State:
D Qn Qn
0 0 0
0 1 1
1 0 0
1 1 1
D Qn Qn+1
0 0 0
0 1 0
1 0 1
1 1 1
RLAC (2008-09) by Luciano Gualà 129A -
FSA for SR flip-flop
• Use Q as state variable• Use S and R as input• Use Q as output• Transitions with multiple conditions
• Unacceptable input configurations are NOT represented
0 1
10/0
00,10/100,01/0
01/1
RLAC (2008-09) by Luciano Gualà 130A -
FSA for JK flip-flop
• Just add condition 11 to existing transitions
• Note stability and instability of states according to input values
0 1
10,11/0
00,10/100,01/0
01,11/1
RLAC (2008-09) by Luciano Gualà 131A -
Synthesis of a SN from a FSA
• Identify input, output and state variables how many FFs are needed? for n states we need k FFs with 2k n label each state with a k-length bit string
• Decide which FF to use to store state values a D-FF is the simplest choice to store 0 present 0 at the input to store 1 present 1 at the input
• Build (and minimize) truth tables for output variables as a function of input and state values
• Build (and minimize) transition tables for state variables as a function of input and state values
RLAC (2008-09) by Luciano Gualà 132A -
Generic architecture of a SN
RLAC (2008-09) by Luciano Gualà 133A -
Example
even odd
1/0
0/1
1/1
0/00 1
Q X Qnex
t
Z
0 0 0 1
0 1 1 0
1 0 1 0
1 1 0 1Qnext= X Q
Z= X Q
X Z
RLAC (2008-09) by Luciano Gualà 134A -
Example 1: a given FSA
0/0
1/1
1/1
01
10
11000/0
0/1
0/1
1/01/0
RLAC (2008-09) by Luciano Gualà 135A -
Example 1: variables
X Y
An+1
Bn+1
An
Bn
Storageelements
Combinationalcircuit
An+1
Bn+1
An
Bn
RLAC (2008-09) by Luciano Gualà 136A -
Example 1: transition tables
• Transition table for output and state variables
An Bn X Y An+1 Bn+
1
0 0 0 0 1 1
0 0 1 0 0 0
0 1 0 0 1 1
0 1 1 1 0 0
1 0 0 1 0 1
1 0 1 1 0 0
1 1 0 1 1 0
1 1 1 0 0 1
RLAC (2008-09) by Luciano Gualà 137A -
Example 1: minimization
State variables Output
Y X
0 1
AB 00 0 0
01 0 1
11 1 0
10 1 1
An+1 X
0 1
AB 11 1 0
01 1 0
00 1 0
10 0 0
Bn+1 X
0 1
AB 11 0 1
01 1 0
00 1 0
10 1 0
RLAC (2008-09) by Luciano Gualà 138A -
Example 1: circuits
B
X’
A’
X’
D
Ck
A
A’
X’
B’X’
ABX
D
Ck
B
A’BX
AB’
A
X’
Y
RLAC (2008-09) by Luciano Gualà 139A -
Example 2: specification
• Two input values are presented together• Recognize with output 10 and 01, respectively, when
a couple 00 or a couple 11 is presented• Recognize with output 11 when two consecutive
couples of identical values (00 00 or 11 11) are presented
• Output is 00, otherwise• Example:
INPUT 01 01 00 00 00 11 11 10 11 11 11 11
OUTPUT
00 00 10 11 10 01 11 00 01 11 01 11
RLAC (2008-09) by Luciano Gualà 140A -
Example 2: corresponding FSA
00/11
00/10
01,10/00
01,10/00
01,10/00
11/1111/01
00/10
11/01
• Show also the initial state (double circle)
00
01 10
RLAC (2008-09) by Luciano Gualà 141A -
Example 2: variables
Y Z
An+1
Bn+1
Storageelements
Combinationalcircuit
X W
An
Bn
An
BnAn+1
Bn+1
RLAC (2008-09) by Luciano Gualà 142A -
Example 2: transition tables
An Bn X Y W Z An+1 Bn+1
0 0 0 0 1 0 1 0
0 0 0 1 0 0 0 0
0 0 1 0 0 0 0 0
0 0 1 1 0 1 0 1
0 1 0 0 1 0 1 0
0 1 0 1 0 0 0 0
0 1 1 0 0 0 0 0
0 1 1 1 1 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 0 0 0 0
1 0 1 0 0 0 0 0
1 0 1 1 0 1 0 1
1 1 0 0 -- -- -- --
1 1 0 1 -- -- -- --
1 1 1 0 -- -- -- --
1 1 1 1 -- -- -- --
Note: here unspecified
inputs can be used for
minimization
RLAC (2008-09) by Luciano Gualà 143A -
Example 2: circuitsA’X’Y’
D
Ck
A
B’XY
D
Ck
B
BXY
W
ZAX’Y’
RLAC (2008-09) by Luciano Gualà 144A -
What happens when the FSA is not complete?
0/0
1/1
1/1
01
10
11000/0
0/1
0/1
1/0
RLAC (2008-09) by Luciano Gualà 145A -
…uncomplete FSA…
• Transition table for output and state variables
An Bn X Y An+1 Bn+
1
0 0 0 0 1 1
0 0 1 - - -
0 1 0 0 1 1
0 1 1 1 0 0
1 0 0 1 0 1
1 0 1 1 0 0
1 1 0 1 1 0
1 1 1 0 0 1
Note: here unspecified
inputs cannot be used for
minimization
RLAC (2008-09) by Luciano Gualà 146A -
State variables Output
• NOTE: we are setting all unspecified values to 0
Y X
0 1
AB 00 0 --
01 0 1
11 1 0
10 1 1
An+1 X
0 1
AB 11 1 0
01 1 0
00 1 --
10 0 0
Bn+1 X
0 1
AB 11 0 1
01 1 0
00 1 --
10 1 0
RLAC (2008-09) by Luciano Gualà 147A -
• …hence:
An Bn X Y An+1 Bn+
1
0 0 0 0 1 1
0 0 1 0 0 0
0 1 0 0 1 1
0 1 1 1 0 0
1 0 0 1 0 1
1 0 1 1 0 0
1 1 0 1 1 0
1 1 1 0 0 1
RLAC (2008-09) by Luciano Gualà 148A -
…the corresponding FSA…
0/0
1/1
1/1
01
10
11000/0
0/1
0/1
1/0
1/0
RLAC (2008-09) by Luciano Gualà 149A -
…a different choice…
State variables Output
… hence we would implement …
An+1 X
0 1
AB 11 1 0
01 1 0
00 1 --
10 0 0
Bn+1 X
0 1
AB 11 0 1
01 1 0
00 1 --
10 1 0
Y X
0 1
AB 00 0 --
01 0 1
11 1 0
10 1 1
RLAC (2008-09) by Luciano Gualà 150A -
• …hence:
An Bn X Y An+1 Bn+
1
0 0 0 0 1 1
0 0 1 1 1 0
0 1 0 0 1 1
0 1 1 1 0 0
1 0 0 1 0 1
1 0 1 1 0 0
1 1 0 1 1 0
1 1 1 0 0 1
RLAC (2008-09) by Luciano Gualà 151A -
…the corresponding FSA…
0/0
1/1
1/1
01
10
11000/0
0/1
0/1
1/0
1/1