LISA-C2 series and FW75-C200

LISA-C2 series and FW75-C200 CDMA 1xRTT Cellular Modules System Integration Manual

Abstract This document describes the features and the integration of u-blox LISA-C2 series & FW75-C200 CDMA2000 1xRTT cellular modules.

The modules are complete and cost efficient CDMA solutions offering 153 kb/s download and upload speeds, supporting dual-band operation (800 / 1900 MHz).

www.u-blox.com

UBX-13000620 - R21

LISA-C2 series and FW75-C200 - System Integration Manual

UBX-13000620 - R21 Early Production Information Page 2 of 103

Document Information

Title LISA-C2 series and FW75-C200

Subtitle CDMA 1xRTT Cellular Modules

Document type System Integration Manual

Document number UBX-13000620

Revision and date R21 08-Aug-2017

Document status Early Production Information

Document status explanation

Objective Specification Document contains target values. Revised and supplementary data will be published later.

Advance Information Document contains data based on early testing. Revised and supplementary data will be published later.

Early Production Information Document contains data from product verification. Revised and supplementary data may be published later.

Production Information Document contains the final product specification.

This document applies to the following products:

Name Type number Firmware version PCN / IN

FW75-C200 FW75-C200-02S-01 E0.S.05.00.04R UBX-TN-12077

LISA-C200 LISA-C200-02S-01 E0.S.05.00.04R UBX-TN-12077

FW75-C200 FW75-C200-22S-01 E0.V.05.00.02R UBX-TN-12077

LISA-C200 LISA-C200-22S-01 E0.V.05.00.03R UBX-TN-12077

LISA-C200 LISA-C200-03S-00 E0.S.06.00.07R UBX-13005454

LISA-C200 LISA-C200-23S-00 E0.V.06.00.06R UBX-13005454

LISA-C200 LISA-C200-04S-00 E0.S.07.00.07R UBX-14042040

LISA-C200 LISA-C200-24S-00 E0.V.07.00.07R UBX-14042040

u-blox reserves all rights to this document and the information contained herein. Products, names, logos and designs described herein may in whole or in part be subject to intellectual property rights. Reproduction, use, modification or disclosure to third parties of this document or any part thereof without the express permission of u-blox is strictly prohibited. The information contained herein is provided “as is” and u-blox assumes no liability for the use of the information. No warranty, either express or implied, is given, including but not limited, with respect to the accuracy, correctness, reliability and fitness for a particular purpose of the information. This document may be revised by u-blox at any time. For most recent documents, visit www.u-blox.com. Copyright © 2017, u-blox AG. u-blox is a registered trademark of u-blox Holding AG in the EU and other countries.


UBX-13000620 - R21 Early Production Information Preface

Page 3 of 103

Preface u-blox Technical Documentation As part of our commitment to customer support, u-blox maintains an extensive volume of technical documentation for our products. In addition to our product-specific technical data sheets, the following manuals are available to assist u-blox customers in product design and development.

• AT Commands Manual: This document provides the description of the AT commands supported by the LISA-C2 series and FW75-C200 modules.

• System Integration Manual: This manual provides hardware design instructions and information on how to set up production and final product tests.

• Application Note: Provides general design instructions and information that applies to all u-blox cellular modules. See Section Related documents for a list of Application Notes related to your cellular module.

How to use this Manual

The LISA-C2 series and FW75-C200 System Integration Manual provides the necessary information to successfully design in and configure these u-blox cellular modules. This manual has a modular structure. It is not necessary to read it from the beginning to the end.

The following symbols are used to highlight important information within the manual:

An index finger points out key information pertaining to module integration and performance.

A warning symbol indicates actions that could negatively impact or damage the module.

Questions If you have any questions about u-blox cellular integration, please:

• Read this manual carefully.

• Contact our information service on the homepage http://www.u-blox.com

• Read the questions and answers on our FAQ database on the homepage http://www.u-blox.com

Technical Support Worldwide Web

Our website (www.u-blox.com) is a rich pool of information. Product information, technical documents and helpful FAQ can be accessed 24h a day.

By E-mail

Contact the nearest Technical Support office by email. To ensure that your request is processed as soon as possible, use our service pool email addresses rather than any personal email address of our staff. You will find the contact details at the end of the document.

Helpful Information when Contacting Technical Support

When contacting Technical Support please have the following information ready:

• Module type (e.g. LISA-C200) and firmware version

• Module configuration

• Clear description of your question or the problem

• A short description of the application

• Your complete contact details

http://www.u-blox.com/




UBX-13000620 - R21 Early Production Information Contents

Page 4 of 103

Contents Preface ................................................................................................................................ 3

Contents .............................................................................................................................. 4

1 System description ....................................................................................................... 7 1.1 Overview .............................................................................................................................................. 7 1.2 Architecture .......................................................................................................................................... 8

1.2.1 LISA-C200 / FW75-C200 ............................................................................................................... 8 1.3 Pin description ...................................................................................................................................... 9 1.4 Operating modes ................................................................................................................................ 10 1.5 Power management ........................................................................................................................... 12

1.5.1 Power supply circuit overview ...................................................................................................... 12 1.5.2 Module supply (VCC) .................................................................................................................. 13 1.5.3 VCC application circuits ............................................................................................................... 14

1.6 System functions ................................................................................................................................ 19 1.6.1 Module power-on ....................................................................................................................... 19 1.6.2 Module power-off ....................................................................................................................... 21 1.6.3 Module reset ............................................................................................................................... 21 1.6.4 Power-on, Power-off and Reset Sequences .................................................................................. 21 1.6.5 Key points to system functions .................................................................................................... 23

1.7 RF connection ..................................................................................................................................... 24 1.8 SIM interface ...................................................................................................................................... 25 1.9 Serial communication ......................................................................................................................... 25

1.9.1 Serial interfaces configuration ..................................................................................................... 26 1.9.2 Asynchronous serial interface (UART)........................................................................................... 26 1.9.3 USB interface............................................................................................................................... 31 1.9.4 MUX Protocol (3GPP 27.010) ...................................................................................................... 34

1.10 DDC (I2C) interface .......................................................................................................................... 34 1.10.1 Overview ..................................................................................................................................... 34 1.10.2 DDC application circuit ................................................................................................................ 35

1.11 Audio Interface (LISA-C200) ............................................................................................................ 39 1.11.1 Analog Audio interface – LISA-C200 ........................................................................................... 39 1.11.2 Digital (PCM) Audio interface ...................................................................................................... 43

1.12 General Purpose Input / Output (GPIO) ........................................................................................... 45 1.13 Reserved pins (RSVD) ...................................................................................................................... 49 1.14 Schematic for LISA-C200 module integration .................................................................................. 50 1.15 Schematic for FW75-C200 modules integration .............................................................................. 51 1.16 Approvals ........................................................................................................................................ 52

1.16.1 LISA-C200 and FW75-C200 US certifications ............................................................................... 52

2 Design-In ..................................................................................................................... 53



Page 5 of 103

2.1 Design-in checklist .............................................................................................................................. 53 2.1.1 Schematic checklist ..................................................................................................................... 53 2.1.2 Layout checklist ........................................................................................................................... 53 2.1.3 Antenna checklist ........................................................................................................................ 54

2.2 Connectors (FW75) ............................................................................................................................. 54 2.2.1 FW75-C200 modem connector ................................................................................................... 54 2.2.2 FW75-C200 Board to Board host connector ................................................................................ 54 2.2.3 FW75-C200 RF antenna connector .............................................................................................. 55

2.3 Design Guidelines ............................................................................................................................... 55 2.3.1 Layout guidelines per pin function ............................................................................................... 55 2.3.2 Footprint and paste mask (LISA-C200 only) ................................................................................. 57

2.4 Antenna guidelines ............................................................................................................................. 59 2.4.1 Antenna termination ................................................................................................................... 60 2.4.2 Antenna radiation ....................................................................................................................... 61 2.4.3 Antenna detection functionality .................................................................................................. 62

2.5 ESD immunity test precautions ........................................................................................................... 63 2.5.1 General precautions .................................................................................................................... 65 2.5.2 Antenna interface precautions ..................................................................................................... 66 2.5.3 Module interfaces precautions ..................................................................................................... 67

3 Features description ................................................................................................... 68 3.1 TCP/IP and UDP/IP ............................................................................................................................... 68 3.2 HTTP ................................................................................................................................................... 68 3.3 FTP ..................................................................................................................................................... 68 3.4 UTEST ................................................................................................................................................. 68

3.4.1 Description .................................................................................................................................. 68 3.4.2 AT+UTEST=0 ............................................................................................................................... 70 3.4.3 AT+UTEST=1 ............................................................................................................................... 70 3.4.4 AT+UTEST=2 ............................................................................................................................... 70 3.4.5 AT+UTEST=3 ............................................................................................................................... 71

3.5 Carrier Provisioning............................................................................................................................. 74 3.5.1 Factory NAM settings .................................................................................................................. 74 3.5.2 Sprint .......................................................................................................................................... 74 3.5.3 Aeris ............................................................................................................................................ 79 3.5.4 Verizon ........................................................................................................................................ 80 3.5.5 US Cellular .................................................................................................................................. 80 3.5.6 Firmware (upgrade) Over AT (FOAT) ............................................................................................ 81

3.6 AssistNow clients and GNSS Integration.............................................................................................. 82 3.7 Hybrid positioning and CellLocateTM .................................................................................................... 82

3.7.1 Positioning through cellular information: CellLocateTM ................................................................. 83 3.9.2 Hybrid positioning ....................................................................................................................... 84

3.8 Audio File Playback ............................................................................................................................. 85 3.9 Network Status Indicator .................................................................................................................... 85

4 Handling and soldering ............................................................................................. 87



Page 6 of 103

4.1 Packaging, shipping, storage and moisture preconditioning ............................................................... 87 4.2 Soldering ............................................................................................................................................ 87

4.2.1 Soldering paste............................................................................................................................ 87 4.2.2 Reflow soldering ......................................................................................................................... 87 4.2.3 Optical inspection ........................................................................................................................ 89 4.2.4 Cleaning ...................................................................................................................................... 89 4.2.5 Repeated reflow soldering ........................................................................................................... 89 4.2.6 Wave soldering............................................................................................................................ 89 4.2.7 Hand soldering ............................................................................................................................ 89 4.2.8 Rework ........................................................................................................................................ 89 4.2.9 Conformal coating ...................................................................................................................... 89 4.2.10 Casting ........................................................................................................................................ 90 4.2.11 Grounding metal covers .............................................................................................................. 90 4.2.12 Use of ultrasonic processes .......................................................................................................... 90

Appendix .......................................................................................................................... 91

A Glossary ...................................................................................................................... 91

B Migration from LISA-U to LISA-C200 ......................................................................... 93

Related documents......................................................................................................... 101

Revision history .............................................................................................................. 102

Contact ............................................................................................................................ 103


UBX-13000620 - R21 Early Production Information System description

Page 7 of 103

1 System description

1.1 Overview u-blox CDMA 1xRTT Cellular ModulesCDMA 1xRTT Cellular Modules CDMA 1xRTT Cellular ModulesCDMA 1xRTT Cellular Modulesintegrate a complete CDMA 1xRTT 153 kb/s packet data modem into the LISA and FW75 form factors.

3G CDMA 2000 1xRTT Characteristics

CDMA Terrestrial Radio Access Frequency Division Duplex (FDD) operating mode

Dual-band support:

Band Class 0 – US Cellular : C200 Band Class 1 – US PCS : C200

CDMA Packet Switched data up to 153 kb/s DL/UL

Table 1: 3G CDMA 2000 1xRTT characteristics

The LISA-C200 and FW75-C200 modems are US CDMA-certified to support 1xRTT data speeds on US CDMA carriers Sprint, Verizon and Aeris.

FW75-C200 is strictly a data modem for embedded solutions while LISA-C200 supports audio (analog and digital) functionality. Data communication is via two data interfaces; 5-wire UART and Full Speed USB. The interfaces are intended to support a vast quantity of AT commands that will enable easy adoption to existing host application processors.

Power-on is initiated by HW logic and Power-down by HW logic and SW control.

The LISA-C2 series antenna interface is provided via a 50 Ω antenna pad, while the FW75-C200 module uses the popular “U.FL” RF connector(s).

Another key component is the extensive collection of SW AT commands, meeting the needs of:

• Carrier AT commands

• Industry standard AT command both 3GPP and 3GPP2

• u-blox AT Commands



Page 8 of 103

1.2 Architecture

1.2.1 LISA-C200 / FW75-C200

WirelessBase-bandProcessor

Memory

Power Management Unit

RF Transceiver

19.2 MHz

DiplexerANT

LNA

3G PA

LNA

3G PA

UART

USB

GPIOs (**)

Power On

HW Reset (**)

Vcc (Supply)

V_INT (I/O)

(U)SIM

HW shutdown (*)

DDC

Digital Audio (I2S)

Figure 1: Block diagram: FW75-C200, LISA-C200

1.2.1.1 Functional blocks

LISA-C200 and FW75-C200 modules consist of the following internal functional blocks: RF front-end, RF transceiver, baseband section, and power management unit.

RF Front-End

The antenna connector is directly connected to the diplexer, which separates the 800 and 1900 MHZ bands. Each 800 & 1900 MHz RF chain is connected to its respective transceiver path via duplexers, as shown in the block diagram.

Each duplexer provides the filtering and Rx/Tx path separation before connecting to the LNA and RF PA devices.

A separate shield compartment houses the 800 MHZ and 1900 MHZ RF power amplifiers. This compartment provides high Tx signal isolation, preventing de-sensing of the Rx frontend circuitry.

RF Transceiver

The transceiver includes the following key components:

• Dual-band 800 & 1900 MHz CDMA transceiver, excluding the RF Power Amplifiers, duplexers and diplexer.

• 19.2 MHz Crystal Oscillator

While operating, the RF transceiver performs direct up-conversion and down-conversion of the baseband I/Q signals, with the RF voltage controlled gain amplifier being used to set the uplink TX power. In the downlink path, the internal LNA enhances the RX sensitivity. An internal automatic gain control amplifier optimizes the signal levels before delivering the analog I/Q to baseband for further digital processing.

The Rx path locks and tracks to the base station carrier. A learning algorithm is implemented to capture the temperature characteristic of the xtal, comparing the XO and carrier frequencies, while measuring the thermistor



Page 9 of 103

in close proximity to the crystal oscillator. A lookup table is saved over temperature and time. The known frequency difference of the free running crystal oscillator is corrected in the baseband processor enabling quick acquisition.

Baseband section and power management unit

Another shielding section includes all the digital circuitry and the power supplies, basically the following functional blocks:

• Wireless baseband mixed signal ASIC, which integrates:

• Microprocessor for controller functions, CDMA upper layer software

• ARM9 coprocessor and HW accelerator for CDMA Layer 1 control software and routines

• Dedicated HW for peripherals control (UART, USB, etc.)

• Memory system in a Multi-Chip Package (MCP) integrating two devices:

• NOR flash non-volatile memory

• DDR SRAM volatile memory

• Power Management Unit (PMU), used to derive all the system supply voltages from the module supply VCC

1.3 Pin description Table 2 provides a summary of the module pin names and descriptions.

For the exact specification including pin numbering and additional information see the LISA-C2 series Data Sheet [1] or the FW75-C200 Data Sheet [2].

Name Module Power domain

I/O Description Remarks

VCC All VCC - Module supply Module supply input

V_INT FW75-C200 LISA-C2

- -

O O

Digital I/O Interfaces supply output Digital I/O Interfaces supply output

V_INT = 2.85V (typical) generated by the module when it is switched-on and the RESET_N (external reset input pin) is not forced to the low level. V_INT = 1.8V (typical) generated by the module when it is switched-on and the RESET_N (external reset input pin) is not forced to the low level.

PWR_ON All POS I Power-on input PWR_ON pin has Internal pull-up resistor.

GPIO1-5 LISA-C2 GDI I/O GPIO

RESET_N LISA-C2 ERS I External reset input RESET_N pin has Internal pull-up resistor.

HW_SHUTDOWN FW75-C200 ERS I External Shutdown input HW_SHUTDOWN pin has Internal pull-up resistor.

ANT(Main RF) All - - Transmit & Receive Primary RF antenna

STATUS FW75-C200 GDI O External transistor base drive for LED Indicator

Indicated by buffered External LED :

Off – not powered

On – powered, associated, and authenticated but not transmitting or receiving.

Slow Blink – powered, but not associated or authenticated; searching.

Intermittent Blink – powered; activity proportional to transmitting/receiving speed. For voice applications, turning off and on the intermittent blink based on the ring pulse cycle can indicate a ring event.

RI LISA-C2 FW75-C200

GDI O UART ring indicator Circuit 125 (RI) in ITU-T V.24. Value at internal reset: T/PU. Use to wake up host processor. The output signal is active low. Internal active pull-up to 1.8 V. Internal active pull-up to 2.85 V



Page 10 of 103

Name Module Power domain

I/O Description Remarks

CTS LISA-C2 FW75-C200

GDI O UART clear to send Circuit 106 (CTS) in ITU-T V.24. Internal active pull-up to 1.8 V. Internal active pull-up to 2.85 V.

RTS LISA-C2 FW75-C200

GDI I UART ready to send Circuit 105 (RTS) in ITU-T V.24. Internal passive pull-up to 1.8 V. Internal passive pull-up to 2.85 V.

RXD

LISA-C2 FW75-C200

GDI O UART received data Circuit 104 (RxD) in ITU-T V.24. Internal active pull-up to 1.8 V. Internal active pull-up to 2.85 V.

TXD

LISA-C2 FW75-C200

GDI I UART transmitted data Circuit 103 (TxD) in ITU-T V.24. Internal passive pull-up to 1.8 V. Internal passive pull-up to 2.85 V.

VUSB_DET All USB I USB detect input Input for VBUS (5 V typical) USB supply sense.

USB_D- All USB I/O USB Data Line D- 90 Ω nominal differential impedance. Pull-up or pull-down resistors and external series resistors as required by the USB 2.0 high-speed specification [10] are part of the USB pad driver and need not be provided externally.

USB_D+ All USB I/O USB Data Line D+ 90 Ω nominal differential impedance. Pull-up or pull-down resistors and external series resistors as required by the USB 2.0 high-speed specification [10] are part of the USB pad driver and need not be provided externally.

MIC_N MICN1

LISA-C200

AUDIO I Differential analog audio input (negative)

Differential analog microphone input. Internal DC blocking 0.1 µF capacitor.

MIC_P MICP1

LISA-C200

AUDIO I Differential analog audio input (positive)

Differential analog microphone input. Internal DC blocking 0.1 µF capacitor.

SPK_P EPP2

LISA-C200

AUDIO O Differential analog audio output (positive)

Earpiece differential analog audio output shared for all path modes

SPK_N EPN2

LISA-C200

AUDIO O Differential analog audio output (negative)

Earpiece differential analog audio output shared for all path modes

PCM_SYNC LISA-C200 GDI O Digital Sync Digital Audio Sync pulse.

PCM_DO LISA-C200 GDI O Data Output Digital Audio Output.

PCM_CLK LISA-C200 GDI O Clock Output Digital Audio Clock Output.

PCM_DI LISA-C200 GDI I Data Input Digital Audio Input.

SCL LISA-C200 DDC O I2C bus clock line Fixed open drain. No internal pull-up. Value at internal reset: T.

SDA LISA-C200 DDC I/O I2C bus data line Fixed open drain. No internal pull-up. Value at internal reset: T.

SIM_CLK LISA-C2 FW75-C200

SIM O SIM clock Value at internal reset: L.

SIM_IO LISA-C2 FW75-C200

SIM I/O SIM data Internal 4.7 kΩ pull-up resistor to VSIM. Value at internal reset: L/PD.

SIM_RST LISA-C2 FW75-C200

SIM O SIM reset Value at internal reset: L.

VSIM LISA-C2 FW75-C200

- O SIM supply output 1.80 V typical or 2.90 V typical generated by the module according to the SIM card type.

SIM_GND FW75-C200 SIM O SIM GROUND

RSVD All RSVD - RESERVED pin Unless otherwise specified, leave unconnected.

GND All GND - Ground All GND pads must be connected to ground.

Table 2: Pin description summary

1.4 Operating modes LISA-C200 and FW75-C200 modules have several operating modes. Table 3 defines the operating modes and Table 4, provides further details and general guidelines for operation.



Page 11 of 103

General Status Operating Mode Definition

Power-down Not-Powered Mode VCC supply not present or below operating range: module is switched off.

Power-Off Mode VCC supply within operating range and module is switched off.

Normal Operation Idle-Mode Module processor core runs with 32 kHz as reference oscillator.

Active-Mode Module processor core runs with 19.2 MHz as reference oscillator.

Connected-Mode Voice or data call enabled and processor core runs with 19.2 MHz as reference oscillator.

Table 3: Module operating modes definition

Operating Mode Description Transition between operating modes

Not-Powered Mode Module is switched off. Application interfaces are not accessible.

When VCC supply is removed, the module enters not-powered mode.

Idle-Mode Application interfaces are disabled: The module automatically enters idle-mode whenever possible if power saving is enabled by the AT+UPSV command (refer to u-blox C2 series AT Commands Manual [3]), and TxD pin is put low by the host, reducing current consumption Power saving configuration is not enabled by default: it can be enabled by the AT+UPSV command (see u-blox C2 series AT Commands Manual [3]).

The module automatically switches from active-mode to idle-mode whenever possible if power saving is enabled (refer to u-blox C2 series AT Commands Manual [3], AT+UPSV). The module wakes up from idle-mode to active-mode in the following events: • Automatic periodic monitoring of the paging

channel for the paging block reception according to network conditions

• The TxD pin is released from GND by the host • The connected USB host forces a remote wakeup

of the module as USB device))

Active-Mode The module is ready to accept data signals from an external device

When the module is switched on by an appropriate power-on event, the module enters active-mode from not-powered. If power saving configuration is enabled by the AT+UPSV command, the module automatically switches from active to idle-mode whenever possible, and the module wakes up from idle to active-mode in the events listed above (refer to idle to active transition description). When a voice call or a data call is initiated, the module switches from active-mode to connected-mode.

Connected-Mode A voice call or a data call is in progress. When a CSD or PSD data call is enabled, the application interfaces are kept enabled: the module is prepared to accept data from an external device.

When a voice call or a data call is initiated, the module enters connected-mode from active-mode. When a voice call or a data call is terminated, the module returns to the active-mode.

Table 4: Module operating modes description



Page 12 of 103

1.5 Power management

1.5.1 Power supply circuit overview

LISA-C200 and FW75-C200 modules feature a power management concept optimized for the most efficient use of supplied power. This is achieved by hardware design utilizing a power efficient circuit topology (Figure 2), and by power management software controlling the module’s power saving mode.

Baseband Processor

Switching Step-Down

u-blox LISA-C2 seriesand FW75-C200

42 µF

VCC

VSIM

V_INT

2 x 3G Power Amplifier(s)

Linear LDO

Linear LDO

Switching Step-Down

Linear LDO

Linear LDO

Linear LDO

I/O

EBU

CORE

Analog

SIM

RTC

NOR Flash

DDR SRAM

RF Transceiver

Memory

Power Management Unit

4.7 µF 2.2 µF

VCC

VCC

Figure 2: Power management simplified block diagram

Pins with supply function are described in Table 5.



Page 13 of 103

LISA-C200 and FW75-C200 modules must be supplied via the VCC pins. There is only one main power supply input, available on the three1 or five2 VCC pins that must all be connected to the external power supply.

The VCC pins are directly connected to the RF power amplifiers and to the integrated Power Management Unit (PMU) within the module: all supply voltages needed by the module are generated from the VCC supply by integrated voltage regulators.

When a 1.8 V or a 3 V SIM card type is connected, LISA-C200 and FW75-C200 modules automatically supply the SIM card via the VSIM pin. Activation and deactivation of the SIM interface with automatic voltage switch from 1.8 to 3 V is implemented, in accordance to the ISO-IEC 7816-3 specifications.

The 2.8 V domain used internally is also available on the V_INT pin, to allow more economical and efficient integration of the FW75-C200 module in the final application.

The 1.8 V domain used internally is also available on the V_INT pin, to allow more economical and efficient integration of the LISA-C200 module in its final application.

The integrated Power Management Unit also provides the control state machine for system start-up and system shut-down control.

1.5.2 Module supply (VCC)

LISA-C200 and FW75-C200 modules must be supplied through the VCC pins by a DC power supply. Voltages must be stable: during operation, the current drawn from VCC can vary by some orders of magnitude.

Though a module can work within a large voltage range, the module’s performance shall be optimized when the nominal VCC voltage of 3.8 V DC is applied. It is strongly suggested that a module be powered in design with a 3.8 V DC power supply VCC.

Name Description Remarks

VCC Module power supply input VCC pins are internally connected, but all the available pads or pins must be connected to the external supply in order to minimize the power loss due to series resistance. Clean and stable supply is required: low ripple and low voltage drop must be guaranteed. Voltage provided must always be above the minimum limit of the operating range.

GND Ground GND pins are internally connected but a good (low impedance) external ground can improve RF performance: all available pads or pins must be connected to ground.

Table 5: Module supply pins

Higher ESD protection level can be required if VCC is externally accessible on the application board. A higher protection level can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) on the line connected to this pin.

The voltage provided to the VCC pins must be within the normal operating range limits as specified in the LISA-C2 series Data Sheet [1] or, FW75-C200 Data Sheet [2]. Complete functionality of the module is only guaranteed within the specified minimum and maximum VCC voltage operating range.

Ensure that the input voltage at the VCC pins never drops below the minimum limit of the operating range when the module is switched on.

Operation above the operating range maximum limit is not recommended and extended exposure beyond it may affect device reliability.

Stress beyond the VCC absolute maximum ratings can cause permanent damage to the module: if necessary, voltage spikes beyond VCC absolute maximum ratings must be restricted to values within the specified limits by using appropriate protection.

1 LISA-C200. 2 FW75-C200 -



Page 14 of 103

When designing the power supply for the application, pay specific attention to power losses and transients. The DC power supply must be able to provide a voltage profile to the VCC pins with the following characteristics:

• Voltage drop during transmission must be lower than 250 mV

Any degradation in power supply performance (due to losses, noise or transients) will directly affect the RF performance of the module since the single external DC power source indirectly supplies all the digital and analog interfaces, and also directly supplies the RF power amplifier (PA).

1.5.2.1 Handling sudden momentary power loss

If the host application board should be susceptible to sudden momentary power loss, then it should ensure either one of the following during such an event:

• The supply to LISA-C200 VCC pin remains stable as described in section 1.5.2 to keep module powered-on.

• If the host supply cannot sustain the VCC requirements to keep the module powered on during the sudden momentary power loss, then the supply to the LISA-200 VCC pin should go to 0V to power down the module. In addition, the falling voltage on the VCC pin must have a minimal of a 2 sec duration timed during the downward segment between 2.6V to 0V. This will allow the module to reach power-off state. The module will then be ready to power-up again provided is meets the criteria described in section 1.6.1.

Failure to handle sudden momentary power loss as outlined in section 1.5.2.1 can result in unpredictable behavior and possible memory corruption within the modem.

1.5.3 VCC application circuits

LISA-C200 and FW75-C200 modules must be supplied through the VCC pins by one (and only one) proper DC power supply that must be one of the following:

• Switching regulator

• Low Drop-Out (LDO) linear regulator

• Rechargeable Li-Ion battery

• Primary (disposable) battery

Main Supply Available?

BatteryLi-Ion 3.7 V

Linear LDO Regulator

Main Supply Voltage >5 V?

Switching Step-Down Regulator

No, portable device

No, less than 5 V

Yes, greater than 5 V

Yes, always available

Figure 3: VCC supply concept selection

The switching step-down regulator is the typical choice when the available primary supply source has a nominal voltage much higher (e.g. greater than 5 V) than the LISA-C200 and FW75-C200 modules operating supply



Page 15 of 103

voltage. The use of switching step-down provides the best power efficiency for the overall application and minimizes current drawn from the main supply source.

The use of an LDO linear regulator becomes convenient for a primary supply with a relatively low voltage (e.g. less than 5 V). In this case the typical 90% efficiency of the switching regulator will diminish the benefit of voltage step-down and no true advantage will be gained in input current savings. On the opposite side, linear regulators are not recommended for high voltage step-down as they will dissipate a considerable amount of energy in thermal power.

If LISA-C200 and FW75-C200 modules are deployed in a mobile unit where no permanent primary supply source is available, then a battery will be required to provide VCC. A standard 3-cell Lithium-Ion battery pack directly connected to VCC is the usual choice for battery-powered devices. During charging, batteries with Ni-MH chemistry typically reach a maximum voltage that is above the maximum rating for VCC, and should therefore be avoided.

The use of primary (not rechargeable) batteries is uncommon, since most available batteries are seldom capable of delivering the peak current due to high internal resistance.

Keep in mind that the use of batteries requires the implementation of a suitable charger circuit (not included in LISA-C200 and FW75-C200 modules). The charger circuit should be designed in order to prevent over-voltage on VCC beyond the upper limit of the absolute maximum rating.

The following sections highlight some design aspects for each of the supplies listed above.

1.5.3.1 Switching regulator

The characteristics of the switching regulator connected to VCC pins should meet the following requirements:

• Power capability: the switching regulator with its output circuit must be capable of providing a voltage value to the VCC pins within the specified operating range and must be capable of delivering greater than 1.2 Amps for safe design margin.

• Low output ripple: the switching regulator together with its output circuit must be capable of providing a clean (low noise) VCC voltage profile.

• High switching frequency: for best performance and for smaller applications select a switching frequency ≥ 600 kHz (since L-C output filter is typically smaller for high switching frequency). The use of a switching regulator with a variable switching frequency or with a switching frequency lower than 600 kHz must be carefully evaluated since this can produce noise in the VCC voltage profile. An additional L-C low-pass filter between the switching regulator output to VCC supply pins can mitigate the ripple on VCC, but adds extra voltage drop due to resistive losses on series inductors.

• PWM mode operation: it is preferable to select regulators with Pulse Width Modulation (PWM) mode. While in active mode, Pulse Frequency Modulation (PFM) mode, and PFM/PWM mode, transitions must be avoided to reduce the noise on the VCC voltage profile. Switching regulators able to switch between low ripple PWM mode and high efficiency burst or PFM mode can be used to provide the mode transition from idle mode (current consumption approximately 2 mA) to active mode (current consumption approximately 100 mA). It is permissible to use a regulator that switches from the PWM mode to the burst or PFM mode at an appropriate current threshold (e.g. 60 mA).

Figure 4 and the components listed in Table 6 show an example of a high reliability power supply circuit, where the module VCC is supplied by a step-down switching regulator with low output ripple and with fixed switching frequency in PWM mode operation greater than 1 MHz. The use of a switching regulator is suggested when the difference from the available supply rail to the VCC value is high: switching regulators provide good efficiency transforming a 12 V supply to the typical 3.8 V value of the VCC supply.



Page 16 of 103

u-blox C20012V

C6

R3

C5

R2

C3

C2

C1

R1

VIN

RUN

VC

RT

PG

SYNC

BDBOOS

TSW

FBGND

6

7

10

9

5C7

1

2

3

8

11

4

C8

C9

L2

D1

R4

R5

L1

C4

U1

VCC

GND

Figure 4: Suggested schematic design for the VCC voltage supply application circuit using a step-down regulator

Reference Description Part Number – Manufacturer

C1 47 µF Capacitor Aluminum 0810 50 V MAL215371479E3 – Vishay

C2 10 µF Capacitor Ceramic X7R 5750 15% 50 V C5750X7R1H106MB – TDK

C3 10 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R71C103KA01 – Murata

C4 680 pF Capacitor Ceramic X7R 0402 10% 16 V GRM155R71H681KA01 – Murata

C5 22 pF Capacitor Ceramic COG 0402 5% 25 V GRM1555C1H220JZ01 – Murata

C6 10 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R71C103KA01 – Murata

C7 470 nF Capacitor Ceramic X7R 0603 10% 25 V GRM188R71E474KA12 – Murata

C8,C9 22 µF Capacitor Ceramic X5R 1210 10% 25 V GRM32ER61E226KE15 – Murata

D1 Schottky Diode 40 V 3 A MBRA340T3G - ON Semiconductor

L1 10 µH Inductor 744066100 30% 3.6 A 744066100 - Wurth Electronics

L2 1 µH Inductor 7445601 20% 8.6 A 7445601 - Wurth Electronics

R1 470 kΩ Resistor 0402 5% 0.1 W 2322-705-87474-L - Yageo



R4 390 kΩ Resistor 0402 1% 0.063 W RC0402FR-07390KL - Yageo


U1 Step Down Regulator MSOP10 3.5 A 2.4 MHz LT3972IMSE#PBF - Linear Technology

Table 6: Suggested components for the VCC voltage supply application circuit using a step-down regulator

1.5.3.2 Low Drop-Out (LDO) linear regulator

The characteristics of the LDO linear regulator connected to the VCC pins should meet the following requirements:

• Power capabilities: the LDO linear regulator with its output circuit must be capable of providing a proper voltage value to the VCC pins and of delivering 1.2 A.

• Power dissipation: the power handling capability of the LDO linear regulator must be checked to limit its junction temperature to the maximum rated operating range (i.e. check the voltage drop from the max input voltage to the min output voltage to evaluate the power dissipation of the regulator).



Page 17 of 103

Figure 5 and the components listed in Table 7 show an example of a power supply circuit, where the VCC module supply is provided by an LDO linear regulator capable of delivering 1.2 Amps, with proper power handling capability. The use of a linear regulator is suggested when the difference from the available supply rail and the VCC value is low: linear regulators provide high efficiency when transforming a 5 V supply to the 3.6 V typical value of the VCC supply.

5V

C1 R1

IN OUT

ADJ

GND

1

2 4

5

3

C2R2

R3

U1

SHDN

u-blox C200

VCC

GND

Figure 5: Suggested schematic design for the VCC voltage supply application circuit using an LDO linear regulator

Reference Description Part Number - Manufacturer

C1 10 µF Capacitor Ceramic X5R 0603 20% 6.3 V GRM188R60J106ME47 - Murata

C2 10 µF Capacitor Ceramic X5R 0603 20% 6.3 V GRM188R60J106ME47 - Murata

R1 47 kΩ Resistor 0402 5% 0.1 W RC0402JR-0747KL - Yageo Phycomp

R2 4.7 kΩ Resistor 0402 5% 0.1 W RC0402JR-074K7L - Yageo Phycomp

R3 2.2 kΩ Resistor 0402 5% 0.1 W RC0402JR-072K2L - Yageo Phycomp

U1 LDO Linear Regulator ADJ 3.0 A LT1764AEQ#PBF - Linear Technology

Table 7: Suggested components for VCC voltage supply application circuit using an LDO linear regulator

1.5.3.3 Rechargeable Li-Ion battery

Rechargeable Li-Ion batteries connected to the VCC pins should meet the following requirements:

• Maximum pulse and DC discharge current: the rechargeable Li-Ion battery with its output circuit must be capable of delivering 1.2 A to the VCC pins and must be capable of delivering a DC current greater than the module maximum average current consumption to VCC pins. The maximum pulse discharge current and the maximum DC discharge current are not always reported in battery data sheets, but the maximum DC discharge current is typically almost equal to the battery capacity in Amp-hours divided by 1 hour.

• DC series resistance: the rechargeable Li-Ion battery with its output circuit must be capable of avoiding a VCC voltage drop greater than 250 mV during peak currents (Max Tx Power).

1.5.3.4 Primary (disposable) battery

The characteristics of a primary (non-rechargeable) battery connected to VCC pins should meet the following requirements:



Page 18 of 103

• Maximum pulse and DC discharge current: the non-rechargeable battery with its output circuit must be capable of delivering 1.2 A to the VCC pins and must be capable of delivering a DC current greater than the module maximum average current consumption at the VCC pins. The maximum pulse and the maximum DC discharge current is not always reported in battery data sheets, but the maximum DC discharge current is typically almost equal to the battery capacity in Amp-hours divided by 1 hour.

• DC series resistance: the non-rechargeable battery with its output circuit must be capable of avoiding a VCC voltage drop greater than 250 mV during peak currents (Max Tx Power).

1.5.3.5 Additional recommendations for the VCC supply application circuits

To reduce voltage drops, use a low impedance power source. The resistance of the power supply lines (connected to the VCC and GND pins of the module) on the application board and battery pack should also be considered and minimized: cabling and routing must be as short as possible in order to minimize power losses.

Three3 or five4 pins are allocated for VCC supply. Another seven pins are designated for GND connection. Even if all the VCC pins and all the GND pins are internally connected within the module, it is recommended to properly connect all of them to supply the module in order to minimize series resistance losses.

The placement of ceramic capacitors on the VCC line on the main board close to the connector will benefit operation.

To reduce voltage ripple and noise, place the following capacitors near the VCC pins:

• 100 nF capacitor (e.g. Murata GRM155R61A104K) to filter digital logic noise from clocks and data sources

• 22 µF capacitor (e.g. Murata GRM31CR60J226K) to supply local DC energy

Figure 6 shows the complete configuration but the mounting of each single component depends on the application design.

3.6V

C1

GND

C2

u-blox C200

VCCVCC

VCC

+ VCCVCC

LISA-C200

FW75

Figure 6: Suggested schematic design to reduce voltage ripple and noise and to avoid undershoot/ overshoot on voltage drops


C1 22 µF Capacitor Ceramic 6.3 V 45 GRM31CR60J226K - Murata

C2 100 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R61A104KA01 - Murata

Table 8: Suggested components to reduce voltage ripple and noise and to avoid undershoot/ overshoot on voltage drops

3 LISA-C200. 4 FW75.



Page 19 of 103

1.6 System functions

1.6.1 Module power-on

The module power-on sequence is initiated in one of these two ways:

• Rising edge on the VCC pin to a valid voltage for module supply AND if the PWR_ON pin is permanently low when VCC is applied

• Falling edge on the PWR_ON pin (hold pin low for >300 ms)


PWR_ON Power-on input PWR_ON pin has internal pull up resistor. Recommended to use open collector or drain configuration to pull down.

Table 9: Power-on pin

The PWR_ON pin ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-A114F). Higher protection level could be required if the line is externally accessible on the application board. Higher protection level can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) on the line connected to this pin.

1.6.1.1 Rising edge on VCC

When a supply is connected to VCC pins, the module supply supervision circuit controls the subsequent activation of the power-up state: the module is switched on when the voltage rises up to the VCC operating range minimum limit (3.4 V). (See LISA-C2 series Data Sheet [1] or the FW75-C200 Data Sheet [2]), provided that the PWR_ON pin is permanently low when VCC is applied.

1.6.1.2 Falling edge on PWR_ON

The module power-on sequence starts when a falling edge is forced on the PWR_ON input pin. After applying a falling edge, it is suggested to hold a low level on the PWR_ON signal for at least 300 ms to properly switch on the module.

The electrical characteristics of the PWR_ON input pin are different from the other digital I/O interfaces: the high and the low logic levels have different operating ranges. The detailed electrical characteristics are described in the LISA-C2 series Data Sheet [1] or the FW75-C200 Data Sheet [2].

Once the module has been turned on, PWR_ON pin has no effect. On the other hand it makes no sense to keep this pin low once the module has been turned on: if the pin is kept low it will draw unnecessary current.

Following are some typical examples of application circuits to turn the module on using the PWR_ON input pin.

The simplest way to turn on the module is to use a push button that shorts the PWR_ON pin to ground.

If the PWR_ON input is connected to an external device (e.g. application processor), it is suggested to use an open drain output on the external device.



Page 20 of 103

u-blox C200

PWR_ON

Power-on push button

ESD

Open Drain Output

Application Processor

u-blox C200

PWR_ON

Figure 7: PWR_ON application circuits using a push button and an open drain output of an application processor

Reference Description Remarks

ESD CT0402S14AHSG - EPCOS Varistor array for ESD protection

Table 10: Example of pull-up resistor and ESD protection for the PWR_ON application circuits

1.6.1.3 Additional considerations

Once the module is powered-on, the proper way to switch off the module is by means of the AT+CPWROFF command. When the module is in power-off mode, i.e. the AT+CPWROFF command has been sent and a voltage value within the operating range limits is still provided to the VCC pin, the digital input-output pads of the baseband chipset (i.e. all the digital pins of the module) are locked in tri-state (i.e. floating). The power down tri-state function isolates the module pins from its environment, when no proper operation of the outputs can be guaranteed.

The module can be switched on from power-off mode by forcing a proper start-up event (i.e. a falling edge on the PWR_ON pin). After the detection of a start-up event, all the digital pins of the module are held in tri-state until all the internal LDO voltage regulators are turned on in a defined power-on sequence. Then the baseband core is still held in reset state for a time interval: the internal reset signal (which is not available on a module pin) is still low and any signal from the module digital interfaces is held in reset state.

The reset state of all the digital pins is reported in the pin description table of the LISA-C2 series Data Sheet [1] or the FW75-C200 Data Sheet [2] . When the internal signal is released, the configuration of the module interfaces starts: during this phase any digital pin is set in a proper sequence from the reset state to the default operational configuration. Finally, the module is ready to operate when all interfaces are configured. However, a complete boot-up will take 10 seconds to complete due to background software tasks loading.

The Internal Reset signal is not available on a module pin.

LISA-C200: Pay special attention when using voltage level shifter connections. V_INT (1.8V) is provided to support biasing of level shifter ASICs. A problem can result when external circuitry back feeds voltage to this V_INT pin at any time, whether ON or OFF. If back feeding occurs it can result in unpredictable behavior and possible memory corruption within the modem.



Page 21 of 103

1.6.2 Module power-off

The correct way to switch off LISA-C200 and FW75-C200 modules is by means of the +CPWROFF AT command (more details in u-blox C2 series AT Commands Manual [3]). Using this method, internal software tasks are properly terminated, the current parameter settings are saved in the module’s non-volatile memory, and a proper network detach is performed.

An under-voltage shutdown will be done if the VCC supply is removed, but in this case the internal software tasks are interrupted, the current modem parameter settings are not saved in the module’s non-volatile memory, and a proper network detach cannot be performed. Once the supply is removed, it takes minimally 2 seconds after the voltage falls below 2.6 V to reach power-off state. It is advised to avoid performing an under-voltage shutdown if not necessary. Do not perform an under-voltage shutdown or reset by asserting RESET_N pin low until the module has been powered on for at least 10 seconds.

The module must have been powered on for at least 10 seconds before a hard reset or an under-voltage can be applied. Failure to comply may result in unpredictable behavior and possible memory corruption.

1.6.3 Module reset

The module reset can be performed by:

• AT+CFUN command (more details in u-blox C2 series AT Commands Manual [3]): in this case an “internal” or “software” reset is performed, causing an asynchronous reset of the baseband processor. This is the preferred method to perform a reset.

• Forcing a low level on the RESET_N input pin, causing an “external” or “hardware” reset (LISA-C200 only). Before performing a reset with this method, allow at least 10 sec for the module to stay powered on. It is advised to minimize or to completely avoid performing a reset with this method

LISA-C200: The recommended hold time to reset modem is 300 ms to 500 ms. Longer hold times approaching 1000 ms will cause the modem to power down.

The RESET_N function should NOT be used as a function to turn OFF the C200 modules. Use the +CPWROFF to do so.

LISA-C200 provides an internal pull-up on the RESET_N pin: an open drain / collector driver is recommended. Driving or pulling RESET_N high externally is NOT permitted.

The module must have been powered on for at least 10 seconds before a hard reset or an under-voltage can be applied. Failure to comply may result in unpredictable behavior and possible memory corruption.

1.6.4 Power-on, Power-off and Reset Sequences

This section describes the recommended sequencing to control the modem:

1.6.4.1 Power-on using PWR_ON method

• Apply VCC • Wait 50 ms • Ensure voltage at V_INT pin is 0V before next step (ie no back feed voltage)

• Pull PWR_ON pin low for 300 ms (boot time) • Release PWR_ON pin back to high • Modem is operational after 3 sec



Page 22 of 103

• After 10 sec, the internal background tasks are fully initialized

It is very important to ensure the module V_INT pin is at 0V before power-on. This will ensure all areas of the internal module are completely powered down. Failure to comply may result in unpredictable behavior and possible memory corruption.

The following figure illustrates the power-on sequence and timing of power supply and control signals.

VCC

P WR_ON

V_INT

Internal Res et

Interface S ignals

S ys tem S tate

Interface S tateBackground

tasks loading

ONOFF

Tristate Internal RST Internal Reset → Operational

Start-up event

Start of interface configuration

PWR_ON can be set high

50 ms 350 ms 3 s

All interfaces are configured

0 ms 200 ms 10 s

Tasks loaded

Figure 8: Module power up timing and sequence of supply and signals

1.6.4.2 Power-on using VCC method

• Pull PWR_ON pin low prior to applying VCC and wait 20 ms, or keep permanently held low • Ensure voltage at VCC pin is 0V before applying VCC • Ensure voltage at V_INT pin is 0V before applying VCC • Apply VCC • Wait 300 ms (boot time) • Release PWR_ON pin back to high, or keep permanently held low • Modem is operational after 3 sec • After 10 sec, the internal background tasks are fully initialized

It is very important to ensure the module VCC pin and V_INT pin is at 0V before power-on. This will ensure all areas of the internal module are completely powered down. Failure to comply may result in unpredictable behavior and possible memory corruption.

1.6.4.3 Power-off

Preferred method

• Issue AT+CPWROFF AT command; either via UART or USB • Wait for OK response • Wait for at least 10 sec after OK response • Remove VCC



Page 23 of 103

Removing VCC is not required though Off current will continue to be drawn from VCC source. However, if VCC is removed, then ensure VCC pin and V_INT pin is 0V before powering back on. Refer to section 1.6.4.1 for details.

• Modem is off

The following figure shows the power-off sequence and timing.

VCC

V_INT

P WR_ON

Interface S ignals

RE S E T_N

S ys tem S tate

Interface S tate Operational

OFF

Tristate / F loating

ON

Operational → Tristate / F loating

AT+CPWROFFsent to the module

0 ms X ms X + 10 sec

OKreplied by the module

Remove all interface signals

Figure 9: Module power up timing and sequence of supply and signals

When designing a host application for robustness, typically it covers a scenario in which the OK response is not returned after issuing AT+CPWROFF to LISA-C200. To add robustness for such a case, wait 20 seconds after issuing the command, and if OK has yet to be returned then as a last option perform either one of these actions:

• Apply a hard reset using asserting RESET_N low for 300 to 500 ms. Refer to section 1.6.4.4 for further details on applying reset.

• Apply an under-voltage shutdown. Refer to section 1.6.2 for more details.

1.6.4.4 Reset

Preferred method using AT command

• Issue AT+CFUN=1 AT command, either via UART or USB • Time to reset is approximately 200 ms; after reset time, the modem is ready for normal operation •

Alternative method using RESET_N pin, when the AT command method not possible

• Ensure modem has been powered on for at least 10 sec • Pull RESET_N pin low for 300 to 500 ms (max) • Modem requires a minimal of 10 sec before another reset with this method and be reattempted

1.6.5 Key points to system functions

This section is a collection of key points from section 1.6 regarding Supply, Power-on/off, and Reset. The goal is to point out important key points to avoid common errors and to avoid misuse.

Power supply

• Handle any sudden momentary power loss gracefully as described in section 1.5.2.1



Page 24 of 103

Power-on

• Ensure V_INT is 0V before power-on (ie no back feed voltage) • Ensure VCC is 0V before applying supply for ‘VCC method’ as described in section 1.6.4.2

Power-off

• Use AT+CPWROFF AT command to gracefully power down • Minimize or avoid entirely using under voltage method to shutdown C200. • If under voltage method is the only option, then wait until the module has been powered on for a

minimal 10 sec before doing so

Reset

• Use AT+CFUN=1 AT command method to perform reset • After power-on, it is not necessary and not recommended to perform a reset to ensure modem is

starting from a “fresh” state • Minimize or avoid entirely using RESET_N pin to perform reset • Asserting RESET_N pin low to perform a reset, should only be 300 to 500 ms • Do not hold RESET_N over 500 ms, because as the time gets near 1000 ms it will cause the module to

abruptly power-off. • RESET_N should only be used as a last option. If it should be utilized then:

1. Allow the module to be powered on for a minimal of 10 sec before apply this reset method 2. Do allow enough time between each reset attempt with the RESET_N pin method

Control pins

• Driving/pulling RESET_N high externally is NOT permitted • Driving/pulling PWR_ON high externally is NOT permitted

1.7 RF connection The ANT connector has a 50 Ω nominal characteristic impedance and must be connected to the antenna through a 50 Ω transmission line to allow transmission and reception of radio frequency (RF) signals in the Cell and PCS operating bands.


ANT RF connector Zo = 50 Ω nominal characteristic impedance.

FW75-C200 Ant U.FL connector

LISA-C200 Ant Surface Mount pad

Table 11: Antenna connector

The ANT port ESD sensitivity rating is 2KV (according to JESD22-A114D / AEC-Q100-002 for Human Body Model). Higher protection level could be required if the line is externally accessible on the application board.

Choose an antenna with optimal radiating characteristics for the best electrical performance and overall module functionality. Focus on minimizing the insertion loss between radiating antenna and the module RF connector. Overall system performance depends on antenna reception and transmission. See section 2.4 for further details regarding antenna guidelines.



Page 25 of 103

1.8 SIM interface LISA-C200 and FW75-C200 modules feature a hardware interface to support SIM cards.

In the CDMA environment, the SIM interface is called R-UIM which stands for Removable User Indentity Module. This card is developed for CDMA products as an extention of the GSM SIM card and its functionality.

Please contact u-blox support for further details on SIM / R-UIM support.

1.9 Serial communication LISA-C200 and FW75-C200 modules provide the following serial communication interfaces, where AT command interface and Packet-Switched Data communication are concurrently available:

• One asynchronous serial interface (UART) that provides RS-232 functionality conforming to ITU-T V.24 Recommendation [5], with limited data rate.

• One full-speed USB 2.0 compliant interface, with maximum data rate of 12 Mb/s.

• Only one interface is active. Default is USB, if no USB is detected then it is assumed that the UART interface is desired.

LISA-C200 and FW75-C200 modules are designed to operate as a CDMA cellular modem, which represents the data circuit-terminating equipment (DCE) as described by the ITU-T V.24 Recommendation [5]. A customer application processor connected to the module through one of the interfaces represents the data terminal equipment (DTE).

All the interfaces listed above are controlled and operated with:

• Sprint / Aeris required AT Commands (C200 series)

• Verizon / US Cellular required AT Commands (C200 series)

• AT commands according to 3GPP TS 27.010 [8]

• AT commands according to 3GPP TS 27.005 [6] • u-blox AT commands

For the complete list of supported AT commands and their syntax refer to the u-blox C2 series AT Commands Manual [3].

• The USB interface, using all the lines provided (VUSB_DET, USB_D+ and USB_D-), can be used for firmware upgrade

To directly enable PC (or similar) connection to the module for firmware upgrade, provide direct access on the application board to the VUSB_DET, USB_D+ and USB_D- lines of the module . Also provide access to the PWR_ON & HW_SHUTDOWN pins, or enable the DC supply connected to the VCC pin to start the module firmware upgrade The following sub-chapters describe serial interface configuration and provide a detailed description of each interface for the application circuits.

For C200 modules, the diagnostics Port is always available on USB

The Diagnostics Port is available after 5 seconds of UART connectivity. It only provides logging information, and cannot be used for AT command interaction once the UART port has been assigned as the AT command interface. See above.



Page 26 of 103

1.9.1 Serial interfaces configuration

UART and USB serial interfaces are available as AT command interface and for Packet-Switched Data communication. The serial interfaces are configured as described in Table 12 (for information about further settings, refer to the u-blox C2 series AT Commands Manual [3]).

The UART is a 5 wire implementation, therefore DTR, DSR and DCD functions are not available.

Interface AT Settings Comments

UART interface Enabled Multiplexing mode can be enabled by AT+CMUX command providing following channels: • Channel 0: control channel • Channel 1: AT commands • Channel 2: data connection

AT+IPR=115200 Baud rate: 115200 b/s

Frame format: 8 bits, no parity, 1 stop bit

USB interface Enabled

Table 12: Default serial interfaces configuration

1.9.2 Asynchronous serial interface (UART)

The UART interface is a 5-wire unbalanced asynchronous serial interface that provides AT commands interface and PSD data communication.

The UART interface provides RS-232 functionality conforming to the ITU-T V.24 Recommendation (more details available in ITU Recommendation [5]), with CMOS compatible signal levels: 0 V for low data bit or ON state, and 1.8/2.8 V for high data bit or OFF state. One external voltage translator (e.g. Maxim MAX13234E) could be used to provide RS-232 (5 lines) compatible signal levels. This chip translates the voltage levels from 1.8 V (module side) to the RS-232 standard. For detailed electrical characteristics, refer to the LISA-C2 series Data Sheet [1], or the FW75-C200 Data Sheet [2].

FW75-C200 logic levels are 2.8 V interface. LISA-C200 logic levels are 1.8 V interface.

The signal names of the LISA-C200 and FW75-C200 modules UART interface conform to the ITU-T V.24 Recommendation [5].

UART interfaces include the following lines:


RI Ring Indicator Module output

RTS

Ready to send Module hardware flow control input Circuit 105 (Request to send) in ITU-T V.24 FW75-C200 - Internal active pull-up to V_INT (2.8 V) interface. LISA-C200- Internal active pull-up to V_INT (1.8 V) interface.

CTS Clear to send Module hardware flow control output Circuit 106 (Ready for sending) in ITU-T V.24 FW75-C200 - Internal active pull-up to V_INT (2.8 V) interface. LISA-C200- Internal active pull-up to V_INT (1.8 V) interface.

TxD Transmitted data Module data input Circuit 103 (Transmitted data) in ITU-T V.24 Internal active pull-up to V_INT (2.8 V) enabled. FW75-C200 - Internal active pull-up to V_INT (2.8 V) interface. LISA-C200- Internal active pull-up to V_INT (1.8 V) interface.



Page 27 of 103


RxD Received data Module data output Circuit 104 (Received data) in ITU-T V.24 FW75-C200 - Internal active pull-up to V_INT (2.8 V) interface. LISA-C200- Internal active pull-up to V_INT (1.8 V) interface.

GND Ground

Table 13: UART interface signals

The UART interface pins ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-A114F). Higher protection level could be required if the lines are externally accessible on the application board. Higher protection level can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) on the lines connected to these pins.

1.9.2.1 RI signal behavior

The RI behaviour on LISA-C200 is different than on GSM/UMTS/HPSA modules, such as LEON, SARA, and LISA-U series modules. On LISA-C200, RI toggles between voice call, SMS, and data session, while on ublox’s GSM/UMTS/HSPA based modules, RI does not toggle while in a data session, unless there is an incoming voice call or SMS. The reason for the difference is that CDMA technology does not support multiple transport types (circuit switched and packet switched) at the same time, where GSM/UMTS/HSPA does support them.

The RI line is available on the first serial interface ASC0 (see also Section 3.10). The signal serves to indicate incoming calls and other types of URCs (Unsolicited Result Code). Although not mandatory for use in a host application, it is strongly suggested to connect the RI line to an interrupt line of the application. In this case, the application can be designed to receive an interrupt when a falling edge on RI line occurs. This solution is most effective, particularly, for waking up a host/application from power saving mode.

The behavior of the RI line varies with the type of event. When a voice/SMS/fax/data call comes in, the RI line goes low for 1 s and high for another 4 s. Every 5 seconds the ring string is generated and sent over the /RXD0 line.

Figure 10: URC transmission for voice/fax/data

If there is a call in progress and call waiting is activated for a connected handset or hands free device, the RI line switches to ground in order to generate acoustic signals that indicate the waiting call.

All other types of Unsolicited Result Codes (URCs) also cause the RI line to go low, however for 1 second only.



Page 28 of 103

Figure 11: Other URC transmissions

1.9.2.2 UART and power saving

During the idle mode, the device turns off non-vital functions to take advantage of the power consumption improvements, and during this time, a 32 KHz clock runs to synchronize all the tasks needed. CDMA states that a device should awake at the designated slotted time given by the System_Parameters_Message using the max_slot_cycle_index value assigned by the network. During this moment, all RF components of the terminal will start running to decode all the messages coming in via the paging channel, will respond accordingly, and will go back to idle mode once the active mode period ends, if no action is requested.

If during the idle mode, the host application sends any interaction data to the device, it will process this information and will respond accordingly; the latency time for the wake-up action is about 20 ms.

UART power saving is implemented in versions C200-02S-01 and C200-22S-01, and onwards.

In comparison to USB, the UART power saving implementation presents a better power consumption for this purpose.

By default, the power saving mode is disabled. In order to force the module to enter power saving mode:

• AT command AT+UPSV=4 must be issued

• Host must keep low the TxD pin (pin 15 on LISA-C200, pin 32 in FW75-C200)

Once the TxD pin has been put low by the host, the UART is disabled. The host must monitor the RI line in order to trigger a system wake up (by releasing the TxD line) in case of network notifications.

• AT+UPSV command is saved in the non-volatile memory.

• If power saving is enabled (+UPSV=1), the UART interface is cyclically enabled and the module enters power save mode once the timeout value is completed.

• If the power saving mode is controlled by the UART RTS signal (+UPSV=2), the UART interface is enabled and the module doesn’t enter power save mode as long as the RTS line is ON.

• AT+UPSV=4 command must be issued before putting low the TxD pin to ensure proper power saving operation.

• If power saving mode is disabled (+UPSV=0), the UART interface is always enabled and the module doesn’t enter power save mode.

• The current consumption profiles when power saving is enabled and disabled are shown in the figures below.

0

RI

1s

URC

1 time [s]



Page 29 of 103

Figure 12: Current consumption profile during cyclic idle/active mode (power saving enabled)

Figure 13: Current consumption profile during cyclic idle/active mode (power saving disabled)

1.9.2.3 UART application circuits

The u-blox C2 series family provides a 5-wire UART (TxD, RxD, RTS, CTS and RI); the application circuit described in Figure 14 must be implemented:

~15 mA

IDLE MODE

(EX enabled)

~300ms

Time [s]

Current [mA]

50

0

Active Mode

~1.4 mA

60-70 mA

Time [s]

Current [mA]

50

0

Active Mode (RX enabled)

~300ms

0.98s / 2.26s / 4.82 s

0.98s / 2.26s / 4.82 s IDLE MODE

60-70 mA



Page 30 of 103

u-blox(DCE)

LISA (1.8v logic)FW75 (3.0v logic)

TxD

Application Processor (DTE)

RxD

RTS

CTS

DTR

DSR

RI

DCD

GND

TXD

RXD

RTS

CTS

RI

GND

0 Ω

0 Ω

TP

TP

0 Ω

0 Ω

TP

TP

Figure 14: UART interface application circuit with partial V.24 link (5-wire) in the DTE/DCE serial communication

If a 3.0 V Application Processor is used, appropriate unidirectional voltage translators must be provided using the module V_INT output as 1.8 V supply, as described in Figure 15.

V_INT

TxD

Application Processor(3.0V DTE)

RxD

RTS

CTS

DTR

DSR

RI

DCD

GND

LISA-C200 series (1.8V DCE)

TXD

DTR

RXD

RTS

CTS

DSR

RI

DCD

GND

0 Ω0 Ω

TP

TP

0 Ω0 Ω

TP

TP

1V8

B1 A1

GND

U1

B3A3

VCCBVCCA

UnidirectionalVoltage Translator

C1 C2

3V0

DIR3

DIR2 OE

DIR1VCC

B2 A2

B4A4

DIR4

1V8

B1 A1

GND

U2

B3A3

VCCBVCCA


C3 C4

3V0

DIR1

DIR3 OE

B2 A2

B4A4

DIR4

DIR2

Figure 15: UART interface application circuit with complete V.24 link in DTE/DCE serial communication (3.0 V DTE)


C1, C2, C3, C4 100 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R61A104KA01 - Murata

U1, U2 Unidirectional Voltage Translator SN74AVC4T774 - Texas Instruments

Table 14: Component for UART application circuit with complete V.24 link in DTE/DCE serial communication (3.0 V DTE)

Additional considerations

If the module USB interface is connected to the application processor, testpoints can be added on the lines to accommodate the access. Each line must have a 0 Ω series resistor mounted on it to detach the module pin from any other connected device. Otherwise, if the USB interface is not connected to the application processor, it is highly recommended to provide direct access to VUSB_DET, USB_D+, USB_D- lines for execution of firmware upgrade over USB and for debugging purposes. In either case, also provide access to the RESET_N pin, or to the PWR_ON pin, or enable the DC supply connected to the VCC pin to start the module firmware upgrade.



Page 31 of 103

Any external signal connected to the UART interface must be tri-stated when the module is in power-down mode, when the external reset is forced low and during the module power-on sequence (at least for 3 s after the start-up event), to avoid latch-up of circuits and allow a proper boot of the module. If the external signals connected to the cellular module cannot be tri-stated, insert a multi channel digital switch (e.g. Texas Instruments SN74CB3Q16244, TS5A3159, or TS5A63157) between the two-circuit connections and set to high impedance during module power down mode, when external reset is forced low and during power-on sequence.

LISA-C200 modules require special attention when used with voltage level shifter connections. V_INT (1.8V) is provided to support biasing of level shifter ASICs. A problem can result with certain level shifter interface buffers, which can back feed voltage to the V_INT line preventing the modem from powering off and/or resetting properly. The back feed voltage typically comes from host output through the level shifter: either from the level shifter VCC pin connected to V_INT, or to the modem TxD input lines though an internal protection diode with modem. With modem VCC = 0 V, a measured voltage can range from 0.3 to 1.0 V on the V_INT, preventing the modem from ever resetting or powering up or down properly.

1.9.3 USB interface

LISA-C200 and FW75-C200 modules provide a full-speed USB interface at 12 Mb/s compliant with the Universal Serial Bus Revision 2.0 specification [10]. It acts as a USB device and can be connected to any USB host such as a PC or other Application Processor.

The USB-device looks for all upper-SW-layers like any other serial device. This means that LISA-C200 and FW75-C200 modules emulate all serial control logical lines.

If the logical DTR line isn't enabled by the USB host, the module doesn’t answer to AT commands by the USB interface.


VUSB_DET USB detect input Apply 5 V typical to enable USB

USB_D+ USB Data Line D+ 90 Ω nominal differential impedance. Pull-up or pull-down resistors and external series resistors as required by the USB 2.0 high-speed specification [10] are part of the USB pad driver and need not be provided externally.

USB_D- USB Data Line D- 90 Ω nominal differential impedance. Pull-up or pull-down resistors and external series resistors as required by the USB 2.0 high-speed specification [10] are part of the USB pad driver and need not be provided externally.

Table 15: USB pins

The USB interface pins ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-A114F). Higher protection level could be required if the lines are externally accessible on the application board. Higher protection level can be achieved by mounting a very low capacitance (i.e. less or equal to 1 pF) ESD protection (e.g. Tyco Electronics PESD0402-140 ESD protection device) on the lines connected to these pins.



Page 32 of 103

LISA-C200 and FW75-C200 modules identify themselves by their VID (Vendor ID) and PID (Product ID) combination, included in the USB device descriptors:

LISA-C200 and FW75-C200

• VID = 0x05C6 PID = 0x9004

1.9.3.1 USB and power saving

When the USB port has been set as the AT command interface (at boot), setting +UPSV mode is not necessary for power save mode to work, it is automatically enabled.

In summary this configuration (USB = AT Interface):

- The +UPSV <mode> setting has no effect; power save mode is automatically enabled - Physical disconnection of the USB cable or suspension by the USB host will allow the module to enter

power save mode - The module’s current drops to the expected <2mA when then USB port is disconnected or the host goes

into sleep mode

The current consumption profiles when power saving is enabled and disabled are shown in Figure 16 & Figure 17.

On FW versions prior to x4S: the module will enter power save mode at a fixed timeout value (default), after the host goes enters suspend mode or physical USB disconnection.

On FW version x4S and onwards, the module will enter power save mode as specified on the +UPSV <timeout> value, after the host enters suspend mode or physical USB disconnection.

Figure 16: Current consumption profile during cyclic idle/active mode (power saving enabled)

~1.4 mA

60-70 mA

0.98s / 2.26s / 4.82 s

Time [s]

Current [mA]

IDLE MODE Active Mode (RX Enabled)

~300ms



Page 33 of 103

Figure 17: Current consumption profile during cyclic idle/active mode (power saving disabled)

1.9.3.2 USB application circuit

Since the module acts as a USB device, the USB supply (5.0 V typ.) must be provided to VUSB_DET by the connected USB host. The USB interface is enabled only when a valid voltage as USB supply is detected by the VUSB_DET input. Neither the USB interface, nor the whole module is supplied by the VUSB_DET input: the VUSB_DET senses the USB supply voltage and absorbs few microamperes.

The USB_D+ and USB_D- lines carry the USB serial data and signaling. The lines are used in single ended mode for relatively low speed signaling handshake, as well as in differential mode for fast signaling and data transfer.

USB pull-up or pull-down resistors on pins USB_D+ and USB_D- as required by the Universal Serial Bus Revision 2.0 specification [10] are part of the USB pad driver and do not need to be externally provided.

External series resistors on pins USB_D+ and USB_D- as required by the Universal Serial Bus Revision 2.0 specification [10] are also integrated: characteristic impedance of USB_D+ and USB_D- lines is specified by the USB standard. The most important parameter is the differential characteristic impedance applicable for odd-mode electromagnetic field, which should be as close as possible to 90 Ω differential, signal integrity may be degraded if the PCB layout is not optimal, especially when the USB signaling lines are very long.

u-blox C200

VBUS

D+

D-

GND

VUSB_DET

USB_D+

USB_D-

GND

C1

USB DEVICE CONNECTO

R

D1

D2

D3

Figure 18: USB Interface application circuit


D1, D2, D3 Very Low Capacitance ESD Protection PESD0402-140 - Tyco Electronics

C2 100 nF Capacitor Ceramic X7R 0402 10% 16 V GRM155R61A104KA01 - Murata

Table 16: Component for USB application circuit

~15 mA

IDLE MODE

0.98s / 2.26s / 4.82 s

(EX enabled)

~300ms

Time [s]

Current [mA]

50

0

Active Mode

60-70 mA



Page 34 of 103

If the USB interface is not connected to the application processor, it is highly recommended to provide direct access to the VUSB_DET, USB_D+, USB_D- lines for execution of firmware upgrade over USB and for debugging purposes: testpoints can be added on the lines to accommodate the access. Provide access to RESET_N pin, or to the PWR_ON pin, or enable the DC supply connected to the VCC pin to start the module firmware upgrade

If the USB interface is not used, the USB_D+, USB_D- and VUSB_DET pins can be left unconnected, but it is highly recommended to provide (test points) direct access to the lines for execution of firmware upgrade and for debugging purposes.

1.9.4 MUX Protocol (3GPP 27.010)

LISA-C200 and FW75-C200 modules have a software layer with MUX functionality, 3GPP TS 27.010 Multiplexer Protocol [8], available on the UART physical link. The USB interface doesn’t support the multiplexer protocol.

This is a data link protocol (layer 2 of OSI model) which uses HDLC-like framing and operates between the module (DCE) and the application processor (DTE) and allows a number of simultaneous sessions over the UART: the user can concurrently use the AT command interface on one MUX channel and Packet-Switched Data communication on another MUX channel. Each session consists of a stream of bytes transferring various kinds of data such as SMS, PSD, AT commands in general. This permits, for example, SMS to be transferred to the DTE when a data connection is in progress.

The following virtual channels are defined:

• Channel 0: control channel

• Channel 1: AT commands

• Channel 2: data connection

1.10 DDC (I2C) interface

DDC(I2C) interface is supported only by LISA-C200-03S/23S and successive versions

1.10.1 Overview

An I2C bus compatible Display Data Channel (DDC) interface for communication with u-blox GNSS receivers is available on LISA-C modules. The communication between a u-blox cellular module and a u-blox GNSS receiver is only provided by this DDC (I2C) interface.


SCL I2C bus clock line Open drain. External pull-up required.

SDA I2C bus data line Open drain. External pull-up required.

Table 17: DDC pins

The DDC (I2C) interface pins ESD sensitivity rating is 1 kV (HBM according to JESD22-A114F). Higher protection level could be required if the lines are externally accessible on the application board. Higher protection level can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) on the lines connected to these pins, close to accessible points.

u-blox has implemented special features in LISA-C200 and FW75-C200 cellular modules to ease the design effort required for the integration of a u-blox cellular module with a u-blox GNSS receiver.

Combining a u-blox cellular module with a u-blox GNSS receiver allows designers to have full access to the GNSS receiver directly via the cellular module: it relays control messages to the GNSS receiver via a dedicated DDC (I2C)



Page 35 of 103

interface. A 2nd interface connected to the GNSS receiver is not necessary: AT commands via the UART serial interface of the cellular module allows a fully control of the GNSS receiver from any host processor.

LISA-C modules feature embedded GNSS aiding that is a set of specific features developed by u-blox to enhance GNSS performance, decreasing Time-To-First-Fix (TTFF), thus allowing it to calculate the position in a shorter time with higher accuracy.

The DDC (I2C) interface of all LISA-C series can be used to communicate with u-blox GNSS receivers. The cellular module acts as an I2C master, which can communicate to two I2C slaves as allowed by the I2C bus specifications.

For more details regarding the handling of the DDC (I2C) interface and the GNSS aiding features, refer to u-blox AT Commands Manual [3] (AT+UGPS, AT+UGPRF, AT+UGPIOC AT commands) and GPS Implementation Application Note [12].

1.10.2 DDC application circuit

The DDC (I2C) interface of LISA-C modules is used to connect the cellular module to a u-blox GNSS receiver: the communication with the u-blox GNSS receiver by DDC (I2C) interface is enabled by the AT+UGPS command (for more details refer to u-blox AT Commands Manual [3]). The SDA and SCL lines must be connected to the DDC (I2C) interface pins of the u-blox GNSS receiver (i.e. the SDA2 and SCL2 pins of the u-blox GNSS receiver) on the application board to allow the communication between the cellular module and the u-blox GNSS receiver.

To be compliant to the I2C bus specifications, the module bus interface pads are open drain output and pull up resistors must be used. Since the pull-up resistors are not mounted on the module, they must be mounted externally. Resistor values must conform to the I2C bus specifications [11]. If a LISA-C module is connected by the DDC (I2C) bus to a u-blox GNSS receiver (only one device can be connected on the DDC bus), use a pull-up resistor of 4.7 kΩ. Pull-ups must be connected to a supply voltage of 1.8 V (typical), since this is the voltage domain of the DDC pins.

Connect the DDC (I2C) pull-ups to the V_INT 1.8 V supply source, or another 1.8 V supply source enabled after V_INT (e.g., as the 1.8 V supply present in Figure 19 application circuit).

DDC Slave-mode operation is not supported, the module can act as master only.

Two lines, serial data (SDA) and serial clock (SCL), carry information on the bus. SCL is used to synchronize data transfers, and SDA is the data line. Since both lines are open drain outputs, the DDC devices can only drive them low or leave them open. The pull-up resistor pulls the line up to the supply rail if no DDC device is pulling it down to GND. If the pull-ups are missing, SCL and SDA lines are undefined and the DDC bus will not work.

The signal shape is defined by the values of the pull-up resistors and the bus capacitance. Long wires on the bus will increase the capacitance. If the bus capacitance is increased, use pull-up resistors with nominal resistance value lower than 4.7 kΩ, to match the I2C bus specifications [11] with respect to rise and fall times of the signals.

Capacitance and series resistance must be limited on the bus to match the I2C specifications (1.0 µs is the maximum allowed rise time on the SCL and SDA lines): route connections as short as possible.

If the pins are not used as DDC bus interface, they can be left unconnected.

LISA-C modules support these GNSS aiding types:

• Local aiding

• AssistNow Online

• AssistNow Offline

• AssistNow Autonomous

The embedded GNSS aiding features can be used only if the DDC (I2C) interface of the cellular module is connected to the u-blox GNSS receivers.

The GPIO pins can handle:



Page 36 of 103

• GNSS receiver power-on/off (“GPS supply enable” function provided by GPIO2)

• The wake up from idle-mode when the GNSS receiver is ready to send data (“GPS data ready” function provided by GPIO3)

The GPIO2 is by default configured to provide the “GPS supply enable” function (parameter <gpio_mode> of AT+UGPIOC command set to 3 by default), to enable or disable the supply of the u-blox GNSS receiver connected to the cellular module by the AT+UGPS command. The pin is set as

• Output / High, to switch on the u-blox GNSS receiver, if the parameter <mode> of AT+UGPS command is set to 1

• Output / Low, to switch off the u-blox GNSS receiver, if the parameter <mode> of AT+UGPS command is set to 0 (default setting)

The pin must be connected to the active-high enable pin (or the active-low shutdown pin) of the voltage regulator that supplies the u-blox GNSS receiver on the application board.

The “GPS supply enable” function improves the power consumption of the GNSS receiver. When the GNSS functionality is not required, the GNSS receiver can be completely switched off by the cellular module that is controlled by the application processor with AT commands.

The GPIO3 is by default configured to provide the “GPS data ready” function (parameter <gpio_mode> of AT+UGPIOC command set to 4 by default), to sense when the u-blox GNSS receiver connected to the cellular module is ready to send data by the DDC (I2C) interface. The pin will be set as:

• Input, to sense the line status, waking up the cellular module from idle-mode when the u-blox GNSS receiver is ready to send data by the DDC (I2C) interface, if the parameter <mode> of +UGPS AT command is set to 1 and the parameter <GPS_IO_configuration> of +UGPRF AT command is set to 16

• Tri-state with an internal active pull-down enabled, otherwise (default setting)

The pin that provides the “GPS data ready” function must be connected to the data ready output of the u-blox GNSS receiver (i.e. the pin TxD1 of the u-blox GNSS receiver) on the application board.

The “GPS data ready” function provides an improvement in the power consumption of the cellular module. When power saving is enabled in the cellular module by the AT+UPSV command and the GNSS receiver doesn’t send data by the DDC (I2C) interface, the module automatically enters idle-mode whenever possible. With the “GPS data ready” function the GNSS receiver can indicate to the cellular module that it is ready to send data by the DDC (I2C) interface: the GNSS receiver can wake up the cellular module if it is in idle-mode, so that data sent by the GNSS receiver will not be lost by the cellular module even if power saving is enabled.

Figure 19 illustrates the application circuit for connecting a LISA-C cellular module to a u-blox GNSS 1.8 V receiver.

SDA and SCL pins of the LISA-C cellular module are directly connected to the relative pins of the u-blox GNSS 1.8 V receiver, with appropriate pull-up resistors.

GPIO3 is directly connected respectively to the TxD1 pin of the u-blox GNSS 1.8 V receiver to provide “GPS data ready” functionality, and GPIO4 is directly connected to the EXTINT0 pin of the GNSS receiver to provide RTC synchronization timing input.

A pull-down resistor is mounted on the GPIO4 line for correct “GPS RTC sharing” function implementation.

A pull-down resistor is mounted on the GPIO2 line to avoid a switch on of the u-blox GNSS receiver when the LISA-C module is in the internal reset state.

The V_BCKP supply output of the u-blox cellular module is connected to the V_BCKP backup supply input pin of the GNSS receiver to provide the supply for the GNSS real time clock and backup RAM when the VCC supply of the cellular module is within its operating range and the VCC supply of the GNSS receiver is disabled. This enables the u-blox GNSS receiver to recover from a power breakdown with either a hot start or a warm start (depending on the duration of the GNSS VCC outage) and to maintain the configuration settings saved in the backup RAM.



Page 37 of 103

LISA-C200 does NOT have V_BCKP output to power the GNSS receiver RTC. Either V_INT or independent LDO can be used to source the RTC. V_INT output is 1.8 VDC after the module is fully powered on. See the LISA-C2 series Data Sheet [1] for details.

u-bloxWireless Module (except LISA-C200)

R1

INOUT

GND

GPS LDORegulator

SHDN

u-blox GPS / GNSS1.8 V receiver

SDA2SCL2

R2

1V8 1V8

VMAIN1V8

U1

21 GPIO2

SDASCL

C1

TxD1EXTINT0

GPIO3GPIO4

46

45

23

24

VCC

R3

V_BCKP V_BCKP / RSVD2

R4

Figure 19: DDC Application circuit for u-blox GNSS 1.8 V receiver


R1, R2, R4 4.7 kΩ Resistor 0402 5% 0.1 W RC0402JR-074K7L - Yageo Phycomp


U1 Voltage Regulator for GNSS Receiver See GNSS Receiver Hardware Integration Manual

Table 18: Components for DDC application circuit for u-blox GNSS 1.8 V receiver

Figure 20 illustrates the application circuit for the connection of a LISA-C cellular module to a u-blox GNSS 3.0 V receiver.

If a u-blox GNSS 3.0 V receiver is used, the SDA, SCL, GPIO3 and GPIO4 pins of the LISA-C cellular module cannot be directly connected to the u-blox GNSS 3.0 V receiver: a proper I2C-bus Bidirectional Voltage Translator must be used for the SDA and SCL signals, and a general purpose Voltage Translator must be used for the GPIO3 and GPIO4 signals. The V_BCKP supply output of the cellular module can be directly connected to the V_BCKP backup supply input pin of the GNSS receiver as in the application circuit for a u-blox GNSS 1.8 V receiver.



Page 38 of 103

u-bloxWireless Module

u-blox GPS / GNSS 3.0 V receiver

23 GPIO324 GPIO4

1V8

B1 A1

GNDU3

B2A2

VCCBVCCA


C4

C5

3V0

TxD1

EXTINT0

R1

INOUT

GND

GPS LDORegulator

SHDN

R2

VMAIN3V0

U1

21 GPIO2

46 SDA45 SCL

R4 R5

1V8

SDA_A SDA_B

GNDU2

SCL_ASCL_B

VCCAVCCB

I2C-bus Bidirectional Voltage Translator

4 V_INT

C1

C2 C3

R3

SDA2

SCL2

VCC

DIR1

DIR2

2 V_BCKP / RSVDV_BCKP

OER7

R6 OE

Figure 20: DDC Application circuit for u-blox GNSS 3.0 V receiver


R1, R2, R4, R5, R7 4.7 kΩ Resistor 0402 5% 0.1 W RC0402JR-074K7L - Yageo Phycomp



C2, C3, C4, C5 100 nF Capacitor Ceramic X5R 0402 10% 10V GRM155R71C104KA01 - Murata

U1, C1 Voltage Regulator for GNSS Receiver and relative output bypass capacitor

See GNSS Receiver Hardware Integration Manual

U2 I2C-bus Bidirectional Voltage Translator TCA9406DCUR - Texas Instruments

U3 Generic Unidirectional Voltage Translator SN74AVC2T245 - Texas Instruments

Table 19: Components for DDC application circuit for u-blox GNSS 3.0 V receiver


Any external signal connected to the DDC and GPIO interfaces must be tri-stated when the module is in power-down mode, when the external reset is forced low, and during the module power-on sequence (at least for 3 s after the start-up event), to avoid latch-up of circuits and allow a proper boot of the module. If the external signals connected to the cellular module cannot be tri-stated, insert a multi-channel digital switch (e.g. Texas Instruments SN74CB3Q16244, TS5A3159, or TS5A63157) between the two-circuit



Page 39 of 103

connections and set to high impedance during module power down mode, when external reset is forced low, and during power-on sequence.

LISA-C200: Pay special attention when using voltage level shifter connections. V_INT (1.8 V) is provided to support biasing of level shifter ASICs. A problem can result with certain level shifter interface buffers, which can back feed voltage to the V_INT line preventing the modem from powering off and/or resetting properly. The back feed voltage typically comes from a host output through the level shifter and out either from the level shifter VCC pin connected to V_INT or to the modem DDC input lines though an internal protection diode with modem. With modem VCC = 0 V, a measured voltage can range from 0.3 to 1.0 V on the V_INT, preventing modem from ever resetting or powering up or down properly.

1.11 Audio Interface (LISA-C200) LISA-C200 module provides analog and digital audio interfaces:

• One differential analog audio input (microphone input)

• One differential analog audio output (speaker output)

• One 4-wire I2S digital audio interface: input and output Audio signal routing can be controlled by the dedicated AT command +USPM

For LISA-C200 refer to u-blox C2 series AT Commands Manual [3]).

This command allows setting the audio path mode, composed by the uplink audio path and the downlink audio path.

Each uplink path mode defines the physical input (i.e. the analog or the digital audio input) and the set of parameters to process the uplink audio signal (uplink gains, uplink digital filters, echo canceller parameters).

Each downlink path mode defines the physical output (i.e. the analog or the digital audio output) and the set of parameters to process the downlink audio signal (downlink gains, downlink digital filters and sidetone).

The set of parameters to process the uplink or the downlink audio signal can be changed with dedicated AT commands for each uplink or downlink path and then stored in the non-volatile memory. (Refer to relevant u-blox AT Commands Manual for Audio parameters tuning commands.)

Figure 21: The modem's internal audio paths

1.11.1 Analog Audio interface – LISA-C200

Detailed electrical characteristics of the differential analog audio input can be found in the LISA-C200 series Data Sheet [1].

Mic LNA Gain ADC Filters

Echo Canceler Block

Input Gain EC Output

Gain

AF Limit

NLPP Gain

NLPP Limit Filter DAC Filter

Mic

Speaker

CodecSTGain

CodecRxGain

CodecTxGain

TX AAGC

TX PCM Filter (UBF)

RX PCM Filter (UBF)

RX AAGC

Modem Module TX

Processin g and

Interface

RX Processin

g and Interface

Rx Volume

Tx Volume PCM Uplink

PCM Downlink



Page 40 of 103

1.11.1.1 Uplink path (differential analog audio input)

The pins related to the differential analog audio input are:

• MIC_P / MIC_N: Differential analog audio signal inputs (positive/negative). These two pins are provided with internal series 100 nF capacitors for DC blocking that connect the module pads to the differential input of a Low Noise Amplifier. The LNA output is internally connected to the digital processing system by an integrated sigma-delta analog-to-digital converter

The analog audio input is selected when the parameter <main_uplink> in AT+USPM command is set to “Analog microphone”: the uplink analog path profiles use the same physical input but have different sets of audio parameters (for more details, refer to u-blox C2 series AT Commands Manual [3], AT+USPM, AT+UMGC, AT+UUBF, AT+UHFP commands).

There is no microphone supply pin available on the module: an external low noise LDO voltage regulator should be added to provide a proper supply for a microphone.

1.11.1.2 Downlink path (differential analog audio output)

The pins related to the differential analog audio output are:

• SPK_N / SPK_P: Differential analog audio signal output (positive/negative). These two pins are internally directly connected to the differential output of a low power audio amplifier, for which the input is internally connected to the digital processing system by to an integrated digital-to-analog converter.

• The Analog audio output is selected when the parameter <main_downlink> in AT+USPM is set to Analog earpiece.

• The differential analog audio output can be directly connected to a headset earpiece or handset earpiece but is not able to drive an 8 Ω speaker.

Warning: excessive sound pressure from headphones can cause hearing loss.


MIC_P Differential analog audio input (Positive) Internal DC blocking capacitor

MIC_N Differential analog audio input (Negative) Internal DC blocking capacitor

SPK_P Differential analog audio output (Positive) No DC blocking capacitor required

SPK_N Differential analog audio output (Negative) No DC blocking capacitor required

Table 20: Signals relating to analog audio functions

The audio pins ESD rating is 1 kV (contact discharge). A higher protection level could be required if the lines are externally accessible on the application board. A higher protection level can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) on the lines connected to these pins.

All corresponding differential audio lines must be routed in pairs, be embedded in GND (have the ground lines as close as possible to the audio lines), and maintain distance from noisy lines such as VCC and from components such as switching regulators.

If the audio pins are not used, they can be left unconnected on the application board.

1.11.1.3 Hands-free profile

The hands-free profile is used by default.

Hands-free functionality is implemented using appropriate digital signal processing algorithms for voice-band handling (echo canceller and automatic gain control), managed via software (refer to u-blox C2 series AT commands manual [3], AT+UHFP command).

Figure 22 shows an example of an application circuit connecting a 2.2 kΩ electret microphone and an 8Ω speaker to the LISA-C200 module, with an external low noise LDO voltage regulator to provide a proper supply for the microphone and with an external audio amplifier to amplify the low power audio signal provided by the module differential output.



Page 41 of 103

Mount an 82 nH series inductor (e.g. Murata LQG15HS82NJ02) on each microphone line and a 27 pF

bypass capacitor (e.g. Murata GRM1555C1H270J) on all audio lines to minimize RF coupling noise.

The physical width of the audio outputs lines on the application board must be wide enough to minimize series resistance.

C1

C2

C3

L1

39MIC_N

53SPK_P

40MIC_P

54SPK_N

D1

Microphone Connector

D2

INOUT

GND

Low Noise LDO Regulator

U1

R4

R1

C6R3

C5

2V5

Sense lines connected to GND in one star point

C4

SPK

L2

MIC

Speaker Connector

OUT+IN+

GND

VMAIN

U2

OUT-IN-

C8C9

R5R6

VDD

C11C10

LISA-C200

Audio Amplifier

J1

J2

VMAIN

C7

Figure 22: Hands-free mode application circuit

Reference Description Part Number - Manufacturer C1, C2, C3, C4 27 pF Capacitor Ceramic COG 0402 5% 25 V GRM1555C1H270JZ01 - Murata

C5, C6, C7, C10 10 µF Capacitor Ceramic X5R 0603 20% 6.3 V GRM188R60J106ME47 - Murata

C8, C9 47 nF Capacitor Ceramic X7R 0402 10% 16V GRM155R71C473KA01 - Murata

C11 100 nF Capacitor Ceramic X5R 0402 10% 10V GRM155R71C104KA01 - Murata

D1, D2 Low Capacitance ESD Protection USB0002RP or USB0002DP - AVX

J1 Microphone Connector

J2 Speaker Connector

L1, L2 82nH Multilayer inductor 0402 (self resonance frequency ~1 GHz)

LQG15HS82NJ02 - Murata

MIC 2.2 kΩ Electret Microphone

R1, R3, R4 2.2 kΩ Resistor 0402 5% 0.1 W RC0402JR-072K2L - Yageo Phycomp



Page 42 of 103

R5, R6 0 Ω Resistor 0402 5% 0.1 W RC0402JR-070RL - Yageo Phycomp

SPK 8 Ω Loudspeaker

U1 Low Noise LDO Linear Regulator 2.5 V 300 mA LT1962EMS8-2.5#PBF- Linear Technology

U2 Filter-less Mono 2.8 W Class-D Audio Amplifier SSM2305CPZ - Analog Devices

Table 21: Part number references

1.11.1.4 Connection to an external analog audio device

The differential analog audio input / output can be used to connect the module to an external analog audio device. Audio devices with a differential analog input / output are preferable, as they are more immune to external disturbances.

If the external analog audio device is provided with a differential analog audio input, the SPK_P / SPK_N balanced output of the module must be connected to the differential input of the external audio device through a DC-block 10 µF series capacitor (e.g. Murata GRM188R60J106M) to decouple the bias present at the module output (see SPK_P / SPK_N common mode output voltage in the LISA-C200 series Data Sheet [1]). Use a suitable power-on sequence to avoid audio bump due to charging of the capacitor: the final audio stage should be always enabled as last one.

If the external analog audio device is provided with a single ended analog audio input, a proper differential to single ended circuit must be inserted from the SPK_P / SPK_N balanced output of the module to the single ended input of the external audio device. Depending on the differential to single ended circuit implementation, a 10 µF series capacitor (e.g. Murata GRM188R60J106M) may not be required to decouple the bias present at the module output.

The DC-block series capacitor acts as high-pass filter for audio signals, with cut-off frequency depending on both the values of capacitor and on the input impedance of the external audio device. For example: in case of differential input impedance of 600 , the two 10 µF capacitors will set the -3 dB cut-off frequency to 53 Hz, while for single ended connection to 600 external device, the cut-off frequency with just the single 10 µF capacitor will be 103 Hz. In both cases the high-pass filter has a low enough cut-off to not impact the audio signal frequency response.

The signal levels can be adapted by setting gain using AT commands, but additional circuitry must be inserted if the SPK_P / SPK_N output level of the module is too high for the input of the audio device.

If the external analog audio device is provided with a differential analog audio output, the MIC_P / MIC_N balanced input of the module must be connected directly to the differential output of the external audio device. Series capacitors are not needed since MIC_P / MIC_N pins are provided with internal 100 nF capacitors for DC blocking (see LISA-C200 series Data Sheet [1]).

If the external analog audio device is provided with a single ended analog audio output, a proper single ended to differential circuit has to be inserted from the single ended output of the external audio device to the MIC_P / MIC_N balanced input of the module. Depending on the single ended to differential circuit implementation, a 10 μF series capacitor (e.g. Murata GRM188R60J106M) may not be required to decouple the bias present at the external audio device output.

The signal levels can be adapted by setting gain using AT commands, but additional circuitry must be inserted if the output level of the audio device is too high for MIC_P / MIC_N. Refer to Figure 23 for the application circuits.

To enable the audio path corresponding to the differential analog audio input / output, refer to u-blox AT Commands Manual: AT+USPM command.

To tune audio levels for the external device, refer to u-blox AT Commands Manual: AT+USGC and AT+UMGC commands.



Page 43 of 103

LISA-C200

C1C254SPK_N

53SPK_P

GND

40MIC_P

GNDNegative Analog INPositive Analog IN

Negative Analog OUT

Positive Analog OUT

Audio Device

Reference

Reference

39MIC_N

LISA-C200

54SPK_N

53SPK_P

GND

40MIC_P

GND

Analog IN

Audio Device

Reference

Reference

39MIC_N

Analog OUT

C3C4 R2

R1

R4

R3

Figure 23: Application circuits to connect the module to audio devices with proper differential or single-ended input/output

Reference Description Part Number – Manufacturer

C1, C2, C3, C4 10 µF Capacitor X5R 0603 5% 6.3 V GRM188R60J106M – Murata

R1, R3 0 Ω Resistor 0402 5% 0.1 W RC0402JR-070RL – Yageo Phycomp

R2, R4 Not populated

Table 22: Connection to an analog audio device

1.11.2 Digital (PCM) Audio interface

The Digital Audio interface enables communication with an external codec to support hands-free applications; linear, µ-law, and A-law codecs are supported.

LISA-C200 modules support PCM data format over a bidirectional 4-wire I2S digital audio interface. The modules act as master only. The applicable pins are described in Table 23:


PCM_SYNC PCM word alignment Module output (master)

PCM_DOUT PCM transmit data Module output

PCM_CLK PCM clock Module output (master)

PCM_DIN PCM receive data Module input

Table 23: Audio Interface pins for LISA-C200



Page 44 of 103

The I2S interface pins ESD rating is 1 kV (contact discharge). A higher protection level could be required if the lines are externally accessible on the application board. A higher protection level can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) on the lines connected to these pins.

If the I2S digital audio pins are not used, they can be left unconnected on the application board.

The PCM interface can be used in two modes:

• Primary PCM running at 2.048 MHz. The primary PCM is disabled at power up or when RESIN_N is asserted.

• AUX PCM (master) running at 128 kHz To select the Primary PCM digital audio interface, the AT+USPM command parameters must assume these values (for more details, refer to u-blox AT Commands Manual [3]):

• <main_uplink>: “PCM_TX”

• <main_downlink>: “PCM_RX”

Parameters of digital path can be configured and saved as the normal analog paths, using appropriate path parameters, as described in the u-blox AT Commands Manual [3] +USGC, +UMGC, +USTN AT commands. Analog gain parameters of microphone and speakers are unused when digital path is selected.

PCM_TX and PCM_RX are parallel to the analog front end, so resources available for analog path can be shared:

• Digital filters and digital gains are available in both uplink and downlink direction. Configure using AT commands

Refer to the u-blox AT Commands Manual [3]: AT+UI2S command for possible combinations of connection and settings.

1.11.2.1 Primary PCM mode

Main features of the Primary PCM interface:

Module functions as I2S master (PCM_CLK and PCM_SYNC signals generated by the module)

PCM_SYNC signal always runs at 8 kHz

PCM_SYNC toggles high for 1 or 2 CLK cycles of synchronization (configurable), then toggles low for 16 CLK cycles of sample width. Frame length can be 1 + 16 = 17 bits or 2 + 16 = 18 bits

PCM_CLK frequency is fixed at 2.048 MHz

PCM_DOUT, PCM_DIN data are 16 bit words with 8 kHz sampling rate, mono. Data is in 2’s complement notation. MSB is transmitted first

When PCM_SYNC toggles high, the first synchronization bit is always low. Second synchronization bit (present only in case of 2 bit long PCM_SYNC configuration) is MSB of the transmitted word (MSB is transmitted twice in this case)

PCM_DOUT changes on PCM_CLK rising edge, PCM_DIN changes on PCM_CLK falling edge

1.11.2.2 AUX PCM mode

The auxiliary codec port operates with standard long-sync timing and a 128 kHz clock. The PCM_SYNC runs at 8 kHz with a 50% duty cycle. Most µ-law and A-law codecs support the 128 kHz AUX_PCM_CLK bit clock.

Module functions as I2S master (PCM_CLK and PCM_SYNC signals generated by the module)

PCM_SYNC signal always runs at 8 kHz

PCM_SYNC toggles high for 1 or 2 CLK cycles of synchronization (configurable), then toggles low for 16 CLK cycles of sample width. Frame length can be 1 + 16 = 17 bits or 2 + 16 = 18 bits



Page 45 of 103

PCM_CLK frequency is fixed 128 KHz

PCM_DOUT, PCM_DIN data are 16 bit words with 8 kHz sampling rate, mono. Data is in 2’s complement notation. MSB is transmitted first

When PCM_SYNC toggles high, the first synchronization bit is always low. Second synchronization bit (present only in case of 2 bit long PCM_SYNC configuration) is MSB of the transmitted word (MSB is transmitted twice in this case)

PCM_DOUT changes on PCM_CLK rising edge, PCM_DIN changes on PCM_CLK falling edge


Any external signal connected to the PCM interfaces must be tri-stated when the module is in power-down mode, when the external reset is forced low and during the module power-on sequence (at least for 3 s after the start-up event), to avoid latch-up of circuits and allow a proper boot of the module. If the external signals connected to the wireless module cannot be tri-stated, insert a multi channel digital switch (e.g. Texas Instruments SN74CB3Q16244, TS5A3159, or TS5A63157) between the two-circuit connections and set to high impedance during module power down mode, when external reset is forced low and during power-on sequence.

LISA-C200: Pay special attention when using voltage level shifter connections. V_INT (1.8 V) is provided to support biasing of level shifter ASICs. A problem can result with certain level shifter interface buffers, which can back feed voltage to the V_INT line preventing the modem from powering off and/or resetting properly. The back feed voltage typically comes from a host output through the level shifter and out either from the level shifter VCC pin connected to V_INT or to the modem PCM input lines though an internal protection diode with modem. With modem VCC = 0 V, a measured voltage can range from 0.3 to 1.0 V on the V_INT, preventing modem from ever resetting or powering up or down properly.

1.12 General Purpose Input / Output (GPIO)

Network status through GPIO, is supported only by LISA-C200 from version 04S / 24S onwards.

LISA-C series modules provide 5 pins (GPIO1-GPIO5) which can be configured as general purpose input or output, or can be configured to provide special functions via u-blox AT commands. (For further details, refer to u-blox C2 series AT Commands Manual [3], +UGPIOC, +UGPIOR, +UGPIOW, +UGPS, +UGPRF).

The following functions are available in the LISA-C modules:

• Network status indication:

The GPIO1, GPIO2, GPIO3, GPIO4 or GPIO5 can be configured to indicate network status (i.e. no service, registered home network, registered visitor network, voice or data call session), by means of the AT+UGPIOC command.

No GPIO pin is by default configured to provide the “Network status indication” function.

The “Network status indication” mode can be configured to only one pin at a time; it is not possible to simultaneously set the same mode on another pin.

See section 3.9, for further details.



Page 46 of 103

• GPS supply enable:

The GPIO2 is configured by the AT+UGPIOC command to enable or disable the supply of the u-blox GNSS receiver connected to the cellular module.

GPIO2 provides the “GPS supply enable” function as:

• Output / High, to switch on the u-blox GNSS receiver, if the parameter <mode> of AT+UGPS command is set to 1

• Output / Low, to switch off the u-blox GNSS receiver, if the parameter <mode> of AT+UGPS command is set to 0 (default setting)

GPIO2 must be connected to the active-high enable pin (or the active-low shutdown pin) of the voltage regulator that supplies the u-blox GNSS receiver on the application board.

• GPS data ready:

Only the GPIO3 pin provides the “GPS data ready” function, to sense when a u-blox GNSS receiver connected to the cellular module is ready to send data via the DDC (I2C) interface, setting the parameter <gpio_mode> of the AT+UGPIOC command to 4.

GPIO3 provides the “GPS data ready” function will be set as:

• Input, to sense the line status, waking up the cellular module from idle-mode when the u-blox GNSS receiver is ready to send data via the DDC (I2C) interface; this is possible if the parameter <mode> of AT+UGPS command is set to 1 and the parameter <GPS_IO_configuration> of AT+UGPRF command is set to 16

• Tri-state with an internal active pull-down enabled, otherwise (default setting)

GPIO3 must be connected to the data ready output of the u-blox GNSS receiver (i.e. the pin TxD1 of the u-blox GNSS receiver) on the application board.

• SIM card detection:

The modem firmware automatically detects the SIM card presence. This is determined at the time the modem powers on.

• General purpose input:

All the GPIOs can be configured as input to sense high or low digital level through the AT+UGPIOR command, setting the parameter <gpio_mode> of the AT+UGPIOC command to 1.

The “General purpose input” mode can be provided on more than one pin at a time: it is possible to simultaneously set the same mode on another pin (also on all the GPIOs).

No GPIO pin is by default configured as “General purpose input”.

The pin configured to provide the “General purpose input” function is set as

• Input, to sense high or low digital level by the AT+UGPIOR command.

The pin can be connected on the application board to an output pin of an application processor to sense the digital signal level.



Page 47 of 103

• General purpose output:

All the GPIOs can be configured as output to set the high or the low digital level through the AT+UGPIOW command, setting the parameter <gpio_mode> of the AT+UGPIOC command to 0.

The “General purpose output” mode can be provided on more than one pin per time: it is possible to simultaneously set the same mode on another pin (also on all the GPIOs).

No GPIO pin is by default configured as “General purpose output”.

The pin configured to provide the “General purpose output” function is set as:

• Output / Low, if the parameter <gpio_out_val> of the AT+UGPIOW command is set to 0

• Output / High, if the parameter <gpio_out_val> of the AT+UGPIOW command is set to 1

The pin can be connected on the application board to an input pin of an application processor to provide a digital signal.

• Pad disabled:

All the GPIOs can be configured in tri-state with an internal active pull-down enabled, as a not used pin, setting the parameter <gpio_mode> of the AT+UGPIOC command to 255.

The “Pad disabled” mode can be provided on more than one pin per time: it is possible to simultaneously set the same mode on another pin (also on all the GPIOs).

The pin configured to provide the “Pad disabled” function is set as

• Tri-state with an internal active pull-down enabled

Table 24 describes the configurations of all the GPIO pins of LISA-C modules.

Pin Module Name Description Remarks

20 LISA-C

GPIO1 GPIO By default, the pin is configured as Pad disabled. Can be alternatively configured by the AT+UGPIOC command as • Output • Input • Network Status indication

21

LISA-C GPIO2 GPIO By default, the pin is configured to provide GPS Supply Enable function. Can be alternatively configured by the +UGPIOC command as • Output • Input • Pad disabled • Network Status indication

23 LISA-C GPIO3 GPIO By default, the pin is configured to provide GPS Data Ready function. Can be alternatively configured by the +UGPIOC command as • Output • Input • Pad disabled • Network Status indication

24 LISA-C

GPIO4 GPIO By default, the pin is configured as Pad disabled. Can be alternatively configured by the +UGPIOC command as • Output • Input • Network Status indication

51 LISA-C

GPIO5 GPIO By default, the pin is configured as Pad disabled. Can be alternatively configured by the +UGPIOC command as • Output • Input • Network Status indication

Table 24: GPIO pins



Page 48 of 103

The GPIO pins ESD sensitivity rating is 1 kV (Human Body Model according to JESD22-A114F). Higher protection level could be required if the lines are externally accessible on the application board. Higher protection level can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array) on the lines connected to these pins, close to accessible points.

An application circuit for a typical GPIOs usage is described in Figure 24:

• GPS supply enable function provided by the GPIO2 pin

• GPS data ready function provided by the GPIO3 pin

Use transistors with at least an integrated resistor in the base pin or otherwise put a 10 kΩ resistor on the board in series to the GPIO.

If the GPIO pins are not used, they can be left unconnected on the application board.

Any external signal connected to GPIOs must be tri-stated when the module is in power-down mode, when the external reset is forced low and during the module power-on sequence (at least for 3 s after the start-up event), to avoid latch-up of circuits and allow a proper boot of the module. If the external signals connected to the module cannot be tri-stated, insert a multi channel digital switch (e.g. Texas Instruments SN74CB3Q16244, TS5A3159, or TS5A63157) between the two-circuit connections and set to high impedance during module power down mode, when external reset is forced low and during power-on sequence.

LISA-C200: Pay special attention when using voltage level shifter connections. V_INT (1.8 V) is provided to support biasing of level shifter ASICs. A problem can result with certain level shifter interface buffers, which can back feed voltage to the V_INT line preventing the modem from powering off and/or resetting properly. The back feed voltage typically comes from a host output through the level shifter and out either from the level shifter VCC pin connected to V_INT or to the modem GPIO input lines though an internal protection diode with modem. With modem VCC = 0 V, a measured voltage can range from 0.3 to 1.0 V on the V_INT, preventing modem from ever resetting or powering up or down properly.



Page 49 of 103

4V_INT51GPIO5

OUTIN

GND

LDO Regulator

SHDN

3V8 1V8

GPIO3

GPIO4

TxD1

EXTINT0

23

24

R1

VCC

GPIO2 21

LISA-C series u-blox GPS / GNSS1.8 V receiver

U1

C1

GPS Supply Enable

GPS Data Ready

GPS RTC Sharing

R2

Figure 24: GPIO application circuit


R1 47 kΩ Resistor 0402 5% 0.1 W Various manufacturers

U1 Voltage Regulator for GNSS Receiver See GNSS Module Hardware Integration Manual

R2 4.7 kΩ Resistor 0402 5% 0.1 W Various manufacturers



R7 820 Ω Resistor 0402 5% 0.1 W Various manufacturers

DL1 LED Red SMT 0603 LTST-C190KRKT - Lite-on Technology Corporation

T1 NPN BJT Transistor BC847 - Infineon

Table 25: Components for GPIO application circuit

1.13 Reserved pins (RSVD) The LISA-C200 module has pins reserved for future use. Refer to the LISA-C Data Sheet [1] for the list of LISA-C200 reserved pins and connectivity guidelines.



Page 50 of 103

1.14 Schematic for LISA-C200 module integration Figure 25 shows the integration of a LISA-C200 module into an application schematic.

47pF

SIM Card HolderCCVCC

(C1)

CCIO (C7)

CCCLK (C3)

CCRST (C2)

GND (C5)

47pF 47pF 100nF

VSIM

SIM_IO

SIM_CLK

SIM_RST

47pF

V_INT

GPIO5

ESD ESD ESD ESD

TXD

RXD

RTS

CTS

RI

GND

TXD

RXDRTS

CTS

RI

GND

3V6

22µF 100nF

LISA-C200

VCC

VCC

VCC

+

VBUS

D+

D-

GND

VUSB_DETUSB_D+

USB_D-

GND100nF

GND

ANTAntenna ConnectionLISA-C200 SMT PAD

DTE LISA – 1.8V

USB 2.0 Host

GPIO1

3V8

RESET_NFerrite Bead

47pF


Open Drain

Output

PWR_ON

Open Drain

Output

0Ω

0Ω

TP

TP

0Ω

0Ω

TP

TP

DTR

DSR

DTR

DSR

GPIO3

GPIO4

GPIO2

SCL

SDA

TP

TP

TP

PCM DO

PCM CLK

PCM SYNC

PCM DI

SPK_N

GND

SPK_P

MIC_N

GND

MIC_P

C1

C2

Negative Analog OUT

Positive Analog OUT

Audio Device

Reference

Negative Analog IN

Positive Analog IN

Reference

Figure 25: Example: integrating LISA-C200 module in an application schematic

UART FW75-C200 and LISA-C200 pins use different voltage levels (1.8V LISA-C200, 2.8V FW75-C200)



Page 51 of 103

1.15 Schematic for FW75-C200 modules integration Figure 26 shows the integration of a FW75-C200 module into an application schematic.

TXD

RXD

RTS

CTS

RI

GND

TXD

RXDRTS

CTS

RI

GND

3V6

22µF VCC100nF

FW75-C200

VCCVCC

VCC

+

VCC

VBUS

D+

D-

GND

VUSB_DETUSB_D+

USB_D-

GND100nF

GND

ANT MainAntenna Connection

FW75-C200 – U.FL Connector

DTE FW75 - 2.8V

USB 2.0 Host

Status

3V8

StatusIndicator

HW_SHUTDOWNFerrite Bead

47pF


Open Drain

Output

PWR_ON

Open Drain

Output

0Ω

0Ω

TP

TP

0Ω

0Ω

TP

TP

DTR

DSR

DTR

DSR

47pF

SIM Card Holder

47pF 47pF 100nF

VSIM

SIM_IO

SIM_CLK

SIM_RST

47pFESD ESD ESD ESD

GPIO3

GPIO4

GPIO2

GPIO5

V_INT

TP

TP

TP

Figure 26: Example: integrating FW75-C200 module in an application schematic

Note different voltage levels for UART pins: FW75-C200 use 2.8 V and LISA-C200 uses 1.8 V.



Page 52 of 103

1.16 Approvals LISA-C200 and FW75-C200 modules have been or will be approved under the following schemes:

• CDG1 CDMA Development Group 1 Radio Conformance Testing

• CDG2 CDMA Development Group 2 Inter-operability

• Sprint Carrier Certification

• Verizon Carrier Certification

• Aeris Carrier Certification

• US Cellular Carrier Certification

• FCC (Federal Communications Commission)

• IC (Industry Canada)

1.16.1 LISA-C200 and FW75-C200 US certifications

1.16.1.1 Declaration of Conformity for products marked with the FCC logo - United States only

Radiofrequency radiation exposure Information: this equipment complies with FCC radiation exposure limits prescribed for an uncontrolled environment. This equipment should be installed and operated with a minimum distance of 20 cm between the radiator and your body.

1.16.1.2 Modifications

The FCC requires the user to be notified that any changes or modifications made to this device that are not expressly approved by u-blox could void the user's authority to operate the equipment.

Manufacturers of mobile or fixed devices incorporating the LISA-C200 and FW75-C200 modules are authorized to use the FCC Grants and Industry Canada Certificates of the LISA-C200 and FW75-C200 modules for their own final products according to the conditions referenced in the certificates.

The FCC Label shall in the above case be visible from the outside, or the host device shall bear a second label stating:

• for FW75-C200: “Contains FCC Id XU9-FW75”

• for LISA-C200 and onwards: “Contains FCC Id R5Q-LISAC200A ”

The IC Label shall in the above case be visible from the outside, or the host device shall bear a second label stating

• for FW75-C200: “Contains IC 8694A-FW75”

• for LISA-C200: “Contains IC 8595B-LISAC200A”

Canada, Industry Canada (IC) Notices

Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment.

Canada, avis d'Industrie Canada (IC)

Les changements ou modifications n'ont pas était expressément approuvés par la partie responsable de la conformité, ils pourraient annulée l'autorité de l'utilisateur pour exploiter l'équipement.


UBX-13000620 - R21 Early Production Information Design-In

Page 53 of 103

2 Design-In

2.1 Design-in checklist

2.1.1 Schematic checklist

The following are the most important points for a simple schematic check:

DC supply must provide a nominal voltage at VCC pin above the minimum operating range limit.

DC supply must be capable of supporting 1.2 A, providing a voltage at VCC pin above the minimum operating range limit and with a maximum 250 mV voltage drop from the nominal value.

VCC supply should be clean, with very low ripple/noise: suggested passive filtering parts can be inserted.

Sudden momentary power loss to host application is properly handled to either provide the C200 module with adequate supply during loss or to turn off/remove supply 2 seconds or longer to permit the module properly reach the powered-off state.

Connect only one DC supply to VCC: different DC supply systems are mutually exclusive.

Don’t apply loads which might exceed the limit for maximum available current from V_INT supply.

Check that voltage level of any connected pin does not exceed the relative operating range.

Check that there is no back-feeding voltage provided to any UART and/or I2C lines

Check that there is no voltage input coming through the V_INT Line

Check that the Power-on sequence works as the option selected, and no voltage is back-fed prior to C200 modules initialization

Capacitance and series resistance must be limited on each SIM signal to match the SIM specifications.

Insert the suggested low capacitance ESD protection and passive filtering parts on each SIM signal.

Check UART signals direction, since the signal names follow the ITU-T V.24 Recommendation [5].

Provide appropriate access to USB interface and/or to UART RxD, TxD lines and access to PWR_ON and/or HW_SHUTDOWN lines on the application board in order to flash/upgrade the module firmware.

Provide appropriate access to USB interface and/or to UART RxD, TxD, CTS, RTS lines for debugging.

Add a proper pull-up resistor to a proper supply on each DDC (I2C) interface line, if the interface is used.

Capacitance and series resistance must be limited on each line of the DDC interface.

Use transistors with at least an integrated resistor in the base pin or otherwise put a 10 kΩ resistor on the board in series to the GPIO when those are used to drive LEDs.

Insert the suggested passive filtering parts on each used analog audio line.

Provide proper precautions for ESD immunity as required on the application board.

All unused pins can be left floating on the application board Layout checklist

2.1.2 Layout checklist

The following are the most important points for a simple layout check:

Check 50 Ω nominal characteristic impedance of the RF transmission line connected to ANT coax connector or Printed Circuit Board 50 transmission line impedance for LISA-C200

Follow the recommendations of the antenna producer for correct antenna installation and deployment.

Ensure no coupling occurs with other noisy or sensitive signals (primarily SIM signals).

VCC line should be wide and short.

Ensure proper grounding.

Consider “No-routing” areas for the Data Module footprint.

Optimize placement for minimum length of RF line and closer path from DC source for VCC.



Page 54 of 103

Design USB_D+ / USB_D- connection as 90 Ω differential pair.

2.1.3 Antenna checklist

Antenna should have 50 Ω impedance, V.S.W.R less then 3:1, recommended 2:1 on operating bands in deployment geographical area.

Follow the recommendations of the antenna producer for correct antenna installation and deployment (PCB layout and matching circuitry).

2.2 Connectors (FW75) The following design information is to aid the design for proper selection of mating connectors and antennas.

2.2.1 FW75-C200 modem connector

Manufacturer Series Name

Part No. Specification Description Remarks

Molex SlimStack 52991-0808

PS-54-167-002 Receptacle 80 pins, 0.50mm pitch, 4mm stacking height

Website : www.molex.com

• Drawing: 529910708_sd.pdf (mechanical, land pattern and reel specifications)

• Data sheet : 05339160208_PCB_RECEPTABLES.pdf

Table 26: FW75-C200 modem connector

Figure 27: FW75-C200 modem connector

2.2.2 FW75-C200 Board to Board host connector



Molex SlimStack 53916-0808

PS-54-167-002 Header 80 pins, 0.50mm pitch, 4mm stacking height



• Data sheet : 05339160208_PCB_HEADERS.pdf

Table 27: FW75-C200 host mate connector

http://www.molex.com/

http://www.molex.com/



Page 55 of 103

Figure 28: FW75-C200 host mate connector

2.2.3 FW75-C200 RF antenna connector



Molex 73412 73412-0110

PS-73598-02 Microcoaxial RF, 50 Ω, PCB Vertical Jack Receptacle, SMT, 1.25 mm (0.049”) Mounted Height



• Data sheet: 0734120110_RF_COAX_CONNECTORS.pdf

Table 28: FW75-C200 antenna connector

Figure 29: FW75-C200 antenna connector

2.3 Design Guidelines The following design guidelines must be met for optimal integration of LISA-C200 module on the final application board.

2.3.1 Layout guidelines per pin function

Table 29 groups the u-blox C2 series module pins by signal function and provides a ranking of importance in layout design. See the LISA-C2 series Data Sheet [1] or FW75-C200 Data Sheet [2] for the complete pin lists.



Page 56 of 103

Rank Function Pin(s) Layout Remarks

1st RF Connector Very Important Design for 50 Ω characteristic impedance.

2nd Main DC Supply

Very Important VCC line should be wide and short. Route away from sensitive analog signals.

3rd USB Signals

Very Important Route USB_D+ and USB_D- as differential lines: design for 90 Ω differential impedance.

4th Analog Audio Careful Layout Avoid coupling with noisy signals.

Audio Inputs MIC_P, MIC_N

Audio Outputs SPK_P, SPK_N

5th Ground GND Careful Layout Provide proper grounding.

6th Sensitive Pin : Careful Layout Avoid coupling with noisy signals.

Power-on PWR_ON

HW_SHUTDOWN HW_SHUTDOWN

RESET_N RESET_N

7th Digital pins and supplies: Common Practice Follow common practice rules for digital pin routing. SIM Card Interface VSIM, SIM_CLK,

SIM_IO, SIM_RST

UART TXD, RXD, CTS, RTS, RI

General Purpose I/O1 GPIO1, GPIO2, GPIO3, GPIO4, GPIO5

USB detection VUSB_DET

I2C1 SDA,SCL

PCM Audio1 PCM_SYNC, PCM_DO, PCM_CLK, PCM_DI

Supply for Interfaces V_INT

Table 29: Pin list in order of decreasing importance for layout design

1 LISA-C200



Page 57 of 103

2.3.2 Footprint and paste mask (LISA-C200 only)

The following figure describes the footprint and provides recommendations for the paste mask for LISA-C200 modules. These are recommendations only and not specifications. Note that the copper and solder masks have the same size and position.

33.2

mm

[13

07.1

mil]

22.4 mm [881.9 mil]

2.3

mm

[9

0.6

mil]

0.8

mm

[3

1.5

mil]

1.1

mm

[4

3.3

mil]

0.8

mm

[3

1.5

mil]

1.0 mm [39.3 mil]

5.7 mm [224.4 mil]

33.2

mm

[13

07.1

mil]

22.4 mm [881.9 mil]

2.3

mm

[9

0.6

mil]

1.2

mm

[4

7.2

mil]

1.1

mm

[4

3.3

mil]

0.8

mm

[3

1.5

mil]

0.9 mm [35.4 mil]

5.7 mm [224.4 mil]

0.6

mm

[2

3.6

mil]

Stencil: 150 µm

Figure 30: LISA-C200 modules suggested footprint and paste mask

To improve the wetting of the half vias, reduce the amount of solder paste under the module and increase the volume outside of the module by defining the dimensions of the paste mask to form a T-shape (or equivalent) extending beyond the copper mask. The solder paste should have a total thickness of 150 µm.

The paste mask outline needs to be considered when defining the minimal distance to the next component.

The exact geometry, distances, stencil thicknesses and solder paste volumes must be adapted to the specific production processes (e.g. soldering etc.) of the customer.

The bottom layer of LISA-C200 series modules has one unprotected copper area for GND, shown in Figure 31.

Consider “No-routing” areas for the LISA-C200 modules footprint as follows: signal keep-out area on the top layer of the application board, below LISA-C200 modules, due to GND opening on module bottom layer (see Figure 31).



Page 58 of 103

33

.2 m

m

11.85 mm

22.4 mm

5.3 mm 5.25 mm

1.4 mm1.0 mmPIN 1

LISA-C2 bottom side (through module view)

Exposed GND on LISA-C2 module bottom layer

Signals keep-out area on application board

Figure 31: Signals keep-out area on the top layer of the application board, below LISA-C200 modules



Page 59 of 103

2.4 Antenna guidelines Antenna characteristics are essential for good functionality of the module. Antenna radiating performance has direct impact on the reliability of connections over the Air Interface. A bad termination of ANT can result in poor performance of the module.

The following parameters should be checked:

Item Recommendations

Impedance 50 Ω nominal characteristic impedance

Frequency Range Depends on the Mobile Network used. LISA-C200 & FW75-C200: - Cell Band BC0: 824..894 MHz - PCS Band BC1:1850..1990 MHz

Input Power >2 W peak

V.S.W.R <2:1 recommended, <3:1 acceptable

Return Loss S11<-10 dB recommended, S11<-6 dB acceptable

Gain <3 dBi

Table 30: General recommendation for CDMA antenna

To preserve the original u-blox FCC ID, antenna gain shall remain below 3 dBi.

CDMA antennas are typically available as:

• Linear monopole: typical for fixed applications. The antenna extends mostly as a linear element with a dimension comparable to lambda/4 of the lowest frequency of the operating band. Magnetic base may be available. Cable or direct RF connectors are common options. The integration normally requires the fulfillment of some minimum guidelines suggested by antenna manufacturer.

• Patch-like antenna: better suited for integration in compact designs (e.g. mobile phone). These are mostly custom designs where the exact definition of the PCB and product mechanical design is fundamental for tuning of antenna characteristics.

For integration observe these recommendations:

• Ensure 50 Ω antenna termination by minimizing the V.S.W.R. or return loss, as this will optimize the electrical performance of the module. See section 2.4.1.

• Select antenna with best radiating performance. See section 2.4.2.

• If a cable is used to connect the antenna radiating element to application board, select a short cable with minimum insertion loss. The higher the additional insertion loss due to low quality or long cable, the lower the connectivity.

• Follow the recommendations of the antenna manufacturer for correct installation and deployment.

• Do not include antenna within closed metal case.

• Do not place antenna in close vicinity to end user since the emitted radiation in human tissue is limited by S.A.R. regulatory requirements.

• Do not use directivity antenna since the electromagnetic field radiation intensity is limited in some countries.

• Take care of interaction between co-located RF systems since the RF transmitted power may interact or disturb the performance of companion systems.

• Place antenna far from sensitive analog systems or employ countermeasures to reduce electromagnetic compatibility issues that may arise.



Page 60 of 103

2.4.1 Antenna termination

The LISA-C200 and FW75-C200 modules are designed to work on a 50 Ω load. However, real antennas do not have a perfect 50 Ω load on all the supported frequency bands. Therefore, to reduce as much as possible performance degradation due to antenna mismatch, the following requirements should be met:

Measure the antenna termination with a network analyzer. Connect the antenna through a coaxial cable to the measurement device. |S11| indicates which portion of the power is delivered to antenna and which portion is reflected by the antenna back to the module output.

A good antenna should have an |S11| below -10 dB over the entire frequency band. Due to miniaturization, mechanical constraints and other design issues, this value will not be achieved. An |S11| value of about -6 dB – (in the worst case) - is acceptable.

Figure 32 shows an example of this measurement:

Figure 32: |S11| sample measurement of a penta-band antenna that covers in a small form factor the 4 bands (850 MHz, 900 MHz, 1800 MHz and 1900 MHz)

Figure 33 shows comparable measurements performed on a wideband antenna. The termination is better, but the size of the antenna is considerably larger.

Figure 33: |S11| sample measurement of a wideband antenna



Page 61 of 103

2.4.2 Antenna radiation

An indication of the antenna’s radiated power can be approximated by measuring the |S21| from a target antenna to the measurement antenna, using a network analyzer with a wideband antenna. Measurements should be done at a fixed distance and orientation, and results compared to measurements performed on a known good antenna. Figure 34 through Figure 35 show measurement results. A wideband log periodic-like antenna was used, and the comparison was done with a half lambda dipole tuned at 900 MHz frequency. The measurements show both the |S11| and |S21| for the penta-band internal antenna and for the wideband antenna.

Figure 34: |S11| and |S21| comparison between a 900 MHz tuned half wavelength dipole (green/purple) and a penta-band internal antenna (yellow/cyan)

The half lambda dipole tuned at 900 MHz is known and has good radiation performance (both for gain and directivity). Then, by comparing the |S21| measurement with antenna under investigation for the frequency where the half dipole is tuned (e.g. marker 3 in Figure 34) it is possible to make a judgment on the antenna under test: if the performance is similar then the target antenna is good.

Figure 35: |S11| and |S21| comparison between a 900 MHz tuned half wavelength dipole (green/purple) and a wideband commercial antenna (yellow/cyan)

Instead if |S21| values for the tuned dipole are much better than the antenna under evaluation (like for marker 1/2 area of Figure 35, where dipole is 5 dB better), then it can be argued that the radiation of the target antenna (the wideband dipole in this case) is considerably less.

The same procedure should be repeated on other bands with half wavelength dipole re-tuned to the band under investigation.



Page 62 of 103

For good antenna radiation performance, antenna dimensions should be comparable to a quarter of the wavelength. Different antenna types can be used for the module, many of them (e.g. patch antennas, monopole) are based on a resonating element that works in combination with a ground plane. The ground plane, ideally infinite, can be reduced down to a minimum size that must be similar to one quarter of the wavelength of the minimum frequency that has to be radiated (transmitted/received). Numerical sample: frequency = 1 GHz wavelength = 30 cm minimum ground plane (or antenna size) = 7.5 cm. Below this size, the antenna efficiency is reduced.

2.4.3 Antenna detection functionality

The internal antenna detect circuit is based on ADC measurement at ANT: the RF port is DC-coupled to the ADC unit in the baseband chip, which injects a DC current on ANT and measures the resulting DC voltage to evaluate the resistance from ANT pad to GND.

The antenna detection is forced by the +UANTR AT command: refer to the u-blox LISA-C200 AT Commands Manual [3] for more details on how to access this feature.

To achieve antenna detection functionality, use an RF antenna with built-in resistor from ANT signal to GND, or implement an equivalent solution with a circuit between the antenna cable connection and the radiating element, as shown in Figure 36.

Application Board Antenna Assembly

Diagnostic Circuit

LISA-C series

ADC

Current Source

RF Choke

DC Blocking

Front-End RF Module

RF Choke

DC Blocking

Radiating Element

Zo=50 Ω

Resistor for Diagnostic

Coaxial Antenna Cable

ANT

Figure 36: Antenna detection circuit and antenna with diagnostic resistor

Examples of components for the antenna detection diagnostic circuit are reported in Table 31:

Description Part Number - Manufacturer

DC Blocking Capacitor Murata GRM1555C1H220JA01 or equivalent

RF Choke Inductor Murata LQG15HS68NJ02, LQG15HH68NJ02 or equivalent (Self Resonance Frequency ~1GHz)

Resistor for Diagnostic 15 kΩ 5%, various Manufacturers

Table 31: Example of components for the antenna detection diagnostic circuit



Page 63 of 103

The DC impedance at the RF port for some antennas may be a DC open (e.g. linear monopole) or a DC short to reference GND (e.g. PIFA antenna). For antennas without the diagnostic circuit (shown in Figure 36), the measured DC resistance will always be at the limits of the measurement range (respectively open or short), and there will be no means to distinguish between a defect on antenna path with similar characteristics (respectively: removal of linear antenna or RF cable shorted to GND for PIFA antenna).

Furthermore, any other DC signal injected to the RF connection from ANT connector to radiating element will alter the measurement and produce invalid results for antenna detection.

It is recommended to use an antenna with a built-in diagnostic resistor in the range of 10 kΩ to 20 kΩ to assure good antenna detection functionality and to avoid a reduction of module RF performance. The choke inductor should exhibit a parallel Self Resonance Frequency (SRF) of about 1 GHz to improve the RF isolation of load resistor.

For example:

Consider a CDMA antenna with built-in DC load resistor of 15 kΩ. Using the +UANTR AT command, the module reports the resistance value evaluated from ANT connector to GND:

• Reported values close to the used diagnostic resistor nominal value (i.e. values from 13 kΩ to 17 kΩ if a 15 kΩ diagnostic resistor is used) indicate that the antenna is properly connected

• Values close to the measurement range maximum limit (approximately 37 kΩ) or an open-circuit “over range” report (see u-blox LISA-C200 AT Commands Manual [3]) means that that the antenna is not connected or the RF cable is broken

• Reported values below the measurement range minimum limit (1 kΩ) will highlight a short to GND at antenna or along the RF cable

• Measurement inside the valid measurement range and outside the expected range may indicate an improper connection, damaged antenna or wrong value of antenna load resistor for diagnostic

• Reported values could differ from the real resistance value of the diagnostic resistor mounted inside the antenna assembly due to antenna cable length, antenna cable capacity and the used measurement method

2.5 ESD immunity test precautions The immunity of the device (i.e. the application board where the LISA-C200 or FW75-C200 module is mounted) Electrostatic Discharge must be certified in compliance to the testing requirements standard [13], and the requirements for radio and digital cellular radio telecommunications system equipment standards [14] and [15].

The ESD test is performed at the enclosure port referred to as the physical boundary through which the EM field radiates. If the device implements an integral antenna, the enclosure port is seen as all insulating and conductive surfaces housing the device. If the device implements a removable antenna, the antenna port can be separated from the enclosure port. The antenna port comprises the antenna element and its interconnecting cable surfaces.

The applicability of the ESD test depends on the device classification, as well the test on other ports or on interconnecting cables to auxiliary equipments depends to the device accessible interfaces and manufacturer requirements.

Contact discharges are performed at conductive surfaces whereas air discharges are performed on insulating surfaces. Indirect contact discharges are performed on the measurement setup horizontal and vertical coupling planes.

Implement the following precautions to satisfy ESD immunity test requirements performed at the device enclosure in compliance to the category level and shown in the following table.



Page 64 of 103

Application Category Immunity Level

All exposed surfaces of the radio equipment and ancillary equipment in a representative configuration

Contact Discharge 4 kV

Air Discharge 8 kV

Table 32: Electromagnetic Compatibility (EMC) ESD immunity requirement, standards “EN 61000-4-2, EN 301 489-1 V1.8.1, EN 301 489-7 V1.3.1”

Although EMC certification (including ESD immunity testing) must be performed in the final application of the radio equipment EUT, results are provided for LISA modules performing the test with a representative configuration to show that requirements can be met.

Since an external antenna is used, the antenna port can be separated from the enclosure port. The reference application is not enclosed in a box so the enclosure port is not identified with physical surfaces. Therefore, some test cases cannot be applied. Only the antenna port is identified as accessible for direct ESD exposure.

The reference application implements all precautions described in the sections below. ESD immunity test results and applicability are reported in Table 33 according to test requirements [13], [14] and [15].

Category Application Immunity Level

Contact Discharge to coupling planes (indirect contact discharge)

Enclosure +2 kV / -2 kV

+4 kV / -4 kV

Contact Discharges to conducted surfaces (direct contact discharge)

Enclosure port Not Applicable5

Contact Discharges to conducted surfaces (direct contact discharge)

Antenna port (only antenna with completely insulating surface can be used)

Not Applicable6

Air Discharge at insulating surfaces Enclosure port Not Applicable7

Air Discharge at insulating surfaces Antenna port (only antenna with completely insulating surface can be used)

+2 kV / -2 kV

+4 kV / -4 kV

+8 kV / -8 kV

Table 33: Enclosure ESD immunity level result, standards “EN 61000-4-2, EN 301 489-1 V1.8.1, EN 301 489-7 V1.3.1” for LISA application reference design.

5 LISA mounted on application design:

Not Applicability -> EUT with insulating enclosure surface, EUT without enclosure surface

Applicability -> EUT with conductive enclosure surface 6 LISA mounted on application design:

Not Applicability -> Antenna with insulating surface

Applicability -> Antenna with conductive surface 7 LISA mounted on application design:

Applicability -> EUT with insulating enclosure surface

Not Applicability -> EUT with conductive enclosure surface, EUT without enclosure surface



Page 65 of 103

2.5.1 General precautions

The following module interfaces can have a critical influence in ESD immunity testing, depending on the application board handling. The following precautions are suggested:

HW_SHUTDOWN pin (FW75-C200 only)

Sensitive interface is the hardware shutdown line (HW_SHUTDOWN pin):

• A 47 pF bypass capacitor (e.g. Murata GRM1555C1H470JA01) have to be mounted on the line termination connected to the HW_SHUTDOWN pin to avoid a module reset caused by an electrostatic discharge applied to the application board enclosure.

• A series ferrite bead (e.g. Murata BLM15HD182SN1) must be added on the line connected to the HW_SHUTDOWN pin to avoid a module reset caused by an electrostatic discharge applied to the application board enclosure.

• It is recommended to keep the connection line to HW_SHUTDOWN as short as possible.

RESET_N pin (LISA-C200 only)

Sensitive interface is the reset line (RESET_N pin):

• A 47 pF bypass capacitor (e.g. Murata GRM1555C1H470JA01) have to be mounted on the line termination connected to the RESET_N pin to avoid a module reset caused by an electrostatic discharge applied to the application board enclosure.

• A series ferrite bead (e.g. Murata BLM15HD182SN1) must be added on the line connected to the RESET_N pin to avoid a module reset caused by an electrostatic discharge applied to the application board enclosure.

• It is recommended to keep the connection line to RESET_N as short as possible.

LISA-C200 provides an internal pull-up on the RESET_N pin: an open drain / collector driver is recommended. Driving RESET_N high externally is NOT permitted

u-blox C200

RESET_N – LISA-C200

Reset push button

ESD

Open Drain Output


u-blox C200

FB1

C1

FB2

C2

( HW_SHUTDOWN – FW75-C200)

RESET_N – LISA-C200( HW_SHUTDOWN – FW75-C200)

Figure 37: Reset_N and HW_SHUTDOWN application circuits for ESD immunity test



Page 66 of 103

Reference Description Remarks

ESD Varistor for ESD protection. CT0402S14AHSG - EPCOS

C1, C2 47 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1H470JA01 - Murata

FB1, FB2 Chip Ferrite Bead for Noise/EMI Suppression BLM15HD182SN1 - Murata

Rint 10 kΩ Resistor 0402 5% 0.1 W Internal pull-up resistor

Table 34: Example of components as ESD immunity test precautions for the HW_SHUTDOWN line

SIM interface

Sensitive interface is the SIM interface (VSIM pin, SIM_RST pin, SIM_IO pin, SIM_CLK pin):

• A 47 pF bypass capacitor (e.g. Murata GRM1555C1H470J) have to be mounted on the lines connected to VSIM, SIM_RST, SIM_IO and SIM_CLK to assure SIM interface functionality when an electrostatic discharge is applied to the application board enclosure.

• It is suggested to use as short as possible connection lines at SIM pins.

SIM card interface is supported in software only by LISA-C200 versions 03S/23S onwards

2.5.2 Antenna interface precautions

The antenna interface ANT can have a critical influence on the ESD immunity test depending on the application board handling. Antenna precaution suggestions are provided:

• If the device implements an embedded antenna and the device insulating enclosure avoids air discharge up to +8 kV / -8 kV to the antenna interface, no further precautions to ESD immunity test should be needed.

• If the device implements an external antenna and the antenna and its connecting cable are provided with a completely insulating enclosure to avoid air discharge up to +8 kV / -8 kV to the whole antenna and cable surfaces, no further precautions to ESD immunity test should be needed.

• If the device implements an external antenna and the antenna or its connecting cable are not provided with completely insulating enclosure to avoid air discharge up to +8 kV / -8 kV to the whole antenna and cable surfaces, the following precautions to ESD immunity test should be implemented on the application board.

A higher protection level is required at the ANT port if the line is externally accessible on the application board. ESD immunity test requires protection up to +4 kV / -4 kV for direct Contact Discharge and up to +8 kV / -8 kV for Air Discharge applied to the antenna port. One possible suggested solution for higher protection is to implement an external high pass filter, consisting of a series 15 pF capacitor (Murata GRM1555C1H150JA01) and a shunt 39 nH coil (Murata LQG15HN39NJ02) at the antenna port as described in Figure 38 and Table 35.

Antenna detection functionality is not provided when implementing the high pass filter described in Figure 38 and Table 35., as ESD protection for the antenna port LISA-C200 / FW75-C200.



Page 67 of 103

External Antenna Enclosure

Application Board

LISA-C200 or FW75-C200

ANT

Radiating Element

Zo = 50 Ohm

Coaxial Antenna Cable

Antenna Port

Enclosure Port

C

L

Figure 38: Antenna port ESD immunity protection application circuit


C 15 pF Capacitor Ceramic C0G 0402 5% 50 V GRM1555C1H150JA01 - Murata

L 39 nH Multilayer Chip Inductor L0G 0402 5% LQG15HN39NJ02 - Murata

Table 35: Example of components for Antenna port ESD protection application circuit

2.5.3 Module interfaces precautions

All the module pins that are externally accessible should be included in the ESD immunity test since they are considered to be a port as defined in [13]. Depending on applicability, and in order to satisfy ESD immunity test requirements and ESD category level, pins connected to the port should be protected up to +4 kV / -4 kV for direct Contact Discharge, and up to +8 kV / -8 kV for Air Discharge applied to the enclosure surface.

The maximum ESD sensitivity rating of all the pins of the module, except the ANT pin, is 1 kV (Human Body Model according to JESD22-A114F). A higher protection level can be achieved by mounting an ESD protection (e.g. EPCOS CA05P4S14THSG varistor array or CT0402S14AHSG).

For the USB interface a very low capacitance (i.e. less or equal to 1 pF) ESD protection (e.g. Tyco Electronics PESD0402-140 ESD protection device) can be mounted on the lines connected to USB_D+ and USB_D- pins.

For the SIM interface a low capacitance (i.e. less than 10 pF) ESD protection (e.g. Infineon ESD8V0L2B-03L or AVX USB0002) must be placed near the SIM card holder on each line (VSIM, SIM_IO, SIM_CLK, SIM_RST).


UBX-13000620 - R21 Early Production Information Features description

Page 68 of 103

3 Features description

3.1 TCP/IP and UDP/IP Via the AT commands it’s possible to access the TCP/IP and UDP/IP functionalities over the Packet Switched data connection. For more details about AT commands see the u-blox C2 series AT Commands Manual [3].

LISA-C200 modules support the Direct Link mode for TCP and UDP sockets. Sockets can be set in Direct Link mode to establish a transparent end-to-end communication with an already connected TCP or UDP socket via serial interface. In Direct Link mode, data sent to the serial interface from an external application processor is forwarded to the network and vice-versa.

To avoid data loss while using Direct Link, enable HW flow control on the serial interface.

3.2 HTTP HTTP client is implemented in LISA-C200 modules. HEAD, GET, POST, DELETE and PUT operations are available. The file size to be uploaded / downloaded depends on the free space available in the local file system (FFS) at the moment of the operation.

For more details about AT commands see the u-blox C2 series AT Commands Manual [3].

3.3 FTP

FTP direct link feature is supported only by LISA-C200 from version 04S / 24S onwards.

LISA-C200 modules support File Transfer Protocol functionalities via AT commands. Files are read and stored in the local file system of the module. Alternatively, FTP Direct Link option can be used, which does not require files to be read and stored in the local file system of the module; data sent to the serial interface from an external application processor is forwarded to the network and vice-versa.

For more AT commands details, see u-blox C2 series AT Commands Manual [3].

3.4 UTEST

3.4.1 Description

LISA-C200 modules support +UTEST via AT command. This command enables the module to enter a non-signaling mode. In this mode, within the support 800 / 1900 MHz bands, the module can be set to transmit a defined output RF signal or measure a receive RF signal in a specified channel.

There are various test applications that +UTEST can help facilitate with. This includes, but not limited to:

• Check application board RF TX / RX path connection for integrity, which can potentially detect: o If antenna is installed properly or not o Unintended short or open circuits in the RF path

In addition to +UTEST, the module offers an antenna detection function, which is described in section 2.4.3.

• Investigation of the power supply performance on a host application board • Checking current consumption for a given output TX output power level • Evaluate thermal dissipation for a given TX output power level



Page 69 of 103

This command gives the user a simple interface to set the cellular module to transmitting and receiving states ignoring cellular signaling protocol. When the +UTEST interface is activated, the module is set to test mode. For the module to return to normal operational mode +UTEST must be deactivated (AT+UTEST=0) and a reset or power cycle must be performed.

The following definitions will be used in this document:

• Normal Mode / Signaling mode: The cellular module is able to access cellular networks. All functionalities are enabled according to normal operation status (idle mode, active mode, connected mode); this is typical operating mode of the cellular module.

• Test mode / Non-signaling mode: The test interface is activated. The cellular module is set to a state in which it is not able to access the cellular network. The main software providing CDMA (and all supported systems) network signaling protocol is not running. The test interface provides direct access to the basic transceiver subsystem functionality, only for testing the hardware RF performance of the transmitter or receiver. Complete RF performance required for cellular networks can only be evaluated with the signaling protocol activating a radio link with a base station (or simulator)

The user can activate the test interface using the +UTEST AT command, to set the cellular module into these test modes:

• Transmit mode, to transmit a CDMA signal, selecting: o Channel o Output power level o Band Class o Reserved o Time period of the Tx signal generation

• Receive mode, to measure the CDMA received signal, selecting: o Channel o Time period of the Rx signal measurement o Band Class

The purpose of the +UTEST AT command is to:

• Test and troubleshoot device during host application board prototype stage • Test the device (i.e. the application board where the cellular module is mounted) in production • Execute measurements without a CDMA network simulator

The usage of this command shall be restricted to controlled (shielded chamber/box) environments and for test purpose only. Improper usage of this command on real network could disturb other users and the network itself.

+UTEST should not be used to test the receiver sensitivity. Those kind of tests have to be tested in online mode with call box and correct call control parameter setting.

Cell Band Channel Number Preferred Channel

Number Center Frequency for Forward Channel N (MHz)

Center Frequency for Reverse Channel N (MHz)

Band Class 0

1-799

384

0.03*N+870.000 0.03*N+825.000 991-1023 0.03*(N-1023)+870.000 0.03*(N-1023)+825.000 1024-1323 0.030*(N-1024) + 860.000 0.030*(N-1024) + 815.000 1324-1424 0.030*(N-1324) + 866.010 0.030*(N-1324) + 821.010

Band Class 1 0-1199 525 1930.000+0.05*N 1850.000+0.05*N

Table 36: Generic CDMA Channel Number to CDMA Frequency Assignment



Page 70 of 103

3.4.2 AT+UTEST=0

This command is only available in non-signaling mode. Send AT+UTEST=0 command after terminating the testing procedure. This command allows the module to enter normal mode and closes the test interface. Nevertheless, the module automatically returns to normal mode after switch-off or reset.

Since no other AT command is available in available in non-signaling mode, the AT+CPWROFF command cannot be used

After sending the AT+UTEST=0 command, wait until the normal switch-on boot sequence initializes the AT interface before entering any AT commands.

3.4.3 AT+UTEST=1

This command allows the module to enter non-signaling mode. All other +UTEST command modes are only available in non-signaling mode.

Since no other AT commands are allowed during non-signaling mode, the AT+CMEE=2 command should be sent before activating the test interface. The error description can also be displayed in non-signaling mode.

3.4.4 AT+UTEST=2

The AT+UTEST=2 command tests the receiving power level. This measurement of power level can be done using the following syntax:

AT+UTEST=2,<par1>,<par2>,<par3>

<par1>,<par2>,<par3> are command parameters that can optionally be set. If the parameter is omitted, the default value is used

The command response provides the receiver measurement report as shown below, where min,avg and max values are antenna RF level estimates.

+UTEST: <par1>,<par2>,<par3>,min,avg,max

An OK response will be sent after a time interval when the receiver is switched off. After the OK response, another test command can be sent.

3.4.4.1 <par1>: Channel

For testing in CDMA network, the channel number is configured by <par1> according to +UTEST AT command syntax. The channel numbers can be the same on two different bands, but +UTEST has an internal logic which along with <par3> calculates the frequency at which the module transmits CDMA signal

3.4.4.2 <par2>: Time Interval

<par2> defines the time interval (expressed in milliseconds) over which the receiver is active.

3.4.4.3 <par3>: Band Class

The <par3> in UTEST is reserved for Band Class selection. This along with <par1> determines the frequency at which the module receives. Band Class 0 (800 MHz) and Band Class 1 (1900 MHz) each have their own codes. Refer to AT commands manual for more information.



Page 71 of 103

3.4.4.4 Response, receiver power level estimation:

After the time interval, the command response is the RMS received power level (minimum, average and maximum level) expressed in dBm. The average level is calculated during the whole time interval

The receiver power levels(min, avg, max) range from -95 to -30 dBm. Although in this case, the protocol stack is inoperative, the reported results can be assumed to be good estimates.

Rx path test should have a clearly specified input signal strength level ( e.g. -50dBm ) of a CW waveform. Expected accuracy of the measurement level will be approximately +/- 1.0 dB. If the measured value is incorrect, this indicates the Rx path is broken or has defects.

For the maximum allowed receive signal level at the antenna port, refer to the LISA-C200 datasheet [1].

A Signal Generator should be connected to the Ant port when this test is performed.

If a unmodulated signal from a signal generator is used, a 30KHz offset should be applied to the signal generated relative to the measurement channel. Without the offset, the majority of signal may not be measured because the zero-IF direct down coversion receiver ignores the center of the channel component, since the center frequency becomes the DC value once down converted. Example: If you measure a receive channel #384 at 881.52 MHz (band class 0), then set the signal generator at 881.49 MHz or 881.55 MHz. If you set the signal generate at 881.52 MHz, then utest may not read the expected RF level at the antenna port.

3.4.5 AT+UTEST=3

The AT+UTEST=3 command sets the module to RF power emission ignoring the CDMA protocol. This emission can generate interference that is prohibited by law in some countries. The use of this feature is only intended for testing purposes in controlled environments by qualified users, and must not be used during normal module operation. Follow the instructions provided in u-blox documentation. U-blox assumes no responsibilities for the inappropriate use of this feature.

RF signal transmission can be triggered with this command:

AT+UTEST=3,<par1>,<par2>,<par3>,<par4>,<par5>

<par1>,…<par5> are command parameters that can be optionally set. If not set, the default value is used for each parameter. For more AT commands details, see u-blox C2 series AT Commands Manual [3].

OK response will be sent after a time interval when the transmitter is turned off. After the OK response, any other test command can be sent.

3.4.5.1 <par1>: Channel

For testing in CDMA network, the channel number is configured by <par1> according to +UTEST AT command syntax. The channel numbers can be the same on two different bands, but +UTEST has an internal logic which along with <par3> calculates the frequency at which the module transmits CDMA signal

The output is a modulated signals that occupies a 1.25MHz bandwidth around the center of the channel



Page 72 of 103

3.4.5.2 <par2>: Power Level

For testing in CDMA networks, the output power level is configured with the absolute power level (dBm) by <par2> ranging from -56 dBm up to 5 dBm. For example, if <par2>=-5, the RMS output power of the CDMA signal is -5 dBm, within tolerances.

Max output power levels vary between different firmware versions. See u-blox C2 series AT Commands Manual [3] for max power output levels corresponding to the various firmware version available.

3.4.5.3 <par3>: Band Class

The <par3> in UTEST is reserved for Band Class selection. This along with <par1> determines the frequencies at which the module transmits and receives. Band Class 0 (800 MHz) and Band Class 1 (1900 MHz) each have their own codes. Refer to AT commands manual for more information.

Figure 39: Band Class 0 Cell Channels (BC0)



Page 73 of 103

Figure 40: Band Class 1 PCS Channels (BC1)

3.4.5.4 <par4>: Reserved

The <par4> is reserved for development purposes. For now, even if this value is not mentioned in the syntax, module will fill in with its default value which is 0

3.4.5.5 <par5>: Time Interval

<par5> configures the length of time (expressed in milliseconds) for which the module will transmit.

With time parameter set to 0, the RF signal is continuosly transmitted and an OK response will be sent soon after the command execution. After the OK response, another test command can be sent. The transmission is stopped sending the commands AT+UTEST=0, AT+UTEST=1 or AT+UTEST=2. The transmission is changed, updating the parameters with the another AT+UTEST=3 command.

Tx path test should be performed with spectrum analyzer connected to the antenna port. It should be tuned to the center frequency of the expected test channel. Based on the default +UTEST Tx signal level setting, which is -45dBm, after the +UTEST Tx test command is executed, the spectrum analyzer should illustrate a CDMA signal with the signal level of -45dBm +/- 0.5 dB in the expected channel center frequency and bandwidth. If the expected response is not received, then it indicates that the Tx path is broken or has defects.

When +UTEST is used the correct band and its corresponding channel have to be used. If the channel and band are not correct, the command will throw “ +CME ERROR : Invalid parameter “

After any +UTEST command has been executed, AT+UTEST=0 should be used to turn OFF UTEST mode and the module or UUT (unit under test) has to be power cycled to bring the module back to the normal operational mode.



Page 74 of 103

3.5 Carrier Provisioning

3.5.1 Factory NAM settings

Factory Number Assignment Module (NAM) items are of interest when checking if the module is provisioned and what carrier profile the unit is set up for. The NAM settings include:

• MDN/MIN

• Default PRL version

• MIP Profile

The MDN/MIN from the factory has the format 000000XXXX, with six leading zeros and XXXX representing a numeric value that may not be zero. After successful provisioning, the MDN/MIN will change to a subscriber number assigned by the carrier. The $RTN command will restore the MDN/MIN number to the factory value and format.

From the factory, a default PRL is loaded. This default PRL varies between carriers and changes over time. Depending on the carrier and geographic location, the PRL may change upon successful provisioning. The $PRL command is used to check what PRL version is presently loaded in the module. If the default PRL from the factory has changed, the $RTN command does not restore the PRL to the original factory version that it came with.

The MIP Profile is specific to each carrier and changes after provisioning. Use AT$QCMIPGETP to check the MIP profile. Further details on the MIP profile are covered in both this chapter and LISA-C200 & FW75-C200 AT commands examples u-blox CDMA 1xRTT wireless modules Application Note [17]

3.5.2 Sprint

3.5.2.1 OMA device management

The OMA device management feature is supported only by Sprint versions.

The OMA-DM process can be divided into three distinct operations:

• Device configuration

• PRL programming

• Firmware update

Each operation can occur as the result of a network initiated trigger, a client initiated trigger, or as part of the hands-free activation process.

3.5.2.2 Components

The OMA-DM implementation on u-blox CDMA devices is set up by an application library from Red Bend. This library holds the needed SW components to establish an OMA-DM session for a successful completion of the device’s provisioning.

The most relevant files involved in the OMA-DM provisioning procedure are:



Page 75 of 103

• Tree.xml that contains:

• Routine Script

• Server URL, Proxy of the OMA-DM server

• Device Access information: MIP, NAI, SSD, PRL information

• Device profile

• Reg.conf that contains:

• Routine tracker

• Updated per every OMADM session, it continues from the previous stored state

3.5.2.3 Device configuration

Device configuration is the programming of parameters needed to access network voice and/or data services. Device configuration data is provided by the Sprint Provisioning System. It is conveyed to the device via the OMA-DM server. Device configuration parameters include:

• NAM Parameters (MDN and MSID)

• MIP Parameters (MIP Profile 1)

3.5.2.4 PRL programming

Sprint requires that devices be able to update a subscriber’s PRL as needed. This may be up to or exceeding 4 times per year. The OMA-DM Client will trigger a PRL commit following the successful completion of the management session. No power cycle is performed here. Instead, the device performs a radio reset to load the new PRL. The device will not have service for approximately 10 seconds after the PRL commit.

3.5.2.5 Firmware update

Sprint requires that OMA Clients support firmware updates using an alternative download (OMA-DL) where retrieval of the update packages is completed using the “alternative” download mechanism. To satisfy this requirement, the device may make two data calls during the FUMO session – one to check for the existence of an update package and, if an update exists, a second data call to perform the download of the update package.

When the update package download completes the DM Client will send +UOMASTAT:2,1,0 before jumping to the boot loader to install the update package. The device will not respond to AT commands while the update package is being installed. The device will power cycle when the update package installation is complete.

After the firmware update (success or failure) the device will report its final state to the OMA-DM Server. After completing a FUMO update, whether it was network-initiated or client-initiated, the device will perform another client-initiated FUMO to check for additional updates. FUMO transactions may loop multiple times to ensure that the device receives all available updates.



Page 76 of 103

Figure 41: FUMO update flow chart

3.5.2.6 Hands Free Activation

Hands-Free Activation (HFA) is a series of client-initiated commands performed when the device is powered on in a factory default state. The device is considered to be in the factory default state when any of the following conditions are true:

• MSID is default (000-000-xxxx)

• MDN is default (000-000-xxxx)

Applications can reset the device to the factory default state by sending the $RTN command.

The transactions below are performed in the order listed during HFA:

1. Client-initiated Device configuration 2. Client-initiated PRL update 3. Client-initiated FUMO

3.5.2.7 Session establishment

Device management sessions can be established by the OMA-DM Server using a Notification Initiation Alert (NIA). The NIA is sent in the payload of a WAP-encoded SMS message. The NIA will be processed immediately if the device is not in an active data session.

In general, the message payload consists primarily of a server account identification pointing to a server account preconfigured in a DM tree node (tree.xml file).

If a data session is active, the LISA/FW75-C200’s DM Client will store the NIA until it can be executed. The conditions required for execution are:

• The current data session has moved to an idle or dormant state (i.e. the traffic channel is idle)

• The modem is on either a home or roaming signal.

It should be noted that the dormant data connection will be torn down when the device process the NIA.



Page 77 of 103

Applications should not attempt to re-establish the connection until the OMA-DM session has completed. The +UOMASTAT URC should be monitored to determine if an OMA-DM session is in progress.

Device management sessions can also be Client Initiated (CI). In general, the initiation of such sessions are triggered by the Host Application, but they can also be triggered by events external to the OMA-DM Client, for example:

• Asynchronous actions (e.g. reporting status of some action on device)

• After a firmware update

• Extensible exec operations (per-device)

• After a PRL upgrade

• Device initiated sessions

• Diagnostic events

• Business logic driven (DSS, etc.)

• Periodic (monthly, quarterly, etc.)

Applications should not attempt to establish a connection until the OMA-DM session has completed. The +UOMASTAT URC should be monitored to determine if an OMA-DM session is in progress. Client initiated attempts will fail if an OMA-DM session is already in progress.

3.5.2.8 Best practices

Host applications should not initiate data calls or power down / cycle the module while an OMA-DM session is active. Specifically:

• Applications should monitor the +UOMASTAT URC to determine if an OMA-DM session is in progress.

• Applications should wait a minimum 15 seconds after power-on before initiating a data call as asynchronous operations may be triggered by the OMA-DM Client (e.g. processing a queued NIA or performing HFA).

• Applications should wait approximately 30 seconds after the completion of an OMA-DM session (e.g. +UOMASTAT:1,1,0 or +UOMASTAT:2,1,0) before initiating a data call as additional asynchronous operations may be triggered by the OMA-DM Client.

In an event that the module is in factory default state and no +UOMASTAT URC is received after 60 seconds of the module’s power up, then it is recommended to execute the AT+UOMADMCLEAN=0 command.

The module is considered in factory default state if:

• AT$MDN? Returns : 000000XXXX

• AT$MSID? Returns : 000000XXXX

• AT$QCMIPGETP=1 : Returns : [email protected]

The flow diagram in Figure 42 describes how to use the AT+UOMADMCLEAN=0 command.



Page 78 of 103

Figure 42: AT+UOMADMCLEAN practical use

+UOMADMCLEAN use is not needed from version 03S / 23S onwards

3.5.2.9 FACTORY ENVIRONMENT

3.5.2.9.1 OMA-DM provisioning

Given that in a factory environment the OMA-DM session will start during the testing process, it is highly recommended to include a checking routine to make sure the reg.conf file isn’t halting the OMA-DM sessions, or to leave the device on factory default values.

The factory setup procedure should be:

1. Check for DC values.

• AT$MDN? Returns : 000000XXXX

• AT$MSID? Returns : 000000XXXX

• AT$QCMIPGETP=1 : Returns : [email protected]

2. Check for +UOMASTAT URC messages.

3. Allow 45 seconds from the C200 device’s power up and monitor the URCs. If no URCs received, then execute: AT+UOMADMCLEAN=0.

4. Check for DC values.

5. If no +UOMASTAT URC is received, use:

• AT+OMADM=2 to force a start

6. If still no URC is seen, perform AT$RTN=000000.

7. Allow for the URC +UOMASTAT to be displayed.

8. If the device needs to be powered down, then execute: AT+CPWROFF and allow 5 seconds to disconnect the power source.

9. You can check if the device has been ever provisioned with AT+UPROVSTATE?

a. +PROVSTATE: 0 response means it has never been provisioned before

b. +PROVSTATE: 1 response means it has been provisioned before



Page 79 of 103

3.5.3 Aeris

3.5.3.1 Preparation

EDF (electronic data file) information has to be loaded into the Aeris database prior to starting any provisioning attempt. Access to the AT Command interface through a COM port is required.

3.5.3.2 Conversion steps

The u-blox LISA-C200 can be migrated to Aeris mode using +UAERIS AT command. Once in Aeris mode, the MIN and MDN can be programmed using the appropriate AT commands. All other settings are preprogrammed at the factory and should not be modified. After the device is provisioned using AerPort, enter the device parameters following the steps below, where: XXXXXXXXXX=Device MDN YYYYYYYYYY=Device MIN Step AT Command Response Comment

02 AT+UAERIS=0 OK Migrate to Aeris mode

03 AT$MDN=000000,<MDN> OK Program the MDN

04 AT$MSID=000000,<MIN> OK Program the MIN

Post Activation Validation (Optional) These optional steps may be performed to confirm that the module has been correctly programmed. Step AT Command Response Comment

02 AT$MDN? XXXXXXXXXX OK

Confirm the MDN

03 AT$MSID? YYYYYYYYYY OK

Confirm the MIN

The command AT+UAERIS=0 needs to be sent within the first 15 seconds of powering-up the device

If the module has gone through an OMA-DM session (Sprint,) and received the provisioning values, then the following URC is seen and repeated three times (each time corresponding to: device configuration, PRL update, FUMO):

• +UOMASTAT:1,0,0

If there is a failure in the OMA-DM session, then a returning URC appears as:

• +UOMASTAT:1,1,0

If the above URC sequence pair is not observed three times or a URC indicates failure, it is recommended to:

• Run AT$MDN? to confirm the device is not provisioned with a valid phone number

• Perform AT$RTN=000000

• Run again AT+UAERIS=0

The easiest way to check for the Aeris profile is by AT$QCMIPGETP=1 command.

• Aeris profile returns: MEID(HEX)@tsp08.sprintpcs.com

• Sprint will use the format: <username/MDN>@sprintpcs.com



Page 80 of 103

3.5.4 Verizon

The provisioning is implemented using the OTASP protocol. See LISA-C200 & FW75-C200 AT commands examples u-blox CDMA 1xRTT wireless modules Application Note [17]

3.5.4.1 Verizon Device Configuration and PRL update

Verizon’s Device Configuration and PRL update is implemented following the OTASP standard by means of *22899.

Once the LISA-C200 module is provisioned, new OTASP session can be attempted, and will take effect by updating the PRL version of the module.

3.5.5 US Cellular

US Cellular profile is supported only by LISA-C200 from version 24S onwards. Device must be inside the US Cellular network to successfully complete the OTASP session.

3.5.5.1 Preparation

EDF (electronic data file) information has to be loaded into the “US Cellular” Database prior to starting any provisioning attempt. Access to the AT Command interface through a COM port is required.

3.5.5.2 Conversion steps

The LISA-C200 module can be migrated to “USCC” mode using +UUSCELL=3 AT command. Once in “USCC” mode, the MIN and MDN can be programmed using OTASP operations. For details, see LISA-C200 & FW75-C200 AT commands examples u-blox CDMA 1xRTT wireless modules Application Note [17]

All other settings are preprogrammed at the factory and should not be modified. Step AT Command Response Comment

01 AT+UUSCELL=3 OK Migrate to “USCC” mode

Post Activation Validation (Optional) These optional steps may be performed to confirm that the module has been correctly programmed. Step AT Command Response Comment

02 AT$MDN? XXXXXXXXXX OK

Confirm the MDN

03 AT$MSID? YYYYYYYYYY OK

Confirm the MIN

If the device needs to be returned to a factory default state (Verizon mode) to restart the conversion procedure to US Cellular, then the following steps are recommended:

• Run AT$RTN=000000 to return the device to factory default (Verizon mode).

• Run AT+UUSCELL=3 this set the device to USCC mode.

• Run AT$MDN? to check if it is set to 000000xxxx factory format.



Page 81 of 103

The easiest way to check for the “USCC” profile is by AT$QCMIPGETP=1 command:

• US Cellular profile returns: [email protected]

• Verizon profile returns: [email protected]

3.5.6 Firmware (upgrade) Over AT (FOAT)

This feature is supported only by LISA-C200 from version 04S.

3.5.6.1 Overview

This feature allows upgrading the module Firmware over UART or USB using AT Commands.

• AT Command AT+ UFWUPD triggers a upgrade procedure at specified a baud rate (see u-blox C2 series AT Commands Manual [3] for more details)

• The Xmodem protocol is used for downloading the new firmware image via a terminal application

• Firmware authenticity verification is performed via a security signature during the download. The firmware is then installed, overwriting the current version.

• After completing the upgrade, the module is reset again and wakes-up in normal boot

In case of power loss during upgrade / downgrade, the boot loader detects a fault at the next wake-up, and reverts back to the original firmware.

If the FW package is not the expected incremental upgrade or decremental downgrade, the boot loader detects a version fault at the next wake-up, and reverts back to the original firmware.

3.5.6.2 FOAT procedure

The application processor must proceed in the following way:



Page 82 of 103

• Send the AT+UFWUPD=3 command through the UART or over the USB interface

• A command will respond with a prompt (special character), indicating it is ready for the file transfer

• Select the target FW package to upgrade to

• Send the new FW image via Xmodem (see Figure 43 for details)

Figure 43: FOAT Update via Xmodule protocol

3.6 AssistNow clients and GNSS Integration

This feature is supported only by LISA-C200 from version 03S / 23S onwards.

For customers using u-blox GNSS receivers, LISA-C cellular modules feature embedded AssistNow clients. AssistNow A-GNSS improves GNSS performance and Time-To-First-Fix. The clients can be enabled and disabled with an AT command (see the u-blox C2 series AT Commands Manual [3]).

LISA-C modules act as a stand-alone AssistNow client, making AssistNow available with no additional requirements for resources or software integration on an external host micro controller. Full access to u-blox GNSS receivers is available via the LISA-C200, through a dedicated DDC (I2C) interface, while the available GPIOs can handle the positioning unit power-on/off. This means that CDMA and GNSS can be controlled through a single serial port from any host processor.

3.7 Hybrid positioning and CellLocateTM

These features are supported only by LISA-C200 from version 04S / 24S onwards.

Although GNSS is a widespread technology, its reliance on the visibility of extremely weak GNSS satellite signals means that positioning is not always possible. Especially difficult environments for GNSS are indoors, in enclosed or underground parking garages, as well as in urban canyons where GNSS signals are blocked or jammed by multipath interference. The situation can be improved by augmenting GNSS receiver data with cellular network



Page 83 of 103

information to provide positioning information even when GNSS reception is degraded or absent. This additional information can benefit numerous applications.

3.7.1 Positioning through cellular information: CellLocateTM

u-blox CellLocateTM enables the estimation of device position based on the parameters of the mobile network cells visible to the specific device. To estimate its position the u-blox cellular module sends the CellLocateTM server the parameters of network cells visible to it using a UDP connection. In return the server provides the estimated position based on the CellLocateTM database. For AT command details, see u-blox C2 series AT Commands Manual [3].

The CellLocateTM database is compiled from the position of devices which observed, in the past, a specific cell or set of cells (historical observations) as follows:

1. Several devices reported their position to the CellLocateTM server when observing a specific cell (the As in Figure 44 represent the position of the devices which observed the same cell A)

Figure 44: Devices represented by “A” notation observe the same Cell A and report their position to CellLocateTM server

2. CellLocateTM server defines the area of Cell A visibility

Figure 45: CellLocateTM server defines the area where devices are able to observe Cell A

3. If a new device reports the observation of Cell A CellLocateTM is able to provide the estimated position from the area of visibility



Page 84 of 103

Figure 46: CellLocateTM server provides position estimation to new device that observes Cell A.

4. The visibility of multiple cells provides increased accuracy based on the intersection of areas of visibility.

Figure 47: A device that observes multiple cells (A, B, C in this example) can receive relatively higher accuracy position from the CellLocateTM server based on the intersection of areas of visibility.

CellLocateTM is implemented using a set of two AT commands that allow configuration of the CellLocateTM service (AT+ULOCCELL) and requesting position according to the user configuration (AT+ULOC). The answer is provided in the form of an unsolicited AT command including latitude, longitude and estimated accuracy.

The accuracy of the position estimated by CellLocateTM depends on the availability of historical observations in the specific area.

3.9.2 Hybrid positioning

With u-blox Hybrid positioning technology, u-blox cellular devices can be triggered to provide their current position using either a u-blox GNSS receiver or the position estimated from CellLocateTM. The choice depends on which positioning method provides the best and fastest solution according to the user configuration, exploiting the benefit of having multiple and complementary positioning methods.

Hybrid positioning is implemented through a set of three AT commands that allow configuration of the GNSS receiver (AT+ULOCGNSS), configuration of the CellLocateTM service (AT+ULOCCELL), and requesting the position according to the user configuration (AT+ULOC). The answer is provided in the form of an unsolicited AT command including latitude, longitude and estimated accuracy (if the position has been estimated by CellLocateTM), and additional parameters if the position has been computed by the GNSS receiver.

The configuration of mobile network cells does not remain static (e.g. new cells are continuously added or existing cells are reconfigured by the network operators). For this reason, when a Hybrid positioning method has been triggered and the GNSS receiver calculates the position, a database self-learning mechanism has been implemented so that these positions are sent to the server to update the database and maintain its accuracy.



Page 85 of 103

The use of hybrid positioning requires a connection via the DDC (I2C) bus between the LISA-C cellular module and the u blox GNSS receiver (see section 1.10).

Refer to GNSS Implementation Application Note [18] for the complete description of the feature.

u-blox is extremely mindful of user privacy. When a position is sent to the CellLocateTM server u-blox is unable to track a specific celluar module.

3.8 Audio File Playback

Audio file playback from locally stored AMR audio file feature is supported only by LISA-C200 from version 04S / 24S onwards

Audio file playback is stopped and terminated if there is a incoming or terminated voice call during playback

When transferring a file using +UDWNFILE into the LISA-C200 file system a slower baud than 115200 KB/sec is recommended

Total AMR audio files should not exceed 400KB to avoid memory issues

LISA-C200 modules permits audio files in AMR format to be stored and played back using the +UPLAYFILE command. During playback if there is an incoming voice call or if a call is terminated during playback, then the playback instance will stop and will not resume.

Playback can be initiated during an active voice call.

If the playback is prematurely terminated, a URC is generated to reflect the incomplete playback. In such a case, one option is to configure the audio file to be played multiple times and / or have the host application monitor the URC and replay the audio file as needed. For URC message details, see u-blox C2 series AT Commands Manual [3].

To load and delete the AMR files from memory:

• +UDWNFILE command to load the AMR file into the module in binary mode

• +UDELFILE command to delete the AMR file

For more details, see u-blox C2 series AT Commands Manual [3].

3.9 Network Status Indicator

This feature is supported only by LISA-C200 from version 04S / 24S onwards.

The GPIO1, GPIO2, GPIO3, GPIO4 or GPIO5 alternatively from their default settings, can be configured to indicate network status (i.e. no service, registered home network, registered visitor network, voice or data call session), by means of the AT+UGPIOC command. For further details, see u-blox C2 series AT Commands Manual [3].

The different Network Status Indicator states are defined as:



Page 86 of 103

• No Service: Indicates No Network coverage or Not Registered (but there can be coverage in limited service). GPIO output is low.

• Registered Home Network CDMA: - Indicates registered with home CDMA network (full or limited service). GPIO cyclic output sequence:

• High for 100ms

• Low for 2sec

• Registered Roaming CDMA: Indicates registered with visitor CDMA network (roaming, full or limited service). GPIO cyclic output sequence:

• High for 100ms

• Low for 100ms

• High for 100ms

• Low for 2sec

• Transmission: Indicates ongoing voice or data call. GPIO output is high


UBX-13000620 - R21 Early Production Information Handling and soldering

Page 87 of 103

4 Handling and soldering This chapter applies to LISA-C200 only

No natural rubbers, no hygroscopic materials or materials containing asbestos are employed.

4.1 Packaging, shipping, storage and moisture preconditioning For information pertaining to reels and tapes, Moisture Sensitivity levels (MSD), shipment and storage information, as well as drying for preconditioning see the LISA-C Data Sheet [1].

The LISA-C modules are Electro-Static Discharge (ESD) sensitive devices.

Ensure ESD precautions are implemented during handling of the module.

4.2 Soldering

4.2.1 Soldering paste

Use of "No Clean" soldering paste is strongly recommended, as it does not require cleaning after the soldering process has taken place. The paste listed in the example below meets these criteria.

Soldering Paste: OM338 SAC405 / Nr.143714 (Cookson Electronics)

Alloy specification: 95.5% Sn / 3.9% Ag / 0.6% Cu (95.5% Tin / 3.9% Silver / 0.6% Copper)

95.5% Sn / 4.0% Ag / 0.5% Cu (95.5% Tin / 4.0% Silver / 0.5% Copper)

Melting Temperature: 217°C

Stencil Thickness: 150 µm for base boards

The final choice of the soldering paste depends on the approved manufacturing procedures.

The paste-mask geometry for applying soldering paste should meet the recommendations in section 2.3.2

The quality of the solder joints on the connectors (’half vias’) should meet the appropriate IPC specification.

4.2.2 Reflow soldering

A convection type-soldering oven is strongly recommended over the infrared type radiation oven. Convection heated ovens allow precise control of the temperature and all parts will be heated up evenly, regardless of material properties, thickness of components and surface color.

Consider the "IPC-7530 Guidelines for temperature profiling for mass soldering (reflow and wave) processes, published 2001".

Reflow profiles are to be selected according to the following recommendations.

Failure to observe these recommendations can result in severe damage to the device!

Be aware that IPC/JEDEC J-STD-020 applies to integrated circuits, cannot be properly applied to module devices.



Page 88 of 103

Preheat phase

Initial heating of component leads and balls. Residual humidity will be dried out. Note that this preheat phase will not replace prior baking procedures.

• Temperature rise rate: max 3°C/s If the temperature rise is too rapid in the preheat phase it may cause excessive slumping.

• Time: 60 – 120 s If the preheat is insufficient, rather large solder balls tend to be generated. Conversely, if performed excessively, fine balls and large balls will be generated in clusters.

• End Temperature: 150 - 200°C If the temperature is too low, non-melting tends to be caused in areas containing large heat capacity.

Heating/ reflow phase

The temperature rises above the liquidus temperature of 217°C. Avoid a sudden rise in temperature as the slump of the paste could become worse.

• Limit time above 217°C liquidus temperature: 40 - 60 s

• Peak reflow temperature: 245°C

Cooling phase

A controlled cooling avoids negative metallurgical effects (solder becomes more brittle) of the solder and possible mechanical tensions in the products. Controlled cooling helps to achieve bright solder fillets with a good shape and low contact angle.

• Temperature fall rate: max 4°C / s

To avoid falling off, modules should be placed on the topside of the motherboard during soldering.

The soldering temperature profile chosen at the factory depends on additional external factors like choice of soldering paste, size, thickness and properties of the base board, etc.

Exceeding the maximum soldering temperature and the maximum liquidus time limit in the recommended soldering profile may permanently damage the module.

Preheat Heating Cooling[°C] Peak Temp. 245°C [°C]250 250

Liquidus Temperature217 217200 200

40 - 60 s

End Temp. max 4°C/s150 - 200°C

150 150

max 3°C/s 60 - 120 s

100 Typical Leadfree 100Soldering Profile

50 50

Elapsed time [s] Figure 48: Recommended soldering profile

LISA-C modules must not be soldered with a damp heat process.

When soldering lead-free LISA-C200 and FW75-C200 modules in a leaded process, review the guidelines in this section to ensure any changes in temperature still conform to the soldering profile characteristics and its limits.



Page 89 of 103

4.2.3 Optical inspection

After soldering the LISA-C modules, inspect the modules optically to verify that he module is properly aligned and centered.

4.2.4 Cleaning

Cleaning the soldered modules is not recommended. Residues underneath the modules cannot be easily removed with a washing process.

• Cleaning with water will lead to capillary effects where water is absorbed in the gap between the baseboard and the module. The combination of residues of soldering flux and encapsulated water leads to short circuits or resistor-like interconnections between neighboring pads. Water will also damage the sticker and the ink-jet printed text.

• Cleaning with alcohol or other organic solvents can result in soldering flux residues flooding into the two housings, areas that are not accessible for post-wash inspections. The solvent will also damage the sticker and the ink-jet printed text.

• Ultrasonic cleaning will permanently damage the module, in particular the quartz oscillators.

For best results use a "no clean" soldering paste and eliminate the cleaning step after the soldering.

4.2.5 Repeated reflow soldering

Only a single reflow soldering process is encouraged for boards with a LISA-C module populated on it. The reason for this is the risk of the module falling off due to high weight in relation to the adhesive properties of the solder.

4.2.6 Wave soldering

Boards with combined through-hole technology (THT) components and surface-mount technology (SMT) devices require wave soldering to solder the THT components. Only a single wave soldering process is encouraged for boards populated with LISA-C modules.

4.2.7 Hand soldering

Hand soldering is not recommended.

4.2.8 Rework

The LISA-C modules can be unsoldered from the baseboard using a hot air gun.

Avoid overheating the module.

After the module is removed, clean the pads before placing.

Never attempt a rework on the module itself, e.g. replacing individual components. Such actions immediately terminate the warranty.

4.2.9 Conformal coating

Certain applications employ a conformal coating of the PCB using HumiSeal® or other related coating products.

These materials affect the HF properties of the LISA-C modules and it is important to prevent them from flowing into the module.

The RF shields do not provide 100% protection for the module from coating liquids with low viscosity, therefore care is required in applying the coating.

Conformal Coating of the module will void the warranty.



Page 90 of 103

4.2.10 Casting

If casting is required, use viscose or another type of silicone-pottant. The OEM is strongly advised to qualify such processes in combination with the LISA-C modules before implementing this in the production.

Casting will void the warranty.

4.2.11 Grounding metal covers

Attempts to improve grounding by soldering ground cables, wick or other forms of metal strips directly onto the EMI covers is done at the customer's own risk. The numerous ground pins should be sufficient to provide optimum immunity to interferences and noise.

u-blox gives no warranty for damages to the LISA-C modules caused by soldering metal cables or any other forms of metal strips directly onto the EMI covers.

4.2.12 Use of ultrasonic processes

LISA-C modules contain components which are sensitive to Ultrasonic Waves. Use of any Ultrasonic Processes (cleaning, welding etc.) may cause damage to the module.

u-blox gives no warranty against damages to the LISA-C modules caused by any Ultrasonic Processes.


UBX-13000620 - R21 Early Production Information Appendix

Page 91 of 103

Appendix

A Glossary ADC Analog to Digital Converter

AP Application Processor

AT AT Command Interpreter Software Subsystem, or attention

CBCH Cell Broadcast Channel

CS Coding Scheme

CSD Circuit Switched Data

CTS Clear To Send

DC Direct Current

DCD Data Carrier Detect

DCE Data Communication Equipment

DCS Digital Cellular System

DDC Display Data Channel

DSP Digital Signal Processing

DSR Data Set Ready

DTE Data Terminal Equipment

DTM Dual Transfer Mode

DTR Data Terminal Ready

EBU External Bus Interface Unit

CDMA CODE Division Multiple Access

FDD Frequency Division Duplex

FEM Front End Module

FOAT Firmware Over AT commands

FTP File Transfer Protocol

FTPS FTP Secure

GND Ground

GPIO General Purpose Input Output

GNSS Global Navigation Satellite System (general term that includes satellite systems: GPS, GLONASS, BeiDou, QZSS, Galileo)

GPS Global Positioning System

HF Hands-free

HTTP HyperText Transfer Protocol

HTTPS Hypertext Transfer Protocol over Secure Socket Layer

HW Hardware

I/Q In phase and Quadrature

I2C Inter-Integrated Circuit

I2S Inter IC Sound

IP Internet Protocol

IPC Inter Processor Communication



Page 92 of 103

LNA Low Noise Amplifier

MCS Modulation Coding Scheme

NOM Network Operating Mode

PA Power Amplifier

PBCCH Packet Broadcast Control Channel

PCM Pulse Code Modulation

PCS Personal Communications Service

PFM Pulse Frequency Modulation

PMU Power Management Unit

RF Radio Frequency

RI Ring Indicator

RTC Real Time Clock

RTS Request To Send

RUIM R-UIM, Removable User Identity Module: card that extends a GSM SIM card for CDMA use

RXD RX Data

SAW Surface Acoustic Wave

SIM Subscriber Identification Module

SMS Short Message Service

SMTP Simple Mail Transfer Protocol

SRAM Static RAM

TCP Transmission Control Protocol

TDMA Time Division Multiple Access

TXD TX Data

UART Universal Asynchronous Receiver-Transmitter

UDP User Datagram Protocol

USB Universal Serial Bus



Page 93 of 103

B Migration from LISA-U to LISA-C200 Overview The LISA-C200 module provides dual-band CDMA2000 1xRTT data and voice communication in the same compact LISA SMT LCC form factor (22.4 x 33.2 mm) as the LISA-U series UMTS/HSPA and GSM/EGPRS/EDGE modules, enabling straightforward development of products supporting either CDMA, W-CDMA or GSM/GPRS cellular technology with the same application board.

u-blox offers the flexibility to easily migrate from LISA-U series application designs to LISA-C200 module application designs in a straight forward procedure. This allows customers to take maximum advantage of their hardware and software investments. In such a migration, there are some points to consider, as explained in this section.

Checklist for migration

Have you chosen the optimal module version?

LISA-C200-03S: 1xRTT module, 800/1900 MHz, Sprint / Aeris custom features

LISA-C200-23S: 1xRTT module, 800/1900 MHz, Verizon / US Cellular custom features

Check LISA-C200 series hardware requirements

Check the application circuit of the VCC pins. A power supply circuit properly designed for LISA-U series modules is compatible for LISA-C200 as long as the voltage is within the LISA-C200 specification, but LISA-C200 doesn’t automatically switch on when applying VCC supply. It switches on if the PWR_ON input pin is permanently low when VCC is applied.

Check the application circuit of the pin 2. This pin is Reserved (RSVD) on LISA-C200 modules and doesn’t provide supply for Real Time Clock (V_BCKP) as on LISA-U series modules.

Check the application circuit of pin 5. On LISA-C200 this RSVD pin may be connected to GND for compatibility with LISA-U or leave NC if no compatibility is required.

Check the application circuit of the pins 9, 11 and 12. These pins are Reserved (RSVD) on LISA-C200 modules and do not provide DSR, DCD and DTR signals as LISA-U series modules do. Leave these pins unconnected on LISA-C200 modules.

Check the application circuit of pins 55, 56, 57, 58, and 59. These pins are Reserved (RSVD) on LISA-C200 modules and do not provide an SPI / IPC interface as LISA-U series modules do.

Check the application circuit of USB_D+, USB_D- pins: LISA-C200 provides one USB communication device class over a full-speed USB 2.0 interface, whereas LISA-U series modules provide multiple USB communication device classes over a high-speed USB 2.0 interface.

Check the application circuit of the PWR_ON pin: LISA-C200 provides an internal pull-up. An open drain or open collector driver is recommended.

Check the application circuit of the RESET_N pin: LISA-C200 provides an internal pull-up. An open drain or open collector driver is recommended.

Check the application circuit of pins 39, 40, 53, and 54. On LISA-C200, the Analog Audio input (MIC_N, MIC_P) and output (SPK_P, SPK_N) are compatible with LISA-U120 and LISA-U130, but the other LISA-U series modules don’t provide the same functionality.

Check the application circuit of pins 41, 42, 43, and 44. LISA-C200 provides an I2S interface that only supports PCM digital audio format (PCM_SYNC, PCM_DO, PCM_CLK, PCM_DI). This is comparable with the digital audio interface provided by LISA-U120, LISA-U130, LISA-U230 and LISA-U200.



Page 94 of 103

Check the application circuit of pin 52. This pin is Reserved (RSVD) on LISA-C200, as it is on LISA-U1 series modules. On LISA-U230 and LISA-U200 modules, it provides clock output (CODEC_CLK).

Check the application circuit of pins 20, 21, 23, 24, and 51. LISA-C200 provides GPIOs, as do LISA-U series modules, but LISA-U series modules provide additional functionalities.

Check the application circuit of the SIM interface pins. Upon request to u-blox, LISA-C200 can support an external SIM (RUIM) card.

Check the application circuit of pin 74. This pin is Reserved (RSVD) on LISA-C200, as it is on LISA-U1 series and LISA-U200. On LISA-U230, it provides RF input for Rx diversity antenna (ANT_DIV).

Check the application circuit of the ANT pin. An antenna circuit properly designed for LISA-U series modules is compatible for LISA-C200, because LISA-C200 transmits and receives on a subset of the frequencies used by LISA-U series modules.

Check the temperature requirements. The LISA-C200 operating temperature range (refer to LISA-C2 series Data Sheet [1]) is comparable to that of the LISA-U series modules, but LISA-C200 doesn’t support embedded Smart Temperature Supervisor as LISA-U series modules do.

Check the board layout, since some signal keep-out areas must be implemented on the top layer of the application board, below LISA-U modules, due to GND opening on the module bottom layer.

See the “Hardware migration” section in this appendix for further details.

Check LISA-C200 series software requirements

Check the AT commands supported by LISA-C200 via UART and USB serial interfaces, including Carrier AT commands, Industry standard AT commands and u-blox AT Commands (for the complete list refer to u-blox LISA-C200 Commands Manual [3]).

Check the LISA-C200 firmware upgrade capabilities. Firmware can be upgraded by USB interface, but cannot be upgraded by UART interface.

Check the power-on and reset timings. LISA-U series modules differ from LISA-C200 modules (refer to LISA-C2 series Data Sheet [1]).

Check the difference in the power-on sequence by reviewing the LISA-C2 power management section (see section 1.5) and the LISA-U2 series power management section (see the LISA-U2 series System Integration Manual [4]). Make sure the different power-on sequence complies to the specific module’s requirements.

One important difference between the LISA-C200 and LISA-U series power-on sequence is that for the LISA-C200, the RESET_N pin must be left alone (not driven externally) during the boot-up sequence.

Check the following functionalities that are not supported by LISA-C200:

o V_BCKP supply for Real Time Clock o DSR, DCD and DTR signals of the UART interface o SPI interface o DDC (I2C) interface for the integration with u-blox GPS receivers* o Jamming detection o Smart Temperature Management o Embedded SSL o In-Band modem

*DDC(I2C) interface is supported only by LISA-C200-03S/23S and successive versions

If applicable, check the following functionality that is supported upon request by LISA-C200: o External SIM (RUIM)

Review the “Software migration” section in this appendix.



Page 95 of 103

Software migration Software migration from LISA-U to LISA-C200 modules is a straightforward procedure. Nevertheless, there are some differences to be considered depending on the firmware version. The LISA-C200 module supports AT commands according to carrier (Sprint, Verizon, Aeris, and US Cellular) AT commands, Industry standard (both 3GPP and 3GPP2) AT commands, and u-blox AT commands. Backward compatibility has been maintained as far as possible.

On the UART interface, RI behavior is different for data sessions between LISA-C200 and LISA-U series modules. See section 1.9.2.1 for details.

For the complete list of supported AT commands and their syntax see u-blox LISA-C200 AT Commands Manual [3].

Hardware migration

The LISA-C200 module has been designed with backward compatibility in mind, but some minor differences were unavoidable. These minor differences will however not be relevant for the majority of the LISA-U series designs.

A clean and stable supply is required by LISA-C200, as it is by the LISA-U series: low ripple and low voltage drop must be guaranteed at VCC pins. A power supply circuit properly designed for LISA-U series modules can be directly compatible for LISA-C200, as long as the VCC supply input voltage range is within the relatively tighter LISA-C200 range (refer to LISA-C2 series Data Sheet [1]). Between the two modules, the maximum average current consumption is comparable (refer to LISA-C2 series Data Sheet [1]), and LISA-C200 doesn’t require the high peak of current pulses that are typical of the GSM system.

LISA-C200 doesn’t automatically switch on when applying VCC supply, but the module switches on if the PWR_ON input pin is permanently low when VCC is applied.

The ANT pin of LISA-C200 has 50 Ω nominal characteristic impedance and must be connected to the antenna through a 50 Ω transmission line to allow transmission and reception of radio frequency (RF) signals in the CDMA2000 1xRTT operating bands (800/1900 MHz). The recommendations of the antenna producer for correct installation and deployment (PCB layout and matching circuitry) must be followed.

An antenna circuit properly designed for LISA-U series modules is straightforward compatible for LISA-C200, because LISA-C200 transmits and receives on a subset of frequencies used by LISA-U modules.

LISA-U230 modules provide the RF antenna input for Rx diversity on the pin 74 (named ANT_DIV): it has an impedance of 50 Ω. The same pin on a LISA-C200 module is a reserved pin, which is not internally connected.

LISA-C200 doesn’t provide supply for the Real Time Clock (V_BCKP) on pin 2 as LISA-U series modules do. On LISA-C200 modules, pin 2 is a reserved pin, internally not connected.

The output of the internal voltage regulator that generates the supply for the digital interfaces is available on pin 4 (V_INT) of LISA-C200 modules, as it is on LISA-U series modules.

LISA-C200 provides an internal pull-up on the PWR_ON pin: an open drain / collector driver is recommended.

LISA-C200 power-on timings and sequence are different from LISA-U series (refer to LISA-C2 series Data Sheet [1] and the Power management section in this System Integration Manual, section 1.5).

LISA-C200 modules cannot be switched off by PWR_ON pin, as provided by LISA-U2 modules.

LISA-C200 provides an internal pull-up on the RESET_N pin: an open drain / collector driver is recommended. Driving RESET_N high externally is not permitted

Reset timings are comparable but slightly different from LISA-U series (refer to the LISA-C2 series Data Sheet [1]).



Page 96 of 103

LISA-C200 modules cannot be switched on by RESET_N pin, as provided by LISA-U series modules.

LISA-C200 offers a 5-wire UART interface (TxD, RxD, RTS, CTS and RI lines only): pins 9, 11, and 12 are

Reserved (RSVD) on LISA-C200 that do not provide DSR, DCD, and DTR signals as done so with LISA-U series modules. For LISA-C200, these three Reserved pins are to be left unconnected.

The firmware of LISA-C200 cannot be upgraded by UART interface, but can be upgraded by USB interface.

LISA-C200 doesn’t provide SPI / IPC interface as LISA-U series modules: these related pins 55, 56, 57, 58, and 59 are Reserved (RSVD).

LISA-C200 provides one USB communications device class over a full-speed USB 2.0 interface on the USB_D+ and USB_D- pins instead of multiple USB communications device classes over a high-speed USB 2.0 interface provided by LISA-U series modules. The VUSB_DET input pin on the LISA-U series modules, is provided to sense the VBUS (5 V typical) USB supply provided by the USB host.

LISA-C200 can support an external SIM (RUIM) card by the SIM interface pins. Contact u-blox support if this feature is needed.

LISA-C200 provides an analog audio interface (MIC_N, MIC_P differential input and SPK_P, SPK_N differential output) compatible with LISA-U120 and LISA-U130, but the other LISA-U series modules don’t provide the same functionality on the paired pins 39, 40 and 53, 54.

LISA-C200 provides a PCM digital audio interface (PCM_SYNC, PCM_DO, PCM_CLK, PCM_DI) comparable with the digital audio interface provided by LISA-U120, LISA-U130, LISA-U230 and LISA-U200. Migration from LISA-U series is possible according to external device capabilities.

Pin 52 is Reserved (RSVD) on LISA-C200, while LISA-U230 and LISA-U200 provide a clock output (CODEC_CLK). Leave this pin unconnected on LISA-C200.

LISA-C200 provides GPIOs (GPIO1 to GPIO5) on the pins 20, 21, 23, 24 and 51, as does the LISA-U series, but LISA-U series modules provide additional functionalities.

LISA-C200 operating temperature range (refer to LISA-C2 series Data Sheet [1]) is comparable to LISA-U series modules, but LISA-C200 doesn’t support embedded Smart Temperature Supervisor as LISA-U series modules.

The LISA-C200 is an SMT module and comes in the same compact form factor of LISA-U series, featuring Leadless Chip Carrier (LCC) packaging technology. The signals keep-out area must be implemented on the top layer of the application board, due to GND openings on module bottom layer.

Detailed pin assignment and layout comparisons between LISA-U series and LISA-C200 modules, with remarks for migration, are provided in “Pin-out comparison LISA-U series vs. LISA-C200 module” section of this appendix. For more information regarding the LISA-C200 module’s electrical characteristics, refer to the LISA-C2 series Data Sheet [1].



Page 97 of 103

Pin-out comparison LISA-U series vs. LISA-C200 module

Figure 49: LISA-U1 series, LISA-U2 series and LISA-C200 modules pin assignment (highlighted pin function changes in white)

No LISA-U Name

Description LISA-C200 Name

Description Remarks for Migration

1 GND Ground GND Ground

2 V_BCKP RTC supply I/O RSVD RESERVED pin Internally not connected


4 V_INT Digital I/O supply output

V_INT Digital I/O supply output

No difference: V_INT output = 1.8V typ.

5 RSVD RESERVED pin RSVD RESERVED pin This pin must be connected to GND for LISA-U, which is also permitted to do for LISA-C200




9 DSR UART DSR output RSVD RESERVED pin Tri-stated with internal active pull-up to V_INT Leave unconnected on LISA-C200

10 RI UART RI Output RI UART RI Output Compatible: Circuit 125 (RI) in ITU-T V.24. RI behavior different. Refer to section 1.9.2.1 RI Signal Behavior

11 DCD UART DCD output RSVD RESERVED pin Tri-stated with internal active pull-up to V_INT Leave unconnected on LISA-C200

12 DTR UART DTR input RSVD RESERVED pin Tri-stated with internal active pull-up to V_INT Leave unconnected on LISA-C200

13 RTS UART RTS input RTS UART RTS input No difference: Circuit 105 (RTS) in ITU-T V.24.

14 CTS UART CTS output CTS UART CTS output No difference: Circuit 105 (RTS) in ITU-T V.24.

15 TXD UART data input TXD UART data input No difference: Circuit 105 (RTS) in ITU-T V.24.

16 RXD UART data output RXD UART data output No difference: Circuit 105 (RTS) in ITU-T V.24.


18 VUSB_DET USB detect input VUSB_DET USB detect input No difference: VBUS (5V typ) USB supply input.

19 PWR_ON Power-on input PWR_ON Power-on input Internal pull-up. Open drain / collector driver recommended. Switch-on: PWR_ON low for T > 300 ms. Switch-off: not supported by PWR_ON

20 GPIO1 GPIO GPIO1 GPIO By default, tri-stated with internal active pull-down.



Page 98 of 103

No LISA-U Name




22 RESET_N External reset input RESET_N External reset input

Internal pull-up. Open drain / collector driver recommended. Reset: RESET_N low for T > 300 ms. Switch-on: not supported by RESET_N




26 USB_D- USB Data Line D- USB_D- USB Data Line D- Full-speed USB 2.0. One USB CDC is available. Pull-up/down & series resistors provided internally.

27 USB_D+ USB Data Line D+ USB_D+ USB Data Line D+ Full-speed USB 2.0. One USB CDC is available. Pull-up/down & series resistors provided internally.












39 MIC_N / RSVD

Analog audio in (-) / RESERVED pin (LISA-U1 series)

MIC_N Differential analog audio input (-)

Compatible with LISA-U120, LISA-U130.

I2S1_RXD/ GPIO6

2nd I2C data input / GPIO (LISA-U2 series)

40 MIC_P/ RSVD

Differential analog audio input (+)

MIC_P Differential analog audio input (+)


I2S1_TXD / GPIO7

RESERVED pin

41 I2S_WA / RSVD

I2S word alignment/ RESERVED pin

PCM_SYNC

PCM Digital Sync Migration from LISA-U120, LISA-U130, LISA-U2x0-01 is possible according to external device capabilities.

42 I2S_TXD / RSVD

I2S data output/ RESERVED pin

PCM_DO PCM Data Output Migration from LISA-U120, LISA-U130, LISA-U2x0-01 is possible according to external device capabilities.

43 I2S_CLK / RSVD

I2S clock/ RESERVED pin

PCM_CLK PCM Clock Output Migration from LISA-U120, LISA-U130, LISA-U2x0-01 is possible according to external device capabilities.

44 I2S_RXD / RSVD

I2S data input/ RESERVED pin

PCM_DI PCM Data Input Migration from LISA-U120, LISA-U130, LISA-U2x0-01 is possible according to external device capabilities.

45 SCL I2C bus clock line SCL I2C bus clock line On LISA-C200 the DDC I2C interface is exclusively used to control an external u-blox GNSS receiver*

.

46 SDA I2C bus data line SDA I2C bus clock line On LISA-C200 the DDC I2C interface is exclusively used to control an external u-blox GNSS receiver*

.

47 SIM_CLK SIM clock SIM_CLK SIM clock No difference: Clock for external SIM (RUIM) card.

48 SIM_IO SIM data SIM_IO SIM data No difference: Internal pull-up resistor to VSIM.

49 SIM_RST SIM reset SIM_RST SIM reset No difference: Reset for external SIM (RUIM) card.

50 VSIM SIM supply output VSIM SIM supply output No difference: VSIM output = 1.80 V or 2.85 V typ.


52 CODEC_CLK / RSVD

Clock output / RESERVED pin

RSVD RESERVED pin Leave unconnected on LISA-C200.

53 SPK_P / RSVD

Differential analog audio output (+) (LISA-U1 series)

SPK_P Differential analog audio output (+)




Page 99 of 103

No LISA-U Name



I2S1_CLK / GPIO8

2nd I2C clock I/O / GPIO (LISA-U2 series)

54 SPK_N Differential analog audio output (-) (LISA-U1 series)

SPK_N Differential analog audio output (-)


I2S1_WA / GPIO9

2nd I2C word align. I/O / GPIO (LISA-U2 series)

55 SPI_SCLK / GPIO10

SPI Serial Clock Input / GPIO

RSVD RESERVED pin Tri-stated with internal active pull-down

56 SPI_MOSI / GPIO11

SPI Data Line Input / GPIO

RSVD RESERVED pin Tri-stated with internal active pull-up to V_INT

57 SPI_MISO / GPIO13

SPI Data Line Output / GPIO

RSVD RESERVED pin Tri-stated with internal active pull-up to V_INT

58 SPI_SRDY / GPIO14

SPI Slave Ready Output / GPIO


59 SPI_MRDY / GPIO15

SPI Master Ready Input / GPIO



61 VCC Module supply input

VCC Module supply input

LISA-C200 VCC range = 3.4 V to 4.2 V Switch on if PWR_ON is low when VCC is applied



LISA-C200 VCC range = 3.4 V to 4.2 V Switch on if PWR_ON is low when VCC is applied



VCC range = 3.4 V to 4.2 V Switch on if PWR_ON is low when VCC is applied

64 GND Ground GND N/A




68 ANT RF input/output ANT RF input/output 50 Ω nominal impedance






74 ANT_DIV / RSVD

RF input for diversity / RESERVED pin

RSVD N/A Internally not connected



Table 37: Pinout comparison: LISA-U series vs. LISA-C200 module

*DDC(I2C) interface is supported only by LISA-C200-03S/23S and successive versions

Layout comparison: LISA-U series vs. LISA-C200 module

An exposed signal keep-out area must be implemented on the top layer of the application board, below the LISA series modules, due to GND opening on the bottom layer of the module, as described in Figure 50 and Figure 51.



Page 100 of 103

Figure 50: Signals keep-out area on the top layer of the application board, below LISA-U series modules

33.2

mm

11.85 mm

22.4 mm

5.3 mm 5.25 mm

1.4 mm1.0 mmPIN 1

LISA-C2 bottom side (through module view)

Exposed GND on LISA-C2 module bottom layer

Signals keep-out area on application board

Figure 51: Signals keep-out areas on the top layer of the application board, below LISA-C200 module


UBX-13000620 - R21 Early Production Information Related documents

Page 101 of 103

Related documents [1] u-blox LISA-C2 series Data Sheet, Docu No UBX-13000623

[2] u-blox FW75-C200 Data Sheet, Docu No CDMA-1X-11006

[3] u-blox LISA-C2 series and FW75-C200 AT Commands Manual, Docu No UBX-13000621

[4] u-blox LISA-U2 series System Integration Manual, Docu No UBX-13001118

[5] ITU-T Recommendation V.24, 02-2000. List of definitions for interchange circuits between data terminal equipment (DTE) and data circuit-terminating equipment (DCE). http://www.itu.int/rec/T-REC-V.24-200002-I/en

[6] 3GPP TS 27.007 - AT command set for User Equipment (UE) (Release 1999)

[7] 3GPP TS 27.005 - Use of Data Terminal Equipment - Data Circuit terminating; Equipment (DTE - DCE) interface for Short Message Service (SMS) and Cell Broadcast Service (CBS) (Release 1999)

[8] 3GPP TS 27.010 - Terminal Equipment to User Equipment (TE-UE) multiplexer protocol (Release 1999)

[9] 3GPP TS 23.060 - General Packet Radio Service (GPRS); Service description; Stage 2 (Release 1999)

[10] Universal Serial Bus Revision 2.0 specification, http://www.usb.org/developers/docs/

[11] I2C-Bus Specification Version 2.1 Philips Semiconductors (January 2000), http://www.nxp.com/acrobat_download/literature/9398/39340011_21.pdf

[12] GPS Implementation Application Note, Docu No GSM.G1-CS-09007

[13] CENELEC EN 61000-4-2 (2001): “Electromagnetic compatibility (EMC) - Part 4-2: Testing and measurement techniques - Electrostatic discharge immunity test”.

[14] ETSI EN 301 489-1 V1.8.1: “Electromagnetic compatibility and Radio spectrum Matters (ERM); ElectroMagnetic Compatibility (EMC) standard for radio equipment and services; Part 1: Common technical requirements”

[15] ETSI EN 301 489-7 V1.3.1 “Electromagnetic compatibility and Radio spectrum Matters (ERM); ElectroMagnetic Compatibility (EMC) standard for radio equipment and services; Part 7: Specific conditions for mobile and portable radio and ancillary equipment of digital cellular radio telecommunications systems (GSM and DCS)“

[16] Sprint OMA-DM Client Functional Requirements Version 2.54

[17] LISA-C200 & FW75-C200 AT commands examples u-blox CDMA 1xRTT cellular modules Application Note, Docu No CDMA-CS-12000

[18] GNSS Implementation Application Note, Docu No UBX-13001849

[19] C200_ATComManual, Docu No UBX-13000621

Some of the above documents can be downloaded from u-blox web-site (http://www.u-blox.com).

http://www.itu.int/rec/T-REC-V.24-200002-I/en

http://www.usb.org/developers/docs/

http://www.nxp.com/acrobat_download/literature/9398/39340011_21.pdf



UBX-13000620 - R21 Early Production Information Revision history

Page 102 of 103

Revision history Revision Date Name Status / Comments

- 24-Nov-2011 rcam Initial Release

1 23-May-2012 smoi Updated product names

2 9-Jul-2012 smoi Unification of SIM nomenclature

3 20-Aug-2012 smoi Document status change

A 12-Dec-2012 smoi Added section 3.4 (OMA device management) and 4 (Handling and soldering)

A1 08-Jan-2013 rcam Added LISA-C200 related sections 1.8 (Audio Interface), 2.3.2 (Footprint and past mask) and 3.4 (FTP)

A2 25-Feb-2013 rcam C200-x2S-01 version introduction

A3 30-May-2013 rcam OMA-DM guideline and best practice added

References to Aeris carrier added

B 03-Jul-2013 rcam FW75- product introduction; New features added: GNSS integration and SIM (R-UIM) support

UART application circuit section updated: Recommended pin status during module power-down, reset and power-on sequence; Interface with a 2.8V host processor

LISA-C200/FW75-C200 USB VID and PID corrected

Last revision with document number CDMA-2X-11004

R10 31-Jan-2014 rcam Added precautions to avoid voltage back-feeding to digital interfaces

Power-on/off and reset recommended sequences added; +UTEST added

R11 25-Feb-2014 clee Removed info in section 1.6.1.2 about PWR_ON pin not tolerable to battery voltage

Added Power-on sequence using VCC method added (section 1.6.4.2)

R12 05-Mar-2014 sses/clee Changed Digital (PCM) Audio interface section to clarify I2S interface supports PCM data format; Added Appendix B: Migration from LISA-U to LISA-C200; Added 2.4.3 Antenna detection functionality; Added details on RI behavior difference during data session, between LISA-C200 and GSM/UMTS modules such as LISA-U, SARA, and LEON

R13 26-Jun-2014 pafe Removed references to FW75-D200

R14 02-Sep-2014 clee Added power-on precautions to section 1.6.4.1 and 1.6.4.3, by checking VCC and V_INT pin voltage is 0V before applying VCC.

Added suggested ESD high pass filter protection circuit regarding ANT pin for any need of higher ESD protection (section 2.5.3)

R15 02-Oct-2014 clee Added 04S/24S features: FOAT for Verizon; Network Indicator Status; CellLocateTM ; Audio Playback; US Cellular support for both (23S and 24S)

R16 06-Feb-2015 clee Added LISA-C210: Document status changed to Objective Specification

R17 14-Nov-2015 clee Updated recommended Power-on, Power-off and Reset procedures in section 1.6.4

Updated UART / USB and power saving sections 1.9.2.2 / 1.9.3.1

Added 3.5.1 Factory NAM settings

Document status changed to Production Information

R18 10-Feb-2016 clee Updated the recommended voltage translator for I2C-bus signals.

Added more details on Migration from LISA-U to LISA-C200

R19 11-May-2016 clee/pafe Added 1.5.2.1 Handing sudden momentary power loss

Improved details on not permitting RESET_N being driven high externally.

R20 26-Sept-2016 clee Added 1.6.5 Key points to system functions

Updated Power-on, Power-off and Reset procedures in section 1.6.4

R21 08-Aug-2017 smoi LISA-C210 removed


UBX-13000620 - R21 Early Production Information Contact

Page 103 of 103

Contact For complete contact information visit us at www.u-blox.com

u-blox Offices

North, Central and South America

u-blox America, Inc.

Phone: +1 703 483 3180 E-mail: [email protected]

Regional Office West Coast:


Technical Support:


Headquarters Europe, Middle East, Africa

u-blox AG

Phone: +41 44 722 74 44 E-mail: [email protected] Support: support @u-blox.com

Asia, Australia, Pacific

u-blox Singapore Pte. Ltd.

Phone: +65 6734 3811 E-mail: [email protected] Support: [email protected]

Regional Office Australia:

Phone: +61 2 8448 2016 E-mail: [email protected] Support: [email protected]

Regional Office China (Beijing):

Phone: +86 10 68 133 545 E-mail: [email protected] Support: [email protected]

Regional Office China (Chongqing):


Regional Office China (Shanghai):


Regional Office China (Shenzhen):


Regional Office India:


Regional Office Japan (Osaka):


Regional Office Japan (Tokyo):


Regional Office Korea:


Regional Office Taiwan:



mailto:[email protected]

mailto:[email protected]

mailto:support%[email protected]

Documents

LISA-C2 series and FW75-C200