IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 8, AUGUST 2005 1923

Linearity of Active Pixel Charge Injection Devices

D. A. Baiko and J. M. Swab

Abstract—Charge injection devices (CID), currently used for a variety ofimaging applications, are discussed. The voltage response of an active CIDpixel is analyzed. The linearity of the photoresponse is assessed in destruc-tive and nondestructive read-out modes of operation. It is shown that undervarious conditions, CID response curves can exhibit dual-slope behaviorwith a steeper initial slope. If undesirable, this behavior can be avoided byadjusting various geometrical parameters of the pixel as well as the oper-ating voltages. The theoretical analysis is in good agreement with experi-mental results.

Index Terms—Active pixel, charge injection device (CID), pixel linearity.

I. INTRODUCTION

Charge injection devices (CIDs) form a class of semiconductorimaging devices alternative to charge-coupled devices (CCDs) andphotodiode-based CMOS imagers. The basic description of a CIDis given in [1]–[3] and references therein. The main advantages ofCIDs include random-access for read-out and clear, nondestructiveread capability, high dynamic range, UV sensitivity, and radiationhardness. The combination of these properties makes a CID imager anexcellent choice for scientific, industrial, machine-vision, and medicalapplications.A CID pixel is built on low-doped epitaxial material, which resides

on top of heavily doped substrate. Each pixel has two photogates anda means of transferring charge between them. During the integrationstage, the photons are absorbed by the epi layer in the areas free ofphotogates. The photogenerated minority carriers diffuse through theepi and are collected by the photogates biased into deep depletion. Inthe read-out mode, considered in this letter, all the photocharge is trans-ferred to one of the photogates (sense gate), which is then reset and leftfloating. After that, by manipulating voltage of the second gate, the mo-bile charge is removed from the floating gate and its voltage change issensed.The charge clear can be accomplished in various ways. Tradition-

ally, both photogates are brought to the epi potential and the minoritycarriers are pushed out (injected) into the epi layer, where they can re-combine or be absorbed by the epi-substrate junction. In this case theepi and the substrate must have different type of doping. Another ap-proach (considered in this paper) consists of removing the photochargeinto a heavily doped drain located at the front surface of the imager. Thechannel between this drain and the photogates is controlled by anothergate. This approach is also suitable for device back-thinning.Traditionally, CIDs had a passive pixel structure, where all the

floating gates in a row were connected to a common bus and thephotosignal to be sensed developed across a large “row” capacitance.Various types of read-out used in this case were discussed in [4]–[9].In general, passive pixel structure resulted in a rather high read-outnoise. However, recently active pixel CIDs were introduced [10]. In

Manuscript received January 24, 2005; revised May 23, 2005. The review ofthis brief was arranged by Editor J. Hynecek.D. A. Baiko is with Thermo CIDTEC, Liverpool, NY 13088 USA (e-mail:

denis.baiko@thermo.com). He is also with Department of Microelectronics,Rochester Institute of Technology, Rochester, NY 14620 USA, and withA.F. Ioffe Physical Technical Institute, St. Petersburg 194021, Russia.J. M. Swab is an independent consultant with Thermo CIDTEC, Liverpool,

NY 13088 USA.Digital Object Identifier 10.1109/TED.2005.852734

Fig. 1. Typical configuration of an active CID pixel.

this case the floating gate is connected only to the gate of a source fol-lower placed in each pixel. Along with the source follower each pixelcontains reset and select switches. These three transistors are placedin a well of the same doping type as the epi layer. This configurationresults in a significant reduction of the CID read-out noise. The aim ofthe present paper is to analyze the voltage response of such an activeCID pixel.The models for destructive and nondestructive active CID pixel

read-out are developed in Sections II and III, respectively. The theo-retical findings are illustrated by raw experimental data obtained froma test chip fabricated in 0.18 �m process. The test chip containedover 2400 active pixel structures with different geometries. Section IVdiscusses certain problems for nondestructive read-out stemming frominadequate coupling of the photogates.

II. DESTRUCTIVE READ-OUT

The typical configuration of an active CID pixel is shown in Fig. 1.For the sake of discussion let us assume that the epitaxial layer is ofp-type. The polysilicon sense photogate is connected to the gate of asource follower (SF) and to the source of a reset switch. The source ofthe SF is connected to the output bus through a select switch. Anotherpolysilicon gate (storage gate) is located in close proximity to the sensegate (in a single poly process) and is driven by a pulsed source. The n+

diffusion lateral drain (LD), connected to a fixed positive dc voltage,provides means of removing photogenerated electrons from the sensegate. Finally, another gate called a lateral drain gate (LDG) controls thechannel between the sense gate and the LD.The capacitance C represents a lumped linear capacitance that acts

as if it was placed between the sense node and a dc power supply. Inparticular, it includes various parasitic capacitors (such as gate/draincapacitance of the SF) as well as the gate/source capacitance of the SFmultiplied by 1� , where is the gain of the SF.Consider the simplest operation of a CID pixel with the storage gate

set to 0 (same as epi) at all times. This mode of operation is knownas destructive read-out (DRO). During the integration the LDG is atVskim = 0, while the sense gate is kept at a positive voltage Vi. Forsimplicity of notation, from here on we assume that the gate flat-bandvoltage is 0. It is straightforward to include a realistic flat-band voltagein the equations below.During the read-out stage the select switch is turned on, the reset

switch is turned off, and the first sample is taken on the output bus. Thenthe LDG is brought to a positive voltage Vinject, photogenerated elec-trons are drained into the LD, and the LDG is brought back to Vskim.After that the second sample is taken on the output bus. The differencebetween the two samples represents the photosignal, Vs.

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1924 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 8, AUGUST 2005

When the charge drains from the sense gate the depletion regionunderneath it widens, and the surface potential becomes more positive.For any given Vinject, there exists such a value of the sense surfacepotential �j , at which no more charge can be drained out. Dependingon the initial amount of the photocharge, the electrons can either bedrained out completely before �j is reached, or the potential reaches�j while some fraction of charge is left under the sense gate. Both thesecases can occur before the sense gate saturates.Here, we analyze the two cases, described above, quantitatively. In

the deep depletion regime of operation the gate voltage V , the surfacepotential �, the absolute amount of the mobile charge under the gateQ, and the depletion widthw are related to each other by the followingequations:

V =eNAw

2

2�Si+

tox�ox

eNAw +Q

S(1)

� =eNAw

2

2�Si(2)

where S is the gate area, tox is the gate oxide thickness, NA is thesubstrate doping density, e is the elementary charge, while �Si and �oxare dielectric constants of silicon and silicon oxide, respectively. At theend of the integration stage V = Vi; Q = Qi, and the depletion widthwi can be found as a solution of the quadratic equation (1).If the electronswere removed completely, the final sense gate voltage

Vf and the depletion width wf can be found from (1) with Q set to 0,complemented by the charge conservation at the sense node

Vf =eNAw

2f

2�Si+

tox�ox

eNAwf (3)

eNAwfS + CVf = eNAwiS + CVi +Qi: (4)

In the other case,wf = wj � 2�Si�j=(eNA). The two unknownsbecome Vf and the final charge under the sense gate Qf . Hence, weobtain

Vf = �j +tox�ox

eNAwj +Qf

S(5)

eNAwjS + CVf +Qf = eNAwiS + CVi +Qi: (6)

Consider the slope of the response curve in these two cases. Letus denote derivatives with respect to Qi by a prime. We need to findV 0

f at Qi = 0 and V 0

f at Qf = 0 in the first and second regime,respectively. First of all, we note that according to (1), eNAw

0

iS =�(CD kCox)=Cox, where Cox = �oxS=tox is the sense gate oxidecapacitance, and CD = �SiS=wi is its initial depletion capacitance.1

Differentiating (3) and (4) and substituting wf = wi we arrive at

V 0

f(Qi = 0) =1� (CD kCox)=Cox

C + CD kCox

�1

C + CD

(7)

where the last simplification is based on the fact that typically CD �Cox. In the second case an analogous derivation yields

V 0

f(Qf = 0) =1� (CD kCox)=Cox

C + Cox

�1

C + Cox

: (8)

Therefore, the response curve of the CID pixel (i.e., dependence of thevoltage signal on the photocharge) has a dual-slope characteristic withthe knee point determined by the simultaneous solution of (1), (5), and(6) with Qf = 0.

1a k b � ab=(a + b):

Fig. 2. Experimental signal voltage of a CID (in ADUs) as a function of anumber of red LED flashes during the integration. Solid curve correspondsto V = 2 V, V = 5 V, S = 13 �m , and V = 0. Long-dashed,dot-dashed, dotted, and short-dashed curves correspond to V = 2:5 V,V = 4 V, S = 18 �m , and V = 1:1 V, respectively.

Now consider what happens when the sense gate saturates. From (1)it follows that the saturation occurs at wi = 0 andQi = CoxVi. Using(4) we can see that

Vs =1

C(CoxVi � eNAwfS): (9)

The second term in the parenthesis is a small correction that can beexpressed via Vi. More important is that in this case the saturated signalis proportional to the initial voltage Vi.In the second case (6) can be rewritten as

(C + Cox)Vf � Cox�j = eNAwiS + CVi +Qi (10)

and hence at saturation

Vs =Cox�jC + Cox

: (11)

Therefore, in the latter case the saturated signal is completely deter-mined by the LDG voltage, but not by the amount of charge at satura-tion nor the initial sense gate voltage.Fig. 2 shows the experimental signal voltage of a CID operated in the

regime described above as a function of a number of red LED flashesduring the integration (proportional to the amount of photogeneratedelectrons collected by the sense gate). The solid curve corresponds toVi = 2V, Vinject = 5V, S = 13 �m2, and Vskim = 0. One can clearlyobserve the dual-slope characteristic. The saturation occurs at 60 000analog-to-digital converter units (ADUs) of signal for 26 LED flashes.The long-dashed curve corresponds to the same parameters except forVi = 2:5 V. In this case, the saturation occurs at 31 LED flashes forthe same signal level in agreement with (11). The difference in the firstslope between the solid and the long-dashed curves is most likely to beattributed to the quantum efficiency effect: higher Vi improves chargecollection at the integration stage. The dot-dashed curve corresponds toVinject = 4V,which reduces�j and the respective saturation signal [cf.(11)] but not the saturation charge as compared to the solid curve. Thedotted curve corresponds to increased sense gate area S = 18 �m2 and

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 8, AUGUST 2005 1925

illustrates dependence (8) of the second slope on Cox. It also saturatesat higher photocharge corresponding to 36 LED flashes. Finally, shortdashes illustrate the dependence on Vskim. The LDG voltage is keptat 1.1 V at the integration stage. In this way the excess photocharge isskimmed off by the LD and the second slope disappears.

III. NONDESTRUCTIVE- READ-OUT

One of the big advantages of CIDs is a possibility to add the second(storage) photogate. Then the photocharge can be transferred betweenthe sense and storage gates and thus read out multiple times. This non-destructive read-out (NDRO) allows one to 1) improve sensitivity in theregime of weak signal (e.g., N NDROs result in

pN times reduction

in read-out noise); and 2) extend the upper boundary of the dynamicrange by being able to selectively read and drain pixels that receivehigher photon flux (“hot” pixels) instead of servicing the entire array.The latter might take considerably more time and result in the satura-tion of the “hot” pixels.In the NDRO regime, the pixel is operated as follows. During the

integration the storage gate is kept at 0. At the read-out stage the firstsample is taken as described in Section II, then storage gate is broughtup to a positive voltage Vt, photocharge transfers from sense to storageand then the second sample is taken. The photosignal is again given bythe difference2 of the two samples.The pixel response depends on whether or not the charge is trans-

ferred to the storage gate completely. As the electrons move from senseto storage, the surface potential of the sense increases while that of thestorage decreases. If the amount of photocharge is relatively large thesurface potentials of the two gates become equal and the charge transferstops.In the case of full charge transfer the pixel response is described by

the same set of equations (3) and (4). In the other case, (5) and (6) mustbe complemented by a self-consistent expression for �j

Vt = �j +tox�ox

eNAwj +Qi �Qf

St(12)

where St is the area of the storage gate. This equation is based on thefact that in this case storage and sense surface potentials and depletionwidths must be equal.The slope of the response in the case of the full charge transfer is

given by (7). In the second case the situation is now more complex.The slope in question reads

V 0

f(Qf = 0) = 1� CD kCox

Cox

� Cox(Cox kCt)

Ct(Cox + CDj)

� C + CDj kCox +Cox(Cox kCt)

Cox + CDj

�1

: (13)

In this case, Ct = �oxSt=tox is the storage gate oxide capacitance, andCDj = �SiS=wj is the final depletion capacitance of the sense gate.IfCt !1, (13) reduces to (8). IfCD; CDj � Cox, (13) simplifies

to

V 0

f (Qf = 0) � (C + CDj) kCox kCt

Cox(C + CDj): (14)

The important property of (13) and (14) is the dependence of the slopeonCt. In the case of the complete charge transfer (initial slope regime)such a dependence is absent.Let us determine the point of the onset of the second slope (i.e., find

maximum Qi at which Qf is still 0) and provide practical guidelines

2In what follows we neglect direct capacitive coupling between storage andsense. It can be taken out by dark frame subtraction or by having a transfer gatebetween storage and sense.

Fig. 3. Experimental voltage response of a CID operated in the NDRO regime.Solid curve corresponds to S = 8:6 �m and V = 5 V. Dash-dotted anddotted curves show responses for S = 2:3 �m and V = 4 V, respectively.Dashed curve corresponds to the original pixel withS andV adjusted accordingto (15).

for the dual gate CID pixel design. From (5) and (12) we see that atQf = 0; Vt � Vf = Qi=Ct. Based on (7) and assuming that CD �C; Vf can be approximated as Vi+Qi=C . Therefore, the knee point ofthe response curve occurs approximately at Qi = (C kCt)(Vt � Vi).For a practical design this condition should occur simultaneously withthe sense gate saturation Qi = CoxVi. Combining these expressionswe arrive at the final result:

Cox

C kCt

=Vt � ViVi

: (15)

Given Vt and Vi, (15) allows one to size the gates in such a way thatincomplete charge transfer never takes place.The NDRO regime of CID operation is illustrated in Fig. 3. The solid

curve corresponds to the baseline pixel with St = 8:6 �m2 operatedat Vt = 5 V. One can observe a pronounced second slope indicatingincomplete charge transfer. The dash-dotted curve shows response fora similar pixel with a smaller storage gate oxide capacitance, St =

2:3 �m2. The onset of the second slope requires less photocharge. Inaccordance with (14) the second slope is less steep. This is in contrastwith the behavior that one would expect from direct charge sharingbetween the sense and storage gates. In the latter case, the slope woulddecrease as Ct increases approaching 0 in the limit of infinite Ct. Thedotted curve corresponds to the baseline pixel operated at Vt = 4 V. Inthis case, the incomplete charge transfer starts occurring at an earlierstage than for Vt = 5 V. The second slope is the same as at Vt = 5

V (solid curve), and so is the saturation charge. Finally, the dashedcurve shows the original pixel adjusted according to the guidelines putforward by (15). The sense gate area is decreased by about 25% andinitial voltage Vi is slightly reduced. The resulting response curve isoptimized formaximum linear range and shows no dual-slope behavior.

IV. IMPORTANCE OF THE POTENTIAL BARRIER BETWEENSTORAGE AND SENSE GATES

In the previous section, we assumed that the storage and sense gatesurface potentials were the only factors governing the charge transfer.

1926 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 8, AUGUST 2005

Fig. 4. Experimental voltage response for the NDRO (Section III) type of CIDoperation for proximity-coupled (dashed) and n-coupled (solid) structures.

The real situation is more complex because the coupling between thesurface layers under the gates is not ideal. The simplest approach tothis problem is to locate the gates as close to each other as possible fora given process. In this proximity-coupled structure the charge transferrelies on the fringing fields provided by the poly gates. Let us note thatfor any modern process the minimum allowed spacing is still muchlarger than the gate oxide thickness. Extrapolating from the case of verylarge spacing, one can easily see, that if the gates have the same voltageand no charge under them, there will be a potential barrier between thegates. The properties of similar barriers were studied in [11]. The heightof this barrier depends critically on the width of the spacing.When the storage gate is at a somewhat higher voltage than the sense,

as is the case during the charge transfer, the barrier disappears. How-ever, as charge transfers, the potential of the sense gate rapidly increases(being determined by a relatively small value of C), and the barrierappears again. If by this point not all of the charge is transferred thedual-slope scenario takes place again.The coupling can be enhanced (the barrier removed) by introducing a

transfer gate made of the second poly layer that is located in the spacingand overlaps the sense and storage gates. Another way to remove thebarrier is to introduce n-type doping in the spacing. In Fig. 4 we com-pare proximity-coupled and n-coupled structures. The solid and dashedcurves correspond to pixels with doped and undoped spacings, respec-tively. The pixels are identical in all other respects. One can clearly seethe influence of the barrier on the response curves.

V. CONCLUSION

We have considered the linearity of active pixel CIDs. It was shownthat the response curve can exhibit a dual-slope characteristic. Thedual slope is an indication of incomplete removal of the photochargefrom the sense gate due to the voltage increase of the latter. The dualslope can occur when the charge is transferred to either the lateral drain(DRO) or the storage gate (for the NDRO purpose). In the latter casethe second slope increases with increase of the storage gate size in con-trast with the charge sharing scenario. In the limit of very big storagegate the second slope approaches that for the DRO regime.The second slope can be removed by careful gate sizing, capacitorC

sizing, adjustment of the gate voltages, or by skimming off the excess

charge during the integration. However, some applications may findthe dual slopes useful in that a steep first slope provides low light levelsensitivity while the second slope can accommodate highlights.The linearity curve of CID in NDRO regime is very sensitive to the

strength of the coupling between the sense and storage gates. A po-tential barrier between the two gates can give rise to the second slopeeven if all the other parameters related to the pixel and its operation arefixed. This makes a CID pixel with two photogates an excellent tool tostudy the charge transfer phenomena.

ACKNOWLEDGMENT

The authors wish to thank S. Bhaskaran, J. Capogreco, J. Carbone,A. Chapman, R. Gorczynski, G. Lungu, M. Pilon, S. Van Gorden, andthe rest of the Thermo CIDTEC engineering department for valuablediscussions and help.

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