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Circuit Summary Introduction Switching Sequences Half-unary Digital algorithm Simulation Result Layout Objective Mismatch Current-steering DAC Nonlinearity Shaiful Nizam Mohyar and Haruo Kobayashi Division of Electronics & Informatics, Graduate School of Science & Technology, Gunma University Kiryu, Gunma 376-8515 Japan, email:[email protected] P85 1 st International Symposium of Gunma University Medical Innovation and 6 th International Conference on Advanced MicroDevice Engineering (GUMI&AMDE 2014) Linearity Improvement Algorithm for Current-Steering DAC Based on 3-Stage Sorting of Half-Unary Current Sources

Linearity Improvement Algorithm for Current …...RAM to Counter Circuitry LUT Decoder MSB Array Ideal case Current cell Mismatch case Current cell Code Code Algorithm New Mismatch

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Page 1: Linearity Improvement Algorithm for Current …...RAM to Counter Circuitry LUT Decoder MSB Array Ideal case Current cell Mismatch case Current cell Code Code Algorithm New Mismatch

Circuit

Summary

Introduction

Switching Sequences

Half-unary Digital algorithm

Simulation Result

Layout

Objective

Mismatch

Current-steering DAC

Nonlinearity

Shaiful Nizam Mohyar and Haruo Kobayashi

Division of Electronics & Informatics, Graduate School of Science & Technology, Gunma University

Kiryu, Gunma 376-8515 Japan, email:[email protected]

P851st International Symposium of Gunma University Medical Innovation and

6th International Conference on Advanced Micro‐Device Engineering

(GUMI&AMDE 2014)

Linearity Improvement Algorithm for Current-Steering DAC

Based on 3-Stage Sorting of Half-Unary Current Sources