Linear Integrated Circuits Unit2 Raghudathesh VTU

8/20/2019 Linear Integrated Circuits Unit2 Raghudathesh VTU

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LINEAR INTEGRATED CIRCUITS (VTU) - 10EC46

UNIT - 2

Op-Amps as AC Amplifiers: Capacitor coupled Voltage Follower, High input impedance

Capacitor coupled Voltage Follower, Capacitor coupled Non-inverting Amplifiers, High input

impedance - Capacitor coupled Non-inverting Amplifiers, Capacitor coupled Inverting

amplifiers, setting the upper cut-off frequency, Capacitor coupled Difference amplifier, Use of a

single polarity power supply. 7 Hours

TEXT BOOKS:

1. “Operational Amplifiers and Linear IC’s”, David A. Bell, 2nd

edition, PHI/Pearson, 2004.

2. “Linear Integrated Circuits”, D. Roy Choudhury and Shail B. Jain, 2nd

edition, Reprint 2006,

New Age International.

Special Thanks To:

Faculty (Chronological):

Students:

BY:

RAGHUDATHESH G P

Asst Prof

ECE Dept, GMIT

Davangere 577004

Cell: +917411459249

Mail: [email protected]

Website: raghudathesh.weebly.com

Quotes:

A warm smile is the universal language of kindness.

It always seems impossible unitll its done.Everyone thinks of changing the nation; but no one thinks of changing himself The first step towards change is awareness. The second step is acceptance.Trust, but verify.

Op-Amps-AC Amplifiers RAGHUDATHESH G P Asst Professor

Department of ECE raghudathesh.weebly.com Page No - 1

mailto:[email protected]:[email protected]:[email protected]:[email protected]


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Introduction:

Op-Amp can be used as both AC and DC Amplifiers.

The Op-Amp circuit which is used to amplifying AC signals are called as AC amplifiers.

Operational amplifier circuits can readily be capacitor coupled at the input and output so

that they operate only as ac amplifiers.

Capacitors must not be allowed to interrupt the bias current paths to the op-amp

input terminals.

While designing such AC amplifiers, the low and high frequency limits must be taken

care of.

Since capacitors have their highest impedances at the lowest signal frequency, all

coupling capacitor values must be calculated at the desired lower cutoff frequency

(f 1).

The impedance of coupling capacitors at (f 1) is usually determined as one-tenth of the

resistance in series with them.

The largest capacitor in the circuit is normally selected to determine (f 1) and in this case

the capacitive impedance is made equal to the series-connected resistance.

Ex. Application: Audio input which has well defined range of frequencies and any signal

outside this range must be rejected.

Impedance equalization at the two inputs, is not essential as it will only result in DC

shift at the output.

All AC and DC amplifiers have a RC lowpass or high pass circuits at the input and

output.

Figure 2.1: Response of Highpass and Lowpass Filter




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Capacitor Coupled Voltage Follower:

The voltage follower is a unity gain buffer amplifier.

An AC Coupled voltage follower is as shown in the figure 2.2 below. The amplifier

couples both input and output through high pass filter.

Figure 2.2: Capacitor Coupled Voltage Follower

For AC amplifiers it is necessary that the input DC bias currents should not interrupted

by the coupling capacitors at the inputs hence, resistance R 1 is connected between non-

inverting terminal and the ground which carries the input bias current IB.

A resistor equal to R 1 might he included in series with the inverting terminal to equalize

the IBR B voltage drop and thus minimize the out-put offset voltage. However, in the case

of a circuit with its output capacitor-coupled, small DC offset output voltages are

unimportant because they are blocked by the capacitor.

Design:

Involves calculations of R 1, C1 and C2.

To ensure minimum power dissipation and minimum current drawn from the

power supply, larger value resistors are used and is given by,

------- (1) The input impedance of non-inverting voltage follower is very very large which is

in parallel with the resistance R 1, hence circuit input impedance Zin is given as,




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------- (2) Here Since is very very large which is in parallel with the resistance R 1.Thus, parallel combination is smaller than the smallest than R 1 and is almost equal to

R 1.

------- (3)

Load resistor R L normally has a lower resistance than R 1.

Capacitor value is inversely proportional to the resistance in series with it, and C2

is selected usually larger than C1.

At the circuit low 3 dB frequency (f l), the impedance of C1 should be muchsmaller than Zin as the signal voltage gets divide across XC1 and Zin as shown

below.

Figure 2.3: signal voltage gets divide across XC1 and Zin

C1 is calculated as,

------ (4)

From equation (3) and expanding XC1




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--------- (5)

As shown in figure 2.4 below, the circuit output voltage Vo is divided across XC2

and R L to give the load voltage VL.

Figure 2.3: output voltage gets divide across XC2 and R L

The equation for VL is

When XC2 = R L, then

Apply log on both sides we get,




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------- (6)

The circuit low 3 dB frequency (f 1) occurs when XC2 = R L. Therefore, C2 is

calculated from

----------- (7)

The above design approach gives the smallest possible capacitor values. When

selecting standard value components, the next larger standard size should be

chosen to give capacitive impedances slightly smaller than calculated.




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High Zin Capacitor-Coupled Voltage Follower:

The input impedance of the capacitor-coupled voltage follower is set by the value of

resistor R 1 is not very large and has much smaller input impedance than the direct-

coupled voltage follower.

To use voltage follower as buffer it is necessary that the input impedance should be verylarge.

Figure 2.4 shows a method by which the input impedance of the capacitor-coupled

voltage follower can be substantially increased.

Figure 2.4: High input impedance capacitor-coupled voltage follower

Capacitor C2 is connected between inverting input terminal and junction point of R 1 and

R 2.

For AC purpose, C2 acts as an AC short circuit so that Vo is developed across R 2.

Voltage developed across R 1 is given as,




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------- (1) Current i1 is given as,

From equation (1) we get

Input impedance is given by,

------- (2)

Since M (open loop gain) is very large, this modified circuit has very very high input

impedance.

This method is called as bootstrapping of biasing resistance.

Design Steps: The resistors R 1 and R 2 are treated to be single resistors and its value is obtained

as

With R 1 = R 2

Selection of C1 ideally can be done same as the basic capacitor coupled voltage

follower. Due to effect of stray capacitance, XC1 is selected as




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To keep feedback voltage same as output voltage Vo which is equal to inputvoltage vi at the lowest operating frequency

The capacitor C3 is given as,

As R 1 = R 2 = R (max)/2 thus,




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Capacitor-Coupled Non-inverting Amplifier:

Figure 2.5 below shows the circuit for capacitor-coupled non-inverting amplifier

Figure 2.5: Capacitor-Coupled Non-inverting Amplifier

In the above figure the input is connected to the non-inverting terminal by coupling it to a

input capacitor. Thus, to provide a path for DC input bias current, the non-inverting

terminal is grounded through resistance R 1.

The output is capacitor coupled through capacitor C2. As amplifier is used for AC

Quantity, the DC offset voltage present at the output if any is not significant.

To ensure minimum power dissipation and minimum current drawn from the power

supply, larger value resistors are used and is given by,

The input impedance of non-inverting amplifier is very very large which is in parallel

with the resistance R 1, hence circuit input impedance Zin is given as,

Here Since is very very large which is in parallel with the resistance R 1.Thus, parallel

combination is smaller than the smallest than R 1 and is almost equal to R 1.




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From Potential divider logic the resistor values R 2 and R 3 are determined using Vi, Vo, I2.

By convention we select I2 much larger than IB(max) by about 100 times.

From the concept of virtual ground, Vin = VA = VB thus

Using the concept of closed loop voltage gain Av output voltage is given as

As Vo appears across (R 2 + R 3) hence,

At the circuit low 3 dB frequency (f l), the impedance of C1 should be much smaller than

Zin as the signal voltage gets divide across XC1 and Zin as shown below.

Figure 2.6: signal voltage gets divide across XC1 and Zin




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As Zin = R 1 and expanding XC1

The circuit low 3 dB frequency (f 1) occurs when XC2 = R L. Therefore, C2 is calculated

from




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High Zin, Capacitor-Coupled Non-inverting Amplifier:

The input impedance of the capacitor-coupled non-inverting amplifier is set by the value

of resistor R 1 is not very large and needed to be increased in much application.

Improvement in input impedance Zin is done by modifying the circuit as below

Figure 2.7: High Zin Capacitor-Coupled Non-inverting Amplifier

Input impedance Zin for the above circuit is given as,

------ (1)

Within the operating bandwidth, the capacitor C2 act as short circuit. Using potential

divider rule the voltage across resistor R 3 is given as

------- (2) Thus, from above equation we see that the feedback voltage is attenuated by a factor of,

------ (3) Thus substituting equation (3) in (2) we get,

------- (4)




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As open loop gain (M) is very large the modified circuit has large input impedance.

This method is called as bootstrapping of biasing resistance.

Design Steps:

The resistors R 1 and R 2 are treated to be single resistors and its value is obtained

as

In the pass-band the gain of non-inverting amplifier is

The value of resistor R 2 and R 3 for high Zin circuit are determined exactly as for a

direct-coupled non-inverting amplifier. For equal IBR B,

Usually,

With R 1 = R 3

Above is applicable for bipolar op-amps only. For BiFET op-amps must be equal

to and R 2 = 1MΩ. Capacitor value C1 is chosen as 1000pF to be much larger than stray capacitances.

At lower 3dB frequency f L the gain of the amplifier is given wrt pass band as




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--------- (11) At frequency f L the gain of the amplifier considering impedance is given as,

Since Av >> 1 the above equation is written as,

Considering only real terms we get,

------- (12) In pass-band the gain is dependant only on resistive terms hence,

Since Av >> 1 the above equation is written as,

------- (13) Substitute equations (12) and (13) in (11) we get,




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As XC3 is equal to R 3/10 hence, Capacitor C3 is given as,

Capacitor-Coupled Inverting Amplifier:

Figure 2.7 below shows the circuit for capacitor-coupled inverting amplifier

Figure 2.7: Capacitor-Coupled Inverting Amplifier

In the above circuit the bias current to the op-amp inverting input terminal flows via

resistor R 2, so coupling capacitor C1 does not interrupt the input bias current.

No resistor is included in series with the non-inverting input terminal, because a small

DC offset is not important with a capacitor-coupled output.




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If it is desired to equalize the IBR B voltage drops, the resistance in series with the non-

inverting input should equal R 2 because R 1 is not part of the bias current path at the

inverting input terminal.

Design:

From the concept of virtual ground,

As Vo appears across (R 2) hence,




calculated from




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Setting the Upper Cutoff Frequency:

The highest signal frequency that can be processed by an op-amp circuit depends on the

op-amp selected like 741, LF353 etc.

Consider an application where very low frequency signals are to be amplified and

unwanted higher frequency noise voltages are to be excluded. In the above application, the circuit voltage gain should be made to fall off just above the

highest desired signal frequency.

This can be achieved by connecting a feedback capacitor Cf from the op-amp output to its

inverting input terminal as shown in figure 2.8 (a) and (b) below

Figure 2.8 (a): Inverting Amplifier

Figure 2.8 (b): Non-Inverting Amplifier




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Voltage gain for inverting amplifier is given as,

Magnitude of AV is given as,

Say if XCf = R 2 then,




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The above equation indicates that the gain is 3 dB below the normal voltage gain (R 2/R 1).

Hence, upper cut-off frequency f 2 can be set at a desired value by selecting Cf which

makes XCf = R 2 at the required frequency.

For the case of non-inverting amplifier the result derived from inverting amplifier is

equally applicable provided that to implement such circuit upper cut-off frequency of op-

amp must be much higher than the desired maximum frequency for the circuit.

Capacitor Coupled Difference Amplifier or Subtractor:

Capacitor Coupled Difference Amplifier is as shown in figure 2.9 as shown below

Figure 2.9: Capacitor Coupled Difference Amplifier

We employ superposition theorem to solve the circuit

Case1: let V1 be operational and V2 be grounded. Output be represented as Vo1 as shown

in figure 2.10 below




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Figure 2.10: op-amp configured as a difference amplifier with V1 Operational

Looking in to the above figure we see that it is a inverting amplifier configuration, hence

gain is given as

------ (1)

The output voltage is given as

--------- (2)

Case2: let V2 be operational and V1 be grounded. Output be represented as Vo2 as shown

in figure 1.34 below




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Figure 2.11: op-amp configured as a difference amplifier with V2 Operational

Looking in to the above figure we see that it is a non-inverting amplifier configuration,

hence gain is given as

------ (3)

The output voltage is given as

The voltage VA is given by Ohms law as,




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Substituting VA in Vo2 we get, ------- (4) Adding both the outputs we get,

------- (5) Now Say we select the resistances R 1 = R 3 and R 2 = R 4 in such case above equation is

reduced to,

-------- (6)

Now say if R 2 = R 1 in this case the output is the difference value of 2 input voltages.


Resistance R 2 is given as

Resistance R 3 is given as

Resistance R 4 is given as C1 is calculated as,




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from

If upper cut-off frequency is to be set, then the capacitors must be connected across

resistors R 2 and R 4 as shown in figure 2.12 below




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Figure 2.12: Setting Upper cut-off Frequency for Difference Amplifier

For the case of upper cut-off frequency capacitor Cf1 is determined as,

For the case of upper cut-off frequency capacitor Cf2 is determined as,

Here,

f 2 = desired upper cut-off frequency




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Use of Single Polarity Supply: Most of the operational amplifiers are designed to be used with dual supply such that the

magnitudes of both positive and negative supply voltages with respect to ground are

equal.

If we neglect the offset voltage, output voltage is zero when input signal is zero. The DCreference value of the resulting output is also zero and the maximum output voltage

possible is slightly less than the positive and negative supply voltage.

Instead of using bipolar power supply, the operational amplifiers can be externally biased

using a single supply voltage also.

The above case is possible if an additional coupling capacitor is used to remove unwanted

DC levels. As such a capacitor blocks DC, the offset voltage and DC level in the output

has hardly any effect on the operation of the amplifier.

Hence single supply biasing is possible only in case of AC amplifiers.

The operational amplifier using a single supply biasing, must be able to produce both

negative going and positive going signals.

For the above purpose an AC level is purposely inserted, in such a single supply biasing.

The operational amplifier's quiescent DC output voltage is set to one half of the single

positive supply i.e. 1/2 Vcc, in single supply biasing. This ensures that the positive output

swing equals the negative.

The DC level of 1/2 Vcc is inserted by using a voltage divider network at the non-

inverting input terminal. The resistance values of a divider are made equal so that the

output across one resistance is half the supply voltage, +Vcc.




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Voltage Divider Using Single Polarity Supply:

Capacitor coupled op-amp circuits can be easily adapted to use a single polarity supply

voltage because the capacitors block the DC bias voltages at input and output.

A capacitor coupled voltage follower circuit using a single-polarity supply is illustrated in

figure 2.13 below

Figure 2.13: capacitor coupled voltage follower using single polarity supply

If the op-amp data sheet lists the minimum supply voltage as ±9 V, then a minimum of 18

V should be used in a single-polarity supply situation. Also, the specified maximum

supply voltage should not be exceeded.

The potential divider (R 1 and R 2) sets the bias voltage at the non-inverting input terminal

as approximately Vcc/2. This means that the DC levels of the output terminal and the

inverting input are also at Vcc/2.

Thus, with an 18 V supply, the positive supply terminal is +9 V with respect to the bias

level at the input and output terminals, and the negative supply terminal is -9 V with

respect to those terminals.

The voltage drop across each resistor is usually selected as Vcc/2; although it could be

above or below this point within the specified input voltage range for the op-amp.

Design Steps:

Current I2 is selected larger than IB thus,

As voltage drop across each resistor is usually selected as Vcc/2 hence each

resistor value is given as,




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Thus the input impedance becomes,

The input capacitor C1 at input side is given as,

Expanding XC1


calculated from




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High Input Impedance Voltage Follower Using a Single-Polarity Supply:

Figure 2.14 shows a high input impedance voltage follower using a single-polarity supply

Figure 2.14: High Input Impedance Voltage Follower Using a Single-Polarity Supply

In the above circuit the resistors R 1 and R 2 provides a potential of Vcc/2 which is applied

to non-inverting input via resistor R 3, which is used to provide a bias current path.

The capacitor bootstraps R 3 making input impedance very large and is given as


As voltage drop across each resistor is usually selected as V cc/2 hence each resistor value

is given as,

As input impedance Zin is very large and resistors (R 1||R 2) are in series with with C2 it is

given as,




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Capacitor Coupled Non-Inverting Amplifier Using a Single-Polarity Supply:

Figure 2.15 shows the circuit of a capacitor coupled non-inverting amplifier using a

single-polarity supply.

Figure 2.15: capacitor coupled non-inverting amplifier using a s ingle-polarity supply

In the above circuit Potential divider R 1 and R 2 used to set the bias voltage at

approximately Vcc/2.

The bottom of resistor R 4 is capacitor-coupled to ground via capacitor C3. If this point

was directly grounded, the DC voltage at the op-amp output terminal would tend toward

AV∙(bias level at the non-inverting input), or AV∙Vcc/2. This would saturate the output at

approximately Vcc - 1 V.




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With C3 in the circuit as shown in figure 2.15, and R 3 connecting the inverting input

terminal to the output, the op-amp behaves as a DC voltage follower.

The DC voltage level at the op-amp output terminal is then the same as that at the non-

inverting input terminal (Vcc/2).

For ac voltages, C3 behaves as a short circuit, so that the AC voltage gain AV is given as

Design Steps:

Current I2 & I4 is selected larger than IB thus,



AC voltage Gain is given as

From the concept of virtual ground, Vin = VA = VB thus

As Vo appears across (R 3 + R 4) hence,




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Thus the input impedance becomes,

The input capacitor C1 at input side is given as,

Expanding XC1


calculated from

Capacitor C3 should be selected to have impedance very much smaller than R 4 at

the low 3 dB frequency of the circuit for a fixed load.




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For variable load:

High Input Impedance Capacitor-Coupled Non-Inverting Amplifier Using a

Single-Polarity Supply:

Figure 2.16 shows a high input impedance Capacitor-Coupled Non-Inverting Amplifier

using a single-polarity supply

Figure 2.16: High Input Impedance Capacitor-Coupled Non-Inverting Amplifier Using a Single-Polarity Supply




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The above circuit is very similar to the high input impedance voltage follower circuit as

discussed above but the only difference is that resistor R 4 is included in the non-inverting

amplifier circuit to give a voltage gain greater than 1 and is given as

The resistor R 3 is included to increase the input impedance by providing feedback

through the capacitor C2.


As voltage drop across each resistor is usually selected as V cc/2 hence each resistor valueis given as,

Resistor R 4 is calculated using the voltage gain equation as above






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from

As C2 is in series with the resistor combination R 1||R 2 it is calculated as,




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Capacitor Coupled Inverting Amplifier Using a Single-Polarity Supply:

The circuit of an inverting amplifier using a single-polarity supply is shown in figure.

2.17 below

Figure 2.17: capacitor coupled non-inverting amplifier using a s ingle-polarity supply

In the above circuit Potential divider R 3 and R 4 used to set the bias voltage at

approximately Vcc/2.

The DC voltage level of the output and the inverting input terminal will then also be

Vcc/2.

Design Steps:

The potential divider is designed by first selecting a current (I 4) which is much

greater than the current flowing out of the potential divider (IB)







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VTU Questions:

1. Draw a neat circuit diagram of a capacitor coupled voltage follower and explain its

operation with necessary design steps. December 2015 (08 Marks), December 2014 (07

Marks), June 2013 (06 Marks), December 2012 (10 Marks) 2. Design a high impedance capacitor coupled non-inverting amplifier to have a low cutoff

frequency of 200Hz. The input and output voltages are to be 16mV and 4V respectively

and minimum load resistance is 10k Ω. select R 2 = 1 MΩ and C1 = 0.1µF. December

2015 (06 Marks)

3. Explain how the upper cutoff frequency can be set for inverting amplifier with the help of

neat circuit diagram and also explain design steps. December 2015 (06 Marks),

December 2014 (06 Marks), June 2013 (06 Marks), June 2014 (07 Marks)

4. Design a capacitor coupled inverting amplifier using IC741. Op-amp to have a voltage

gain of 75 output voltage amplitude of 3 V and a single frequency range of 20 Hz to 12kHz. The load resistance is 470 Ω. December 2014 (06 Marks)

5. Sketch a neat circuit diagram of a high Z in capacitor coupled voltage follower and explain

its operation with necessary design steps. June 2014 (08 Marks)

6. A capacitor coupled non-inverting amplifier using IC741 op-amp has Av = 100 and Vo =

5 V. The load resistance is 10 kΩ and the lower cut-off frequency is to be 100 Hz. Design

a suitable circuit. June 2014 (08 Marks), June 2013(06 Marks)

7. Explain inverting AC amplifier with neat diagram and mention its design steps using only

single-supply op-amp. June 2014 (06 Marks), December 2013 (08 Marks)

8.

Sketch a neat circuit diagram of a high Zin capacitor coupled non-inverting amplifier.

Briefly explain its operation and show that the input impedance is very high compared to

capacitor coupled non-inverting amplifier. December 2013 (08 Marks)

9. Design a high Zin capacitor coupled voltage follower using op-amp having lower cut-off

frequency of 50 Hz and maximum input bias current of 500 nA. The load resistance is 3.9

kΩ. If the open-loop gain is 2x105. Find the value of input impedance. Consider M(min) =

50,000. December 2013 (06 Marks)

10. Draw a neat circuit diagram and design steps for a Capacitor coupled inverting amplifier.

June 2013 (08 Marks)

11.

With a neat circuit diagram, explain the design of high impedance capacitor coupled non-

inverting amplifier. December 2012 (10 Marks)

12. Design a capacitor coupled voltage follower using a 741 op-amp. The lower cut-off

frequency for the circuit is to be 50 Hz and the load resistance is R L = 3.9 kΩ. June 2014

(07 Marks)




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13. Explain the use of a single polarity supply for capacitor coupled non- inverting amplifier

with circuit diagram using op-amp. June 2014 (06 Marks)

14. Explain the realization of a CC voltage follower for AC amplifier applications, discussing

cut-off frequency design concept. June 2015 (06 Marks)

15.

Design a BIFET op-amp based high Zin CC non-inverting amplifier for a lower cut-offfrequency of 120 Hz. Given Vin = 20 mV, Vo = 5 V and R L-min = 10 kΩ. June 2015 (08

Marks)

16. Explain the concept and construction of a CC inverting amplifier using a single polarity

supply (+ Vcc). June 2015 (08 Marks)




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Linear Integrated Circuits Unit2 Raghudathesh VTU