Library

LIBRARIES

GUIDE

ONLINER

0401410

TABLE OF CONTENTS

INDEX

GO TO OTHER BOOKS

Contents

Libraries Guide

Chapter 1 XO

NF

Chapter 2 SF

O

Copyright 1993-1995 Xilinx Inc. All Rights Reserved.ilinx Unified Librariesverview ...................................................................................... 1-1

Xilinx Unified Libraries ............................................................ 1-2Selection Guide ...................................................................... 1-2Design Elements..................................................................... 1-2Attributes, Constraints, and Carry Logic ................................. 1-3

aming Conventions.................................................................... 1-4lip-Flop, Counter, and Register Performance ............................ 1-5

election Guideunctional Categories .................................................................. 2-2

Arithmetic Functions ............................................................... 2-3Buffers .................................................................................... 2-5Comparators ........................................................................... 2-6Counters ................................................................................. 2-7Data Registers ........................................................................ 2-14Decoders ................................................................................ 2-14Edge Decoders ....................................................................... 2-15Encoders................................................................................. 2-15Flip-Flops ................................................................................ 2-16General ................................................................................... 2-19Input/Output Flip-Flops ........................................................... 2-21Input/Output Functions ........................................................... 2-23Input Latches .......................................................................... 2-24Latches ................................................................................... 2-24Logic Primitives....................................................................... 2-25Map Elements......................................................................... 2-30Memory Elements................................................................... 2-30Multiplexers............................................................................. 2-31PLD Elements......................................................................... 2-32Shift Registers ........................................................................ 2-33Shifters.................................................................................... 2-35

bsolete Macros.......................................................................... 2-35XC2000 Replacement and Obsolete Macro Functions........... 2-37 0401410 01 i

Libraries Guide

ii

XC3000 Replacement and Obsolete Macro Functions........... 2-43XC4000 Replacement and Obsolete Macro Functions........... 2-52XC7000 Replacement and Obsolete Macro Functions........... 2-62

Chapter 3 Design ElementsACC1

1-Bit Loadable Cascadable Accumulator with

A

A

A

A

A

A

A

A

A

A

AXilinx Development System

Carry-In, Carry-Out, and Synchronous Reset......................... 3-1CC1X1

1-Bit Loadable Cascadable Accumulator withCarry-Out and Synchronous Reset for EPLD ......................... 3-4

CC1X21-Bit Loadable Cascadable Accumulator withCarry-In, Carry-Out, and Synchronous Reset......................... 3-6

CC44-Bit Loadable Cascadable Accumulator withCarry-In, Carry-Out, and Synchronous Reset......................... 3-8

CC4X14-Bit Loadable Cascadable Accumulator withCarry-Out and Synchronous Reset for EPLD ......................... 3-11








Libraries Guide

ACLKAlternate Clock Buffer ............................................................. 3-32

ADD11-Bit Full Adder with Carry-In and Carry-Out .......................... 3-33

ADD1X11-Bit Cascadable Full Adder with Carry-Out for EPLD ........... 3-34

ADD1X21-Bit Cascadable Full Adder with Carry-In and

A

A

A

A

A

A

A

A

A

A

Aiii

Carry-Out for EPLD ................................................................ 3-35DD4

4-Bit Cascadable Full Adder with Carry-In, Carry-Out,and Overflow........................................................................... 3-36

DD4X14-Bit Cascadable Full Adder with Carry-Out for EPLD ........... 3-38

DD4X24-Bit Cascadable Full Adder with Carry-In andCarry-Out for EPLD ................................................................ 3-39

DD88-Bit Cascadable Full Adder with Carry-In, Carry-Out,and Overflow........................................................................... 3-40

DD8X18-Bit Loadable Cascadable Full Adder with Carry-Outfor EPLD ................................................................................. 3-44

DD8X28-Bit Cascadable Full Adder with Carry-In andCarry-Out for EPLD ................................................................ 3-45

DD1616-Bit Cascadable Full Adder with Carry-In,Carry-Out, and Overflow......................................................... 3-46

DD16X116-Bit Cascadable Full Adder with Carry-Out for EPLD ......... 3-49

DD16X216-Bit Cascadable Full Adder with Carry-In and Carry-Outfor EPLD ................................................................................. 3-51

DSU11-Bit Cascadable Adder/Subtracter with Carry-In andCarry-Out ................................................................................ 3-52

DSU1X11-Bit Cascadable Adder/Subtracter with Carry-Out forEPLD ...................................................................................... 3-54

Libraries Guide

iv

ADSU1X21-Bit Cascadable Adder/Subtracter with Carry-In andCarry-Out for EPLD................................................................. 3-55

ADSU44-Bit Cascadable Adder/Subtracter with Carry-In,Carry-Out, and Overflow ......................................................... 3-56

ADSU4X1

A

A

A

A

A

A

A

A

B

B

B

BXilinx Development System

4-Bit Cascadable Adder/Subtracter with Carry-Outfor EPLD ................................................................................. 3-59

DSU4X204-Bit Cascadable Adder/Subtracter with Carry-In andCarry-Out for EPLD................................................................. 3-60

DSU88-Bit Cascadable Adder/Subtracter with Carry-In,Carry-Out, and Overflow ......................................................... 3-61

DSU8X18-Bit Cascadable Adder/Subtracter with Carry-Outfor EPLD ................................................................................. 3-66


DSU1616-Bit Cascadable Adder/Subtracter with Carry-In,Carry-Out, and Overflow ......................................................... 3-68

DSU16X116-Bit Cascadable Adder/Subtracter with Carry-Outfor EPLD ................................................................................. 3-72


ND2- to 9-Input AND Gates with Inverted andNon-Inverted Inputs ................................................................ 3-76

RLSHFT44-Bit Barrel Shifter................................................................... 3-78

RLSHFT88-Bit Barrel Shifter................................................................... 3-79

SCANBoundary Scan Logic Control Circuit ...................................... 3-81

UF, BUF4, BUF8, and BUF16General-Purpose Buffers ........................................................ 3-82

Libraries Guide

BUFCEGlobal Clock-Enable Buffer for EPLD..................................... 3-83

BUFE, BUFE4, BUFE8, and BUFE16Internal 3-State Buffers........................................................... 3-84

BUFFOEGlobal Fast Output Enable Buffer for EPLD ........................... 3-86

BUFGGlobal Clock Buffer ................................................................. 3-87

BUFGP

B

B

B

C

C

C

C

C

C

Cv

Primary Global Buffer for Driving Clocks or Longlines(Four per PLD Device)............................................................ 3-88

UFGSSecondary Global Buffer for Driving Clocks or Longlines(Four per PLD Device)............................................................ 3-90

UFODOpen-Drain Buffer................................................................... 3-92

UFT, BUFT4, BUFT8, and BUFT16Internal 3-State Buffers........................................................... 3-93

B2CE2-Bit Cascadable Binary Counter with Clock Enable andAsynchronous Clear ............................................................... 3-95

B2CLE2-Bit Loadable Cascadable Binary Counter with ClockEnable and Asynchronous Clear ............................................ 3-97

B2CLED2-Bit Loadable Cascadable Bidirectional Binary Counterwith Clock Enable and Asynchronous Clear ........................... 3-99

B2RE2-Bit Cascadable Binary Counter with Clock Enable andSynchronous Reset ................................................................ 3-101

B2RLE2-Bit Loadable Cascadable Binary Counter with ClockEnable and Synchronous Reset ............................................. 3-103

B2X12-Bit Loadable Cascadable Bidirectional Binary Counterwith Clock Enable and Asynchronous Clear ........................... 3-105

B2X22-Bit Loadable Cascadable Bidirectional Binary Counterwith Clock Enable and Synchronous Reset ............................ 3-107

Libraries Guide

vi

CB4CE4-Bit Cascadable Binary Counter with Clock Enable and Asynchronous Clear............................................................... 3-109

CB4CLE4-Bit Loadable Cascadable Binary Counter with ClockEnable and Asynchronous Clear ............................................ 3-111

CB4CLED4-Bit Loadable Cascadable Bidirectional Binary Counter

C

C

C

C

C

C

C

C

C

CXilinx Development System

with Clock Enable and Asynchronous Clear ........................... 3-113B4RE

4-Bit Cascadable Binary Counter with Clock Enable andAsynchronous Reset............................................................... 3-115



B4X24-Bit Loadable Cascadable Bidirectional Binary Counterwith Clock Enable and Synchronous Reset ............................ 3-121

B8CE8-Bit Cascadable Binary Counter with Clock Enable andAsynchronous Clear................................................................ 3-123

B8CLE8-Bit Loadable Cascadable Binary Counter with ClockEnable and Asynchronous Clear ............................................ 3-127


B8RE8-Bit Cascadable Binary Counter with Clock Enable andSynchronous Reset................................................................. 3-136



Libraries Guide

CB8X28-Bit Loadable Cascadable Bidirectional Binary Counterwith Clock Enable and Synchronous Reset ............................ 3-144

CB16CE16-Bit Cascadable Binary Counter with Clock Enable andAsynchronous Clear ............................................................... 3-146

CB16CLE16-Bit Loadable Cascadable Binary Counter with ClockEnable and Asynchronous Clear ............................................ 3-148

C

C

C

C

C

C

C

C

C

Cvii


B16RE16-Bit Cascadable Binary Counter with Clock Enable andSynchronous Reset ................................................................ 3-152



B16X216-Bit Loadable Cascadable Bidirectional Binary Counter with Clock Enable and Synchronous Reset ........................... 3-158

C8CE8-Bit Cascadable Binary Counter with Clock Enable and Asynchronous Clear .............................................................. 3-160

C8CLE8-Bit Loadable Cascadable Binary Counter with ClockEnable and Asynchronous Clear ............................................ 3-163

C8CLED8-Bit Loadable Cascadable Bidirectional Binary Counterwith Clock Enable and Asynchronous Clear ........................... 3-166

C8RE8-Bit Cascadable Binary Counter with Clock Enable andAsynchronous Reset............................................................... 3-170

C16CE16-Bit Cascadable Binary Counter with Clock Enable andAsynchronous Clear ............................................................... 3-173

Libraries Guide

viii

CC16CLE16-Bit Loadable Cascadable Binary Counter with ClockEnable and Asynchronous Clear ............................................ 3-175

CC16CLED16-Bit Loadable Cascadable Bidirectional Binary Counter with Clock Enable and Asynchronous Clear .......................... 3-177

CC16RE

C

C

C

C

C

C

C

C

C

C

CXilinx Development System

16-Bit Cascadable Binary Counter with Clock Enable andSynchronous Reset................................................................. 3-179

D4CE4-Bit Cascadable BCD Counter with Clock Enable andAsynchronous Clear................................................................ 3-181

D4CLE4-Bit Loadable Cascadable BCD Counter with ClockEnable and Asynchronous Clear ............................................ 3-184

D4RE4-Bit Cascadable BCD Counter with Clock Enable andSynchronous Reset................................................................. 3-187

D4RLE4-Bit Loadable Cascadable BCD Counter with ClockEnable and Synchronous Reset ............................................. 3-190

J4CE4-Bit Johnson Counter with Clock Enable and AsynchronousClear ....................................................................................... 3-193

J4RE4-Bit Johnson Counter with Clock Enable and SynchronousReset....................................................................................... 3-195





LBCLB Configuration Symbol...................................................... 3-203

Libraries Guide

CLBMAPLogic-Partitioning Control Symbol .......................................... 3-207

COMP22-Bit Identity Comparator ........................................................ 3-211

COMP44-Bit Identity Comparator ........................................................ 3-212

COMP8

C

C

C

C

C

C

C

C

C

D

D

D

D

F

Fix

8-Bit Identity Comparator ........................................................ 3-213OMP16

16-Bit Identity Comparator ...................................................... 3-214OMPM2

2-Bit Magnitude Comparator................................................... 3-215OMPM4



16-Bit Magnitude Comparator................................................. 3-219OMPMC8

8-Bit Magnitude Comparator................................................... 3-220OMPMC16

16-Bit Magnitude Comparator................................................. 3-222R8CE

8-Bit Negative-Edge Binary Ripple Counter with ClockEnable and Asynchronous Clear ............................................ 3-224

R16CE16-Bit Negative-Edge Binary Ripple Counter with ClockEnable and Asynchronous Clear ............................................ 3-226

2_4E2- to 4-Line Decoder/Demultiplexer with Enable .................... 3-227

3_8E3- to 8-Line Decoder/Demultiplexer with Enable .................... 3-228

4_16E4- to 16-Line Decoder/Demultiplexer with Enable .................. 3-230

ECODE4, DECODE8, and DECODE 164-, 8-, and 16-Bit Active-Low Edge Decoders......................... 3-232

D, FD4, FD8, and FD16Single and Multiple D Flip-Flops ............................................. 3-234

D_1D Flip-Flop with Negative-Edge Clock .................................... 3-236

Libraries Guide

x

FD4CE4-Bit Data Register with Clock Enable and AsynchronousClear ....................................................................................... 3-237

FD4RE4-Bit Data Register with Clock Enable and SynchronousReset....................................................................................... 3-238

FD8CE8-Bit Data Register with Clock Enable and Asynchronous

F

F

F

F

F

F

F

F

F

F

F

FXilinx Development System

Clear ....................................................................................... 3-239D8RE

8-Bit Data Register with Clock Enable and Synchronous Reset...................................................................................... 3-241

D16CE16-Bit Data Register with Clock Enable and AsynchronousClear ....................................................................................... 3-243

D16RE16-Bit Data Register with Clock Enable and SynchronousReset....................................................................................... 3-244

DCD Flip-Flop with Asynchronous Clear...................................... 3-245

DC_1D Flip-Flop with Negative-Edge Clock and AsynchronousClear ....................................................................................... 3-246

DCED Flip-Flop with Clock Enable and Asynchronous Clear ........ 3-248

DCE_1D Flip-Flop with Negative-Edge Clock, Clock Enable,and Asynchronous Clear......................................................... 3-249

DCPD Flip-Flop with Asynchronous Preset and Clear ................... 3-251

DCPED Flip-Flop with Clock Enable and Asynchronous Presetand Clear ................................................................................ 3-252

DPD Flip-Flop with Asynchronous Preset.................................... 3-254

DP_1D Flip-Flop with Negative-Edge Clock and AsynchronousPreset...................................................................................... 3-255

DPED Flip-Flop with Clock Enable and Asynchronous Preset....... 3-256

Libraries Guide

FDPE_1D Flip-Flop with Negative-Edge Clock, Clock Enable,and Asynchronous Preset....................................................... 3-257

FDRD Flip-Flop with Synchronous Reset ...................................... 3-258

FDRED Flip-Flop with Clock Enable and Synchronous Reset ......... 3-259

FDRS

F

F

F

F

F

F

F

F

F

F

F

Fxi

D Flip-Flop with Synchronous Reset and SynchronousSet .......................................................................................... 3-260

DRSED Flip-Flop with Synchronous Reset and Set and ClockEnable..................................................................................... 3-261

DSD Flip-Flop with Synchronous Set .......................................... 3-262

DSED Flip-Flop with Clock Enable and Synchronous Set ............. 3-263

DSRD Flip-Flop with Synchronous Set and Reset ......................... 3-264

DSRED Flip-Flop with Synchronous Set and Reset and ClockEnable..................................................................................... 3-265

JKCJ-K Flip-Flop with Asynchronous Clear................................... 3-266

JKCEJ-K Flip-Flop with Clock Enable and Asynchronous Clear ..... 3-267

JKCPJ-K Flip-Flop with Asynchronous Clear and Preset ................ 3-269

JKCPEJ-K Flip-Flop with Asynchronous Clear and Preset andClock Enable........................................................................... 3-271

JKPJ-K Flip-Flop with Asynchronous Preset ................................. 3-273

JKPEJ-K Flip-Flop with Clock Enable and AsynchronousPreset ..................................................................................... 3-274

JKRSEJ-K Flip-Flop with Clock Enable and Synchronous Resetand Set ................................................................................... 3-276

Libraries Guide

xii

FJKSREJ-K Flip-Flop with Clock Enable and Synchronous Set andReset....................................................................................... 3-278

FMAPF Function Generator Partitioning Control Symbol ................. 3-280

FTCToggle Flip-Flop with Toggle Enable and Asynchronous

F

F

F

F

F

F

F

F

F

F

FXilinx Development System

Clear ....................................................................................... 3-283TCE

Toggle Flip-Flop with Toggle and Clock Enable and Asynchronous Clear............................................................... 3-284

TCLEToggle/Loadable Flip-Flop with Toggle and Clock Enableand Asynchronous Clear......................................................... 3-285

TCPToggle Flip-Flop with Toggle Enable and AsynchronousClear and Preset ..................................................................... 3-287

TCPEToggle Flip-Flop with Toggle and Clock Enable andAsynchronous Clear and Preset ............................................. 3-288

TCPLELoadable Toggle Flip-Flop with Toggle and Clock Enableand Asynchronous Clear and Preset ...................................... 3-289

TPToggle Flip-Flop with Toggle Enable and AsynchronousPreset...................................................................................... 3-291

TPEToggle Flip-Flop with Toggle and Clock Enable and Asynchronous Preset............................................................. 3-292

TPLEToggle/Loadable Flip-Flop with Toggle and Clock Enableand Asynchronous Preset....................................................... 3-293

TRSEToggle Flip-Flop with Toggle and Clock Enable andSynchronous Reset and Set ................................................... 3-295

TRSLEToggle/Loadable Flip-Flop with Toggle and Clock Enableand Synchronous Reset and Set ............................................ 3-296

TSREToggle Flip-Flop with Toggle and Clock Enable andSynchronous Set and Reset ................................................... 3-298

Libraries Guide

FTSRLEToggle/Loadable Flip-Flop with Toggle and Clock Enableand Synchronous Set and Reset ............................................ 3-299

GCLKGlobal Clock Buffer ................................................................. 3-301

GNDGround-Connection Signal Tag .............................................. 3-302

GXTL

H

I

I

I

I

I

I

I

I

I

I

I

I

I

Ixiii

Crystal Oscillator with ACLK Buffer ........................................ 3-303MAP

H Function Generator Partitioning Control Symbol................. 3-304BUF, IBUF4, IBUF8, and IBUF16

Single- and Multiple-Input Buffers........................................... 3-306FD, IFD4, IFD8, and IFD16

Single- and Multiple-Input D Flip-Flops................................... 3-307FD_1

Input D Flip-Flop with Inverted Clock...................................... 3-310FDX1, IFD4X1, IFD8X1, and IFD16X1

Input D Flip-Flops for EPLD.................................................... 3-312FDI

Input D Flip-Flop (Asynchronous Set)..................................... 3-314FDI_1

D Flip-Flop with Inverted Clock (Asynchronous Set) .............. 3-316LD, ILD4, ILD8, and ILD16

Input Transparent Data Latches ............................................. 3-318LD_1

Transparent Input Data Latch with Inverted Gate................... 3-322LDI

Input Transparent Data Latch (Asynchronous Set) ................ 3-324LDI_1

Transparent Input Data Latch with Inverted Gate(Asynchronous Set) ................................................................ 3-326

NV, INV4, INV8, and INV16Single and Multiple Inverters .................................................. 3-328

OBIOB Configuration Symbol ...................................................... 3-329

OPAD, IOPAD4, IOPAD8, and IOPAD16Input/Output Pads................................................................... 3-332

PADSingle- and Multiple-Input Pads.............................................. 3-333

Libraries Guide

xiv

LD, LD4, LD8, and LD16Single and Multiple Transparent Data Latches ....................... 3-334

LD_1Transparent Data Latch with Inverted Gate ............................ 3-335

LDCTransparent Data Latch with Asynchronous Clear ................. 3-336

LD4CE, LD8CE, and LD16CE

L

L

L

M

M

M

M

M

M

M

M

M

M

NXilinx Development System

Transparent Data Latches with Asynchronous Clearand Clock Enable.................................................................... 3-337

DCPTransparent Data Latch with Asynchronous Clear andPreset...................................................................................... 3-340

DCPETransparent Data Latch with Asynchronous Clear andPreset and Clock Enable ........................................................ 3-341

DC_1Transparent Data Latch with Asynchronous Clear andInverted Gate Input ................................................................. 3-343

D0Mode 0/Input Pad Used for Readback Trigger Input .............. 3-344

D1Mode 1/Output Pad Used for Readback Data Output............. 3-345

D2Mode 2/Input Pad.................................................................... 3-346

2_12-to-1 Multiplexer .................................................................... 3-347

2_1B12-to-1 Multiplexer with D0 Inverted ......................................... 3-348

2_1B22-to-1 Multiplexer with D0 and D1 Inverted............................. 3-349

2_1E2-to-1 Multiplexer with Enable................................................. 3-350



16_1E16-to-1 Multiplexer with Enable............................................... 3-354

AND2- to 9-Input NAND Gates with Inverted andNon-Inverted Inputs ................................................................ 3-355

Libraries Guide

NOR2- to 9-Input NOR Gates with Inverted andNon-Inverted Inputs ................................................................ 3-357

OBUF, OBUF4, OBUF8, and OBUF16Single- and Multiple-Output Buffers........................................ 3-359

OBUFE, OBUFE4, OBUFE8, and OBUFE163-State Output Buffers with Active-High Output Enable ......... 3-360

OBUFEX1, OBUFE4X1, OBUFE8X1, and OBUFEX2EPLD 3-State Output Buffers with Active-High Output

O

O

O

O

O

O

O

O

O

O

Oxv

Enable..................................................................................... 3-362BUFT, OBUFT4, OBUFT8, and OBUFT16

Single and Multiple 3-State Output Buffers withActive-Low Output Enable ...................................................... 3-364

FD, OFD4, OFD8, and OFD16Single- and Multiple-Output D Flip-Flops................................ 3-366

FD_1Output D Flip-Flop with Inverted Clock ................................... 3-369

FDE, OFDE4, OFDE8, and OFDE16D Flip-Flops with Active-High Enable Output Buffers ............. 3-370

FDE_1D Flip-Flop with Active-High Enable Output Buffer andInverted Clock......................................................................... 3-373

FDEID Flip-Flop with Active-High Enable Output Buffer(Asynchronous Set) ................................................................ 3-374

FDEI_1D Flip-Flop with Active-High Enable Output Buffer andInverted Clock (Asynchronous Set) ........................................ 3-375

FDIOutput D Flip-Flop (Asynchronous Set) .................................. 3-376

FDI_1Output D Flip-Flop with Inverted Clock(Asynchronous Set) ................................................................ 3-377

FDT, OFDT4, OFDT8, and OFDT16Single and Multiple D Flip-Flops with Active-High3-State Active-Low Output Enable Buffers ............................. 3-378

FDT_1D Flip-Flop with Active-High 3-State and Active-LowOutput Buffer and Inverted Clock ........................................... 3-381

Libraries Guide

xvi

OFDTID Flip-Flop with Active-High 3-State and Active-LowOutput Buffer (Asynchronous Set) .......................................... 3-382

OFDTI_1D Flip-Flop with Active-High 3-State, Active-Low OutputBuffer and Inverted Clock ....................................................... 3-383

OPAD, OPAD4, OPAD8, and OPAD16Single- and Multiple-Output Pads ........................................... 3-384

O

O

O

P

P

P

P

P

P

P

R

R

R

R

RXilinx Development System

R2- to 9-Input OR Gates with Inverted andNon-Inverted Inputs ................................................................ 3-385

SCCrystal Oscillator Amplifier...................................................... 3-387

SC4Internal 5-Frequency Clock-Signal Generator ........................ 3-388

L20PIN, PL24PIN, and PL48PINGeneric PLD Symbols for EPLD ............................................. 3-389

L20V820V8-Compatible PLD Symbol for EPLD................................ 3-390

L22V1022V10-Compatible PLD Symbol for EPLD.............................. 3-393

LFB9EPLD High-Density Function Block PLD Symbol ................... 3-396

LFFB9EPLD Fast Function Block PLD Symbol ................................. 3-400

ULLDOWNResistor to GND for Input Pads .............................................. 3-402

ULLUPResistor to VCC for Input PADs, Open-Drain, and3-State Outputs....................................................................... 3-403

AM16X116-Deep by 1-Wide Static RAM .............................................. 3-404


AM16X416-Deep by 4-Wide Static Ram .............................................. 3-406



Libraries Guide

RAM32X232-Deep by 2-Wide Static RAM.............................................. 3-410



READBACK

R

R

S

S

S

S

S

S

S

S

S

Sxvii

FPGA Bitstream Readback Controller .................................... 3-414OM16X1

16-Deep by 1-Wide ROM ....................................................... 3-415OM32X1

32-Deep by 1-Wide ROM ....................................................... 3-416OP

Sum Of Products .................................................................... 3-417R4CE

4-Bit Serial-In Parallel-Out Shift Register with ClockEnable and Asynchronous Clear ............................................ 3-418

R4CLE4-Bit Loadable Serial/Parallel-In Parallel-Out Shift Registerwith Clock Enable and Asynchronous Clear ........................... 3-419

R4CLED4-Bit Shift Register with Clock Enable and AsynchronousClear ....................................................................................... 3-420

R4RE4-Bit Serial-In Parallel-Out Shift Register with ClockEnable and Synchronous Reset ............................................. 3-421

R4RLE4-Bit Loadable Serial/Parallel-In Parallel-Out Shift Register with Clock Enable and Synchronous Reset ........................... 3-422

R4RLED4-Bit Shift Register with Clock Enable and SynchronousReset ...................................................................................... 3-423

R8CE8-Bit Serial-In Parallel-Out Shift Register with Clock Enableand Asynchronous Clear ........................................................ 3-424



Libraries Guide

xviii

SR8RE8-Bit Serial-In Parallel-Out Shift Register with ClockEnable and Synchronous Reset ............................................. 3-430

SR8RLE8-Bit Loadable Serial/Parallel-In Parallel-Out ShiftRegister with Clock Enable and Synchronous Reset.............. 3-432

SR8RLED

S

S

S

S

S

S

S

T

T

T

T

TXilinx Development System

8-Bit Shift Register with Clock Enable and SynchronousReset....................................................................................... 3-434

R16CE16-Bit Serial-In Parallel-Out Shift Register with ClockEnable and Asynchronous Clear ............................................ 3-436



R16RE16-Bit Serial-In Parallel-Out Shift Register with Clock Enable and Synchronous Reset ............................................ 3-439

R16RLE16-Bit Loadable Serial/Parallel-In Parallel-Out Shift Registerwith Clock Enable and Synchronous Reset ............................ 3-440

R16RLED16-Bit Shift Register with Clock Enable and SynchronousReset....................................................................................... 3-441

TARTUPUser Interface to Global Clock, Reset, and 3-StateControls................................................................................... 3-442

CKBoundary-Scan Test Clock Input Pad..................................... 3-443

DIBoundary-Scan Test Data Input Pad ...................................... 3-444

DOBoundary-Scan Data Output Pad ........................................... 3-445

IMEGRPSchematic-Level Table of Basic Timing SpecificationGroups .................................................................................... 3-446

IMESPECSchematic-Level Timing Requirement Table .......................... 3-447

Libraries Guide

TMSBoundary-Scan Test Mode Select Input Pad.......................... 3-448

UPADConnects the I/O Node of an IOB to the Internal PLDCircuit...................................................................................... 3-449

VCCVCC-Connection Signal Tag................................................... 3-450

W

W

X

X

X

X

X

X

X

X

X

X

Xxix

AND1, WAND4, WAND8, and WAND16Open-Drain Buffers................................................................. 3-451

OR2AND2-Input OR Gate with Wired-AND Open-Drain BufferOutput ..................................................................................... 3-452

NOR2- to 9-Input XNOR Gates with Non-Inverted Inputs .............. 3-453

OR2- to 9-Input XOR Gates with Non-Inverted Inputs ................. 3-455

74_424- to 10-Line BCD-to-Decimal Decoder withActive-Low Outputs................................................................. 3-457

74_L854-Bit Expandable Magnitude Comparator............................... 3-459

74_1383- to 8-Line Decoder/Demultiplexer with Active-LowOutputs and Three Enables.................................................... 3-462

74_1392- to 4-Line Decoder/Demultiplexer with Active-LowOutputs and Active-Low Enable ............................................. 3-464

74_14710- to 4-Line Priority Encoder with Active-Low Inputsand Outputs ............................................................................ 3-465

74_1488- to 3-Line Cascadable Priority Encoder withActive-Low Inputs and Outputs............................................... 3-467

74_15016-to-1 Multiplexer with Active-Low Enable and Output ......... 3-469

74_1518-to-1 Multiplexer with Active-Low Enable andComplementary Outputs......................................................... 3-471

74_1528-to-1 Multiplexer with Active-Low Output .............................. 3-473

Libraries Guide

xx

X74_153Dual 4-to-1 Multiplexer with Active-Low Enables andCommon Select Input ............................................................. 3-475

X74_1544- to 16-Line Decoder/Demultiplexer with Two Enablesand Active-Low Outputs.......................................................... 3-477

X74_157Quadruple 2-to-1 Multiplexer with Common Select andActive-Low Enable .................................................................. 3-479

X

X

X

X

X

X

X

X

X

XXilinx Development System

74_158Quadruple 2-to-1 Multiplexer with Common Select,Active-Low Enable, and Active-Low Outputs .......................... 3-480

74_1604-Bit BCD Counter with Parallel and Trickle Enables, Active-Low Load Enable, and Asynchronous Clear............... 3-481

74_1614-Bit Counter with Parallel and Trickle EnablesActive-Low Load Enable and Asynchronous Clear................. 3-484

74_1624-Bit Counter with Parallel and Trickle Enables andActive-Low Load Enable and Synchronous Reset.................. 3-487

74_1634-Bit Counter with Parallel and Trickle Enables,Active-Low Load Enable, and Synchronous Reset................. 3-490

74_1648-Bit Serial-In Parallel-Out Shift Register withActive-Low Asynchronous Clear ............................................. 3-493

74_165S8-Bit Loadable Serial/Parallel-In Parallel-Out ShiftRegister with Clock Enable ..................................................... 3-495

74_1684-Bit BCD Bidirectional Counter with Parallel and TrickleClock Enables and Active-Low Load Enable .......................... 3-497

74_1746-Bit Data Register with Active-Low AsynchronousClear ....................................................................................... 3-500

74_1944-Bit Loadable Bidirectional Serial/Parallel-In Parallel-OutShift Register .......................................................................... 3-502

Libraries Guide

X74_1954-Bit Loadable Serial/Parallel-In Parallel-Out ShiftRegister .................................................................................. 3-504

X74_2738-Bit Data Register with Active-Low AsynchronousClear ....................................................................................... 3-506

X

X

X

X

X

X

X

X

Chapter 4 AAxxi

74_2809-Bit Odd/Even Parity Generator/Checker.............................. 3-508

74_2834-Bit Full Adder with Carry-In and Carry-Out .......................... 3-509

74_298Quadruple 2-Input Multiplexer with Storage andNegative-Edge Clock .............................................................. 3-511

74_352Dual 4-to-1 Multiplexer with Active-Low Enables andOutputs ................................................................................... 3-513

74_3778-Bit Data Register with Active-Low Clock Enable ................. 3-515

74_3904-Bit BCD/Bi-Quinary Ripple Counter withNegative-Edge Clocks and Asynchronous Clear .................... 3-517

74_5188-Bit Identity Comparator with Active-Low Enable.................. 3-519

74_5218-Bit Identity Comparator with Active-Low Enable andOutput ..................................................................................... 3-520

ttributes, Constraints, and Carry Logicttributes...................................................................................... 4-1

BASE ...................................................................................... 4-2Architectures...................................................................... 4-2Description......................................................................... 4-2Syntax................................................................................ 4-4

BLKNM ................................................................................... 4-4Architectures...................................................................... 4-4Description......................................................................... 4-4Syntax................................................................................ 4-6Example............................................................................. 4-6

CAP ........................................................................................ 4-6Architectures...................................................................... 4-6Description......................................................................... 4-6Syntax................................................................................ 4-7

Libraries Guide

xxii

CLOCK_OPT .......................................................................... 4-7Architectures...................................................................... 4-7Description......................................................................... 4-7Syntax................................................................................ 4-7

CMOS ..................................................................................... 4-8Architectures...................................................................... 4-8Description......................................................................... 4-8Syntax................................................................................ 4-8

CONFIG .................................................................................. 4-8Xilinx Development System

Architectures...................................................................... 4-8Description......................................................................... 4-8Syntax................................................................................ 4-9Example............................................................................. 4-10

DECODE................................................................................. 4-11Architectures...................................................................... 4-11Description......................................................................... 4-11Syntax................................................................................ 4-11

DOUBLE ................................................................................. 4-11Architectures...................................................................... 4-11Description......................................................................... 4-11Syntax................................................................................ 4-12

EQUATE_F and EQUATE_G ................................................. 4-12Architectures...................................................................... 4-12Description......................................................................... 4-12Syntax................................................................................ 4-12Example............................................................................. 4-13

FAST....................................................................................... 4-13Architectures...................................................................... 4-13Description......................................................................... 4-13Syntax................................................................................ 4-13

FILE ........................................................................................ 4-13Architectures...................................................................... 4-13Description......................................................................... 4-13Syntax................................................................................ 4-14Example............................................................................. 4-14

FOE_OPT ............................................................................... 4-15Architectures...................................................................... 4-15Description......................................................................... 4-15Syntax................................................................................ 4-15

Libraries Guide

HBLKNM................................................................................. 4-16Architectures...................................................................... 4-16Description......................................................................... 4-16Syntax................................................................................ 4-17Example............................................................................. 4-17

HU_SET.................................................................................. 4-17xxiii

Architectures...................................................................... 4-17Description......................................................................... 4-17Syntax................................................................................ 4-18

INIT ......................................................................................... 4-18Architectures...................................................................... 4-18Description......................................................................... 4-18Syntax................................................................................ 4-18

LOC ........................................................................................ 4-19Architectures...................................................................... 4-19Description for FPGAs....................................................... 4-19Description for EPLDs ....................................................... 4-20Syntax for FPGAs.............................................................. 4-21Syntax for EPLDs .............................................................. 4-22Examples........................................................................... 4-22Single LOC Constraints ..................................................... 4-22Area LOC Constraints ....................................................... 4-23Prohibit LOC Constraints ................................................... 4-23Multiple LOC Constraints................................................... 4-24CLB Placement Examples................................................. 4-24IOB Placement Examples.................................................. 4-25BUFT Placement Examples .............................................. 4-26Global Buffer Placement Examples (XC4000 Only) .......... 4-27Decode Logic Placement Examples (XC4000 Only) ......... 4-28

LOGIC_OPT ........................................................................... 4-28Architectures...................................................................... 4-28Description......................................................................... 4-28Syntax................................................................................ 4-28

LOWPWR ............................................................................... 4-29Architectures...................................................................... 4-29Description......................................................................... 4-29Syntax................................................................................ 4-29

MAP ........................................................................................ 4-29Architectures...................................................................... 4-29Description......................................................................... 4-29Syntax................................................................................ 4-30Example............................................................................. 4-30

Libraries Guide

xxiv

MEDFAST and MEDSLOW .................................................... 4-31Architectures...................................................................... 4-31Description......................................................................... 4-31Syntax................................................................................ 4-31

MINIMIZE................................................................................ 4-31Architectures...................................................................... 4-31Description......................................................................... 4-31Syntax................................................................................ 4-32Xilinx Development System

MRINPUT................................................................................ 4-32Architectures...................................................................... 4-32Description......................................................................... 4-32Syntax................................................................................ 4-32

Net .......................................................................................... 4-32Architectures...................................................................... 4-32Description......................................................................... 4-33Syntax................................................................................ 4-35

NODELAY............................................................................... 4-35Architectures...................................................................... 4-35Description......................................................................... 4-35Syntax................................................................................ 4-36

OPT......................................................................................... 4-36Architectures...................................................................... 4-36Description......................................................................... 4-36Syntax................................................................................ 4-36

PLD ......................................................................................... 4-37Architectures...................................................................... 4-37Description......................................................................... 4-37Syntax................................................................................ 4-37

PRELOAD_OPT ..................................................................... 4-38Architectures...................................................................... 4-38Description......................................................................... 4-38Syntax................................................................................ 4-38

REG_OPT............................................................................... 4-39Architectures...................................................................... 4-39Description......................................................................... 4-39Syntax................................................................................ 4-39

RES......................................................................................... 4-39Architectures...................................................................... 4-39Description......................................................................... 4-39Syntax................................................................................ 4-40

Libraries Guide

RLOC...................................................................................... 4-40Architectures...................................................................... 4-40Description......................................................................... 4-40Syntax................................................................................ 4-40

RLOC_ORIGIN ....................................................................... 4-41Architectures...................................................................... 4-41

Pxxv

Syntax................................................................................ 4-41RLOC_RANGE ....................................................................... 4-42

Architectures...................................................................... 4-42Description......................................................................... 4-42Syntax................................................................................ 4-42

TNM ........................................................................................ 4-42Architectures...................................................................... 4-42Description......................................................................... 4-42Syntax................................................................................ 4-43

TSidentifier.............................................................................. 4-43Architectures...................................................................... 4-43Description......................................................................... 4-43Syntax................................................................................ 4-43

TTL ......................................................................................... 4-44Architectures...................................................................... 4-44Description......................................................................... 4-44Syntax................................................................................ 4-44

UIM_OPT................................................................................ 4-44Architectures...................................................................... 4-44Description......................................................................... 4-44Syntax................................................................................ 4-45

USE_RLOC ............................................................................ 4-45Architectures...................................................................... 4-45Description......................................................................... 4-45Syntax................................................................................ 4-45

U_SET .................................................................................... 4-45Architectures...................................................................... 4-45Description......................................................................... 4-45Syntax................................................................................ 4-46

PR Placement Constraints ........................................................ 4-46Schematic Syntax ................................................................... 4-46Constraints File Syntax........................................................... 4-47

Instances and Blocks......................................................... 4-47Place Instance Constraints ................................................ 4-48Place Block Constraints..................................................... 4-49Syntactical Conventions .................................................... 4-50

Libraries Guide

xxvi

Wildcards ........................................................................... 4-50Statements......................................................................... 4-51Place Constraints............................................................... 4-51Flag Constraints................................................................. 4-52Weight Constraints ............................................................ 4-52TIMESPEC Constraints ..................................................... 4-52TIMEGRP Constraints ....................................................... 4-54Xilinx Development System

Restrictions ........................................................................ 4-54Determining Symbol Names ................................................... 4-54Flip-Flop Constraints............................................................... 4-55

Example 1:......................................................................... 4-55Example 2:......................................................................... 4-55Example 3:......................................................................... 4-56Example 4:......................................................................... 4-56Example 5:......................................................................... 4-56Example 6:......................................................................... 4-56

ROM and RAM Constraints .................................................... 4-57Example 1:......................................................................... 4-57Example 2:......................................................................... 4-58Example 3:......................................................................... 4-58Example 4:......................................................................... 4-58

Mapping Constraints ............................................................... 4-59FMAP and HMAP Constraints ........................................... 4-59Example 1:......................................................................... 4-60Example 2:......................................................................... 4-61Example 3:......................................................................... 4-61Example 4:......................................................................... 4-61CLBMAP Constraints......................................................... 4-61Example 1:......................................................................... 4-63Example 2:......................................................................... 4-63

CLB Constraints...................................................................... 4-63Example 1:......................................................................... 4-63Example 2:......................................................................... 4-63Example 3:......................................................................... 4-64Example 4:......................................................................... 4-64

I/O Constraints ........................................................................ 4-64Example 1:......................................................................... 4-64Example 2:......................................................................... 4-65Example 3:......................................................................... 4-65Example 4:......................................................................... 4-66Example 5:......................................................................... 4-66

Libraries Guide

IOB Constraints ...................................................................... 4-67BUFT Constraints ................................................................... 4-67

Example 1:......................................................................... 4-68Example 2:......................................................................... 4-68Example 3:......................................................................... 4-68Example 4:......................................................................... 4-69

Edge Decoder Constraints...................................................... 4-69

R

RCxxvii

Global Buffer Constraints........................................................ 4-70elative Location (RLOC) Constraints......................................... 4-71

Description.............................................................................. 4-71Syntax..................................................................................... 4-72RLOC Sets.............................................................................. 4-74

U_SET ............................................................................... 4-75H_SET ............................................................................... 4-76Set Linkage........................................................................ 4-78Set Modification ................................................................. 4-80HU_SET ............................................................................ 4-82

Set Modifiers........................................................................... 4-85RLOC................................................................................. 4-86RLOC_ORIGIN.................................................................. 4-86RLOC_RANGE.................................................................. 4-89USE_RLOC ....................................................................... 4-90

Xilinx Macros .......................................................................... 4-93LOC Propagation Through Design Flattening......................... 4-94Summary ................................................................................ 4-94

elationally Placed Macros (RPMs) ............................................ 4-96arry Logic in XC4000 LCAs ....................................................... 4-97

Primitives and Symbols .......................................................... 4-98Carry Logic Handling in XNFPrep........................................... 4-100Carry Mode Configuration Mnemonics ................................... 4-101Carry Logic Configurations ..................................................... 4-102

ADD-F-CI ........................................................................... 4-102ADD-FG-CI ........................................................................ 4-103ADD-G-F1.......................................................................... 4-103ADD-G-CI .......................................................................... 4-104ADD-G-F3- ........................................................................ 4-104SUB-F-CI ........................................................................... 4-105SUB-FG-CI ........................................................................ 4-105SUB-G-1 ............................................................................ 4-106SUB-G-F1.......................................................................... 4-106SUB-G-CI .......................................................................... 4-107

Libraries Guide

xxviii

SUB-G-F3-......................................................................... 4-107ADDSUB-F-CI.................................................................... 4-108ADDSUB-FG-CI................................................................. 4-108ADDSUB-G-F1 .................................................................. 4-109ADDSUB-G-CI ................................................................... 4-110ADDSUB-G-F3- ................................................................. 4-110INC-F-CI ............................................................................ 4-111

Index ................Trademark InXilinx Development System

INC-FG-CI.......................................................................... 4-111INC-G-1 ............................................................................. 4-112INC-G-F1 ........................................................................... 4-112INC-G-CI............................................................................ 4-113INC-G-F3- .......................................................................... 4-113INC-FG-1 ........................................................................... 4-114DEC-F-CI ........................................................................... 4-114DEC-FG-CI ........................................................................ 4-115DEC-G-0 ............................................................................ 4-115DEC-G-F1.......................................................................... 4-116DEC-G-CI .......................................................................... 4-116DEC-G-F3-......................................................................... 4-117DEC-FG-0.......................................................................... 4-117INCDEC-F-CI..................................................................... 4-118INCDEC-FG-CI .................................................................. 4-118INCDEC-G-0...................................................................... 4-119INCDEC-G-F1.................................................................... 4-119INCDEC-G-CI .................................................................... 4-120INCDEC-FG-1.................................................................... 4-120FORCE-0 ........................................................................... 4-121FORCE-1 ........................................................................... 4-121FORCE-F1......................................................................... 4-121FORCE-CI ......................................................................... 4-121FORCE-F3-........................................................................ 4-121EXAMINE-CI...................................................................... 4-122

.................................................................................................... i

formation

Libraries Guide

Chapter 1

Xilinx Unified Libraries

Overview 0401410 01 1-1

Xilinx maintains software libraries with thousands of functionaldesign elements (primitives and macros) for different devicearchitectures. New functional elements are assembled with eachrelease of development system software. The latest catalog of designelements are known as Unified Libraries. Elements in theselibraries are common to all Xilinx device architectures. This unifiedapproach means that you can use your circuit design created withunified library elements across all current Xilinx devicearchitectures that recognize the element you are using.

Elements that exist in multiple architectures look and function thesame, but their implementations might differ to make them more effi-cient for a particular architecture. A separate library still exists foreach architecture and common symbols are duplicated in each one,which is necessary for simulation (especially board level) wheretiming depends on a particular architecture.

Note: OrCAD symbols differ in appearance. They do not supportbusing; each input and output pin appears on the symbol. Inputs andoutputs only appear on the left and right sides of symbols, respec-tively (none appear on the top or bottom).

If you have active designs that were created with former Xilinxlibrary primitives or macros, you may need to change references tothe design elements that you were using to reflect the new UnifiedLibraries elements.

The XACT Libraries Guide describes the primitive and macro logicelements available in the new Unified Libraries for XC2000, XC3000,XC4000, and XC7000 architectures. Common logic functions can be

Libraries Guide

1-2

implemented with these elements and more complex functions can bebuilt by combining macros and primitives. Several hundred designelements (primitives and macros) are available across multiple devicearchitectures, providing a common base for programmable logicdesigns.

This libraries guide provides a functional selection guide, describes

Xilin

Selec

DesiXilinx Development System

the design elements, and addresses attributes, constraints, and carrylogic.

This book is organized into four parts.

l Xilinx Unified Libraries

l Selection guide

l Design elements

l Constraints, attributes, and carry logic

x Unified LibrariesThis chapter describes the Unified Libraries, briefly discusses thecontents of the other chapters, the general naming conventions, andperformance issues.

tion GuideThe Selection Guide briefly describes, then tabularly lists the macrologic elements that are described in detail in the Design Elementschapter. The tables included in this section are organized into func-tional categories specifying all the available elements from each of theXC2000, XC3000, XC4000, and XC7000 families. Also included aretables that list Unified Libraries replacements for existing and obso-lete elements for each family.

gn ElementsDesign elements are organized in alphanumeric order, with allnumeric suffixes in ascending order. For example, ADD4 precedesADD8 and FDR precedes FDRS.

The following information is provided for each library element.

l Graphic symbol

l Functional description


Libraries Guide

l Primitive versus macro table

l Truth table (when applicable)

l Topology (when applicable)

l Schematic for macros

Note: Schematics are included for each architecture if the implemen-

Attri1-3

tation differs. Also, design elements with bused or multiple I/O pinstypically include just one schematic generally the 8-bit version. (Incases where no 8-bit version exists, an appropriate smaller or largerelement serves as the schematic example.)

butes, Constraints, and Carry LogicThe Attributes, Constraints, and Carry Logic chapter providesinformation on all attributes and constraints. Attributes are instruc-tions placed on symbols or nets in a schematic to indicate their place-ment, implementation, naming, directionality, and so forth.Constraints are a type of attribute used only to indicate where anelement should be placed. The chapter describes Partition, Place, andRoute (PPR) constraints, in particular, the relative location (RLOC)constraint, as well as Relationally Placed Macros (RPMs), and carrylogic.

Libraries Guide

1-4

Naming ConventionsExamples of the general naming conventions for the Unified Librariesare shown in the following figures.

Example 1Xilinx Development System

Figure 1-1 Naming Conventions

Figure 1-2 Combinatorial Naming Conventions

Refer to the Selection Guide for examples of functional componentnaming conventions.

X4565

Clear (Asynchronous)4-BitCounter, Binary

Precendence of Control Pins

LoadClock EnableBi-Directional

C B 4 C L E D

CONTROL PINSSIZEFUNCTION

Example 2

16-BitFlip-Flop, D-type

Precendence of Control Pins

Reset (Synchronous)Clock Enable

F D 1 6 R E

CONTROL PINSSIZEFUNCTION

X4316

AND3B2Logic Function

Number of InputsInverting (Bubble) Inputs

Number of Inverting Inputs


Libraries Guide

Flip-Flop, Counter, and Register PerformanceAll counter, register, and storage functions are derived from the flip-flops (and latches in XC2000) available in the Configurable LogicBlocks (CLBs).

The D flip-flop is the basic building block for all four architectures.1-5

Differences occur from the availability of asynchronous Clear (CLR)and Preset (PRE) inputs, and the source of the synchronous controlsignals, such as, Clock Enable (CE), Clock (C), Load enable (L),synchronous Reset (R), and synchronous Set (S). The basic flip-flopconfiguration for each architecture follows.

The basic XC2000 and XC7000 flip-flops have both Clear and Presetinputs.

The XC3000 has a direct-connect Clock Enable input and a Clearinput.

The XC4000 has a direct-connect Clock Enable input and a choice ofeither the Clear or the Preset inputs, but not both.

QD

C

FDCP

PRE

CLR X4397

X3717CLR

CCE

QD FDCE

X3717CLR

CCE

QD FDCE

X3721

FDPE

CCE

QD

PRE

Libraries Guide

1-6

The asynchronous and synchronous control functions, when used,have a priority that is consistent across all devices and architectures.These inputs can be either active-High or active-Low as defined bythe macro. The priority, from highest to lowest is as follows.

l Asynchronous Clear (C)

l Asynchronous Preset (PRE)Xilinx Development System

l Synchronous Set (S)

l Synchronous Reset (R)

l Load Enable (L)

l Shift Left/Right (LEFT)

l Clock Enable (CE)

Note: The asynchronous C and PRE inputs, by definition, have prior-ity over all the synchronous control and clock inputs.

The Clock Enable (CE) function is implemented using two differentmethods in the Xilinx Unified Libraries; both are shown in thefollowing figure. In method 1, CE is implemented by connecting theCE pin of the macro directly to the dedicated Enable Clock (EC) pin ofthe internal Configurable Logic Block (CLB) flip-flop. In method 2,CE is implemented using function generator logic. CE takes prece-dence over the L, S, and R inputs in method 1. CE has the samepriority as the L, S, and R inputs in method 2. The method used in aparticular macro is indicated in the macros description.


Libraries Guide

EC

CE

C C

C1C2

CEC1

C2

QFunction

GeneratorFunction

Generator1-7

Figure 1-3 Clock Enable Implementation MethodsX4675

Method 1CE implemented

using dedicated EC pin.

Method 2CE implemented as a

function generator input.

EC

C C

C1C2

C1

C2

CE QFunction

GeneratorFunction

Generator

Libraries Guide

1-8 Xilinx Development System

Libraries Guide

Chapter 2

Selection Guide 0401410 01 2-1

The Selection Guide briefly describes, then tabularly lists the macrologic elements that are described in detail in the Design Elementschapter. The tables included in this section are organized into func-tional categories specifying all the available macros from each of theXC2000, XC3000, XC4000, and XC7000 families. The tables categorizethe elements into sub-categories based on similar functions. Thesequence of each sub-category is based on an ascending order ofcomplexity. The categories are as follows.

l Arithmetic functions

l Buffers

l Comparators

l Counters

l Data registers

l Decoders

l Edge decoders

l Encoders

l Flip-Flops

l General

l Input/output flip-flops

l Input/output functions

l Input latches

l Latches

l Logic primitives

l Map elements

l Memory elements

Libraries Guide

2-2

l Multiplexers

l PLD elements

l Shift registers

l Shifters

The elements from each architecture that provide the same function

FunctionaXilinx Development System

are listed adjacent to each other in the table, even though they mightnot have the same name. For particular elements, use the name speci-fied for the architecture of interest.

Note: When converting your design between FPGA families, usemacros that have equivalent functions in each of the families to mini-mize re-designing.

There are a number of standard TTL 7400-type functions in theXC2000, XC3000, XC4000, and XC7000 architectures. All 7400-typefunctions are in alphanumeric order starting with X, and thenumeric sequence uses ascending numbers following the 74 prefix.For example, X74_42 precedes X74_138.

l CategoriesThe following sections briefly describe, then tabularly list the UnifiedLibraries design element functions by category. Elements are listed inalphanumeric order according to architecture in each applicablearchitecture column. N/A means the element does not exist in thatparticular architecture.

Following these functional listings, replacement and obsoleteelements are discussed.

Selection Guide

Libraries Guide

Arithmetic FunctionsThere are three types of arithmetic functions: accumulators (ACC),adders (ADD), and adder/subtracters (ADSU). With an ADSU, eitherunsigned binary or twos-complement operations cause an overflow.If the result crosses the overflow boundary, an overflow is generated.Similarly, when the result crosses the carry-out boundary, a carry-out

XC2000 XC3ACC1 N/A

N/A N/A

N/A N/A

N/A ACC

N/A N/A

N/A N/A

N/A ACC2-3

is generated. The following figure shows the ADSU carry-out andoverflow boundaries.

Figure 2-1 ADSU Carry-Out and Overflow Boundaries

000 XC4000 XC7000 DescriptionN/A ACC1 1-Bit Accumulator with Carry-In,

Carry-Out, and Synchronous ResetN/A ACC1X1 1-Bit Accumulator with Carry-Out for

EPLDN/A ACC1X2 1-Bit Accumulator with Carry-In and

Carry-Out for EPLD4 ACC4 ACC4 4-Bit Accumulator with Carry-In,



Carry-Out for EPLD8 ACC8 ACC8 8-Bit Accumulator with Carry-In,

Carry-Out, and Synchronous Reset

TWOS

COM

PLEMEN

TO

RSIGNEDTW

OSCO

MPL

EMEN

TO

RSI

GNED

UNSI

GNED

BIN

ARY

UNSIGN

EDB

INARY

X4720

255

-127 127

127128

00-1

Overflow

Carry-Out

Libraries Guide

2-4

N/A N/A N/A ACC8X1 8-Bit Accumulator with Carry-Out forEPLD

N/A N/A N/A ACC8X2 8-Bit Accumulator with Carry-In andCarry-Out for EPLD

N/A ACC16 ACC16 ACC16 16-Bit Accumulator with Carry-In,

N/A N/A

N/A N/A

ADD1 N/A

N/A N/AN/A N/A

N/A ADD

N/A N/AN/A N/A

N/A ADD

N/A N/AN/A N/A

N/A ADD

N/A N/AN/A N/A

ADSU1 N/A

N/A N/A

N/A N/A

N/A ADS

XC2000 XC3000 XC4000 XC7000 DescriptionXilinx Development System



Carry-Out for EPLDN/A ADD1 1-Bit Full Adder with Carry-In and

Carry-OutN/A ADD1X1 1-Bit Adder with Carry-Out for EPLDN/A ADD1X2 1-Bit Adder with Carry-In and Carry-

Out for EPLD4 ADD4 ADD4 4-Bit Cascadable Full Adder with

Carry-In and Carry-OutN/A ADD4X1 4-Bit Adder with Carry-Out for EPLDN/A ADD4X2 4-Bit Adder with Carry-In and

Carry-Out for EPLD8 ADD8 ADD8 8-Bit Cascadable Full Adder with


Carry-Out for EPLD16 ADD16 ADD16 16-Bit Cascadable Full Adder with


Carry-Out for EPLDN/A ADSU1 1-Bit Adder/Substracter with Carry-In

and Carry-OutN/A ADSU1X1 1-Bit Adder/Subtracter with

Carry-Out for EPLDN/A ADSU1X2 1-Bit Adder/Subtracter with Carry-In

and Carry-Out for EPLDU4 ADSU4 ADSU4 4-Bit Cascadable Adder/Subtracter

with Carry-In and Carry-Out

Selection Guide

Libraries Guide

Buffe

N/A N/A N/A ADSU4X1 4-Bit Adder/Subtracter withCarry-Out for EPLD

N/A N/A N/A ADSU4X2 4-Bit Adder/Subtracter with Carry-Inand Carry-Out for EPLD

N/A ADSU8 ADSU8 ADSU8 8-Bit Adder/Subtracter with Carry-In,

N/A N/A

N/A N/A

N/A ADS

N/A N/A

N/A N/A

X74_280 X74_

X74_283 X74_

XC2000 XACLK ACBUF BUN/A N/

N/A N/

XC2000 XC3000 XC4000 XC7000 Description2-5

rsThe buffers in this section route high fan-out signals, 3-state signals,and clocks inside a PLD device. The Input/Output Functionssection later in this chapter covers off-chip interface buffers.

Carry-Out, and OverflowN/A ADSU8X1 8-Bit Adder/Subtracter with

Carry-Out for EPLDN/A ADSU8X2 8-Bit Adder/Subtracter with Carry-In

and Carry-Out for EPLDU16 ADSU16 ADSU16 16-Bit Adder/Subtracter with

OverflowN/A ADSU16X1 16-Bit Adder/Subtracter with

Carry-Out for EPLDN/A ADSU16X2 16-Bit Adder/Subtracter with

Carry-In and Carry-Out for EPLD280 X74_280 X74_280 9-Bit Odd/Even Parity Generator/

Checker283 X74_283 X74_283 4-Bit Full Adder with Carry-In and

Carry-Out

C3000 XC4000 XC7000 DescriptionLK N/A N/A Alternate Clock BufferF BUF BUF General Purpose BuffersA N/A BUF4,

BUF8,BUF16

A N/A BUFCE Global Clock-Enable Input Bufferfor EPLD

Libraries Guide

2-6

Com

N/A BUFE,BUFE4,BUFE8,BUFE16

BUFE,BUFE4,BUFE8,BUFE16

BUFE,BUFE4,BUFE8,BUFE16

Internal 3-State Buffers withActive-High Enable

N/A N/A N/A BUFFOE Global Fast-Output-Enable (FOE)

BUFG BUN/A N/

N/A N/

N/A N/N/A BU

BUBUBU

GCLK GC

XC2000 XCOMP2 COCOMP4 COCOMP8 COCOMP16 COCOMPM2 COCOMPM4 COCOMPM8 COCOMPM16 CON/A N/N/A N/X74_L85 X74

XC2000 XC3000 XC4000 XC7000 DescriptionXilinx Development System

paratorsThere are two types of comparators, identity (COMP) and magnitude(COMPM).

Input Buffer for EPLDFG BUFG BUFG Global Clock BufferA BUFGP BUFGP Primary Global Buffer for Driving

Clocks or Longlines (4 per device)A BUFGS BUFGS Secondary Global Buffer for Driv-

ing Clocks or LonglinesA BUFOD N/A Open-Drain BufferFT,FT4,FT8,FT16

BUFT,BUFT4,BUFT8,BUFT16

BUFT,BUFT4,BUFT8,BUFT16

Internal 3-State Buffers withActive-Low Enable

LK N/A N/A Global Clock Buffer

C3000 XC4000 XC7000 DescriptionMP2 COMP2 COMP2 2-Bit Identity ComparatorMP4 COMP4 COMP4 4-Bit Identity ComparatorMP8 COMP8 COMP8 8-Bit Identity ComparatorMP16 COMP16 COMP16 16-Bit Identity ComparatorMPM2 COMPM2 COMPM2 2-Bit Magnitude ComparatorMPM4 COMPM4 COMPM4 4-Bit Magnitude ComparatorMPM8 COMPM8 COMPM8 8-Bit Magnitude ComparatorMPM16 COMPM16 N/A 16-Bit Magnitude ComparatorA COMPMC8 N/A 8-Bit Magnitude ComparatorA COMPMC16 N/A 16-Bit Magnitude Comparator_L85 X74_L85 X74_L85 4-Bit Expandable Magnitude

Comparator

Selection Guide

Libraries Guide

Coun

X74_518 X74_518 X74_518 X74_518 8-Bit Identity Comparator withActive-Low Enable

X74_521 X74_521 X74_521 X74_521 8-Bit Identity Comparator withActive-Low Enable and Output

XC2000 XC3000 XC4000 XC7000 Description2-7

tersThere are six types of counters with various synchronous and asyn-chronous inputs. The name of the counter defines the modulo or bitsize, the counter type, and which control functions are included. Thecounter naming convention is shown in the following figure.

Figure 2-2 Counter Naming Convention

A carry-lookahead design accommodates large counters withoutextra gating. On TTL 7400-type counters with trickle clock enable(ENT), parallel clock enable (ENP), and ripple carry-out (RCO), boththe ENT and ENP inputs must be High to count. ENT is propagatedforward to enable RCO, which produces a High output with theapproximate duration of the QA output. The following figure illus-trates a carry-lookahead design.

X4577

Binary (B)BCD (D)Binary, Carry Logic (C)Johnson (J)Ripple (R)

Counter

Asynchronous Clear (C)Synchronous Reset (R)Modulo (Bit Size)

Loadable

C B 1 6 C L E D

Clock Enable

Directional

Libraries Guide

2-8

ENTEN

Documents

Library