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Service Manual
Mo
del : U
8110
Service ManualU8110
P/N : MMBD0032201 Date: May, 2004 / Issue 1.0
- 3 -
1. INTRODUCTION .............................. 6
1.1 Purpose................................................... 6
1.2 Regulatory Information............................ 6
1.3 Abbreviations .......................................... 8
2. PERFORMANCE............................ 10
2.1 System Overview.................................. 10
2.2 Usable environment .............................. 11
2.3 Radio Performance ............................... 11
2.4 Current Consumption............................ 17
2.5 RSSI...................................................... 17
2.6 Battery Bar ............................................ 17
2.7 Sound Pressure Level........................... 18
2.8 Charging ............................................... 19
3. Technical Brief .............................. 20
3.1 Digital Baseband(DBB)&
Multimedia Processor ........................... 20
3.1.1 General Description ........................ 20
3.1.2 Hardware Architecture .................... 21
3.1.3 External memory interface.............. 25
3.1.4 RF Interface .................................... 26
3.1.5 SIM Interface .................................. 28
3.1.6 UART Interface ............................... 28
3.1.7 GPIO (General Purpose Input/Output)
map................................................. 29
3.1.8 USB ................................................ 31
3.1.9 IrDA Interface.................................. 33
3.1.10 Folder ON/OFF Operation ............ 34
3.1.11 Power On Sequence..................... 35
3.1.12 Key Pad ........................................ 36
3.2 GAM Hardware Subsystem .................. 37
3.2.1 General Description ........................ 37
3.2.2 Block Description ............................ 38
3.2.3 Camera & Camera FPC Interface... 40
3.2.4 Camera Position Detection ............. 42
3.2.5 Camera Regulator .......................... 42
3.2.6 Display & LCD FPC Interface ......... 43
3.2.7 Main LCD Backlight Illumination ..... 46
3.2.8 Sub LCD Backlight Illumination ...... 47
3.2.9 Keypad Illumination ........................ 48
3.2.10 Camera Flash Illumination ............ 49
3.3 LCD Module .......................................... 50
3.4 Analog Baseband (ABB) Processor...... 51
3.4.1 Overview of Audio path................... 51
3.4.2 Audio Signal Processing &
Interface.......................................... 52
3.4.3 Audio Mode..................................... 54
3.4.4 Voice Call........................................ 55
3.4.5 MIDI (Ring Tone Play) .................... 59
3.4.6 MP3 (Audio Player)......................... 60
3.4.7 Video Telephony............................. 61
3.4.8 Audio Main Component .................. 62
3.4.9 GPADC(General Purpose ADC) and
AUTOADC2 .................................... 64
3.4.10 Charger control ............................. 65
3.4.11 Fuel Gauge ................................... 66
3.4.12 Battery Temperature
Measurement ................................ 67
3.4.13 Charging Part................................ 68
3.5 Voltage Regulation ............................... 71
3.5.1 Internal Regulation.......................... 71
3.5.2 External Regulation ........................ 71
3.6 General Description .............................. 73
3.7 GSM Mode............................................ 75
3.7.1 Receiver.......................................... 75
3.7.2 Transmitter...................................... 80
3.8 WCDMA Mode ...................................... 82
3.8.1 Receiver.......................................... 82
Table Of Contents
Table Of Contents
- 4 -
3.8.2 Transmitter...................................... 85
3.8.3 Frequency Generation .................... 89
4. TROUBLE SHOOTING .................. 91
4.1 Power ON Trouble ................................ 91
4.2 USB Trouble ......................................... 93
4.3 SIM Detect Trouble ............................... 94
4.4 Keypad Trouble..................................... 95
4.5 Camera Trouble .................................... 96
4.6 Main LCD Trouble................................. 98
4.7 Sub LCD Trouble .................................. 99
4.8 Keypad Backlight Trouble ................... 100
4.9 Folder ON/OFF Trouble ...................... 102
4.10 Camera Detection Trouble................ 104
4.11 Camera Flash Trouble ...................... 106
4.12 Audio Trouble Shooting .................... 108
4.13 Charger Trouble Shooting................. 123
4.14 RF Component.................................. 126
4.15 Procedure to check ........................... 128
4.16 Checking Common
Power Source Block.......................... 129
4.16.1 Step 1 ......................................... 130
4.16.2 Step 2 ......................................... 131
4.16.3 Step 3 ......................................... 132
4.16.4 Step 4 ......................................... 133
4.16.5 Checking Regular Part................ 136
4.17 Checking VCXO Block ...................... 137
4.18 Checking Ant. SW Module Block ...... 142
4.19 Checking Antenna Switch Block
input logic.......................................... 143
4.19.1 Mode Logic by TP Command ..... 143
4.19.2 Checking Switch Block
power source .............................. 145
4.20 Checking WCDMA Block .................. 151
4.20.1 Checking..................................... 152
4.20.2 Checking Ant. SW module.......... 152
4.20.3 Checking Control Signal ............. 152
4.20.4 Checking RF TX Level ................ 155
4.20.5 Checking PAM Block .................. 158
4.20.6 Checking RX I,Q ......................... 162
4.20.7 Checking RX Level ..................... 164
4.21 Checking GSM Block ........................ 166
4.21.1 Checking Regulator Circuit ........ 167
4.21.2 Checking VCXO Block ............... 167
4.21.3 Checking Ant. SW Module.......... 167
4.21.4 Checking Control Signal ............. 168
4.21.5 Checking RF Tx Path.................. 170
4.21.6 Checking RF Rx Path ................. 175
5. BLOCK DIAGRAM....................... 180
5.1 GSM & WCDMA RF Block.................. 180
5.2 Interface Diagram ............................... 182
5.3 Detailed Interface Signal..................... 184
6. DISASSEMBLY INSTRUCTION... 186
7. DOWNLOAD ................................ 194
8. CALIBRATION ............................. 207
8.1 General Description ............................ 207
8.2 XCALMON Environment ..................... 207
8.2.1 H/W Environment.......................... 207
8.2.2 S/W Environment .......................... 207
8.2.3 Configuration Diagram of
Calibration Environment................ 207
8.3 Calibration Explanation ....................... 208
8.3.1 Overview....................................... 208
8.3.2 Calibration Items........................... 208
8.3.3 EGSM 900 Calibration Items ........ 209
Table Of Contents
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8.3.4 DCS 1800 Calibration Items ......... 214
8.3.5 WCDMA Calibration Items............ 217
8.3.6 Baseband Calibration Item ........... 225
8.4 Program Operation ............................. 226
8.4.1 XCALMON Program Overview ..... 226
8.4.2 XCALMON Icon Description ......... 227
8.4.3 Calibration Procedure ................... 230
8.4.4 Calibration Result Message.......... 232
9. CIRCUIT DIAGRAM ..................... 235
10. PCB LAYOUT............................. 244
11. EXPLODED VIEW &
REPLACEMENT PART LIST ..... 248
11.1 EXPLODED VIEW ............................ 248
11.2 Replacement Parts
<Mechanic component>.................... 249
<Main component> ........................... 252
11.3 Accessory ......................................... 271
1. INTRODUCTION
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1.1 Purpose
This manual provides the information necessary to repair, calibration, description and download thefeatures of this model.
1.2 Regulatory Information
A. Security
Toll fraud, the unauthorized use of telecommunications system by an unauthorized part (for example,persons other than your company’s employees, agents, subcontractors, or person working on yourcompany’s behalf) can result in substantial additional charges for your telecommunications services.System users are responsible for the security of own system. There are may be risks of toll fraudassociated with your telecommunications system. System users are responsible for programming andconfiguring the equipment to prevent unauthorized use. The manufacturer does not warrant that thisproduct is immune from the above case but will prevent unauthorized use of common-carriertelecommunication service of facilities accessed through or connected to it. The manufacturer will notbe responsible for any charges that result from such unauthorized use.
B. Incidence of Harm
If a telephone company determines that the equipment provided to customer is faulty and possiblycausing harm or interruption in service to the telephone network, it should disconnect telephoneservice until repair can be done. A telephone company may temporarily disconnect service as long asrepair is not done.
C. Changes in Service
A local telephone company may make changes in its communications facilities or procedure. If thesechanges could reasonably be expected to affect the use of the phones or compatibility with thenetwork, the telephone company is required to give advanced written notice to the user, allowing theuser to take appropriate steps to maintain telephone service.
D. Maintenance Limitations
Maintenance limitations on the phones must be performed only by the manufacturer or its authorizedagent. The user may not make any changes and/or repairs expect as specifically noted in this manual.Therefore, note that unauthorized alternations or repair may affect the regulatory status of the systemand may void any remaining warranty.
1. INTRODUCTION
1. INTRODUCTION
- 7 -
E. Notice of Radiated Emissions
This model complies with rules regarding radiation and radio frequency emission as defined by localregulatory agencies. In accordance with these agencies, you may be required to provide informationsuch as the following to the end user.
F. Pictures
The pictures in this manual are for illustrative purposes only; your actual hardware may look slightlydifferent.
G. Interference and Attenuation
A phone may interfere with sensitive laboratory equipment, medical equipment, etc.Interference from unsuppressed engines or electric motors may cause problems.
H. Electrostatic Sensitive Devices
ATTENTION
Boards, which contain Electrostatic Sensitive Device (ESD), are indicated by the sign.Following information is ESD handling:
• Service personnel should ground themselves by using a wrist strap when exchange system boards.• When repairs are made to a system board, they should spread the floor with anti-static mat which is
also grounded.• Use a suitable, grounded soldering iron.• Keep sensitive parts in these protective packages until these are used.• When returning system boards or parts like EEPROM to the factory, use the protective package as
described.
1. INTRODUCTION
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1.3 Abbreviations
For the purposes of this manual, following abbreviations apply:
APC Automatic Power Control
BB Baseband
BER Bit Error Ratio
CC-CV Constant Current – Constant Voltage
CLA Cigar Lighter Adapter
DAC Digital to Analog Converter
DCS Digital Communication System
dBm dB relative to 1 milliwatt
DSP Digital Signal Processing
DTC DeskTop Charger
EEPROM Electrical Erasable Programmable Read-Only Memory
EL Electroluminescence
ESD Electrostatic Discharge
FPCB Flexible Printed Circuit Board
GMSK Gaussian Minimum Shift Keying
GPIB General Purpose Interface Bus
GPRS General Packet Radio Service
GSM Global System for Mobile Communications
IPUI International Portable User Identity
IF Intermediate Frequency
LCD Liquid Crystal Display
LDO Low Drop Output
LED Light Emitting Diode
OPLL Offset Phase Locked Loop
PAM Power Amplifier Module
PCB Printed Circuit Board
PGA Programmable Gain Amplifier
PLL Phase Locked Loop
1. INTRODUCTION
- 9 -
PSTN Public Switched Telephone Network
RF Radio Frequency
RLR Receiving Loudness Rating
RMS Root Mean Square
RTC Real Time Clock
SAW Surface Acoustic Wave
SIM Subscriber Identity Module
SLR Sending Loudness Rating
SRAM Static Random Access Memory
UMTS Universal Mobile Telephony System
2. PERFORMANCE
- 10 -
2.1 System Overview
2. PERFORMANCE
Item Specification
Shape GSM900/1 800 & WCDMA Folder- Dual Mode Handset
Size 49.5 x 95.7 x 22.5 mm
Weight 120g (with Battery)
Power 4.0V > 1200mAh Li-Ion
Talk TimeOver 140 Min (WCDMA, Tx=12 dBm, Voice)
Over 180 Min (GSM, Tx=Max, Voice)
Standby TimeOver 120 hrs (WCDMA, DRX=1.28)
Over 1 50 hrs (GSM, Paging period=9)
Antenna Fixed Type (Fixed Screw)
LCD 176 x 220 Pixel
Main LCD BL White LED Back Light
Sub LCD BL 7-color LED
Vibrator Yes (Coin Type)
LED Indicator 7-color(Sub LCD BL)
C-MIC Yes
Receiver Yes
Earphone Jack Yes
SIM Socket Yes (3.0V/1.8V)
Volume Key Push Type(+,-)
Voice Key Push Type (Memo)
I/O Connect 24 Pin
2. PERFORMANCE
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2.2 Usable environment
1) Environment
2) Environment(Accessory)
* CLA: 12~24V(DC)
2.3 Radio Performance
1) Transmitter -GSM Mode
Item Spec. Unit
Voltage 4.0 (Typ), 3.4 (Min), (Shut Down: 3.2) V
Size -20 ~ + 60 °C
Storage -30 ~ + 85 °C
Humidity max. 85 %
Item Spec. Min Typ. Max Unit
Power Available power 100 220 240 Vac
No Item GSM DCS
100k ~ 1GHz -39dBm9k ~ 1GHz -39dBm
MS allocated 1G ~ 1710MHz -33dBm
Channel1G ~ 12.75GHz -33dBm
1710M ~ 1785MHz -39dBm
Conducted 1785M ~ 12.75GHz -33dBm
1 Spurious 100k ~ 880MHz -60dBm 100k ~ 880MHz -60dBm
Emission 880M ~ 915MHz -62dBm 880M ~ 915MHz -62dBm
Idle Mode915M ~ 1000Mz -60dBm 915M ~ 1000MHz -60dBm
1G ~ 1.71GHz -50dBm 1G ~ 1.71GHz -50dBm
1.71G ~ 1.785GHz -56dBm 1.71G ~ 1.785GHz -56dBm
1.785G ~ 12.75GHz -50dBm 1.785G ~ 12.75GHz -50dBm
2. PERFORMANCE
- 12 -
No Item GSM DCS
30M ~ 1GHz -36dBm30M ~ 1GHz -36dBm
MS allocated 1G ~ 1710MHz -30dBm
Channel1G ~ 4GHz -30dBm
1710M ~ 1785MHz -36dBm
Radiated 1785M ~ 4GHz -30dBm
1 Spurious 30M ~ 880MHz -57dBm 30M ~ 880MHz -57dBm
Emission 880M ~ 915MHz -59dBm 880M ~ 915MHz -59dBm
Idle Mode915M ~ 1000Mz -57dBm 915M ~ 1000MHz -57dBm
1G ~ 1.71GHz -47dBm 1G ~ 1.71GHz -47dBm
1.71G ~ 1.785GHz -53dBm 1.71G ~ 1.785GHz -53dBm
1.785G ~ 4GHz -47dBm 1.785G ~ 4GHz -47dBm
2 Frequency Error ±0.1ppm ±0.1ppm
3 Phase Error±5(RMS) ±5(RMS)
±20(PEAK) ±20(PEAK)
3dB below reference sensitivity 3dB below reference sensitivity
Frequency Error Under RA250: ±200Hz RA250: ±250Hz
4 Multipath and Interference HT100: ±100Hz HT100: ±250Hz
Condition TU50: ±100Hz TU50: ±150Hz
TU3: ±150Hz TU1.5: ±200Hz
0 ~ 100kHz +0.5dB 0 ~ 100kHz +0.5dB
200kHz -30dB 200kHz -30dB
250kHz -33dB 250kHz -31dB
Due to 400kHz -60dB 400kHz -33dB
Output RFmodulation 600 ~ 1800kHz -66dB 600 ~ 1800kHz -60dB
5 1800 ~ 3000kHz -69dB 1800 ~ 6000kHz -60dBSpectrum
3000 ~ 6000kHz -71dB ≥6000kHz -73dB
≥6000kHz -77dB
Due to400kHz -19dB 400kHz -22dB
Switching600kHz -21dB 600kHz -24dB
transient1200kHz -21dB 1200kHz -24dB
1800kHz -24dB 1800kHz -27dB
2. PERFORMANCE
- 13 -
No Item GSM DCS
Frequency offset 800kHz
7 Intermodulation attenuation –Intermodulation product should
be Less than 55dB below the
level of Wanted signal
Power control Power Tolerance Power control Power Tolerance
Level (dBm) (dB) Level (dBm) (dB)
5 33 ±3 0 30 ±3
6 31 ±3 1 28 ±3
7 29 ±3 2 26 ±3
8 27 ±3 3 24 ±3
9 25 ±3 4 22 ±3
10 23 ±3 5 20 ±3
8 Transmitter Output Power 11 21 ±3 6 18 ±3
12 19 ±3 7 16 ±3
13 17 ±3 8 14 ±3
14 15 ±3 9 12 ±4
15 13 ±3 10 10 ±4
16 11 ±5 11 8 ±4
17 9 ±5 12 6 ±4
18 7 ±5 13 4 ±4
19 5 ±5 14 2 ±5
15 0 ±5
9 Burst timing Mask IN Mask IN
2. PERFORMANCE
- 14 -
2) Transmitter-WCDMA Mode
No Item Specification
1 Maximum Output PowerClass3: +24dBm(+1/-3dB)
Class4: +21dBm(±2dB)
2 Frequency Error ±0.1ppm
3 Open Loop Power control in uplink ±9dB@normal, ±12dB@extreme
Adjust output(TPC command)
cmd 1dB 2dB 3dB
+1 +0.5/1.5 +1/3 +1.5/4.5
4 Inner Loop Power control in uplink 0 -0.5/+0.5 -0.5/+0.5 -0.5/+0.5
-1 -0.5/-1.5 -1/-3 -1.5/-4.5
group(10equal command group)
+1 +8/+12 +16/+24
5 Minimum Output Power -50dBm(3.84MHz)
Qin/Qout:DPCCH quality levels
6 Out-of-synchronization handling of output power Toff@DPCCH/lor:-22->-28dB
Ton@DPCCH/lor:-24->-18dB
7 Transmit OFF Power -56dBm(3.84M)
8 Transmit ON/OFF Time Mask±25us
PRACH, CPCH, uplink compressed mode
±25us
9 Change of TFCpower varies according to the data rate
DTX: DPCH off
(minimize interference between UE)
10 Power setting in uplink compressed ±3dB(after 14slots transmission gap)
11 Occupied Bandwidth(OBW) 5MHz(99%)
-35-15*(∆f-2.5)dBc@∆f=2.5~3.5MHz, 30k
12 Spectrum emission Mask-35-1*(∆f-3.5)dBc@∆f=3.5~7.5MHz, 1M
-39-10*(∆f-7.5)dBc@∆f=7.5~8.5MHz, 1M
-49 dBc@∆f=8.5~12.5MHz, 1M
2. PERFORMANCE
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3)Receiver - GSM Mode
No Item Specification
13 Adjacent Channel Leakage Ratio(ACLR)33dB@5MHz, ACP>-50dBm
43dB@10MHz, ACP>-50dBm
-36dBm@f=9~150KHz, 1k BW
-36dBm@f=150KHz~30MHz, 10k
-36dBm@f=30~1000MHz, 100k
14Spurious Emissions -30dBm@f=1~12.75GHz, 1M
*: additional requirement -41dBm*@1893.5~1919.6MHz, 300k
-67dBm*@925~935MHz, 100k
-79dBm*@935~960MHz, 100k
-71dBm*@1805~1880MHz, 100k
15 Transmit Intermodulation-31dBc@5MHz, Interferer -40dBc
-41dBc@10MHz, Interferer -40dBc
16 Error Vector Magnitude(EVM)17.5% (>-20dBm)
(@12.2k, 1DPDCH+1DPCCH)
17 Transmit OFF Power-15dB@SF=4, 768kbps, multi-code
transmission
No Item GSM DCS
1 Sensitivity (TCH/FS Class II) -105dBm -105dBm
2Co-Channel Rejection
C/Ic=7dB C/Ic=7dB(TCH/FS Class II, RBER, TUhigh/FH)
3 Adjacent Channel 200kHz C/Ia1=-12dB C/Ia1=-12dB
Rejection 400kHz C/Ia2=-44dB C/Ia2=-44dB
Wanted Signal: -98dBm Wanted Signal: -96dBm
4 Intermodulation Rejection 1’st interferer: -44dBm 1’st interferer: -44dBm
2’st interferer: -45dBm 2’st interferer: -44dBm
5Blocking Response Wanted Signal: -101dBm Wanted Signal: -101dBm
(TCH/FS Class II, RBER) Unwanted Signal: Depend on freq. Unwanted Signal: Depend on freq.
2. PERFORMANCE
- 16 -
4) Receiver - WCDMA Mode
No Item Specification
18 Reference Sensivitivity Level -106.7dBm(3.84M)
-25dBm(3.84MHz)
19 Maximum Input Level -44dBm/3.84MHz(DPCH_Ec)
UE@+20dBm output power(class3)
20 Adjacent Channel Selectivity(ACS)33dB
UE@+20dBm output power(class3)
-56dBm/3.84MHz@10MHz
21 In-band Blocking UE@+20dBm output power(class3)
-44dBm/3.84MHz@15MHz
UE@+20dBm output power(class3)
-44dBm/3.84MHz@f=2050~2095 &
2185~2230MHz, band a)
UE@+20dBm output power(class3)
-30dBm/3.84MHz@f=2025~2050 &
22 Out-band Blocking 2230~2255MHz, band a)
UE@+20dBm output power(class3)
-15dBm/3.84MHz@f=1~2025 &
2255~12500MHz, band a)
UE@+20dBm output power(class3)
23 Spurious Response-44dBm CW
UE@+20dBm output power(class3)
-46dBm CW@10MHz &
24 Intermodulation Characteristic -46dBm/3.84MHz@20MHz
UE@+20dBm output power(class3)
-57dBm@f=9KHz~1GHz, 100k BW
25 Spurious Emissions -47dBm@f=1~12.75GHz, 1M
-60dBm@f=1920~1980MHz, 3.84MHz
-60dBm@f=2110~2170MHz, 3.84MHz
2. PERFORMANCE
- 17 -
2.4 Current Consumption
(VT test : Speaker off, LCD backlight On)
2.5 RSSI
TBD
2.6 Battery Bar
Stand by Voice Call VT
WCDMA 120Hours=10mA 140Min=514mA 100Min=720mA
(DRX=1.28) (Tx=12dBm) (Tx=12dBm)
GSM 150Hours=8mA 180Min=400mA
(paging=9period) (Tx=Max)
GSM WCDMA(TBD)
BAR 4 → 3 -91 ±2dBm
BAR 3 → 2 -96 ±2dBm
BAR 2 → 1 -101 ±2dBm
BAR 1 → 0 -106 ±2dBm
Indication Voltage
BAR 4 → 3 (68%) 3.87 ±0.03V
BAR 3 → 2 (47%) 3.77 ±0.03V
BAR 2 → 1 (26%) 3.72 ±0.03V
BAR 1 → Icon Blinking (5%) 3.50 ±0.03V
Low voltage, warning message3.50 ±0.03V(Talk: 1min. interval) -5%
3.46 ±0.03V(Standby: 3min. Inverval) -3%
Power OFF3.10 ±0.03V ↓ (WCDMA Talk)
3.20 ±0.03V ↓ (else)
2. PERFORMANCE
- 18 -
2.7 Sound Pressure Level
No Test Item Specification
1 Sending Loudness Rating (SLR)NOM
8±3dBMAX
2 Receiving Loudness Rating (RLR)NOM -1±3dB
MAX -13±1dB
3 Side Tone Masking Rating (STMR)NOM
17dB overMAX
4 Echo Loss (EL)NOM
40dB overMAX
5 Sending Distortion (SD) refer to TABLE 30.3
6 Receiving Distortion (RD) refer to TABLE 30.4
7 Idle Noise-Sending (INS)NOM
-64dBm0p underMAX
8 Idle Noise-Receiving (INR)NOM -47dBPA under
MAX -36dBPA under
9 Sending Loudness Rating (SLR)NOM
8±3dBMAX
10 Receiving Loudness Rating (RLR)NOM -1±3dB
MAX -12±3dB
11 Side Tone Masking Rating (STMR)NOM
25dB overMAX
12 Echo Loss (EL)NOM
40dB overMAX
13 Sending Distortion (SD) refer to TABLE 30.3
14 Receiving Distortion (RD) refer to TABLE 30.4
15 Idle Noise-Sending (INS)NOM
-55dBm0p underMAX
16 Idle Noise-Receiving (INR)NOM -45dBPA under
MAX -40dBPA under
TDMA NOISEGSM
SEND
–.GSM: Power Level: 5MS
REV.
DCS: Power Level: 0DCS
SEND
17(Cell Power: -90 ~ -105dBm) REV.
-62dBm under–.Acoustic(Max Vol.)
GSMSEND
MS/HEADSET SLR: 8±3dBHeadset
REV.
MS/HEADSET RLR: -13±1dB/-15dBDCS
SEND
(SLR/RLR: mid-Value Setting) REV.
A
C
O
U
S
T
I
C
MS
HEAD
SET
2. PERFORMANCE
- 19 -
2.8 Charging
• Normal mode: Complete Voltage: 4.2VCharging Current: 600mA
• Await mode: In case of During a Call, should be kept 3.9V(GSM: It should be kept 3.9V in all power level WCDMA: It will not be kept 3.9V in some power level)
Extend await mode: At Charging prohibited temperature(-20C under or 60C over)(GSM: It should be kept 3.7V in all power level WCDMA: It will not be kept 3.7V in some power level)
3. TECHNICAL BRIEF
- 20 -
3.1 Digital Baseband(DBB) & Multimedia Processor
3.1.1 General Description
A. Features
• CPU ARM946 running at 104 MHz- 32 kB Instruction Cache, 16 kB Data Cache, 128 kB Instruction TCM and 128 kB Data TCM- 8 channel DMAC
• DSP C55x (LEAD3) Megastar (MGS3_2.0B) running at 170 MHz- 144 kWord ROM, 32 kWord DARAM, 32 kWord SARAM- 7 channel DMAC- Dedicated API channel to DSP memory (not locked up to other DMA channels)
• UMTS Access- Support for WCDMA/GSM Dual Mode- GSM/GPRS network signaling (from Layer 1 to 3)- WCDMA Ciphering and Integrity- High Speed Serial Link (HSSL) to the WCDMA Modem (at Layer 1)- GSM AMR- Multislot Class 8- HSCSD 14.4 kb/s
• MMI- Keypad Interface- Tone Generator Interface- Camera Data and Programmable Display Interfaces- Enhanced graphics support for QCIF display
• Operation and Services- I2C™ Interface- SIM Interfaces- General Purpose I/O (GPIO) Interface- External Memory Interface that supports FLASH, SRAM and PSRAM- JTAG- RTC- ETM (in Prototype Package)
• Data Communication- IrDA ® (SIR)- UARTs (ACB, EDB (RS232))- Slave USB
• Package- 12 by 12 mm 289 pin FPBGA Production Package
3. Technical Brief
3. TECHNICAL BRIEF
- 21 -
3.1.2 Hardware Architecture
The hardware structure is delivered as five separate hardware macros to the top-level design, alsodepicted in Figure.
Figure. Simplified Block Diagram
3. TECHNICAL BRIEF
- 22 -
A. Block Diagram
B. CPU Hardware Subsystem
The CPU subsystem incorporates: • CPU Sub chip • Backplane • JTAG • DMA Controller • System Buffer RAM • Boot ROM • External Memory Interface (EMIF) for connection to external SRAM and Flash memories.The bus architecture is built on the ARM AMBA standard with multi-layer AHB (Advanced High-speedBus) and APB (Advanced Peripheral Bus) for the peripheral buses.There are two AHB busses, the CPU AHB and the DMA AHB. Clocks to the CPU subsystem are distributed from the system control (SYSCON) backplane clocking.The reset lines are all asynchronously asserted low and synchronously negated high.The CPU subsystem has separate clocking and reset for the ARM946, AHB system, EMIF and DMAC.
Figure. Simplified Block Diagram
3. TECHNICAL BRIEF
- 23 -
C. Peripheral Hardware Subsystem
There are 29 peripherals within the peripheral hardware subsystem. With the exception of the USB, all hardware peripheral blocks are APB slave peripherals. From an architecture-hierarchy perspective,the SYSCON block is an APB slave on the slow APB bridge, but resides at the top level of the ASIC.The APB provides a simple interface to support low-performance peripherals.Within the peripheral subsystem, there are four separate APB busses with AHB to APB (AHB2APB)bridges to the multi-layer AHB.
D. DSP Hardware Subsystem
The DSP subsystem provides support for processor intensive activity, such as voice coding andmultimedia application support. The DSP subsystem includes the standard C55xTM Core (LEAD3)from Texas Instruments with associated memory system and peripherals.
E. GAM Hardware Subsystem
The Graphics Accelerator Module (GAM) subsystem provides hardware support in the creation ofvisual imagery and the transfer of this data to the display. GAM also provides support for the cameramodule. The visual data could be graphics, still images or video.The GAM subsystem consists of five modules:• GRAM - graphics memory (160 kB). • GAMCON . GAM controller. • GRAPHCON . graphics controller. • PDI/SSI - programmable display interface for parallel/serial displays. • CDI - camera data interface.
F. GSM Hardware Subsystem
The GSM subsystem is a stand-alone sub-chip incorporating GSM modem and interface to GSM radiotogether with memory control (MEMSYS) and internal RAM (IRAM).The hardware peripheral blocks are RXIF, FCHDET, CRYPTO, EQU, NODI, 4 x CHD, GPRSCRYPTO, GPRS CRC24, CHE, DIRMOD, CLKCON, SERCON, TIMGEN, MEMSYS and IRAM. The peripherals are accessible to the AHB (CPU-only) by an asynchronous I/O bridge.The dual port IRAM is accessible to the AHB (CPU and DMA) by a synchronous AHB slave interface.
3. TECHNICAL BRIEF
- 24 -
G. System Control Subsystem
The system controller subsystem (SYSCON) is primarily responsible for generating clock signals anddistributing the clock and reset signals within the ASIC and certain external devices. The GSM core,GAM and DSP subsystems include their own system controllers that are sourced from SYSCON.SYSCON consists of analog and digital PLL clocks and a clock squarer. The block is a slaveperipheral on the slow APB bus under control of the CPU.The programming of SYSCON controls the fundamental modes of operation within the ASIC.Individual blocks can also be reset and their clocks held inactive by accessing the appropriate controlregisters. SYSCON also controls the requesting protocol through which different sub-blocks inEricsson DB 20000 can request clocks derived from the system clock. The system controller also stores the chip-ID number in a read only register.
3. TECHNICAL BRIEF
- 25 -
3.1.3 External memory interface
There are four independent chip selects (CS0, CS1, CS2, CS3) provided for external memories andeach has an address range of 256 Mb.RF calibration data, Audio parameters and battery calibration data etc are stored in flash memoryarea.
A. U8100 & U8110
• 384Mb flash memory + 64Mb PSRAM• 4-CS(Chip Select) are used
B. U8120
• 512Mb flash memory + 64Mb PSRAM• 3-CS(Chip Select) are used
Interface Spec.
Read Access Time Write Device Part Name Maker Access
Async Page Burst Time
MCP S71WS256HC0BAW00 AMD 56 ns –13.5 ns
56 nsat 54MHz
FLASH Am29BDS128HD9VKI AMD 56 ns –13.5 ns
70 nsat 54MHz
PSRAM S71WS256HC0BAW00 AMD 70 ns 20 ns – 70 ns
Table External memory interface for U8100 & U8110
Interface Spec.
Read Access Time Write Device Part Name Maker Access
Async Page Burst Time
MCP RD38F4050L0YTQ0 Intel 85 ns 25 ns14 ns
85 nsat 54MHz
FLASH NZ48F4000L0YBQ0 Intel 85 ns 25 ns14 ns
85 nsat 54MHz
PSRAM RD38F4050L0YTQ0 Intel 85 ns 25 ns10 ns
85 nsat 66MHz
Table External memory interface for U8120
3. TECHNICAL BRIEF
- 26 -
3.1.4 RF Interface
A. MARITA Interface
Marita controls GSM RF part using these signals through GSM RF chip-Ingela.• RFCLK, RFDAT, RFSTR : Control signals for Ingela• TXON, RXON : Control signals for TX and RX part of Ingela• PCTL : Control signal for GSM TX PAM• BANDSEL0 : Band selection signal for GSM or DCS• ANTSW[0:3] : Control signals for antenna switch• DCLK, IDATA, QDATA : GSM/DCS RX Data• DIRMOD[A:D] : GSM/DCS TX Data
B. WANDA Interface
Wanda controls WCDMA RF part using these signals through W-CDMA RF chip-Wopy & Wivi.
Figure. Schematic of MARITA RF Interface
Figure. Schematic of WANDA RF Interface
3. TECHNICAL BRIEF
- 27 -
• RADIO_CLK, RADIO_DAT, RADIO_STR : Control signals for Wivi & Wopy• RXIA, RXIB, RXQA, RXQB : WCDMA RX Data• TXIA, TXIB, TXQA, TXQB : WCDMA TX Data• HSSLRX_D, HSSLRX_CLK : Marita & Wanda Communication Signal• HSSLTX_D, HSSLTX_CLK : Marita & Wanda Communication Signal
Figure. Schematic of WANDA RF Interface
3. TECHNICAL BRIEF
- 28 -
3.1.5 SIM Interface
SIMDAT0, SIMCLK0, SIMRST0 ports are used to communicate DBB(MARITA) with ABB(VINCENNE)and filter.
3.1.6 UART Interface
UART signals are connected to MARITA GPIO through IO connector
SIM (Interface between DBB and ABB)
SIMDAT0 SIM card bidirectional data line
SIMCLK0 SIM card reference clock
SIMRST0 SIM card async/sync reset
Table. SIM Interface
VDDDAT
CLK CARDRST
SIMVCC
VINCENNEVINCENNE
SDAT SIMDAT
SCLK SIMCLK
SRST SIM RST
MARITAMARITA
SIMDAT0
SIMCLK0
SIMRST0
VDIG
10K15K
Figure. SIM Interface
UART0
Resource Name Note
GPIO10 UARTRX0 Transmit Data
GPIO11 UARTTX0 Receive Data
UART1
GPIO14 UARTRX1 Transmit Data (UART1)
GPIO15 UARTTX1 Receive Data (UART1)
GPIO16 UARTRTS1 Request To Send
GPIO17 UARTCTS1 Clear To Send
Table. UART Interface
3. TECHNICAL BRIEF
- 29 -
3.1.7 GPIO (General Purpose Input/Output) map
In total 40 allowable resources. This model is using 25 resources.GPIO Map, describing application, I/O state, and enable level are shown in below table.
IO # Application IO Resource Inactive State Active State
GPIO00 Not used – – – –
GPIO01 BL_PWL O GPIO Low High
GPIO02 7C_LED_VDD_EN O GPIO Low High
GPIO03 PULSESKIP (Not used) I GPIO – –
GPIO04 CAMERA_DET I GPIO High Low
GPIO05 GPIO05 (Not used) O – – –
GPIO06 AMPCTR O GPIO Low High
GPIO07 TGBUZZ (Not used) O GPIO Low High
GPIO10 UARTRX0 I UART0 High Low
GPIO11 UARTTX0 O UART0 High Low
GPIO12 Not used – – – –
GPIO13 Not used – – – –
GPIO14 UARTRX1 I UART1 High Low
GPIO15 UARTTX1 O UART1 High Low
GPIO16 UARTRTS1 I UART1 High Low
GPIO17 UARTCTS1 O UART1 – –
GPIO20 CAM_REG_EN O GPIO Low High
GPIO21 CAM_FLASH_ON O GPIO Low High
GPIO22 TP2125 (Not used) – – – –
GPIO23 CAM_FLASH_SHOT O GPIO Low High
GPIO24 Not used – – – –
GPIO25 Not used – – – –
GPIO26 Not used – – – –
GPIO27 Not used – – – –
GPIO30 Not used – – – –
GPIO31 Not used – – – –
3. TECHNICAL BRIEF
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IO # Application IO Resource Inactive State Active State
GPIO32 KEY_LED_ONOFF O GPIO Low High
GPIO33 Not used – – – –
GPIO34 Not used – – – –
GPIO35 LCDVSYNCI (Not used) I GPIO Low High
GPIO36 SPKMUTE O GPIO LOW (Ear piece) HIGH (Speaker)
GPIO37 Not used – – – –
GPIO40 USBSENSE I GPIO Low High
GPIO41 Not used – – – –
GPIO42 BL_EN O GPIO Low High
GPIO43 FOLDER_DET I GPIO High Low
GPIO44 EN_LED_R O GPIO Low High
GPIO45 EN_LED_G O GPIO Low High
GPIO46 EN_LED_B O GPIO Low High
GPIO47 IRDA_REG_CTRL O GPIO Low High
Table. MARITA GPIO Map Table
3. TECHNICAL BRIEF
- 31 -
3.1.8 USB
The USB block supports the implementation of a "full-speed" device fully compliant to USB 2.0standard. It provides an interface between the CPU (embedded local host) and the USB wire, andhandles USB transactions with minimal CPU intervention.The USB specification allows up to 15 pairs of endpoints. Data for each endpoint is buffered in RAMwithin the USB block and is read/written from the endpoint FIFO using DMA transfers or FIFO registeraccess. High-speed (high throughput) endpoints can use DMA while slower endpoints can use FIFOregister access.The USB block can request up to six DMA channels, three for IN endpoints and three for OUTendpoints.
USB Function Note
USBDP USB differential (+) line
USBDM USB differential (-) line
USBSENSE (GPIO40) USB detection (input)
USBPUEN USB pull-up control
VDDUSB Power supply for MARITA USB block
Table. USB Signal Interface of MARITA
Figure. Schematic of MARITA USB block
3. TECHNICAL BRIEF
- 32 -
USB regulator input voltage is 5V and uses external USB device power through IO Connector.Output voltage is 3.3V and supply to MARITA USB block.USB is detected by MARITA GPIO40(USBSENES).• VUSB / (10K + 51K) = VUSBSENSE / 51K
Figure. Schematic of USB Regulator
Figure. Schematic of USB filter
3. TECHNICAL BRIEF
- 33 -
3.1.9 IrDA Interface
MARITA supports FIR, MIR and SIR mode. In this model, the IrDA block supports SIR (Standard IrDA) mode.SIR supports data rates up to 115,200 bps, including 9,600/19,200/38,400/57,600 bps.In this mode, IrDA uses eight data bits per character and one stop bit. IrDA supports a protocol defined by the IrDA Association.
Figure. Schematic of MARITA IrDA Interface
3. TECHNICAL BRIEF
- 34 -
3.1.10 Folder ON/OFF Operation
There is a magnet to detect the folder status, opened or closed.If a magnet is close to the hall-effect switch (U1 on keypad), the voltage at pin2 of U1 goes to 0V.Otherwise, 2.8V.This folder signal is delivered to MARITA GPIO43.
VCAM
0.1uC3204
OU
T21
VD
DA
3212
EL
HN
3200
GN
D3 10pC3205
R3206
100K
CAMERA_DET
Figure. Schematic of MARITA IrDA Interface
3. TECHNICAL BRIEF
- 35 -
3.1.11 Power On Sequence
1 User press END key and ONSWAn signal is changed to Low.2 VINCENNE initiate the internal oscillator and power up the regulators.3 VINCENNE generate a power for MARITA.4 VINCENNE release the power reset signal(PWRRSTn) and generate an interrupt(IRQ0n) to
MARITA.
1 Press END key
1 ONSWAn
3 Power for MARITA
4 PWRRSTn
4 IRQ0n
ONSWA
PWRRST
IRQ
RESPOW_N
IRQ0_N
RESETB RESOUT0_N
2
VINCENNE MARITA
Figure. Power On Sequence
3. TECHNICAL BRIEF
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3.1.12 Key Pad
There are 26 buttons and 3 side keys in Figure 3-xx.Shows the Keypad circuit.‘END’ Key is connectedONSWAn from Vincenne.
Figure. Power On Sequence
KEYIN0 KEYIN1 KEYIN2 KEYIN3 KEYIN4
KEYOUT0 SIDE1 SIDE2 SIDE3
KEYOUT1 1 4 7 * UP
KEYOUT2 2 5 8 0 DOWN
KEYOUT3 3 6 9 # RIGHT
KEYOUT4 SEND CLEARER BACK GAME LEFT
KEYOUT5 MENU SEARCH MULTI CAM OK
Table Key Matrix Mapping Table
3. TECHNICAL BRIEF
- 37 -
3.2 GAM Hardware Subsystem
3.2.1 General Description
The Graphics Accelerator Module (GAM) subsystem provides hardware support in the creation ofvisual imagery and the transfer of this data to the display. GAM also provides support for the cameramodule. The visual data could be graphics, still images or video. The GAM subsystem consists of fivemodules:
• GRAM - graphics memory (160 kB). • GAMCON . GAM controller. • GRAPHCON . graphics controller. • PDI/SSI - programmable display interface for parallel/serial displays. • CDI - camera data interface.
Figure. GAM Subsystem Functional Block Diagram
3. TECHNICAL BRIEF
- 38 -
3.2.2 Block Description
GAM Controller(GAMCON)The GAM Controller (GAMCON) is responsible for clock gating and distribution within the GAMmodule. GAMCON receives the HCLK from SYSCON and distributes to GRAPHCON, GRAM, PDI andCDI. GAMCON also distributes the GAM reset signal to GRAPHCON, GRAM, PDI and CDI. The resetsignals CIRES_N and PDIRES_N are distributed from GAMCON to the camera and display modulerespectively, see Figure. The CIPCLK is used to clock the received data into the camera datainterface. The CIPCLK can be in the range of 100 kHz to 16 MHz.
Graphics RAM (GRAM) Block GAM includes 160 kB of graphics memory (GRAM) in order to support display screen sizes of QCIF +alfa display size and three frame buffers when decoding QCIF video. The GRAM can be accessed in 8, 16 or 32-bit mode. Write access takes a single AHB clock cycle.Non-sequential read and the first access of a sequential read access takes two AHB clock cycles.Subsequent sequential read access take a single AHB clock cycle. The GRAM contains both frame buffer and temporary data. There are three image areas with oneused for normal MMI graphics and the other two areas used for still images, video frames or cameraframes. The three image areas can be combined into one frame buffer. GRAM is required to transfer a VGA (640 by 480 pixels) image from the camera data interface (CDI)over DMA at 100 MBit/s, within a 50 ms timeframe. The GRAM is used as a buffer, but the averagetransfer bandwidth required is approximately 3 Mword/s (32-bit word), that is 12 MByte/s.
Graphics Controller (GRAPHCON) Block GRAPHCON is controlled by the application CPU and can perform operations on pixels and imageareas. Images can be moved and merged with other images and text. The GRAPHCON block receives graphical objects from GRAM and performers the appropriategraphical manipulation. The resulting data is transfers to the display interface (PDI). GRAPHCON canreceive images from the camera data interface (CDI) and send them to the PDI automatically. GRAPHCON performs conversion from YUV to RGB and can scale (zoom) still or video images.
Programmable Display Interface (PDI) Block The programmable display interface (PDI) is designed to interface both parallel and serial displaymodules. The display data is transferred from the 32 word FIFO on GAMCON to the display modulevia the PDI block. The PDI block is built around a micro controller and executes 16-bit instructionwords to individually control the I/O ports. It has a 128 byte program memory, programmable by theCPU, which can store up to 64 instructions.The CPU transfers all set-up and control data to the display. Data is transferred to PDI as 32-bit words,which in turn writes 8-bit data to the display. The programmable PDI block is configured at thesoftware build stage, to support either parallel interface such as PPI or serial interface such as SSI orI2C.
3. TECHNICAL BRIEF
- 39 -
Camera Data Interface (CDI) Block The camera data interface (CDI) block is designed to support a range of still image camera modules.An 8-bit parallel bus supports data transfer from the camera module to the CDI. The pixel clock is an output clock from the camera module to the CDI and qualifies the data on theparallel bus. One byte of data is captured on each rising edge of the pixel clock. CDI allows the pixelclock to be in the range of 100 kHz to 16 MHz. The horizontal synchronization line is an input from the camera module and defines one scan-line ofimage data. The horizontal synchronization line can be programmed to be active high or low. Thevertical synchronization line is an input from the camera module and defines one image frame (imageheight) of data. The vertical synchronization line can be programmed to be active high or low. The frame rate can be adjusted by skipping frames and various interrupts are used to inform theapplication CPU regarding the progress of incoming images and potential errors. The normal dataformat on the data bus is YUV 4:2:2 (raw binary image data) according to the CCIR-656 standard. Afunction within the CDI can be programmed to reorder the YUV parameters as they pass through theCDI. In addition, the CDI is able to detect the end of an image and perform some truncation as well asoverflow conditions. There is nothing preventing the use of other data types such as JPEG or RGB (aslong as the timing is followed), but only YUV data can be sent to the display. Camera images can also be sent to a DMA channel to store the image in external memory.The I2Cinterface and GPIO are part of the interface to the camera module, but they are not part of the CDIblock. The I2C is used to set-up and control the camera module. The camera module I2C lines must go high impedance when the supply is removed from the camera.The I2C commands needed to control the camera, as well as the functional behavior of the module,are also different for each implementation. The ON-signal (GPIO) is used to power-on the camera from Standby or Off mode (implementationdependent). This signal must be held low when the mobile equipment is powered down and during themobile equipment reset period. The GPIO pin can also be an input or high impedance during mobileequipment reset and start. In this case, it must have pull-down to ground. The camera module reset signal is an output to the camera module.
3. TECHNICAL BRIEF
- 40 -
3.2.3 Camera & Camera FPC Interface
CAMERA I/F
VDIG
Q32
02P
MS
T390
42
31
R33
303.
3K
4.7K
R33
29
R23
03
4.7K
VCORE VDIG
J18
RTC_GND
VS
SM
CK
18
R11
VS
SR
TCV
SS
US
B
V12
VS
SA
0V
SS
A1
W13
VS
SA
2V
14E3
VS
SD
M
PDID1PDID2
C18B19
PDID3PDID4
A20
PDID5H13G14
PDID6PDID7
B20Y2
I2CSCLI2CSDA
W3
E20E21
CID1H14
CID2CID3
F19
CID4F20
CID5G18G19
CID6CID7
G20
G21CIHSYNC
CIPCLKH18
E19CIRES_N
H15CIVSYNC
CID0
R3333 NA
3.3K
R23
04
VDIG
I2CCLK
I2CDAT
I2CCLK_CAMERA
PDID1PDID2PDID3PDID4PDID5PDID6PDID7
CIPCLKCIVSYNCCIHSYNCCIRES_N
CID0CID1CID2CID3CID4CID5CID6CID7
Figure. Camera Interface (in Marita)
Figure. Camera Board to Board Connector
3. TECHNICAL BRIEF
- 41 -
The Camera module is connected to main board with 20pin Board to Board connector (AXK7L80225).Its interface is dedicated camera interface port in Marita. The camera port supply 24MHz master clockto camera module and receive 12MHz pixel clock (30fps), vertical sync signal, horizontal sync signal,reset signal and 8bits YUV data from camera module. The camera module is controlled by I2C port.
NO Pin Name Pin Type Description
1 DOUT4 DO Image data output
2 DOUT5 DO Image data output
3 VD DO Vertical Synchronization Pulse Output
4 DOUT1 DO Image data output
5 DOUT2 DO Image data output
6 DCLK DO Clock for Output Data
7 DOUT0 DO Image data output
8 DOUT3 DO Image data output
9 EXTCLK DI External Clock Input
10 GND Ground
11 FSSTB DO Strobe Pulse for Flash
12 DVDD VDD for the Digital Circuit
13 GND Ground
14 SCL Clock for IIC bus Command
15 RESET DI Reset Terminal
16 AVDD VDD for the Sensor and PLL
17 HD DO Horizontal Synchronization Pulse Output
18 SDA Clock for IIC bus Command
19 DOUT6 DO Image data output
20 DOUT7 DO Image data output
Table. Interface between Camera Module and Main Board (in camera module)
3. TECHNICAL BRIEF
- 42 -
3.2.4 Camera Position Detection
GPIO_04 detects the Camera Position (front or back)
3.2.5 Camera Regulator
GPIO_20 enables Camera Regulator Operation
Figure. Camera Position Detection
Figure. Camera Regulator
3. TECHNICAL BRIEF
- 43 -
3.2.6 Display & LCD FPC Interface
LCD module include device in table 3-2
LCD module is connected to key board with 40-pin BtoB connector (CONN_40_AXK840145J) andSpeaker, Receiver, Vibrator, Camera Flash is connected by soldering the leads to 9 pads in LCDmodule.The Main LCD is controlled by 8-bit PDI(Parallel Data Interface) in Marita and Sub LCD is controlledby 8-bit PDI in Marita.
Device Type
Main LCD 176 x RGB x 220 65K Color TFT LCD
Sub LCD 96 x 64 Mono FSTN LCD
Main LCD Backlight White LED
Sub LCD Backlight 7 color LED
Table. Devices in LCD Module
PIN SYMBOL FUNCTION I/O REMARKS
SPK TERMINAL
1 EARP Ear Piece Plus O
2 EARM Ear Piece Minus O
3 SPKP Loud Speaker Plus O
4 SPKM Loud Speaker Minus O
MOTOR TERMINAL
1 MOTOR_BATT MOTOR Power O
2 MOTOR_GND MOTOR Ground O
CAMERA FLASH TERMINAL
1 VOUT_F1 FLASH Power O
2 VSIG_F2 FLASH Signal O
3 F3 Dummy Ground O
Table. Interface between LCD module and Speaker, Receiver, Vibrator, Flash
3. TECHNICAL BRIEF
- 44 -
PIN SYMBOL FUNCTION I/O REMARKS
1 GND Ground
2 CAM_FLASH_SHOT Turn ON the Camera Flash Shot
3 MOTOR_BATT MOTOR Power
4 SPKP Loud Speaker Plus
5 SPKM Loud Speaker Minus
6 EN_LED_GEnable Signal for Sub LCD Backlight LED(Green)
7 7C_LED_VDD Power Supply for Sub LCD Backlight
8 BL_EN Enable Signal for Main LCD Backlight
9 PDID0 Parallel Data 0 bit for Main/Sub LCD
10 PDID2 Parallel Data 2 bit for Main/Sub LCD
11 PDID4 Parallel Data 4 bit for Main/Sub LCD
12 PDID6 Parallel Data 6 bit for Main/Sub LCD
13 LCDRDX Read Signal for Main/Sub LCD status
14 LCDRS Register Select Pin
15 LCDCSX_SUB Chip Select Signal for Sub LCD
16 LCDVSYNCI Main LCD Vertical Synch. Signal
17 GND Ground
18 GND Ground
19 GND Ground
20 GND Ground
21 GND Ground
22 GND Ground
23VDIG_2.8V
Power Supply for system
24 and I/O Logic(2.8V)
25 LCDERESX Reset Signal for Main/Sub LCD
26 LCDCSX_MAIN Chip Select Signal for Main LCD
27 LCDWRX Write Signal for Main/Sub LCD
28 PDID7 Parallel Data 7 bit for Main/Sub LCD
29 PDID5 Parallel Data 5 bit for Main/Sub LCD
3. TECHNICAL BRIEF
- 45 -
PIN SYMBOL FUNCTION I/O REMARKS
30 PDID3 Parallel Data 3 bit for Main/Sub LCD
31 PDID1 Parallel Data 1 bit for Main/Sub LCD
32 BL_PWL Main LCD PWL signal
33 VBATI_4.2V Battery Power(4.2V)
34 EN_LED_B Enable Signal for Sub LCD Backlight LED(Blue)
35 EN_LED_R Enable Signal for Sub LCD Backlight LED(Red)
36 EARP Ear Piece Plus
37 ERAM Ear Piece Minus
38 GND Ground
39 CAM_FLASH_ON Turn ON the Camera Flash Continuous ON
40 GND Ground
Table. Interface between LCD module and main board(in LCD Module)
3. TECHNICAL BRIEF
- 46 -
3.2.7 Main LCD Backlight Illumination
There are 4 white LEDs in Main LCD Backlight circuit which are driven by 4.5V Regulated OutputCharge Pump(SC604). GPIO_01(BL_PWL) is used for Backlightbrightness control.
* LED : SSC-HWTS902(Seoul Semiconductor)
Figure. Charge Pump Circuit for Main LCD Backlight
3. TECHNICAL BRIEF
- 47 -
3.2.8 Sub LCD Backlight Illumination
GPIO_02(7C_LED_VDD_EN) in Marita enables 7 color LED. 7 color LED consists of Red LED, GreenLED and Blue LED. GPIO_44(EN_LED_R), GPIO_45(EN_LED_G) and GPIO_46(EN_LED_B) inMarita does ON or OFF its own LEDs.
In case of power off mode, if TA is inserted, Red LED is turned-on.
Figure. Sub LCD Backlight 4.5V
3. TECHNICAL BRIEF
- 48 -
3.2.9 Keypad Illumination
There are 19 blue LEDs in key board backlight circuit, which aredriven by GPIO_32(KEY_LED_ONOFF) line form Marita.
Figure. Keypad Backlight Blue LED Interface
Figure. Keypad Backlight Circuit
3. TECHNICAL BRIEF
- 49 -
3.2.10 Camera Flash IlluminationCamera Flash illumination circuit make 3 modes using white LED. Mode 1. Is Continuous ON modeusing GPIO_21(CAM_FLASH_ON), Mode 2. Is Flash Shot using GPIO_23(CAM_FLASH_SHOT) andMode 3. combines Mode 1. and Mode 2.
Figure. Camera Flash FPCB & Circuit
Figure. Camera Flash Circuit
3. TECHNICAL BRIEF
- 50 -
3.3 LCD Module
Figure. LCD Module Block Diagram
Figure. LCD Module(Main & Sub LCD)
3. TECHNICAL BRIEF
- 51 -
3.4 Analog Baseband (ABB) Processor
3.4.1 Overview of Audio path
Figure. Audio Path Block Diagram
3. TECHNICAL BRIEF
- 52 -
3.4.2 Audio Signal Processing & Interface
Audio signal processing is divided Uplink path and downlink path.The uplink path amplifies the audio signal from MIC and converts this analog signal to digital signaland then transmit it to DBB Chip (Marita).This transmitted signal is reformed to fit in GSM & WCDMA Frame format and delivered to RF Chip. The downlink path amplifies the signal from DBB chip (Marita) and outputs it to Receiver (or Speaker).The audio interface consists of PCM encoding and decoding circuitry, microphone amplifiers andearphone drivers.The PCM encoder and decoder blocks are two-channel, 16-bit circuits with programmable gainamplifiers (PGA). The decoder has a receive volume control. The audio inputs and outputs can be switched to normal orauxiliary ports.
Figure. Audio Interface Detailed Diagram (VICENNE)
3. TECHNICAL BRIEF
- 53 -
Figure. Audio Section scheme
3. TECHNICAL BRIEF
- 54 -
3.4.3 Audio Mode
Audio Mode includes three states. (Voice call, Midi.MP3). Each states is sorted by the total 7 Modes according to external Devices (Receiver, Loud Speaker, Headset). Video Telephony Mode Operate on state of the WCDMA CALL.
ModeVINCENNE In/Out Port
IN OUT
Receiver Mode MIC1P/MIC1N BEARP/BEARN
Voice callLoud Speaker Mode MIC1P/MIC1N BEARP
Headset Mode AUXI1 AUXO1/AUXO2
Video Telephony Mode MIC1P/MIC1N BEARP
MIDI Only Loud Speaker BEARP
MP3 Loud Speaker Mode BEARP
Headset Mode AUXO1/AUXO2
Table Audio Mode
3. TECHNICAL BRIEF
- 55 -
3.4.4 Voice Call
3.4.4.1 Voice call Downlink Mode(Receiver, Speaker, Headset)
This section provides a detailed description of the Voice Call RX functions.
Figure. Voice call Downlink Scheme
3. TECHNICAL BRIEF
- 56 -
The voice decoder accepts a serial input stream of linear PCM coded speech. The receive band-passfilter is the next step in the CODEC receive path. Following the filter is the DAC, followed by a PGAenabling to adjust or trim the circuit in the product for different sensitivity of the earphone and spread inthe RX path. The final step in the receive path is the earphone amplifier and the auxiliary output.The auxiliary audio amplifier is intended to drive low impedance headphones. The earphoneamplifier and the auxiliary audio outputs can be powered down (muted) via I2C. Both the earphonedriver and one of the auxiliary drivers can simultaneously provide an output signal during voicedecoding. • Receiver Mode : Earphone amplifier → BEARP/N Port → Receiver(32Ω)• Loud Speaker Mode : Earphone amplifier → BEARP Port → Analog S/W(ADG702) →
AUDIO AMP(LM4894IBP) → Speaker(8Ω) •Video Telephony Mode : Earphone amplifier → BEARP Port → Analog S/W(N2603) →
AUDIO AMP (LM4894IBP) → Speaker(8Ω)• Headset Mode : Auxiliary audio amplifier → AUXO1/2 →
TJATTE2 IN (AFMS_R_INT/AFMS_L_INT) →TJATTE2 OUT(AFMS_R/AFMS_L) → Head Phone
Speaker Phone Mode has two GPIO switching control ports. One is SPKMUTE and the other isAMPCTRL. SPKMUTE controls analog switch( ADG702) and AMPCTRL controls shutdown ofAUDIOAMP(LM4894IBP). Video Telephony Mode has same paths with Loud Speaker Mode.
Mode SPKMUTE AMPCTRL
Receiver High Low
Headset High Low
Loud Speaker Low High
Video Telephony Low High
Table Speaker Phone Mode GPIO control state
* SPKMUTE; MARITA GPIO36* AMPCTRL; MARITA GPIO06
3. TECHNICAL BRIEF
- 57 -
3.4.4.2 Voice Call Uplink Mode (Receiver, Speaker, Headset)
This section provides a detailed description of the Voice Call TX functions.
The Uplink supports two microphones and two auxiliary inputs to the speech encoder blocks. Bothmicrophone inputs are compatible with an electric microphone.The VINCENNE internal voltage source (CCO) provides the necessary drive current for the electricmicrophone. The voltage source is via I2C programmable to supply 2.2V or 2.4V. But the voltagesource of our Model is to supply 2.4V. The auxiliary audio inputs can be used as an alternative source of speech, a source from an externalmicrophone or as an analog loop connection. Figure shows that the audio inputs are fed to thetransmit PGAs, which enables to adjust the total gain in the product for different sensitivities of themicrophones and spread in the transmit paths. The ADCs are followed by the transmit band passfilters, which accept the maximum output swing that the microphone preamplifiers can deliver withoutclipping, and maintain a good signal-to-noise ratio. The high pass filter in the TX-paths can be disabledvia I2C; still removing the DC offset from the signal. For one of the two transmit paths, a transmit gaincontrol amplifier precedes the final encoding of the PCM output.
Figure. Voice call Uplink Scheme
3. TECHNICAL BRIEF
- 58 -
Each Voice Uplink Mode paths shown below.
Receiver Mode : C-MIC(OBG-15S44) → TJATTE2 IN (MICP/N) → TJATTE2 OUT(MICP_INT/MICN_INT) → VICENNE Input(MIC1N/1P)
Loud Speaker Mode : C-MIC(OBG-15S44) → TJATTE2 IN (MICP/N) →TJATTE2 OUT(MICP_INT/MICN_INT) → VICENNE Input(MIC1N/1P)
Video Telephony Mode : C-MIC(OBG-15S44) → TJATTE2 IN (MICP/N) → TJATTE2 OUT(MICP_INT/MICN_INT) → VICENNE Input(MIC1N/1P)
Headset Mode : Headset MIC → EARJACK S/W(X2602, Pin Num 2) → TJATTE2 IN(ATMS_CAP)TJATTE2 OUT (ATMS_INT) VICENNE Input(AUXI1)
When the headset is inserted, GPA6(Circuit Diagram net Name) converted into low state.So, the headset icon is displayed on Main LCD.
3. TECHNICAL BRIEF
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3.4.5 MIDI (Ring Tone Play)
This section provides a detailed description of the MIDI and WAV-file functions.
External MIDI path is the same as Voice Loudspeaker downlink Mode, except source in MARITA (DSPand Audio Mixer).
• MIDI : MARITA → PCM Decoder → Earphone amplifier → BEARP Port → Analog S/W(ADG702) →AUDIO AMP(LM4894IBP) → Speaker(8Ω)
MIDI being played through external Device Speaker only. MIDI Mode control port shown below
Figure. MIDI Scheme
STATE(SPK ONLY) SPKMUTE AMPCTRL
MIDI ON LOW High
MIDI OFF High Low
Tabel MIDI GPIO Control STATE
* SPKMUTE; MARITA GPIO36* AMPCTRL; MARITA GPIO06
3. TECHNICAL BRIEF
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3.4.6 MP3 (Audio Player)
This section provides a detailed description of the MP3 file functions.
MP3 function supports PCM 44/48KHz sampling rate.The PCM44/48 RX-path is intended to be usedas a stereo music headphones. It is also possible to connect a differential load or to use the RX-pathwith only one channel running (mono). In stereo mode, auxiliary outputs (AUXO1 and AUXO2) can be used to drive the headset.
In single channel mode (mono), BEARP can be used to drive a load (Speaker).
Figure. MP3 Scheme
3. TECHNICAL BRIEF
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3.4.7 Video Telephony
This section provides a description of the Video Telephony functions.
Video Telephony Mode has same paths with Loud Speaker Mode.
Figure. Video Telephony Scheme
STATE(SPK ONLY) SPKMUTE AMPCTRL
Video Telephony ON LOW High
Video Telephony OFF High Low
Tabel Video Telephony GPIO Control STATE
* SPKMUTE; MARITA GPIO36* AMPCTRL; MARITA GPIO36
3. TECHNICAL BRIEF
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3.4.8 Audio Main Component
There are 6 components in U8100 schematic Diagram. Part Number marked on U8100 SchematicDiagram.
TJATTE2 Description
The TJATTE2 is a 6-channel RC low pass filter array that is designed to provide filtering of undesiredRF signals in the 800-2700 MHz frequency band.In addition, the TJATTE2 incorporates diodes to provide protection to downstream components fromElectrostatic Discharge (ESD) voltages as high as 8 kV.
N0 ITEM Part Name Part Number
1 Dual Speaker EMD1940A
1 C-MIC OBG-15S44 X2603
3 Audio AMP LM4894IBP N2601
4 TJATTE2 IP4025CS20 N2602
5 Ear-JACK HSJ1730 X2602
6 Analog Switch ADG702 N2603
Tabel Audio Component List
PIN DESCRIPTION PIN DESCRIPTION PIN DESCRIPTION PIN DESCRIPTION
A1 MICN B1 GND C1 CCO D1 MICN-int
A2 MICP B2 GND C2 ATMS_AD D2 MICP-int
A3 ATMS B3 GND C3 GND D3 ATMS-int
A4 ATMS-cap B4 AFMS_R C4 GND D4 AFMS_R-int
A5 AFMS_L B5 VDD C5 GND D5 AFMS_L-int
Tabel TJATTE Pin Description
3. TECHNICAL BRIEF
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Figure. TJATTE2 Block Diagram
3. TECHNICAL BRIEF
- 64 -
3.4.9 GPADC(General Purpose ADC) and AUTOADC2
The GPADC consists of a 14 input MUX and an 8-bit ADC. The analog input signal is selected with theMUX and converted in the ADC. The GPADC has a built in controller, AUTOADC2, which is able to operate in the background withoutsoftware intervention. The AUTOADC2 periodically measures the battery voltage or current. Figureshows the schematic of GPADC part. The GPADC channel spec is as following Table.
ADC 6 channels
Resource Name Description
GPA0 RTEMP Radio temperature sense
GPA2 VLOOP Loop voltage sense
GPA3 WPOWERSENSE Reference voltage for PAM
GPA4 WRFLOOP Lock inform
GPA6 GPA6 Headset detect
GPA7 VBACKUP Backup battery
Table. GPADC channel spec
Figure. Schematic of GPADC and AUTOADC2
Figure. GPADC and AUTOADC2 Block diagram
3. TECHNICAL BRIEF
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3.4.10 Charger control
A programmable charger in AB2000 is used for battery charging. It is possible to set limits for theoutput voltage at CHSENSE- and the output current from DCIO via the sense resistor to CHSENSE-.The voltage at CHSENSE- and the current feed to CHSENSE- cannot be measured directly by theGPADC. Instead, the two measuring amplifiers translate these inputs to a voltage proportional to theinput and within the range of the GPADC. Figure shows the schematic of charging control part.
1608
C2280
NA
DCIOE2D1
CHREGD3
CHSENSE+CHSENSE-
D2
0.1
R2214
1D1
2D2
3D3
6D4
7D5D6
8
4G S
5
Si5441DCQ2201
VBATI
DCIN_2
DCIN_3
Figure. Battery charging block diagram
Figure. Schematic of charging control part
3. TECHNICAL BRIEF
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3.4.11 Fuel Gauge
AB2000 supports the measurement of the current consumption/charging current in the U8100 with afuel gauge block. By constantly integrating the current flowing into and out of the battery, the fuelgauge block is used to determine the remaining battery capacity. The function of the fuel gauge block is schematically described in Figure. A sense resistorR_FGSENSE is connected in series with the battery. The voltage across the resistor, equivalent to thecurrent entering/leaving the battery, is integrated using an ADC block.
Figure. The analog front-end of the fuel gauge block
Figure. The Schematic of the fuel gauge block
Name Type Unused Description
FGSENSE+ Analog VBAT Fuel gauge current sensing input positive
FGSENSE- Analog VBAT Fuel gauge current sensing input negative
Table. Fuel Gauge channel spec
3. TECHNICAL BRIEF
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3.4.12 Battery Temperature Measurement
The BDATA node, the constant current source, feed the battery data output while monitoring thevoltage at the battery data node with GPADC. This battery data is converted to the batterytemperature. Figure shows the schematic of battery temperature measurement part.
Figure. Battery Temperature Measurement
Name Type Unused Description
BDATA Digital Input/Output Unconnected Current output
Table BDATA channel spec
3. TECHNICAL BRIEF
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3.4.13 Charging Part
The charging block in AB2000 processes the charging operation by using VBAT voltage. It is enabledor disabled by the assertion/negation of the external signal DCIO. Part of the charging block areactivated and deactivated depending on the level of VBAT. Figure shows the schematic of chargingpart.
When VBAT is below a certain value, 3.2V, a current generator take care of initial charging of theCHSENSE+ node and internal trickle charge signal is active. This part of the charging block ispowered on and active when DCIO is asserted. The DCIO signal is asserted when its voltage is abovethe voltage at VBAT. As soon as generator is turned off and all parts of the charging block arefunctional and active.Battery block indication as shown in Fig
Figure. Charging Part
Figure. Battery Block Indication
4.20 ~ 3.87 (V)
100 ~ 68 (%)
3.87 ~ 3.77 (V)
68 ~ 47 (%)
3.77 ~ 3.72 (V)
47 ~ 26 (%)
3.72 ~ 3.50 (V)
26 ~ 5 (%)
3.50 ~ 3.20 (V)
5 ~ 0 (%)
3. TECHNICAL BRIEF
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Trickle chargingWhen the VBAT is below a certain value, 3.2V, a current generator take care of internal trickle chargesignal is active. The charging current is set to 50mA.
Normal charging
When the VBAT voltage is within limits or the internal regulators are turned on, the current source fortrickle charging is turned off and all parts of the charging block are active. The charging method is‘CCCV’. (Constant Current Constant Voltage)This charging method is used for Lithium chemistry battery packs. The CCCV method regulates thecharge current and the VBAT voltage. This charging method prevents the battery voltage to go abovethe charge set in the CCCV algorithm. This picture shows the charging voltage(a) and charging currentchange(b).
Figure. CCCV charging method
(a) Charging voltage
(b) Charging current
Parameter Min Typ Max Unit
Trickle current 30 50 60 mA
Table BDATA channel spec
3. TECHNICAL BRIEF
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• Charging Method : CCCV (Constant Current Constant Voltage)• Maximum Charging Voltage : 4.2V• Maximum Charging Current : 600mA• Nominal Battery Capacity : 1200 mAh• Charger Voltage : 4.6V• Charging time : Max 3.5h• Full charge indication current (icon stop current) : 80mA• Low battery POP UP : Idle - 3.46V, Dedicated – 3.50V• Low battery alarm interval : Idle - 3 min, Dedicated - 1 min• Cut-off voltage : WCDMA call - 3.1V, ELSE – 3.2V
Charging of Extended Temperature
When the battery temperature is outside the normal charging specification, the battery voltage, VBAT,is maintained at 3.7V.
•Under 0 °C : Extended temperature•From 0 °C to 55 °C : Normal charging temperature•Over 55 °C : Extended temperature
3. TECHNICAL BRIEF
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3.5 Voltage Regulation
3.5.1 Internal Regulation
There are LDO (Low Drop Output) regulators and BUCK converter in AB2000 (Vincenne) chip. LDOregulators and BUCK converter generate the following voltages : 1.5V, 1.8V and 2.75V. The output ofthese LDOs supply VDD-A, VDD-B and VDIG with 2.75V. BUCK converter steps down the VBAT to1.5V for VCORE and VRTC, and to 1.8V for VMEM voltage. The output of these LDOs and BUCKconverter are as following Table. Figure shows the power supply of each module in U8100.
3.5.2 External Regulation
1.5V LDO - supply 1.5V for wanda core2.8V LDO - supply 2.8V for IrDA2.8V LDO - supply 2.8V for Camera3.3V LDO - supply 3.3V for USB4.5V DC-DC converter – supply 4.5V for LCD back light
3. TECHNICAL BRIEF
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Figure. Power Supply Scheme
Pin Name Type Output voltage Description
B12 VDD_A Power Supply 2.75V Supply output
A11 VDD_B Power Supply 2.75V Supply output
M11 VDD_D Power Supply 2.75V Supply output
L12 VDD_E Power Supply 1.8V Supply output
L2 VDDLP Power Supply 1.5V Low Power supply output
A2 VDDBUCK Power Supply Unused: VBAT Buck converter switch supply
B1 VSSBUCK Power Supply GND Buck converter switch ground
Table BDATA channel spec
3. TECHNICAL BRIEF
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3.6 General Description
The RF part includes a dual-band GSM/DCS part (900 and 1800MHz) and W-CDMA part for IMT-2000(UL 1900MHz, DL 2100MHz). It also contains Antenna Switch, WCDMA duplexer, WCDMA PowerAmplifier and GSM Power Amplifier.
The whole structure of Radio part is shown in Figure 3-1.
Starting at the antenna end, an antenna switch provides switching capability needed for threefrequency bands (900, 1800 and 2100MHz). For the W-CDMA part, duplexer is included to facilitatethe simultaneous transmission and reception required for the FDD mode.The main components in the radio are Wopy (W-CDMA receiver ASIC), Wivi(W-CDMA transmitterASIC), Ingela(GSM/GPRS transceiver) and two power amplifiers.The mixed-signal circuit ASIC, Vincenne provides power supply for the main RF components.
Tank
RF PLL/VCO
IF PLL/VCO
XO
Loopfilter
PD
Pre-scaler
ADC
Clk
ADC
GSM Herta
÷
÷
DC/DCRosalie
GSM Ingela
UMTS Wivi
UMTS WopyAntenna
Test point
Antenna Switch
DCS RX SAW
GSM RX SAW
DCS Balun
GSM Balun
Duplexer
Isola torUMTS PA
UMTS TX SAW
UMTS RX SAW UMTS RX IF SAW
XO (13MHz)Diode
GSM Dual PA
Figure 3-1. Block diagram of RF part
3. TECHNICAL BRIEF
- 74 -
The control flow for the Radio is shown in Figure 3-2.
The Marita(the main processor) controls the overall radio system. In the GSM/GPRS air interfacemode, this control is handled via direct interfaces to individual RF components. The Marita(the mainprocessor) also handles the antenna switch mechanism for selection of mode.In the W-CDMA mode, the RF system is managed via the Wanda (WCDMA digital base-bandcoprocessor ASIC) and its DSP processor.
Figure 3-2. RF control signal flow diagram
3. TECHNICAL BRIEF
- 75 -
3.7 GSM Mode
3.7.1 Receiver
The received RF signal on the antenna connector arrives via antenna switch at external band passfilters for band selectivity. One filter is required per supported GSM band. The corresponding LNAamplifies the signal for optimum noise suppression.The LNA output signal is mixed with the on-channel LO generated by the proper VCO and transformedinto a Q and an I signal. The I and Q signals are low pass filtered with two parallel high dynamic rangefilters.Finally, the filtered I and Q signals are converted by a sigma-delta converter into two 13 Mbps digitalbit streams by Herta(A/D converter), then fed to the Marita baseband ASIC.
A. Front end.
RF Front end consists of antenna, antenna switch(N1000), two RF SAWs(Z1100, Z1110) and dualband LNAs integrated in transceiver(N1100). The Received RF signals(GSM 925MHz ~ 960MHz, DCS1805MHz ~ 1880MHz) are fed into the antenna or coaxial connector. An antenna matching circuit isbetween the antenna and the coaxial connector.The Antenna Switch(N1000) is used to select the signal path, which is one of WCDMA, GSM RX,GSM TX, DCS RX, and DCS TX. The control signals VC1, VC2 and VCG of antenna switch (N1000)are connected to Marita baseband ASIC(D2000) to control the signal path. For example, when theGSM RX path is turned on, the received RF signal, which has passed through the antenna switch, isfiltered by GSM RF SAW filter to suppress any unwanted signal except GSM RX band. The filtered RFsignal is amplified by an LNA integrated in the transceiver IC(N1100) and is passed to a directconversion demodulator. The process for DCS RX is also the same as GSM RX case.
The logic for antenna switch is given below Table 3-1.
VC1 VC2 VCG
GSM TX 0V 0V 2.8V ~ 3.0V
GSM RX 0V 0V 0V
DCS TX 2.8V ~ 3.0V 2.8V ~ 3.0V 0V
DCS RX 0V 2.8V ~ 3.0V 0V
WCDMA 0V 0V 0V
Table 3-1. Antenna Switch logic
3. TECHNICAL BRIEF
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B. Receiver Block.
The circuit contains one frequency down-conversion section for each receive band and a commonbase band amplifier and filter section. The GSM900 RF part consists of a low noise amplifier followedby high dynamic range mixers.The DCS 1800 RF part also has low noise amplifier connected to the other mixers.The amplified RF signal is mixed with the quadrature local oscillator signal to create in-phase (I) andquadrature phase (Q) baseband signals. The I and Q signals are then buffered and low pass filtered.The same baseband circuitry is used for all bands.Balanced signals are used for minimizing cross talk due to package parasitics. An impedance level atRF of 150 ohms for the GSM 900 input and 50 ohms for the DCS 1800 input is chosen to minimmizecurrent consumption at best noise performance.The low gain mode in GSM 900 is used in high input signal mode. There is no gain switch in DCS1800.
Figure 3-3 shows a block diagram of the receiver block.
Figure 3-3. Block diagram of receiver part.
3. TECHNICAL BRIEF
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C. LO Block
The LO signals from the receive VCO section drive the dividers for GSM 900 and DCS 1800respectively to provide quadrature LO signals to the receive mixers. The LO signal is also supplied tothe prescaler and transmit output buffer.
Figure 3-4 shows a block diagram of the LO block.
Figure 3-4. Block diagram of the LO part.
3. TECHNICAL BRIEF
- 78 -
D. VCO Block
The VCOs are fully integrated balanced LC oscillators with on-chip resonators. The receive VCOs runon double frequency.Different frequency ranges can be selected in the VCOs for GSM/DCS band operation.The VCOs are supplied from a separated external voltage regulator to avoid frequency pushing and upconversion of low frequency noise. A separate ground pin is also used as varactor ground reference toprevent DC voltage drop changes from affecting the VCO frequency.
Figure 3-5 shows a block diagram of the VCO block.
Figure 3-5. Block diagram of the VCO part.
3. TECHNICAL BRIEF
- 79 -
E. PLL Block
The PLL consists of a programmable prescaler with multiple division ratios and a phase and frequencydetector with a charge pump with programmable output current. Channel frequency selection andtransmitter modulation is controlled via the prescaler modulus inputs MODA ~ MODD and theprescaler offset value N offset. The MODA ~ MODD signals could be delayed 0, 5, 10 or 15 ns withMD bits to be synchronized with the XO signal.
Figure 3-6 shows a block diagram of the PLL block.
Figure 3-6. Block diagram of the PLL part.
3. TECHNICAL BRIEF
- 80 -
3.7.2 Transmitter
A 4-bit sigma-delta bit stream comes from the Marita ASIC including both channel information and theGMSK phase information. Via the 3-wire control bus also driven from Marita, the selection oftransmitter band is made. The 4bits from the bit stream provides the fine-tuning of the division ratiobefore going to the divider of the used VCO (low band, 900MHz or high band, 1800MHz).The modulated VCO signal is fed to the output buffer. One buffer is available for each of the low andhigh bands. Trimming capability is included for best match versus the PA used.The GSM/GPRS transceiver, Ingela, output is passed to the dual-band PA that after amplificationfeeds the signal via a low pass filter to the antenna switch and further to the antenna.The transmit block consists of two differential high power transmit output buffers with controllableoutput power. The modulated transmit signal from the VCO buffer is amplified to a level suitable todrive the external power amplifier. The buffer outputs are of open collector type and must beterminated into a suitable load.
Figure 3-7 shows a block diagram of the transmitter block.
Figure 3-7. Block diagram for the transmitter.
3. TECHNICAL BRIEF
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B. Power Amplifier
The Power Amplifier (N1300) is intended for use in EGSM and DCS/PCS mobile equipment. It is amodule with two parallel amplifier chains, with one chain for the EGSM transmitter section and one forthe DCS/PCS transmitter section. Each chain amplifies the RF signal from the respective transmitter tothe antenna. The power amplifier supports class 10.Band selection and the output power level of the RF amplifier are controlled by discrete signals Vbandand Vapc respectively from the digital baseband controller ASIC.
Figure 3-8. Block diagram of the Power Amplifier with Two Parallel chains.
3. TECHNICAL BRIEF
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3.8 WCDMA Mode
3.8.1 Receiver
The received RF signal on the antenna connector arrives via the antenna switch to the duplexer. Theduplexer directs the signal to the LNA, which resides in Wopy (W-CDMA Receive ASIC) as every otheractive part of the radio receiver. The LNA has two different gain settings. From the output of the LNA,the signal is fed to the input of a RF SAW filter, and then appears at the differential output of the filter.The differential output of the RF SAW filter is connected to the differential mixer input, and thereceived signal is down-converted to a 190MHz IF frequency (with the RFLO signal) by the mixer.At 190MHz, the signal is filtered in a differential (input and output) IF SAW filter, with the approximatebandwidth of 4MHz, and then again the signal is fed to Wopy (W-CDMA Receive ASIC), this time tothe differential IF input, which also has a LNA.From the 190MHz, the signal is mixed down to base-band I and Q which represented signals (usingthe IFLO signal). Finally the signals are filtered in low pass filters and amplified in base-band VGAs.The I and Q represented signals appear at the output of Wopy (W-CDMA Receive ASIC) as differentialvoltages.The large signal gain provided by the processing steps from the antenna down to base-band gives aDC offset at the outputs of Wopy (W-CDMA Receive ASIC). To eliminate this, there are DC-offsetcompensation loops included, one in the VGA of each of the I and the Q signals.
A. IFLO Section
The balanced IFLO signal from an external IFVCO drives the divider to provide qaudrature LO signalsto the RxIF mixers. The LO buffers amplifies the signal to a suitable amplitude and DC level to drivethe RxIF mixers.
Figure 3-9. Block diagram of the IFLO section.
3. TECHNICAL BRIEF
- 83 -
B. RFLO Section
The VCO is a fully integrated balanced LC oscillator with on-chip resonator. An on-chip varactor isused to control the frequency over the desired tuning range.A separate external voltage regulator supplies the VCO with power to avoid frequency pushing and upconversion of low frequency noise. A separate ground pin is also used as varactor ground reference toprevent DC voltage drop changes from affecting the VCO frequency. Via the serial interface, theVTUNE voltage can be set to VCC/2 to check the center frequency of the VCO. The PLL consists of aprogrammable prescaler with multiple division ratios and a phase and frequency detector with acharge pump with programmable output current. Channel frequency selection is set via the serialinterface.
Figure 3-10. Block diagram of the RFLO section
3. TECHNICAL BRIEF
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C. Reference Section
The reference block consists of a balanced oscillator and a buffer amplifier. The crystal unit and thefeedback capacitors are external. The current consumption when only the reference oscillator and theoutput buffer are activated must be kept to an absolute minimum.
Figure 3-11. Block diagram of the Reference section.
3. TECHNICAL BRIEF
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3.8.2 Transmitter
Analogue differential signals (currents), representing I and Q, are sent to the radio ASCI Wivi (W-CDMA Transmitter ASIC) from the D/A converter in Wanda (W-CDMA digital base-band coprocessorASIC). The signals are filtered in a reconstruction filter and then modulated up to 380MHz (using theIFLO signal). The signal is then amplified in a VGA and filtered in an external filter (an LC filter). Afterfiltering, the signal is mixed to its final frequency (using the RFLO) and amplified in a differential outputRF buffer with two different gain settings (high gain or low gain).The differential RF signal is fed into a SAW filter with a single ended output, and is then amplified in astand-alone RF buffer. After the RF buffer, the signal is filtered again in a SAW filter before it is fed tothe PA (Power Amplifier).In the PA the signal is amplified for the last time before leaving the radio. After the PA, the signal issent through an isolator and through the duplexer, which directs the transmit signal to the antennaconnector via the antenna switch.The PA has variable supply voltage, which adapts itself by means of a control loop so that the linearityof the PA is kept constant. The variable supply voltage is provided from the battery through a DC/DCconverter and a signal linearity detector sits at the PA output. The detected signal at the PA output iscompared with a reference (supplied by the Vincenne, the mixed-signal circuit ASIC), and the errorsignal is used in a loop filter, which provides the control signal to the DC/DC converter.
A. Reconstruction Filters
The reconstruction filters consist of input buffers that provide the correct DC biasing for the precedingDAC in the digital baseband controller, and a low-pass filter for removing the unwanted high frequencycomponents from the baseband input waveform.The filter inputs are adapted for use with a current-source type of input signal.
B. IQ-modulator
The IQ-modulator receives the incoming I and Q analog baseband signals at baseband frequency andconverts them to an intermediate frequency of 380MHz.
C. Variable Gain Amplifier (VGA)
Comprising two cascaded variable gain amplifiers, the VGA-together with the RF mixer- controls thepower of the transmitter.The first of these two amplifiers, the so-called QVGA, enables fine-tuning of the transmitter by varyingthe gain in 0.25dB steps, that is 0/0.25/0.5/0.75dB. The second amplifier provides a 54dB gain rangein 1 dB steps (54steps = 55 levels).
3. TECHNICAL BRIEF
- 86 -
D. IF Band Bass Filter (IFBP)
The IF filter suppresses spurious signals and eliminates unwanted frequency components generatedin the IQ modulator and subsequently amplified in the VGA. The filter is tuned using an external RLCload as shown in Figure 3-12.
Figure 3-12. Principle Schematic of the IFBP.
3. TECHNICAL BRIEF
- 87 -
E. RF Mixer and Buffer
The RF mixer converts the signal output from the IF BP filter from an intermediate frequency (IF) to thefinal radio frequency (RF). The mixer can be switched between three different gain levels: high gain(HG), medium gain (MG), and low gain (LG).The LO buffer provides the buffering for either an internal LO signal generated within the internalRFPLL, or an external LO signal applied to the RFLO/RFLOBAR pins. External DC blocking isnecessary for the external LO signal.The RF buffer is used to drive an external PA stage. The buffer is of an open-collector design. Thegain switching together with the VGA amplifier at IF will enable an output power control in 0.25 dBsteps over no less than 80dB.The programmable bias in the high and mid-gain settings is specified as a reduction of bias currentfrom the maximum bias condition. It should achieve a reduction of bias current from the nominal valueof 17mA to 3mA (signal ended) in 7 steps.
Figure 3-13. Block Diagram of RF Mixer and Buffer.
3. TECHNICAL BRIEF
- 88 -
F. Power Amplifier
The N1630(RF9266) is a high-power, high-efficiency linear amplifier module targeting W-CDMAtransmitter ASIC. The module is fully matched to 50( for easy system integration and utilizes advancedGaAs HBT process technology. The PA features an integrated RF power output detection network andis compatible with DC-DC converter operation in DC power management applications. Additionally, avariable bias-current allows the idle current to be adjusted for optimum performance at a given RFoutput power.
Figure 3-14. Block Diagram of W-CDMA power amplifier.
3. TECHNICAL BRIEF
- 89 -
3.8.3 Frequency Generation
The Wopy (W-CDMA Receive ASIC) contains the active elements for a 13MHz VCXO, which isdesigned to be the reference frequency of the UE.There are two synthesizers in the W-CDMA part of the radio, an intermediate frequency (IF)synthesizer and a radio frequency (RF) synthesizer. They generate the Intermediate Frequency LocalOscillator (IFLO) and Radio Frequency Local Oscillator (RFLO) signals. Both synthesizers are used inboth the transmitter and the receiver, which gives the radio a fixed duplex distance of 190MHz.The RF synthesizer is in the Wopy (W-CDMA Receive ASIC), except for the loop filter, which isexternal. The 13MHz clock is used as the reference, and the phase detector frequency is 200kHz. Theprogrammable divider makes the RF synthesizer cover the 2300~2360MHz band.The IF synthesizer is in the Wivi (W-CDMA Transmitter ASIC), except for the loop filter. The 13MHz isused as the reference, and the phase detector frequency is 1MHz. The IF VCO runs at 1520MHzgiven that the (programmable) reference divider is set to 13.The synthesizers are controlled by Wanda (W-CDMA digital base-band coprocessor ASIC) via theserial bus to Wivi (W-CDMA Transmitter ASIC) and Wopy (W-CDMA Receive ASIC).
3. TECHNICAL BRIEF
- 90 -
A. IF PLL
The IF LO frequency synthesis comprises the four following parts:
- Input buffer: A 13MHz input buffer with DC-biasing provided at source.- VCO: Operating on 1.52GHz which is 4times the TX-IF frequency (380MHz) and 8 times the RX-IF
(190MHz), this is a fully integrated balanced LC oscillator with on-chip resonator. On-chip varactorare used to tune the VCO frequency.
- Prescaler- Phase-detector with charge pump
For maintaining check on the VCO center frequency, the tuning voltage is set to Vcc/2. External DCblocking capacitors must be used on the IFLO/IFLOBAR signals.
Figure 3-15. Block Diagram of Frequency Synthesizer Part(IF PLL).
4. TROUBLE SHOOTING
- 91 -
4.1 Power ON Trouble
4. TROUBLE SHOOTING
N2000
C2621
ONSWAn
START
No
Change main board
Charge or changemain battery
Yes
No
Follow theLCD Trouble
shooting guide
Yes
Yes
No
No
The vol tage of main batteryis higher than 3.2V ?
END key oper ates wel l?
ONSWAn(C2621) level is low
when END key pressed.
Press END key.
Longer than 3 Seconds
Keypad LED ON?
Follow thekeypad Troubleshooting guide
Check the voltage.
VCORE (R2210) 1.5V
VDIG (R2200) 2.8V
VMEM (R2201) 1.8V
VRTC (R2202) 1.5 V
VEXT1.5 (N2203 Pin#3) 1.5V
VDD_A (R1810) 2.8 V
VDD_B (R1811) 2.8 V
YesThe phone
should work
4. TROUBLE SHOOTING
- 92 -
R1810
R1811
R2201
R2200
R2210
< Main Board - Bottom side >
R2202 N2203
Pin #3
< Main Board - Top side >
4. TROUBLE SHOOTING
- 93 -
4.2 USB Trouble
START(Measure during the state of
USB module running)
Input power(N2204, pin1) is 5V?No
Change main board
Check host USB portor USB cable
Yes
Output power(N2204, pin5) is 3.3V?No
Resolder or change N2204
Yes
USBSENSE level is 2.8V?No
Resolder R2232 or R2233
Yes
VUSB(R3103) is 3.3V?No
Resolder R3103
Yes
R3103R2233R2232N2204
USBSENSE
4. TROUBLE SHOOTING
- 94 -
4.3 SIM Detect Trouble
• SIM control path
- MARITA generates SIM interface signals(2.75V level) to VINCENNE.- Vincenne converts SIM interface signals to 1.8V/3V.
SIM work well? Finish
START
Yes
Reconnect SIM card
Resolder X2300 on main PCBand check the contact
between X2300 and SIM card
Change main board
SIM work well? FinishYes
No
No
SIM work well? FinishYes
No
Change SIM card X2300
4. TROUBLE SHOOTING
- 95 -
4.4 Keypad Trouble
• Keypad signals go to MARITA and VINCENNE through board-to-board connector.
Keypad operates well? Finish
START
Yes
Press the keypad
Change main board
FinishYes
No
No
No
Change Keypad
Keypad operates well?
FinishYes
Keypad operates well?
Resolder X3200 on main boardand CN962 on keypad
ONSWAn
KEYIN0
KEYIN1
KEYIN2
KEYIN3
KEYIN4
CN962
1 60
30 31
KEYOUT5
KEYOUT4
KEYOUT3
KEYOUT2
KEYOUT1
KEYOUT0
Pin #12~#17
Pin #54~#59
X3200
KEYOUT5
KEYOUT4
KEYOUT3
KEYOUT2
KEYOUT1
KEYOUT0
1 60
30 31
ONSWAn
KEYIN0
KEYIN1
KEYIN2
KEYIN3
KEYIN4
Pin # 2~#7
Pin #45~#50
4. TROUBLE SHOOTING
- 96 -
4.5 Camera Trouble
Camera control signals are generated by Marita
4. TROUBLE SHOOTING
- 97 -
Camera control signals are generated by Marita
4. TROUBLE SHOOTING
- 98 -
4.6 Main LCD Trouble
LCD control signals are generated by Marita.
4. TROUBLE SHOOTING
- 99 -
4.7 Sub LCD Trouble
4. TROUBLE SHOOTING
- 100 -
4.8 Keypad Backlight Trouble
4. TROUBLE SHOOTING
- 101 -
4. TROUBLE SHOOTING
- 102 -
4.9 Folder ON/OFF Trouble
4. TROUBLE SHOOTING
- 103 -
VCAM
0.1uC3204
OU
T21
VD
DA
3212
ELH
N32
00
GN
D3 10pC3205
R3206
100K
CAMERA_DET
Be sure that magnet is here
4. TROUBLE SHOOTING
- 104 -
4.10 Camera Detection Trouble
4. TROUBLE SHOOTING
- 105 -
4. TROUBLE SHOOTING
- 106 -
4.11 Camera Flash Trouble
4. TROUBLE SHOOTING
- 107 -
4. TROUBLE SHOOTING
- 108 -
4.12 Audio Trouble Shooting
A. Receiver
• Signals to the receiver– Receiver signals are generated at Vincenne
• BEARP, BEARM– Receiver path :
• 1. Vincenne (BEARP, BEARM) ->• 2. X3200 on main board ->• 3. CN962 on key PCB -> • 4. CN963 on key PCB -> • 5. LCD Module -> • 6. Receiver
• Note : It is recommanded that engineer should check the soldering of R, L, C along thecorresponding path before every step.
4. TROUBLE SHOOTING
- 109 -
START
Connect the phone to networkEquipment and setup call
Setup 1KHz tone out
Does the sine wave appearat R2619 ?
Change the main board
Does the sine wave appearat Number 36, 37 pinin the key B' d CN963?
Change the Key board
Does the sine wave appearat EAR(+) PAD in LCD Module?
Change the LCD module
Is the soldering ot the receiver OK?
Resolder Receiver
Can you hear sine waveout of the receiver ?
Change the Receiver
END
YES
YES
YES
YES
YES
NO
NO
NO
NO
NO
1
2
3
3
4. TROUBLE SHOOTING
- 110 -
1
R2619
3
CN963
1
21
40
20
2
Pin 36, 37
4. TROUBLE SHOOTING
- 111 -
1
2
Measured 1khz Sine Wave Signal
3
Measured 1khz Sine Wave Signal
4. TROUBLE SHOOTING
- 112 -
B. Speaker (Voice Loud Speaker, Midi, MP3, Key Tone)
• Signals to the speaker– Speaker signals are generated at Vincenne
• BEARP– Speaker path :
• 1. Vincenne (BEARP) ->• 2. C2604 on main board ->• 3. N2603(ADG) on main board -> • 4. N2601(Audio Amp) on main board ->• 5. CN963 on key PCB -> • 6. LCD Module -> • 7. Speaker
• Note : It is recommanded that engineer should check the soldering of R, L, C along thecorresponding path before every step.
4. TROUBLE SHOOTING
- 113 -
START
Connect the phone to networkEquipment and setup call
Setup 1KHz tone out
Does the sine wave appearat C2604 ?
Change the main board
Does the sine wave appearat R2607 ? Resolder or change N2603
Does the sine wave appearat R2621 ?
Can you hear sine waveout of the receiver ?
Change the Speaker
END
YES
YES
YES
YES
YES
NO
NO
NO
NO
NO
Change the main board
Does the sine wave appearat number 4 pin in key B' d CN963 ?
Change the key B'd
YES
NODoes the sine wave appear
at spk(+) pad in LCD module ?Change the LCD Module
1
4
3
2
5
4. TROUBLE SHOOTING
- 114 -
1
C2604
2
R2607
N2603
3
R2621
CN963
1
21
40
20
4
Pin 4
5
4. TROUBLE SHOOTING
- 115 -
5
Measured 1khz Sine Wave Signal
4. TROUBLE SHOOTING
- 116 -
C. Microphone (Voice call, Voice Recorder, Video Recorder)
• Microphone Signal Flow– MIC is enable by MIC Bias– MICBAS, MICIP, MICIN signals to ABB ( Vincenne )
• Check Points– Microphone bias– Audio signal level of the microphone– Soldering of components
• Signal from the mic– MIC ->– N2602(TJATTE2) on main board ->– C2615 on main board ->– Vincenne
4. TROUBLE SHOOTING
- 117 -
START
Is the level o f MIC+ AND MIC-2.4V ?
Change the MIC
Check the signal levelat C2615 at the putti ng
Audio signal in MIC
Does it work properly ?
END
Yes
Yes
YES
No
A few hundred of m V of the signal measured ?
Change the main B'd
Check the MIC bias level at the pad of MIC+(X2603)
Resolder C2615,C2617, C2616and try again.If fail again,
chage the main B' d
3
2
1
No
Yes
Yes
No
4. TROUBLE SHOOTING
- 118 -
1
C2616
2
3
C2617
C2615
4. TROUBLE SHOOTING
- 119 -
2
Measured Some Noise Signal
4. TROUBLE SHOOTING
- 120 -
D. Headset Receiver (Voice call, Video Telephony, MP3)
START
Connect the phone to networkEquipment and setup call
Setup 1KHz tone out
Insert Head set.Does the Headset ico n
display on the main LCD?
Can you hear sine waveout of the re ceiver ?
Change the main Bíd
END
YES
YES
YES
YES
NO
NO
NO
Change the main B'd
Does the level of R3381under 0.5Volt ?
NO
Does the level of R2613over 2.0Vo lt ?
YES
N0Change the main B'd
YES
Does the sine wave appearat C2611,C2619 ?
NO
Does the sine wave appearat C3268,C3269 ?
Resolder X2602 Pinsor change the Head set
1
2
5
3
6
Resolde r R2613,R3397R3381,R3303.
And try ag ain fr om the start
4
4. TROUBLE SHOOTING
- 121 -
E. Headset MIC(Voice call, Video Telephony)
START
Insert Head set.Does the Headset ico n
display on the main LCD?
Does it work properly ?? Try again from the start
END
YES
YES
YES
NO
NO
NO
Change the main B'd
Does the level of R3397under 0.5Volt ?
NO
Does the level of R2613over 2.0Vo lt ?
YES
N0Change the main B'd
YES
Check the signal level
at R3397 at the putting
Audio signal in MIC
Resolder C2613,R3397 and try again.
If fail again,Change the main B' d
A few hundred of m V
of the signal measured at C2612 ?
Resolde r R2613,R3397And try again from the start
4
1
2
5
7
8
4. TROUBLE SHOOTING
- 122 -
1
R3381
3
R2613
4
5
7
8
6
2
C2619 C2611
C2612
R3397
X2602
C2613 8
C2610
4. TROUBLE SHOOTING
- 123 -
4.13 Charger Trouble Shooting
• Charging Procedure
- Connecting TA and Charger Detection- Control the charging current by AB2000(Vincenne)- Charging current flows into the battery
• Check Point
- Connection of TA- Charging current path- Battery
• Trouble shooting setup
- Connect TA and battery to the phone
• Trouble Shooting Procedure
- Check the charger connecter- Check the Charging current Path- Check the battery
Figure. 13. Main Battery Charging Path
4. TROUBLE SHOOTING
- 124 -
start
Check the pin and batteryconnect terminals of I/O
connector
Connection OK? Change I /O connectorNO
YES
Is the TA voltage 5.2V? Change TANO
YES
Is it charging properlyafter changing Q2201?
ENDYES
NO
Change the board
start
Check the pin and batteryconnect terminals of I/O
connector
Connection OK? Change I /O connectorNO
YES
Is the TA voltage 5.2V? Change TANO
YES
Is it charging properlyafter changing Q2201?
ENDYES
NO
Change the board
①
②
③
Figure. 14. Trouble Shooting - Charging
4. TROUBLE SHOOTING
- 125 -
③
②
①
Figure. 15. Main Board - I/O connector and FET
4. TROUBLE SHOOTING
- 126 -
4.14 RF Component
N1331 N1330
N1620
B1501
Z1500
N1700
Z1100
Z1420
Z1400
N1400
N1101
B1770
Z1110
Figure 4-1. RF component (Top)
Reference Description Reference Description
B1501 Temperature Sensor N1700 WCDMA TX IC
B1770 Crystal Z1100 DCS RX SAW
N1101 GSM ADC Z1110 GSM RX SAW
N1330 GSM TX Balun Z1400 WCDMA RX RF SAW
N1331 DCS TX Balun Z1420 WCDMA RX IF SAW
N1400 WCDMA RX IC Z1500 WCDMA TX RF SAW
N1620 DC/DC Convertor
4. TROUBLE SHOOTING
- 127 -
N1000
V1001
N1300
W1001 N1002
N1630
N1650
N1850
Figure 4-2. RF component (Bottom)
Reference Description Reference Description
N1000 Ant. SW Module N1650 Isolator
N1002 Duplexer N1850 Regulator
N1300 GSM PAM V1001 Transistor
N1630 WCDMA PAM W1001 Test Connector
4. TROUBLE SHOOTING
- 128 -
4.15 Procedure to check
start
Oscilloscope setting
Agillent 8960 : Test mode(WCDMA)Ch. 9750 (Uplink)
Ch. 10700 (Downlink)
Agillent 8960 : Test mode(GSM)Ch. 62, P.L. 7 level setting
Ch. 62, -60dBm setting
Redownload SW, Cal
1. CheckPower Source Block
2. CheckVCXO Block
3. CheckAnt. SW Module
4. CheckWCDMA Block
5. CheckGSM Block
4. TROUBLE SHOOTING
- 129 -
4.16 Checking Common Power Source Block
Figure 4-3. Common Source Block(Bottom)
4. TROUBLE SHOOTING
- 130 -
4.16.1 Step 1
LP39 81 I LD-2.8
Check VBATI(R1850)
Figure 4-4. Regulator Block 11
R2216 R2215Check Point
(C3215 )
3.7V OK ?
See The Step 2Check Soldering(R2215 & R2216)
In Power Source Block
No
Yes
No
Yes
3.7V OK ?
Check Soldering(C3215)
Change the Board
ResolderingNo
Short?No
Change the Board
Yes
Yes
Check (C3215 & R2215)
in Blockto check inner line connectionFrom R1805 to R2215
Figure 4-5. Power Source Block 55Step 1Check Point (C3215) inPower Source Block 5To Check Power sourceto Check if main powersource input or not
Check Point (R2215) inPower Source Block 5To Check Power source
4. TROUBLE SHOOTING
- 131 -
4.16.2 Step 2
See The Step 3
Check Soldering(R2215 & R2216)
In Power Source Block
No
Yes
3.7V OK ?
Short?No
Change the Board
Yes
Step 2Check VBATI (R1850)in Regulator Block 1 toCheck if main powersource input or not
Check (R2215 & R1805)in Block 1, 5 to checkinner line connectionFrom R1850 to R2215
4. TROUBLE SHOOTING
- 132 -
4.16.3 Step 3
GSM PAM
VBATI( R1326)
L1 300
Figure 4-6. GSM PAM Block 22
See The Step 4
Change L1300
Yes
No
3.7V OK ?
Short?No
Change the Board
Yes
3.7V OK ?No
YesCheck Soldering(R2215 & R2216)
In Power Source Block
Short?No
Change the Board
Yes
Step 3Check VBATI (R1326)in GSM PAM Block 2to Check if main powersource input or not
Check (L1300 & R2215)in Block 2, 5 to checkinner line connectionFrom L1300 to R2215
Check L1300 & R1326inner Line connection
Check L1300 tocheck if powersource input or not
4. TROUBLE SHOOTING
- 133 -
4.16.4 Step 4
WCDMA PAM
VBATI(R163 1)
Figure 4-7. WCDMA PAM Block 33
R22 16Check Po int
(C32 15 )
R22 15
Figure 4-7-1. PAM-Power Source
4. TROUBLE SHOOTING
- 134 -
See the Next Page
Check Soldering(R2215 & R2216)
In Power Source Block
No
Yes
3.7V OK ?
Shor t?No
Change the Board
Yes
Step 4Check R1631 in WCDMAPAM block
4. TROUBLE SHOOTING
- 135 -
VCCA(R181 0)
VCCB(R181 1)
Vincenne(N2000)
Ingela (N1100)
Wopy (N1400)201220124.7uC1811
10uC1802
0
R1811
C181010u
R1810
0VCCA
VCCB
VDD_A
VDD_B
2.75V OK ?No
Yes
2.75V OK ?No
Yes
Check PointVCCA(R1810)
Check PointVCCB(R1811)
Change the Board
Common Input Power is OKSee The Next Part
Before Change,Check soldering
Figure 4-8. Power for Radio ASIC
4. TROUBLE SHOOTING
- 136 -
4.16.5 Checking Regular Part
V_ wivi_B(N1700)
V_ wivi_A(N1700)
EXTLDO(R1851)
LP3981ILD-2.8Regulat or
2.8V OK ?No
Yes
Regulator Circuit is OK,See the next Page
Point High ?
Change The Regulator
Change the BoardNo
YesCheck EXTLOD
Point . To Check regulator e nable
signal
Check Point .or .(R1825)(R1826)
To Check RegulatorOutput Vol tage
or
Figure 4-10. Regular Circuit Diagram
Figure 4-9. Regulator Block
4. TROUBLE SHOOTING
- 137 -
4.17 Checking VCXO Block
The reference frequency (13MHz) from B1770 (Crystal) is used WCDMA TX part, GSM part and BBpart. Therefore you have to check below 4 point.
Check 1Check 2
Check 4
Check 3
Figure 4-12. Top Place
Figure 4-13. Connection for Checking VCXO Block
4. TROUBLE SHOOTING
- 138 -
Check 1. Crystal partIf you already check this crystal part, you can skip check 1.
Figure 4-14. Test Point (Crystal Part)
Figure 4-15. Schematic of the Crystal Part
Figure 4-16. 13MHz at B1770.3
4. TROUBLE SHOOTING
- 139 -
Check 2,3 13MHz at WCDMA TX part and GSM part
N1770.B1 N1770.C1 N1100.K9
Figure 4-17. Test point (13MHz at TX Part)
Figure 4-18. 13MHz at N1770.B1 and N1100.K9
4. TROUBLE SHOOTING
- 140 -
Check 4. 13MHz at BB part
N1400.C1
Figure 4-19. Test Point (13MHz at BB Part)
Figure 4-20. Schematic (13MHz at BB Part)
Figure 4-21. 13MHz at N1400.C1
4. TROUBLE SHOOTING
- 141 -
4. TROUBLE SHOOTING
- 142 -
4.18 Checking Ant. SW Module Block
ANTSW3
ANTSW2
ANT SW 1
ANTSW0
LMSP-00 64
(N1 000 )
VCCB(C101 0)
V10 01
Figure 4-20. Antenna Switch Block(Bottom)
4. TROUBLE SHOOTING
- 143 -
4.19 Checking Antenna Switch Block input logic
4.19.1 Mode Logic by TP Command
ANTSW3W3
ANTSW2W2
ANTSW1W1
ANTSW3W3
ANTSW2W2
ANTSW1W1
Low
Low
Low
Low
Low
HiHigh
HiHigh
HiHigh
Low
Low
HiHigh
Low
EGSM Rx
MODE=0SWRX=64 ,10 24 ,2
MODE=0SWTX=1, 64, 7,1 024 ,1
MODE=2SWRX=699,1024,2
MODE=2SWTX=1,699,0,1024, 1
EGSM Tx
DCS Rx DCS Tx
4. TROUBLE SHOOTING
- 144 -
ANTSW3
ANTSW2
ANTSW1
Low
Low
Low
WCDMA Mode
MODE=4WTXC=9750,0,1,0SYCT=1 07 00TXGN=1,43
Band ANTSW0 ANTSW1 ANTSW2 ANTSW3
EGSM Tx H L L H
EGSM Rx H L L L
DCS Tx H H H L
DCS Rx H L H L
WCDMA H L L L
Table 4-1. Antenna Switch Module Logic
4. TROUBLE SHOOTING
- 145 -
4.19.2 Checking Switch Block power source
Before Checking this part, must check common power source (through Vincenne) part
Open?No
Yes
High?
Check each mode by TP command
No
Yes
OK? Resoldering
Change the Board
No
Yes
Check Soldering .It is necessary to check shor t condition.Using Tester, Check 4 resistorANTSW0(R1003),ANTSW1( R1004),ANTSW2(R1005),ANTSW3( R1006)
Check soldering (R1003)
MODE=0SWRX= 64,1024,2
TP Command
Check ANTSW0(R1003)To check Switch i nput power source.
4. TROUBLE SHOOTING
- 146 -
A. EGSM Rx Mode
ANTSW3
ANTSW2
ANTSW1
Low
Low
Low
EGSM Rx
MODE=0SWRX= 64,10 24 ,2
EGSM RxLogic OK?
No
Yes
See the Next mode(EGSM Tx Mode)
4.4.1 part CheckOK? Try 4.4.1 part
No
Yes
Change the Board
Figure 4-21. EGSM Rx Mode
4. TROUBLE SHOOTING
- 147 -
B. EGSM Tx Mode
ANTSW3
ANTSW2
ANTSW1
Low
Low
High
EGSM Tx
MODE=0SWTX=1,64,7,102 4,1
EGSM TxLogic OK?
No
Yes
See the Next mode(DCS Tx Mode)
4.4.1 part Check OK? Try 4.4.1 partNo
Yes
ANTSW1 : LowANTSW2 : LowANTSW3 : Low
Change the Board
Change V1001
No
Yes
Figure 4-22. EGSM Tx Mode
4. TROUBLE SHOOTING
- 148 -
C. DCS Rx Mode
ANTSW3
ANTSW2
ANTSW1High
High
Low
MODE= 2SWRX=6 99 ,102 4,2
DCS Rx
DCS RxLogic OK?
No
Yes
See the Next mode( DCS Tx Mode)
4.4.1 p art CheckOK? Try 4.4.1 part
No
Yes
Change the Board
Figure 4-23. DCS Rx Mode
4. TROUBLE SHOOTING
- 149 -
D. DCS Tx Mode
ANTSW3
ANTSW2
ANTSW1Low
High
Low
MODE=2SWTX= 1,699 ,0,102 4,1
DCS Tx
DCS TxLogic OK?
No
Yes
WCDMA Mode
4.4.1 p art CheckOK? Try 4.4.1 part
No
Yes
Change the Board
Figure 4-24. DCS Tx Mode
4. TROUBLE SHOOTING
- 150 -
E. WCDMA Mode
ANTSW3
ANTSW2
ANTSW1
Low
Low
Low
WCDMA Mode
MODE=4WTXC=9 75 0,0,1, 0SYCT= 107 00TXGN=1,4 3
WCDMALogic OK?
No
Yes
Input Signal and Power toAntenna Switch Block is OK.See the Next Page
4.4.1 p art CheckOK? Try 4.4.1 part
No
Yes
Change the Board
Figure 4-25. WCDMA Mode
4. TROUBLE SHOOTING
- 151 -
4.20 Checking WCDMA Block
start
1. Check VCXO Block
2. Check Ant. SW Module
3. Check Control Signal
4. Check RF Tx Level
5. Check PAM Block
6. Check Rx IQ
7. Check RF Rx Level
Redownload SW, Cal
①
⑦
⑥⑤
③
② ④
4. TROUBLE SHOOTING
- 152 -
4.20.1 Checking
Refer to 4.4
4.20.2 Checking Ant. SW module
Refer to 4.5
4.20.3 Checking Control Signal
First of all, you have to check control signal. (data, clk, strobe)
TP 1402(CLK)
TP 1402(DATA)
TP 1402(STROBE)
Figure 4-28. Test Point (Control Signal)
Figure 4-29. Schematic (Control Signal)
4. TROUBLE SHOOTING
- 153 -
Figure 4-30. Connection for Checking Control Signal
4. TROUBLE SHOOTING
- 154 -
TP1403(STROBE)
TP1402(CLK)
TP1401(DATA)
TP1403(STROBE)
TP1402(CLK)
TP1401(DATA)
Figure 4-30. Control signal
4. TROUBLE SHOOTING
- 155 -
4.20.4 Checking RF TX Level
Check 1W1001
Check 2N1000.8
Check 4N1650.Out
Check 3N1002.Ant
Check 5N1650.In
Check 6N1630.21
Check 7Z1500.2
Figure 4-31. Test Point (RF TX Level)
4. TROUBLE SHOOTING
- 156 -
Figure 4-32. Connection for Checking RF TX Level
4. TROUBLE SHOOTING
- 157 -
To verify that the phone fulfils requirements on maximum output power.
4. TROUBLE SHOOTING
- 158 -
4.20.5 Checking PAM Block
Step1: Check PAM(N1630) control signal from N2000Step2: Check PAM(N1630) control signal from N1620
Before Checking this part , must check 4.2 Common power source(Battery Direct) part
Rosalie VBATI(R162 9)
WDCDCREF(R1621)
WPAREF(R1617)
WPA(R1630)fro m Rosalie
Wivi in put(R1605)
WCDMA
PAM(N1630)
4. TROUBLE SHOOTING
- 159 -
TP Command-mode =4-Wtxc=9750,0,1,0-Syct=10700-Txgn=1,43-TFTI=10700
Step1: Check PAM control signal from N2000
2.4V ?No
Yes
See the Step 2
Change the Board
Mean Value
Before Change board,Check soldering(R1617)
Check R1617 To Check PAM control signal from Vincenne(WP A REF)
4. TROUBLE SHOOTING
- 160 -
TP Command-mode =4-Wtxc=9750,0,1,0-Syct=10700-Txgn=1,43-TFTI=10700
Step2: Check PAM control signal from DC/DC converter(N1620)
2.4V ?No
Yes
Change the PAM
Change the Board
Mean Value
Before Change board,Check soldering(R1621)
Check R1603To Check PAM VCC BIASfrom DC/ DC conver tor(V CCWPA )
2.5V ?
Mean Value
Change the DC/DCConverter
Before Change board, check soldering VBATI(R1631)
Mean Value
No
Yes
Check R1621To Check DC/DC conver tor control signalFrom Vincenne(N2000)
Check The DC/ DC
(WDCDCREF)
convertor(N1620) Part
4. TROUBLE SHOOTING
- 161 -
23dBm ? Level< -10 dBm?
Download the SW & Calibrate
Level>2 dBm
Check the WCDMA RFTx Chip(Wivi)
2.5V ?Check the Vincenne
to WCDMA PAM Signal line
3.4V ? 2.5V ?Change
the Rosaili
PAM (N1630)
WCDMA PAM i s OKSee t he Next page
Yes Yes
No No
Yes
No
Yes
No
Yes
No No
TP Command -mode =4 -Wtxc=9750,0,1,0 -Syct=10700 -Txgn=1,43
-TFTI=10700
Change The
Check Duplex output(C1012) To Check PAM output
Check R1605 To Check PAM Input level
Check R1617 To Check PAM controlsignal fromVincenne(N2000)(WPAREF)
Check R1603 To Check PAM VCC BIASfrom DC/DCconvertor(N1620)(VCCWPA)
4. TROUBLE SHOOTING
- 162 -
4.20.6 Checking RX I,Q
To verify the RX path you have to check the pk-pk level and the shape of the RX I,Q.
N1400.A8 (RXQB)
N1400.A7 (RXQA)
N1400.A9 (RXIA)
N1400.A10 (RXIB)
Figure 4-33. WCDMA RF RX IC (Top)
Figure 4-34. RX I,Q signal (CW:2142MHz)
Figure 4-35. RX I,Q signal (CW:2141MHz)
4. TROUBLE SHOOTING
- 163 -
Figure 4-36. RX I, Q signal
4. TROUBLE SHOOTING
- 164 -
4.20.7 Checking RX Level
Checkt 1N1002.Ant
Check 2N1400.H1
Check 3N1400.B1
Figure 4-37. Peak level at N1400.B1
Figure 4-38. Connection for Checking RX Level
4. TROUBLE SHOOTING
- 165 -
4.21 Checking GSM Block
4. TROUBLE SHOOTING
- 166 -
start
1. Check Regulator Circuit
2. Check VCXO Block
3. Check Ant. SW Modu le
4. Check Control Signal
5. Check RF Tx Path
6. Check RF Rx Path
Redow nload SW, Cal
①
⑥
⑤
③
④
②
⑤
④
4. TROUBLE SHOOTING
- 167 -
4.21.1 Checking Regulator Circuit
Refer to chapter 4.3 Checking Common Power Source Block.IF you already check this point while Checking Common Power Source Block, You can skip this test.
4.21.2 Checking VCXO Block
Refer to chapter 4.4 Checking VCXO Block.IF you already check this point while Checking VCXO Block, You can skip this test.
4.21.3 Checking Ant. SW Module
Refer to chapter 4.6 Checking Antenna Switch Block input logic.IF you already check this point while Checking Antenna Switch Block input logic, You can skip thistest.
4.21.4 Checking Control Signal
4. TROUBLE SHOOTING
- 168 -
RADSTR
RADCLK
RADDAT
TXON
Vtune
VCCA(C1330)
VCCA(L1200)
LPF block
RADSTR(TP1203)
RADDAT(TP1202)
RADCLK(TP1201)
Vtune(C1223)
VCCA(L1120)
VCCA(L1202)
TXON(R1333)
Figure 4-39. GSM RF Control signal
Test Program ScriptMODE=0SWTX=1,64,7,1024,1
4. TROUBLE SHOOTING
- 169 -
Simiar?
Similar?
Control signal is OK.See next page to check.
No
No
Yes
Yes
VCCA=2.7V?No
Yes
Resoldering LPF block
Resoldering VCCA block(L1120,L1200,L1202,R1335)
Short? Redownload SWNo
Yes
Change the board
Check the short status between TP1201~TP1203
Check voltage of L1120,L1200,L1202,R1335
Check TP1201,TP1202,TP1203
Check if there is any major difference.
Refer to left side of Figure 4-39
Check R1333,C1223.
Check if there is any major difference.
Refer to right side of Figure 4-39
4.21.5 Checking RF Tx Path
A. GSM Tx path Level
4. TROUBLE SHOOTING
- 170 -
Figure 4-40. GSM/DCS Tx Path Level
4. TROUBLE SHOOTING
- 171 -
Figure 4-41. Test Point of GSM/DCS Tx path
B. GSM Tx Output Level Check
4. TROUBLE SHOOTING
- 172 -
Similar?
GSM/DCS Tx Path OK.See chapter 4.8.6 to check Rx path
No
Yes
v. Agilent 8960 setting : GSM BCH+TCH modev. Oscilloscope setting
See next page to check Tx path
Check GSM/DCS output power at ①.
Check if there is any Major difference.
Refer to Figure 4-42.
GSM > 32dBm
DCS > 29dBm
Figure 4-42. GSM Tx Level at 11
Test Program Script
1. GSM Tx
MODE=0SWTX=1,64,5,1024,1
2. DCS Tx
MODE=2SWTX=1,699,0,1024,1
4. TROUBLE SHOOTING
- 173 -
C. GSM RF Transceiver IN/OUT Signal Check
DCS Tx(R1341)
GSM Tx(R1338)
GSM Tx(L1330)
DCS Tx(L1331)
MODA(R1213)
MODB(R1212)
MODC(R1211)
MODD(R1210)
N1331
N1330
MODA
MODB
④
③②
Simiar?
GSM/DCS>- 5dBm
See next page to check Tx path
No
No
Yes
Yes
Resoldering MODE block(R1210,R1211,R1212,R1213)
GSM/DCS>- 7dBm
Resoldering Tx BalunGSM : N1330DCS : N1331
No
Yes
Redownload SW
Check Mode(A/B/C/D)signal at ②.
Check if there is any Major difference.
Refer to right side of Figure 4-43.
Check GSM RF Transceiver
Output power at ③ .
Check GSM/DCS Tx Balun
output power at ④ .
Figure 4-43. GSM Tx MODE signal
D. GSM PAM Check
4. TROUBLE SHOOTING
- 174 -
TXON TXON
Vapc (GSM)Vapc (DCS)
GSM Tx(C1341)
DCS Tx(C1352)
Vapc(C1327)
APCblock
Vapc > 1.5V ?
GSM:>23dBmDCS:>20dBm
GSM Tx Path OK. See Next page t o check
No
No
Ye s
Ye s
Resoldering APC block
Changing GSM PAM(N1300)
Check GSM/DCS PAM
output power at ⑤ .
Check Vapc level.
Check if there is any Major
difference.
Refer to Figure 4-44.
Figure 4-44. GSM/DCS Tx control signal
4. TROUBLE SHOOTING
- 175 -
4.21.6 Checking RF Rx Path
A. GSM Rx path Level
Loo
pfi
lte
rPD Pre
-s
cale
r
AD
C
Clk
AD
C
GS
M H
erta
∏ ∏G
SM
Inge
la
DC
S R
X S
AW
B7
71
4
Mob
ile S
wit
chK
MS-
50
7
Ant
enna
Ant
enna
SW
mod
ule
LM
SP-0
06
4
GS
M R
X
SA
WB
77
05
GSM
Rx
: Ch6
4, -5
0dB
m, C
W
DC
S R
x : C
h699
, -50
dBm
, CW
GSM
: -5
0dB
mD
CS
: -5
0d
Bm
GSM
/D
CS
I/Q L
eve
lI+/
I-/
Q+/Q-
: 20
0m
Vp
p
GSM
: -
51
.5d
Bm
DC
S : -
51
.5d
Bm
GSM
/D
CS
I/Q
Lev
el
I/Q : 2
.5V
pp
Loo
pfi
lte
rPD Pre
-s
cale
r
AD
C
Clk
AD
C
GS
M H
erta
∏ ∏G
SM
Inge
la
Loo
pfi
lte
rPD Pre
-s
cale
r
AD
C
Clk
AD
C
GS
M H
erta
GS
M In
gela
DC
S R
X S
AW
B7
71
4
Mob
ile S
wit
chK
MS-
50
7
Ant
enna
Ant
enna
SW
mod
ule
LM
SP-0
06
4
GS
M R
X
SA
WB
77
05
GSM
Rx
: Ch6
4, -5
0dB
m, C
W
DC
S R
x : C
h699
, -50
dBm
, CW
GSM
: -5
0dB
mD
CS
: -5
0d
Bm
GSM
/D
CS
I/Q L
eve
lI+/
I-/
Q+/Q-
: 20
0m
Vp
p
GSM
: -
51
.5d
Bm
DC
S : -
51
.5d
Bm
GSM
/D
CS
I/Q
Lev
el
I/Q : 2
.5V
pp
Figure 4-45. GSM/DCS Rx Path Level
4. TROUBLE SHOOTING
- 176 -
N1100
N1101
Z1110 Z1100
③
③
②
①
Test Program Script
1. GSM Rx
MODE=0SWRX=64,1024,2
2. DCS Rx
MODE=2SWRX=699,1024,2
v Agilent 8960 SettingCW ModeGSM : -50dBm@Ch65(948MHz)DCS : -50dBm@Ch700(1842.8MHz)v Oscilloscope Setting
4. TROUBLE SHOOTING
- 177 -
B. GSM I/Q Signal Check
Idata(TP1142)
Qdata(TP1141)
DCLK(TP1143)
QRB(R1103)
QRA(R1104)
IRB(R1105)
IRA(R1106)
VDIG_HERTAR1150
I Data
Q Data
DCLK
Figure 4-46. Herta IQ data and DCLK
QRB
QRA
IRB
IRA
Figure 4-47. Ingela IQ signal
4. TROUBLE SHOOTING
- 178 -
Similar?
GSM Rx path OK.
Yes
No
Similar?
IQ signal: 200mV ?
Yes
Yes
VDIG_HERTA=2.7V? Resoldering R1150No
Redownload SW
Yes
Resoldering VCCA block(L1120,L1200,L1202,R1335)
No
See next page to check Rx path
QRB
QRA
Figure 4-48. Ingela IQ signal
Check GSM/DCS Rx IQ data at 1.
Check if there is any Majordifference.
Refer to Figure 4-46.
Check GSM/DCS Rx IQ signal 2.
Refer to Figure 4-47.
Check GSM/DCS Rx IQ signallevel at 2.
Refer to Figure 4-48.
4. TROUBLE SHOOTING
- 179 -
C. GSM RF Level Check
Z1110
Z1100
③
③
Figure 4-49. GSM/DCS Rx Path
GSM:-51.5dBmDCS:-51.5dBm
v Agilent 8960 Setting CW Mode
GSM : -50dBm@Ch65(948MHz) DCS : -50dBm@Ch700(1842.8MHz)
Change Ant. SW module (N1000)
GSM Rx path OK.
Yes
NoCheck GSM/DCS Rx signal level at ③ .
5.1 GSM & WCDMA RF Block
5. BLOCK DIAGRAM
- 180 -
5. BLOCK DIAGRAM
Tank
VCO
VCO
XO
Loopfi l ter
PD
Pre -sc aler
ADC
Clk
ADCGSM ADC
N1101
÷
÷
DC DCN1620
GSM Transceiver
N1100( Ingela)
UMTS Transm itter
N1700(Wivi)
UMTS Receiver
N1400(Wopy)An tennaC2- 6122
Tes t Conn.W1001
SwitchN1000
DCS Rx FilterZ1100
GSM RX FilterZ1110
DCS BalunN1331
GSM BalunN1330
Du plexerN1002
IsolatorN1650
UMTS PAMN1630 UMTS TX Filter
Z1500
UMTS RF FilterZ1400
UMTS IF FilterZ1420
Crys tal - 13MB1770
Varac torV1770
GSM PAMN1300
D2006
Wan da
M arita
D2000
GSM
UMTS
Tank
VCO
VCO
XO
Loopfi l ter
PD
Pre -sc aler
ADC
Clk
ADCGSM ADC
N1101
÷
÷
DC DCN1620
GSM Transceiver
N1100( Ingela)
UMTS Transm itter
N1700(Wivi)
UMTS Receiver
N1400(Wopy)An tennaC2- 6122
Tes t Conn.W1001
SwitchN1000
DCS Rx FilterZ1100
GSM RX FilterZ1110
DCS BalunN1331
GSM BalunN1330
Du plexerN1002
IsolatorN1650
UMTS PAMN1630 UMTS TX Filter
Z1500
UMTS RF FilterZ1400
UMTS IF FilterZ1420
Crys tal - 13MB1770
Varac torV1770
GSM PAMN1300
D2006
Wan da
M arita
D2000
GSM
UMTS
Figure 5-1. RF Block Diagram
5. BLOCK DIAGRAM
- 181 -
Block Ref. Name Part Name Function Comment
N1000 LMSP-0064 Switch Band select
CommonW1001 KMS-507 Test Connector Calibration, etc
B1770 TSX-8A Crystal Reference –13M
N1002 DFYK61G95LBNCB Duplexer TRX
N1400LZT-108-
Receiver RX5323(WOPY)
Z1400 LK20A RX RF Filter RX
Z1420 TMX-M453 RX IF Filter RX
WCDMA N1620 MAX1820ZEBC DC/DC TX
N1630 RF9266 PAM TX
N1650 CEO0401G95DCB Isolator TX
N1700LZT-108-
Transmitter TX5322(WIVI)
Z1500 SX-S205B TX RF Filter TX
D2006ROP-101-3033 Analog
TRX(WANDA) Baseband
Z1100 B7714 DCS RX Filter Direct Conversion
Z1110 B7705 GSM RX Filter Direct Conversion
N1100LZT-108-5325
Transceiver TRXGSM (INGELA)
N1300 CX77304 PAM GSM/DCS Dual
N1330 LDB21897M15C GSM Balun TX
N1331 LDB211G8020C DCS Balun TX
D2000POP-101-3035
Modem(MARITA)
Table 5-1. RF Block Component
5.2 Interface Diagram
5. BLOCK DIAGRAM
- 182 -
WopyN1400
WiviZ1700
MaritaD2000
WandaD2006
G- PAMN1300
W- PAMN1630
SwitchN1000
BuBus_W
HSSLSSL(2bit)
I/ Q_WRWR
I/ Q_WT
13M _M _M CM CLK
32k32k RTC
BuBus - G/G/ W PAG-G- PA C trl
W-W- PA Ctrl
VCVCXO Ctrl
SWSW C trl
BuBus_G
G-G- Band SEL
RXRXON
TXTXON
DIDIRM OD(4bi t)
PcPctl
IngelaN1100
HertaN1101 I/ Q_GD
DCDCLK
1313M _R
1313M ReRef.
RFRFLO IFLO
CrystalB1770
VincenneN2000
I/ Q_GA
W-W- RF RX
W-W- RF TX
Duplex erN1002
G/G/ D- RF T X
G/G/ D- RF RX
WopyN1400
WiviZ1700
MaritaD2000
WandaD2006
G- PAMN1300
W- PAMN1630
SwitchN1000
BuBus_W
HSSLSSL(2bit)
I/ Q_WRWR
I/ Q_WT
13M _M _M CM CLK
32k32k RTC
BuBus - G/G/ W PAG-G- PA C trl
W-W- PA Ctrl
VCVCXO Ctrl
SWSW C trl
BuBus_G
G-G- Band SEL
RXRXON
TXTXON
DIDIRM OD(4bi t)
PcPctl
IngelaN1100
HertaN1101 I/ Q_GD
DCDCLK
1313M _R
1313M ReRef.
RFRFLO IFLO
CrystalB1770
VincenneN2000
I/ Q_GA
W-W- RF RX
W-W- RF TX
Duplex erN1002
G/G/ D- RF T X
G/G/ D- RF RX
Figure 5-2. Interface Diagram 1
5. BLOCK DIAGRAM
- 183 -
Function Block NameSchematic_Signal
FunctionName
13M13M_MCLK MCLK Main clock to BB
13M_R XOOA/XOOB Ref for PLL
LORFLO RFLO/RFLOBAR RF LO Generation
IFLO IFLO/IFLOBAR IF LO Generation
32K 32K RTCCLK Real Time
W-RF RX WCDMA_RX RX RF signal
W-RF TX WCDMA_TX TX RF signal
G/D-RF RX GSM_RX/DCS_RX RX RF signal
SignalG/D-RF TX GSM_TXDCS_TX RX RF signal
I/Q_WR RXIA/RXIB/RXQA/RXQB WCDMA RXIQ
I/Q_WT TXIA/TXIB/TXQA/TXQB WCDMA TXIQ
I/Q_GA IRA/IRB/QRA/QRB GSM RX analog
I/Q_GD IDATA/QDATA GSM RX digital
SW Ctrl ANTSW0/1/2/3 Band/System switch
G-Band SEL BSEL0 GSM/DCS switch
W-PA Ctrl WPAREF PAM Ref. Bias
Control G-PA Ctrl PAREG Power control
Pctl PCTL TX power control
VCXO Ctrl VCXOCONT AFC
RXON RXON RX block ON
TXON TXON TX block ON
Bus_W WDAT/WCLK/WSTR PLL program
Bus Bus_G RADDAT/RADCLK/RADSTR PLL program
Bus-G/WPA DACDAT/DACCLK/DACSTR TX Gain program
Table 5-2. Interface Signal Block
5.3 Detailed Interface Signal
5. BLOCK DIAGRAM
- 184 -
RF BasebandANTSW [3..0]
Reg. On/Off for S wi tch/ GS MI2CDATI2CCLK
MCLKRES ETBQDATAIDATADCLKRXON
STROB EDATA
CLKBSEL
MO D [D..A]P ULS ESKIP
PCTLTXON
VLOOP
BSELPAS ENS E+PAS ENS E-
PAREG
DATACLK
STROB EADCSTRRTEMP
IRA / BQRA /B
REFO N/XO OO NWRFLO OP
MCLKVCXO CO NT
IIN / IINB ARQIN / Q INBAR
WIFLOOP
WDCDCREFWPAREF
WPOW ERS ENS E
GSM / GPRSIngela / Herta
GSM / GPRSPAM
Marita
Vincenne
UMTSWopy
Common
UM TSCommon
UM TSWivi
UM TSPAM
ANTSW [3..0]
I2CSDA (Combi ne to Vince nne)I2CSCL (Combine to Vince nne )SYSCLK2RES ETon (RESO UT3)QDATAIDATADCLKRXONRFSTRRFDATRFCLKBSEL0DIRMOD [D..A]P ULS ESKIP (GP IO03)PCTLTXON (Combine to Vincenne )CLKREQ
VLOOP (GPA2)PAS ENS E+PAS ENS E-PAREG / IO UT
Radi o_DATRadi o_CLKRadi o_STRAD_STR (Combine to Vincenne / Marita)IRA / BQRA /BIIN / IINB ARQIN / QINBAR
WRFLO OP (GP A4)VCXO CO NT (DAC03)WDCDCREF (DAC01)WPAREF (DAC02)WPOW ERS ENS E (GP A3)WIFLOOP (GPA6)EXTLDORTEMP (GP A0)
CLK (to Vincenne / W anda)MCLK (to Vince nne / Wanda / Mari ta)
Wanda
Vincenne
Figure 5-3. Interface Diagram 2
5. BLOCK DIAGRAM
- 185 -
VBATVincenne
V DDRTCV DD_LP(1.5V )
V DD_DV DDMC(2.75V / 200mA)
V DDCODEC
VRTC
V DIG
V EXT15
VDDA0,1,2
1.5V
V DDBUCK
V CORE(1.5V)
SWBUCK
R
L
VSSBUCK
PBUCK
NBUCK
V BUCK
V BAT_C
V DDE0,1,2
V CORE(1.5V )
V DDE2
V DDBEAR
MaritaV DD_E
(1.8V / 100mA)
V DDDM
V DDE1
V MEM
V CC
V CCV CC
FLASH
RAMCS2
VRAM
V FLASH
Wanda
V DDA_TXV DDA_RX
V DDA_BG
V DDA_CS_APLL
V DD_DPLL
VRTC
V DD_CLK32
V EXT15
V DD
V DD_IO
V CCQ
V BAT_A
V DD_A
V DD_B
VBATI
RF
LM4894V BATI
V DD_H
Camera
V DD_L
V DD_D(2.8V )
V DD
V DDI
V DD_D(2.8V )
LCD
V DDLV DD_E(1.8V )
V DD
LCD White LEDV DDI
V DDPA
PASENSE+
V DDBUF
DCIO5.4V
Herta
V CCBIAS
V CC
V CC
V CCA
V CCB
WIVI
V DIG
Ingela
Wopy
REGN1850
V DD_D
DCDCN1620
2.75V
2.75V
2.75V
2.8V
GSM PAM
UMTS PAM
VBATI
0. 1ohm
V _wivi_AV_wivi_B
VBATVincenne
V DDRTCV DD_LP(1.5V )
V DD_DV DDMC(2.75V / 200mA)
V DDCODEC
VRTC
V DIG
V EXT15
VDDA0,1,2
1.5V
V DDBUCK
V CORE(1.5V)
SWBUCK
R
L
VSSBUCK
PBUCK
NBUCK
V BUCK
V BAT_C
V DDE0,1,2
V CORE(1.5V )
V DDE2
V DDBEAR
MaritaV DD_E
(1.8V / 100mA)
V DDDM
V DDE1
V MEM
V CC
V CCV CC
FLASH
RAMCS2
VRAM
V FLASH
Wanda
V DDA_TXV DDA_RX
V DDA_BG
V DDA_CS_APLL
V DD_DPLL
VRTC
V DD_CLK32
V EXT15
V DD
V DD_IO
V CCQ
V BAT_A
V DD_A
V DD_B
VBATI
RF
LM4894V BATI
V DD_H
Camera
V DD_L
V DD_D(2.8V )
V DD
V DDI
V DD_D(2.8V )
LCD
V DDLV DD_E(1.8V )
V DD
LCD White LEDV DDI
V DDPA
PASENSE+
V DDBUF
DCIO5.4V
Herta
V CCBIAS
V CC
V CC
V CCA
V CCB
WIVI
V DIG
Ingela
Wopy
REGN1850
V DD_D
DCDCN1620
2.75V
2.75V
2.75V
2.8V
GSM PAM
UMTS PAM
VBATI
0. 1ohm
V _wivi_AV_wivi_B
Figure 5-4. Power Diagram
6. DISASSEMBLY INSTRUCTION
- 186 -
6. DISASSEMBLY INSTRUCTION
6. DISASSEMBLY INSTRUCTION
- 187 -
6. DISASSEMBLY INSTRUCTION
- 188 -
6. DISASSEMBLY INSTRUCTION
- 189 -
6. DISASSEMBLY INSTRUCTION
- 190 -
6. DISASSEMBLY INSTRUCTION
- 191 -
6. DISASSEMBLY INSTRUCTION
- 192 -
6. DISASSEMBLY INSTRUCTION
- 193 -
The Purpose of Downloading Software
• To make a phone operate at the first manufacturing– A phone = Hardware + Software– A phone cannot operate with hardware alone.– The hardware with the suitable software can operate properly.
• To upgrade the software of the phone– The software of the phone may be changed to enhance the performance of the phone.– The older version software of the phone can be replaced to the newer version.
• Download ToolsFlashRW : Download tool for U81X0 software
Download Environment Setup
7. DOWNLOAD
- 194 -
7. DOWNLOAD
U81X0 UARTdata cable
USB cable
U81X0 Download can be done via UART & USB
7. DOWNLOAD
- 195 -
U81X0 Download (1) – FlashRW configuaration
1. Execute FLASHRW.exe.2. Press the “Global Settings” on the top menu to configure FlashRW environment
U8110 Download (2) – FlashRW configuaration
3. Select Loader File for Product.You can use browse button to select Loader File.You must select only U8120_CXC1325712_R2H(R5E_Signed by cust_brown).pldr for U8120.You may select any loader of 3 loaders in loader folder for U8110.Loader File is provided with FlashRW.
4. Select Port configurations for both RS232 Port and USB Port. Baudrate should be 115200bps.
You have to do FlashRW configuration only at the first time of installation
7. DOWNLOAD
- 196 -
7. DOWNLOAD
- 197 -
U81X0 Download (3) – Phone Model Selection
1. Press Button for Model.2. Select Model to download images
U81X0 Download (4) – Download file selection
1. Press “Add” button to select LGE SSW files to download.2. Press “Add1” button to select LGE GDFS file to download.
7. DOWNLOAD
- 198 -
Click to select file
U81X0 download file is selected
<Before Select>
<After Select>
7. DOWNLOAD
- 199 -
U81X0 Download (5) – Connect & Download
1. Click on connector icon ( ) to connect to the phone Check the Dialog Box that say “Please,switch on the target”.
2. Connect the phone to PC via Cable for Downloading.Phone should be turned off.
3. Turn the phone on to connect to PC.
1
U81X0 Download (6) – USB Driver Install
1. If you use FlashRW Tool firstly, Error will happen because of USB Driver uninstalled.You have to do FlashRW USB Driver Installation only at the first time of installation
7. DOWNLOAD
- 200 -
7. DOWNLOAD
- 201 -
U81X0 Download (7) – USB Driver Install
2. Push “the Next Button” in Found New Hardware Wizard3. Select “Search for a suitable driver for my device” in Found New Hardware Wizard
U81X0 Download (8) – USB Driver Install
4. Select “Specify a location” in Found New Hardware Wizard5. Push “the Browse Button” , and then select “USB driver Information file”
This File is provided with FlashRW.
7. DOWNLOAD
- 202 -
7. DOWNLOAD
- 203 -
U81X0 Download (9) – USB Driver Install
6. Push “the Next Button” in Found New Hardware Wizard7. Push “the Finish Button” in Found New Hardware Wizard
U81X0 Download (10) – USB Driver Install
8. Close FlashRW.exe9. Remove & Insert Main battery to reset the phone
% This action for USB Driver Install is done only at the first time of installationIf you want to download Software, just do as same as U81X0 Download (5) – Connect & Downloadsays
7. DOWNLOAD
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7. DOWNLOAD
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U81X0 Download (11) – Connect & Download
< While Downloading >
< After Downloading finished >
U81X0 Download (12) - Trouble shooting
• Check these questions when trouble happens.1. Check if UART & USB Port configuration is right.
2. Do not change RS-232 baud rate(115200BPS). It is fixed and never changed.
3. Check if UART & USB Cable is connected.
7. DOWNLOAD
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8. CALIBRATION
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8. CALIBRATION
8.1 General Description
This document describes the construction and the usage of the software used for the calibration ofLG’s GSM/GPRS/WCDMA Multimedia Mobile Phone (U8110). The calibration menu and their resultsare displayed in PC terminal by Mobile phone.This calibration software includes GSM, DCS, WCDMA Band RF partscalibration and Batterycalibration. This calibration software was called “XCALMON(eXtended CALibration and MONitorprogram)”. From now on, the calibration software will be called XCALMON in this document.
8.2 XCALMON Environment
8.2.1 H/W Environment
- PC with RS-232 Interface & GPIB card installed- GSM/GPRS/WCDMA Multimedia Mobile Set (U8110)- Agilent 8960 Series 10 E5515C Instrument (E1985B ver04.08)- Tektronix PS2521G Power Supply- ETC (GPIB cable, Serial cable, RF cable, Power cable, Dummy battery)
8.2.2 S/W Environment
- National Instrument GPIB &VISA (ver 2.60 full)driver install- Agilent 8960 VXI driver(E1960)install- XCALMON EXE files- OS :Window98,Window2000,WindowXP- Serial port configuration :
Baud rate:115200 /Char length:8bit /No Parity/No Flow controlStop bits:1 bit
8.2.3 Configuration Diagram of Calibration Environment
Figure 8-1. Calibration Configuration Figure
8.3 Calibration Explanation
8.3.1 Overview
In this section,it is explained each calibration item in the XCALMON.Also the explanation includestechnical information such as basic formula of calibration and settings for key parameters in eachcalibration procedure.At first,when any of calibration is done,the results are displayed in the XCALMON result window andthe result of calibration will be stored in GDFS(Global Data Flash Storage).
8.3.2 Calibration Items
A. EGSM 900 Band
- MODA-D(MD bit)Delay Calibration- RXVCO Varactor Operating Point Calibration- TXVCO Varactor Operating Point Calibration- TX Loop Bandwidth Calibration- VCXO Calibration- TX Power Calibration- RSSI and AGC Calibration
B. DCS 1800 Band
- RXVCO Varactor Operating Point Calibration- TXVCO Varactor Operating Point Calibration- TX Loop Bandwidth Calibration- TX Power Calibration- RSSI Cal i br at i on
C. WCDMA Band
- RF VCO Center Frequency Calibration- TX Carrier Suppression Calibration- TX LPF Bandwidth Calibration- TX Maximum Output Power Calibration- TX Power Table Calibration- TX Open Loop Power Control Calibration- RX LPF Bandwidth Calibration- RX LNA Gain Switch and AGC Hysteresis Calibration- RX AGC Gain Max and Rx RSSI Calibration
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8. CALIBRATION
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8.3.3 EGSM 900 Calibration Items
A. MOD-A(MD bit) Delay Calibration
- Pur poseThe procedure is designed to calibrate the timing alignment between the MODA-D signals and thereference signal (13 MHz).It also ensures that the MOD signals have stable values when they areclocked into the divider of the Phase-Locked Loop (PLL).- Procedure Proposal1. Set the ME to mid channel in the GSM TX band.2. Set the delay setting in default mode,that is,no delay.3. Wait approximately 300 us to 400 us to allow the PLL to lock.4. Measure the RMS phase error.A threshold value of >20 deg indicates that the PLL is running in the
forbidden time region.5. Save the RMS phase error result locally.6. Step up the delay setting according to Table 8.1 below.7. Repeat from step 4.8. Choose delay setting that gives maximum distance to the consecutive field of corrupted RMS phase
error values in the vector.9. Store delay setting both to the GD_RF_Mod_Delay and to the GD_DirMod_Mod_Delay.10. Reset the radio.
Index DIMC MD
[0] 0 00(0)
[1] 0 01(1)
[2] 0 10(2)
[3] 0 11(3)
[4] 1 00(0)
[5] 1 01(1)
[6] 1 10(2)
[7] 1 11(3)
Table 8-1. Delay Settings for the MOD-A
B. RXVCO Varactor Operating Point Calibration
- Pur poseTo adjust the varactor diode to a pre-determined operating point,so that the loop voltage of theRXVCO (measured with an ADC in AB 2000) is within the valid range. This is necessary to secure thatall RX channels can be reached.- Procedure Proposal1. Put the ME in static RX mode.2. Measure the loop voltage with the AB 2000 ADC for all CVCO settings, that is, 0 ~7.
Find a CVCO value that fulfills the requirements on loop voltage for low and high channel.3. If there are several CVCO values that fulfill the loop voltage requirements,then the optimum CVCO
value is the one that centers the loop voltage within the specified limits.4. Store the selected CVCO in the memory.
(GD_RX_VCO_Centre_Frequency_Adjustment_Band)5. Reset the radio.
C. TXVCO Varactor Operating Point Calibration
- Pur poseTo adjust the varactor diode to a pre-determined operating point,so that the loop voltage of the TXVCO(measured with an ADC in AB 2000) is within the valid range. This is necessary to secure that all TXchannels can be reached.- Procedure Proposal1. Put the phone in static TX mode.2. Measure the loop voltage with the AB 2000 ADC for all CVCO settings, that is, 0 ~7.
Find a CVCO value that fulfills the requirements on loop voltage for low and high channel.3. If there are several CVCO values that fulfill the loop voltage requirements,then the optimum CVCO
value is the one that centers the loop voltage within the specified limits.4. Store the selected CVCO in the memory.
(GD_TX_VCO_Centre_Frequency_Adjustment_Band)5. Reset the radio.
D. TX Loop Bandwidth Calibration
- Pur poseThe loop bandwidth is calibrated to match the pre-filtering of the modulation in DB 2000 by adjustingthe phase detector current.Note:This also indirectly adjusts the VCO gain that can otherwise not be calibrated. This will ensure a correct transfer function for the modulation and keep phase error to aminimum.
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- Procedure Proposal1. Put the ME in switched TX mode on mid channel in frequency interval 11 for EGSM
(with random modulation).2. Measure the RMS phase error at the RF connector.3. Tune the phase detector current (IPHD)until the phase error is minimized.If two IPHD settings gave
the same RMS,choose the lowest value.Measure 10 bursts for each value.4. Calculate and store the IPHD values in GDFS
(GD_IPHD_8Temperature_and_24Channel_Compensation_Band)5. The offsets in the table are steps in the IPHD Table 8.2 and all offsets refer to the calibrated value
(Trim) at mid channel in room temperature.
E. VCXO Calibration
- Pur poseThis procedure aims to calibrate the value of DAC3 to establish a VCXO-frequency that is sufficientlyclose to 13 MHz at room temperature.It also ensures that the VCXO tuning range is sufficient,and thatthe temperature compensation table for VCXO is completed accordingly.Note:The frequencies in this section are related to the 13 MHz VCXO-frequency.Depending on the calibration procedure,the 13 MHz VCXO frequency can be acquired by firstmeasuring an EGSM,DCS,or W-CDMA RF frequency at the antenna and then translating themeasured frequency to the 13 MHz VCXO frequency.- Procedure Proposal1. Put the ME in switched low power TX mode with a modulated carrier on a mid channel.
Use the calibrated value of the cap array and phase detector current.2. Tune DAC3 in AB 2000 (VCXOCONT)to end and mid values,and check tuning range.
Frequency Interval
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
0 -2 -2 -2 -2 -1 -1 -1 -1 -1 0 0 0 0 0 1 1 1 1 1 1 2 2 2 2
1 -2 -2 -2 -2 -1 -1 -1 -1 -1 0 0 0 0 0 1 1 1 1 1 1 2 2 2 2
2 -2 -2 -2 -2 -1 -1 -1 -1 -1 0 0 0 0 0 1 1 1 1 1 1 2 2 2 2
3 -2 -2 -2 -2 -1 -1 -1 -1 -1 0 0 0 0 0 1 1 1 1 1 1 2 2 2 2
4 -2 -2 -2 -2 -1 -1 -1 -1 -1 0 0 0 0 0 1 1 1 1 1 1 2 2 2 2
5 -2 -2 -2 -2 -1 -1 -1 -1 -1 0 0 0 0 0 1 1 1 1 1 1 2 2 2 2
6 -2 -2 -2 -2 -1 -1 -1 -1 -1 0 0 0 0 0 1 1 1 1 1 1 2 2 2 2
7 -2 -2 -2 -2 -1 -1 -1 -1 -1 0 0 0 0 0 1 1 1 1 1 1 2 2 2 2
Table 8-2. IPHD Compensation for EGSM Band
Acquire the following VCXO (13 MHz)frequencies:fmin =13 MHz VCXO-frequency @DAC3=1fmid =13 MHz VCXO-frequency @DAC3=1024fmax =13 MHz VCXO-frequency @DAC3=2047
Note that it is necessary to translate the measured RF-frequency (EGSM,DCS,or W- CDMA)to the 13MHz VCXO-frequency.3. Acquire the ME temperature,TCal,from the temperature sensor in ME.4. Store fmin,fmid,fmax and TCal for calculation.5. Calculate the DAC-value,VCXOCONTCal,that gives zero frequency error at the mid channel, using
piecewise linear interpolation,and store the value in the memory(GD_RF_SYNT_CONFIG_ID and GD_VCXO)
6. CalculateK_LO =(fmid –fmin)/1023K_HI =(fmax –fmid)/1023
Each value is then multiplied by 100 and rounded to nearest integer, with the results stored in thememory (GD_RF_SYNT_CONFIG_ID).
AFC_DAC_STEP_LO =ROUND(100*K_LO)AFC_DAC_STEP_HI =ROUND(100*K_HI)
where ROUND(x)=x rounded to the nearest integer.
F. TX Power Calibration
- Pur poseThese procedures describe how to tune the different power levels of the power amplifier to outputpowers corresponding to values in GSM 05.05,and explain how to calculate intermediate power levelsthat will ensure a good power versus time performance.- Procedure Proposal1. Reset the DIRMOD-block, and select a‚ mid channel using the trimmed value on the capacity array
for VCO tuning and a default IPHD value as phase detector current. Turn on dummy burstmodulation.
2. Use the Multi-burst method to characterize the relation between output power and the DAC-value.Then store the DAC values that give the closest approximations to the power targets definedin Table 8-3.
3. To avoid yield problems with the power template and switching transients spectrum a margin to thecompression point of the PA should be observed.However,the output power must be kept within thetolerances specified in Table 8-3.
4. Store DAC values in memory (GD_FullPower_Band).5. Initiate the intermediate value calculation,which calculatesand st or e t he val ues in memory
(GD_IntermediatePower_Up/Down_1.7_Band).6. The difference between the transmitter power at two adjacent power control levels, measured at the
same frequency,shall not be less than 0.5 dB and not more than 3.5 dB.
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G. RSSI and AGC Calibration
- PurposeThis procedure satisfies the two following requirements:Calibrate an absolute power level on the antenna to a corresponding RSSI value. This value togetherwith a pre-defined slope figure is then used to calculate the RSSI value of an arbitrary receivedantenna power. The formula y=kx+m is used. (Where k is the slope value, x the RSSI value, y theactual level, and m is an offset value.)Calculate the attenuation when the Low Noise Amplifier is switched off in the receiver branch. Theattenuation value is stored in the flash memory and used when very high input signals are fed into theME.- Procedure Proposal1. Select switched receiver on a mid EGSM Channel.2. Feed a modulated -68.5dBmsignal, on the same mid EGSM-Channel to the antenna input. Measure
the RSSI value, calculate the RSSI table and store the value in GDFS as parameter:GD_RXLEVS_DBM_BURST_M_BAND.
3. On the same channel, now feed a modulated -50dBmsignal and measure the RSSI value.
Parameter Target Full Power (dBm) Tolerances (dB)
PL 5 33.0 +0.5 – 1.0 Vol
PL 6 31.0 ±0.3 Vol
PL 7 29.0 ±0.5 Vol
PL 8 27.0 ±0.5 Vol
PL 9 25.0 ±0.5 Vol
PL 10 23.0 ±0.5 Vol
PL 11 21.0 ±0.5 Vol
PL 12 19.0 ±0.5 Vol
PL 13 17.0 ±0.5 Vol
PL 14 15.0 ±0.5 Vol
PL 15 13.0 ±0.5 Vol
PL 16 11.0 ±0.5 Vol
PL 17 9.0 ±0.5 Vol
PL 18 7.0 ±0.5 Vol
PL 19 5.0 ±0.5 Vol
Table 8-3. Target Power Levels for EGSM
4. Switch off the LNA, using the command FREC=3,0,1, and measure the RSSI value.5. Calculate the difference between on and off (converting the result to‚ real dB attenuation) and store
the result in GD_MPH_RX_AGC_Parameters_Band.
8.3.4 DCS 1800 Calibration Items
A. RXVCO Varactor Operating Point Calibration
- PurposeTo adjust thevaractordiode to a pre-determined operating point, so that the loop voltage of the RXVCO(measured with an ADC in AB 2000) is withinthe valid range. This is necessary to secure that all RXchannels can be reached.- Procedure Proposal1. Put the ME in static RX mode.2. Measure the loop voltage with the AB 2000 ADC for all CVCO settings, that is, 0 ~ 7. Find a CVCO
value that fulfills the requirements on loop voltagefor low and high channel.3. If there are several CVCO values that fulfill the loop voltage requirements, then the optimum CVCO
value is the one that centers the loop voltage within the specified limits.4. Store the selected CVCO in the memory. (GD_BAND_RX_VCO_Centre_Frequency_Adjustment)5. Reset the radio.
B. TXVCO Varactor Operating Point Calibration
- PurposeTo adjust thevaractordiode to a pre-determined operating point, so that the loop voltage of the TXVCO(measured with an ADC in AB 2000) is withinthe valid range. This is necessary to secure that all TXchannels can be reached.- Procedure Proposal1. Put the phone in static TX mode.2. Measure the loop voltage with the AB 2000 ADC for all CVCO settings, that is, 0 ~ 7. Find a CVCO
value that fulfills the requirements on loop voltagefor low and high channel.3. If there are several CVCO values that fulfill the loop voltage requirements, then the optimum CVCO
value is the one that centers the loop voltage within the specified limits.4. Store the selected CVCO in the memory. (GD_BAND_TX_VCO_Centre_Frequency_Adjustment)5. Reset the radio.
C. TX Loop Bandwidth Calibration
- PurposeThe loop bandwidth is calibrated to match the pre-filtering of the modulation in DB 2000 by adjustingthe phase detector current.Note: This also indirectly adjusts the VCO gain that can otherwise notbe calibrated.This will ensure a correct transfer function for the modulation and keep phase error to a minimum.
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8. CALIBRATION
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- Procedure Proposal1. Put the ME in switched TX mode on mid channel in frequency interval 11 for DCS (with random
modulation).2. Measure the RMS phase error at the RF connector.3. Tune the phase detector current (IPHD) until the phase error is minimized. If two IPHD settings gave
the same RMS, choose the lowest value. Measure 10 bursts for each value.4. Calculate and store the IPHD values in GDFS
(GD_IPHD_8Temperature_and_24Channel_Compensation_Band)5. The offsets in the table are steps in the IPHD Table 8.4 andall offsets refer to the calibrated value
(Trim) at mid channel in room temperature.
D. TX Power Calibration
- PurposeTo tune the different DCS power levels of the power amplifier tooutput powers corresponding to valuesin GSM 05.05 and calculate the intermediate levels that ensure a good power versus timeperformance.- Procedure Proposal1. Reset the DIRMOD-block, and select a ‚mid channel using the trimmed value on the capacity array
for VCO tuning and a default IPHD value as phase detector current. Turn on dummy burstmodulation.
2. Use the Multi-burst method to characterize the relation between output power and the DAC-value.Then store the DAC values that give the closest approximations to the power targets defined inTable 8-5.
Frequency Interval
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
0 -6 -6 -5 -4 -4 -3 -3 -2 -2 -1 -1 0 0 1 1 2 2 3 3 4 4 5 5 5
1 -6 -6 -5 -4 -4 -3 -3 -2 -2 -1 -1 0 0 1 1 2 2 3 3 4 4 5 5 5
2 -6 -6 -5 -4 -4 -3 -3 -2 -2 -1 -1 0 0 1 1 2 2 3 3 4 4 5 5 5
3 -6 -6 -5 -4 -4 -3 -3 -2 -2 -1 -1 0 0 1 1 2 2 3 3 4 4 5 5 5
4 -6 -6 -5 -4 -4 -3 -3 -2 -2 -1 -1 0 0 1 1 2 2 3 3 4 4 5 5 5
5 -6 -6 -5 -4 -4 -3 -3 -2 -2 -1 -1 0 0 1 1 2 2 3 3 4 4 5 5 5
6 -6 -6 -5 -4 -4 -3 -3 -2 -2 -1 -1 0 0 1 1 2 2 3 3 4 4 5 5 5
7 -6 -6 -5 -4 -4 -3 -3 -2 -2 -1 -1 0 0 1 1 2 2 3 3 4 4 5 5 5
Table 8-4. IPHD Compensation for DCS Band
3. To avoid yield problems with the power template and switchingtransients spectrum a margin to thecompression point of the PA should be observed. However, the output power must be kept withinthe tolerances specified in Table 8-5.
4. Store DAC values in memory (GD_FullPower_Band).5. Initiate the intermediate value calculation, which calculatesand store the values in memory
(GD_IntermediatePower_Up/Down_1.7_Band).6. The difference between the transmitter power at two adjacent power control levels, measured at the
same frequency, shall not be less than 0.5 dB and not more than 3.5 dB.
8. CALIBRATION
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Parameter Target Full Power (dBm) Tolerances (dB)
PL 0 30.0 +0.5 – 1.0 Vol
PL 1 28.0 ±0.3 Vol
PL 2 26.0 ±0.5 Vol
PL 3 24.0 ±0.5 Vol
PL 4 22.0 ±0.5 Vol
PL 5 20.0 ±0.5 Vol
PL 6 18.0 ±0.5 Vol
PL 7 16.0 ±0.5 Vol
PL 8 14.0 ±0.5 Vol
PL 9 12.0 ±0.5 Vol
PL 10 10.0 ±0.5 Vol
PL 11 8.0 ±0.5 Vol
PL 12 6.0 ±0.5 Vol
PL 13 4.0 ±0.5 Vol
PL 14 2.0 ±0.5 Vol
PL 15 0.0 ±1 Vol
Table 8-5.Target Power Levels for DCS
8. CALIBRATION
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E. RSSI Calibration
- PurposeThis procedure calibrates an absolute power level on the antennaagainst a corresponding RSSI value.This value together with a pre-defined slope figure is then used to calculate the RSSI value of anarbitrary received antenna power. The formula y=kx+m is used. (Where k is the slope value, x theRSSI value, y the actual level, and m is an offset value).- Procedure Proposal1. Select switched receiver on a mid DCS-Channel.2. Feed a modulated -68.5dBmsignal, on the same mid DCS Channel to the antenna input. Measure
the RSSI value, calculate the RSSI table, and store it to the memory (GD_BAND_RXLEVS_DBM_BURST_M[2]) –1 byte.
8.3.5 WCDMA Calibration Items
A. RF VCO Center Frequency Calibration
- PurposeThis procedure is designed to calibrate the RFVCO (Radio Frequency Voltage Controlled Oscillator)center frequency of the Ericsson RF 2110 (hereafter referred to as the RF 2100) and ensure that allchannels can be reached with sufficient margin.The objective of the calibration is to determine a CVCO (Center VCO) value that guarantees thefunctionality of the RFLO (Radio Frequency Local Oscillator).- Procedure Proposal1. Start the VCXO and RFVCO. VCXOCONT is set to its calibrated value, Ericsson AB 2000 DAC3.2. Measure the loop voltage (WRFLOOP), with the AB 2000 ADC (GPA4), for all CVCO settings, that
is, 0-7. Find a CVCO value that fulfills the requirements on loop voltage for low and high channel. Ifthere are several CVCO values that fulfill the loop voltage requirements, then the optimum CVCOvalue is that that centers the loop voltage within the specified limits.
3. Store the calibrated CVCO value in GD_RF_SYNT_CONFIG_ID.
B. TX Carrier Suppression Calibration
- PurposeDC offset compensation the carrier, to the wanted signal at the IQ-modulator output. The leakage is caused by imperfections in the basebandIQ-path and inside the IQ-modulator. Itimpairs the modulation accuracy and results in a high vector magnitude (EVM). The outcome of thecalibration is values for RECDCI and RECDCQ that minimize the carrier.- Procedure Proposal1. Set the ME in TX mode on mid-channel. Use typical TX settings. Generate 960 kHz square-wave on
both I and Q with amplitude = 8 (sine-wave could be used instead). Start with the best value from earlier calibrated units on RECDCI on RECDCQ.
2. Measure the relative power between the 1950 MHz carrier and 1949.04 MHz at the antenna output.Jump to step 6 if the requirement is met.
3. Step RECDCI from 0 to 3. Set TXON = 0 and wait 1 ms before changing RECDCI from 3 to 5. SetTXON = 1, wait 1 ms and continue with stepping from 5 to 7.
4. Set RECDCI to the value that minimizes the 1950 MHz carrier. If this involves a change of sign theTXON switching and delay sequence in point 3 must beexecuted. Jump to 6 if the requirement ismet.
5. Find and set RECDCQ to the value that minimizes the 1950 MHz carrier. This can be made bystepping RECDCQ from 0 to 7 with the TXON switching and delay sequence in step 3.
6. If the requirements are not met, repeat steps 3, 4 and, if necessary, 5 once with the new RECDCIand RECDCQ (found in 4 and 5) as initial values. Otherwise proceed with step 6.
7. Save the finaldBcvalue (for statistics), RECDCI and RECDCQ. Store the calibrated parameters inGD_RF_TX_CONFIG_ID.
C. TX LPF Bandwidth Calibration
- PurposeThe low pass filters within the Ericsson DB 2100 (hereafter referred to as DB 2100) are designed toprevent spurious emissions output from the TX IQ-D/A (Digital-Analog) converters Œ without adverselyaffecting the signal or causing a deterioration of the modulation accuracy.The objective of this calibration is to determine the values forLPQ and LPBW that offer the best tradeoff against the system-related requirements. These settings determine the cut-off frequency andshould always have the same value.- Procedure Proposal1. Use typical TX settings. Generate a 960 kHz square-wave at baseband without phase shift between
I and Q. The amplitude should be about 50% of fullscale.2. Measure the relative power between 1952.88 MHz (fc+ 3*960 kHz) and 1949.04 MHz (fc Œ 960
kHz) in dB at the antenna output. Find the setting of LPQ =LPBW between 3 and 15 that obtains thedBcvalue closest to the typical value. Start with the best value from earlier calibrated units.Spectrum analyzer settings (example):RBW = 300 kHz, Span = 8 MHz.
3. Set LPQ=LPBW to the found value in 2. Also save thedBcand the decided LPQ = LPBW value forstatistics. Store the calibrated parameters in GD_RF_TX_CONFIG_ID.
D. TX Maximum Output Power Calibration
- PurposeThese procedures verify that the ME can meet the requirements onmaximum output power. Thecalibration aims to establishWPABias, VGA and QVGA settings that fulfill ACLR requirements formaximum output power, both in high, medium, and low gain mode. These calibrations are designed to conform to the ME maximum output power and ACLR requirementsspecified in 3GPP Spec TS34.121.- Procedure Proposal1. Use typical TX settings, mid channel.2. Set gain to the best value based upon previous calibrated units.
8. CALIBRATION
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3. Measure output power as broadband power.4. If the ACLR requirements, described in Table 11 are not met, calculate the test step necessary to
achieve the correct power. Use correlation from earlier calibrated units to calculate the new gainsetting (default correlation between VGA and output power is 1 dB and for QVGA 0.25dB).
5. Measure ACLR at this power level.6. If the ACLR requirement is not met, reduce VGA and QVGA.7. Measure and store the temperature at this point. This provides the value forTPmax.8. This power and gain setting is to be used in calibration of TX power table.9. Set gain to maximum power in medium gain mode and measure ACLR at this power
level.RFBiasshould be set to 1 andWPABiasshould be set to the same value as for maximum outputpower.
10. If the requirements are not met, step the gain down and measure ACLR until the requirements aremet. The correlation between ACLR and output power is that 1 dB in power equals typical 3 dB inACLR. Use correlation from earlier calibrated units to calculate the new gain setting.
11. This power,Pmax measMG, is input to the calibration of TX power table.12. Set gain to maximum power in low gain mode and measure ACLR at this power level.
RFBiasshould be set to 1 andWPABiasshould be set to the same value as for maximum outputpower.
13. If the requirements are not met, step the gain down and measure ACLR until the requirements aremet. Use known correlation from earlier calibrated units to calculate the new gain setting.
14. This power,Pmax measLG, and gain setting provides input to the calibration of TX power table.
E. TX Power Table Calibration
- PurposeThe calibration data contained within the TX Power Table controls the gain for all types of powerchange; including, the inner-loop power control and maximum output power of the platform.The purpose of this calibration is to complete the TX Power gain table with values for VGA, QVGA,RFBIAS, WPABias, and WDCDCREF that meet the specified requirements for inner-loop power-control and Maximum output power. The size of hysteresis area must also be found.These calibrations are designed to conform to the ME maximum output power, inner loop powercontrol, change of TFC and (PRACH preamble tolerances)requirements specified in 3GPP SpecTS34.121.- Procedure ProposalThis calibration consists of two parts: first measurements and then an off-line calculation. Themeasurement results are used for characterizing the hardware so that proper settings can becalculated for all tables. Settings and limitations are also used from maximum output calibration. 1. Perform measurements(1) VGA behavior in LG (Low Gain) mode. PABias should not be offset and RFBIAS should be 1.(2) VGA behavior in MG (Medium Gain mode). PABias should not be offset and RFBIAS should be 1. (3) QVGA behavior in LG mode(4) IQ-Gain behavior in LG mode.(5) WPABias gain step size. Every eighth setting is measured twice. For better accuracy take the
average of each step pair. Interpolate the gain steps in between the averaged measured values.
(6) WDCDCREF gain step size. Every fifth setting is measured twice. For better accuracy take theaverage of each step pair. Interpolate the gain steps in between the averaged measured values.
(7) Size of step between LG/MG and MG/HG and between each setting of RFBIAS (1-7). The mainpurpose is to find the relative difference at different frequencies. Distribute with equal frequencyoffset except if there are known ‚worst-case frequencies. Measured at 5 channels, maximum andminimum steps reported. Average value of minimum and maximum should be used in followingcalculations.
(8) Measure properties: Measure the following properties using a modulated signal:WPA-gain expansion versus output power on mid channel. Compensation needed for maximum output power over the band (13 channels).
2. Perform offline calculations(1) Calculate the compensation values for Table 8-6. Store these values in
GD_RF_TXGAIN_TB_SEL_ID.(2) Extract the range of needed compensation tables (minimum and maximum).(3) Calculate the expected compensation for each table in dB (use ‚table 0 for the table that is ‚0 dB or
closest to ‚0 dB) and spread out the rest to achieve equidistant compensations.(4) Calculate and store the 24 sets of tables, GD_RF_TX_GAIN_TB0_ID to
GD_RF_TX_GAIN_TB23_ID. Each set of tables shall include:One High-gain table: 44 bytes.One Low-gain table: 44 bytes.One RFBias table: 22 bytes.One WDCDCRef table: 44 bytes.One WPABias table: 44 bytes.One value for IQ-Gain: 1 bit (will occupy 1 byte).One value for TABLE_OVERLAP: 1 byte.One value for UPPER_LIMIT: 1 byte.
(5) Calculate the actual compensation (for maximum output power) that each of these 24 tables willgive. Store this in GD_RF_TX_FREC_INT_ID.
3. Store data in GDFS
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Temp.UARFCN
9612 9637 9662 9687 9712 9737 9763 9788 9813 9838 9863 9888
-15
0
15
30
45
60
75
90
Table 8-6.The Complete Gain Compensation Table
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E. TX Open Loop Power Control Calibration
- PurposeThe purpose of the calibration of open loop power control is to store parameters for the Open LoopPower Control algorithm. This is a pure off-line calculation. Use data (positions and output power, indBm) from table 0. Curve fitting should be done preferably with minimum square method. System related requirements:
Open loop power controlMaximum allowed UL TX PowerUE Transmitted power
- Procedure proposal1. Create a curve fitting for the low-gain region, use positions with a power greater than -50 dBm:
Position = B3 * Pout + A3 2. Extract A3 and B3.3. The power level (output power) at the highest position in the low-gain region sets the parameter P2.4. Divide the high-gain region into two regions at the split between mid-gain and high-gain. The output
power at this position sets the parameter P1.5. Do a curve fitting for the mid-gain region (where RFBias > 0) of the high-gain region, use power-
levels from P2: Position = B2 * Pout + A26. Extract A2 and B27. Do a curve fitting for the high-gain region (where RFBias = 0) of the high-gain region:
Position = B1 * Pout + A18. Extract A1 and B19. Save A1, A2, A3, B1, B2, B3, P1 and P2 in GD_RF_TX_GAIN_PARAM_ID.
Figure 8-2. Example of Position versus Power and Calculated Equations
F. RX LPF Bandwidth Calibration
- PurposeThis procedure calibrates the LPF bandwidth. The bandwidth of the channel filters will affect systemparameters as reception sensitivity and adjacent channel selectivity. The procedure also verifies thatthe IF-filter is properly matched.
- Procedure Proposal1. Feed a CW carrier at 2140 MHz with a power of -60dBm into the antenna connector.2. Set UE in RX-mode on 10695ch.3. Set the AGC_UL and AGC_LL to minimum. GLNA is forced to high gain mode.4. Set RF 2110 LPQ and LPBW to 8, that is, LPQ=LPBW=8.5. Get Ak (output2) from N slots. Calculate Average_Ak (Ak_IB) according to the equation below.
N should be as large as possible, with respect to time consumption.
6. Set UE on 10705ch and get Ak (output2). Calculate Average_Ak (Ak_LB) according to the Equation 1.7. Calculate IF-filter symmetry using the following equation.
IF_SYM = Ak_IB - Ak_LB8. Set UE on 10685ch and get Ak (output2). Calculate Ak (Ak_OB) according to the Equation 1.9. Calculate selectivity level using following equation.
Ak_SE = Ak_OB – Ak_IB10. If the requirement is not met, decrease LPBW and LPQ one step and repeat from 8.11. Store the resulting LPBW and LPQ in GD_RF_RX_CONFIG_ID.
8. CALIBRATION
- 222 -
Figure 8-3. AGC Block Diagram (Parameter Ak, Output1, and Pref)
8. CALIBRATION
- 223 -
F. RX LNA Gain Switch and AGC Hysteresis Calibration
- PurposeThis procedure calibrates the gain correction parameter of Ak in the AGC algorithm between GLNA=0and GLNA=1; that is, it establishes the gain difference in the LNA between high gain mode and lowgain mode. It also calibrates AGC_UL and AGC_LL, the upper and lower Ak values where the AGCshould switch between high and low LNA gain (AGC hysteresis).
- Procedure Proposal1. Set the UE in RX-mode on 10695ch.2. Feed a CW carrier at 2140 MHz with a power level of -65dBm.3. Set the AGC_UL and AGC_LL to maximum. GLNA is forced to low gain mode.4. Get average Ak from Equation 1 and save it. (Ak_LG)5. Set the AGC_UL and AGC_LL to minimum. GLNA is forced to high gain mode.6. Get average Ak. (Ak_HG)7. (Ak_LG) - (Ak_HG) = (Correction).8. Round off (Correction) to integer (AGC_CR) and store it in GDFS (GD_RF_RX_CONFIG_ID).
AGC_CR is an AGC algorithm parameter and is set to DB 2100 RFIF.9. Calculate AGC_LL=8+AGC_CR and AGC_UL=18+AGC_CR and store them in GDFS
(GD_RF_RX_CONFIG_ID). AGC_LL and AGC_UL are AGC algorithm parameters and are set toDB 2100 RFIF.
Figure 8-4. LNA Gain Switch and AGC Hysteresis Parameters
G. RX AGC Gain Max and RX RSSI Calibration
- PurposeTo prevent wind up in AGC algorithm, this procedure calibrates the absolute power levels at theantenna connector against RSSI values and the maximum gain setting for AGC. Reference [6]specifies that the reporting range of the RSSI should be between -100 dBm to -25 dBm. The specifiedaccuracy requirement is applied to the received power from -94 through -50 dBm. This is the last RXcalibration.LPBW, LPQ, AGC_CR, AGC_LL and AGC_UL must be calibrated according to above calibrationsrespectively and applied to this calibration. Initially, the AGC anti-wind up is turned on usingAGC_GMAX=127. Use the calibrated value after step 2, otherwise the AGC wind up may occur at thebeginning of the RSSI calibration.- Procedure Proposal1. Set the ME in RX-mode on channel 10695.2. Feed a CW carrier at 2140 MHz with a power level of -105 dBm. Get average_Ak (output2), add 6 to
the value and store it in GDFS as AGC_GMAX (GD_RF_RX_CONFIG_ID), rounded off to aninteger. Set the AGC parameter AGC_GMAX to the calibrated value.
3. Clear Ak ‚table 0.4. Change the CW carrier power level to -95 dBm.5. Read Ak value (output2) and calculate Average_Ak (Equation 1). Store Pin_Corrected (Equation 2)
at Ak=round(Average_Ak). N in Equation 1 should be as large as possible. Pin_Corrected = Pin-round(Average_Ak)+Average_Ak Equation 2
6. Then increase the output level of the signal generator to -80, -60, -40 and -25 dBm and store thecorrected RF input level and Ak to the memory respectively.
7. Use the average Ak values and Pin_Corrected from the two lowest power levels (-95 and -80 dBm)to extrapolate Ak and Pin_Corrected for -110 dBm according to:
Average_Ak_110 = 2*Average_Ak_95 – Average_Ak_80Pin_Corrected_110 = Pin_Corrected_95 – Pin_Corrected_80
8. Store Average_Ak_110 and Pin_Corrected_110 according to step 4.9. Perform the interpolation. AK_BANK_SEL in DB 2100 shall be set to 0.10. Measure the ME temperature (T) and save for offline calculations.11. Store the result to GDFS. (GD_RF_RX_AK_TB0_ID). When stored in GDFS, the first position in
the table (Ak=0) should be replaced with the table number (0-23) in bcd format and the secondposition (Ak=1) set to 0xffff to flag that the table is calibrated. Position 2 to 5 should be set to zero.
12. Perform the offline calculations and check the requirements.
8. CALIBRATION
- 224 -
8. CALIBRATION
- 225 -
8.3.6 Baseband Calibration Item
A. Battery Voltage Calibration
- PurposeCalibrates the voltage table for the power management functionality. Some voltage measurements inthe remaining test will be done with calculated voltage levels from this test.- Procedure Proposal1. Send the command LVBA=0 to reset local values in Test Program.2. Set voltage on VBATT to 3.20 V.3. Send the command LVBA=5,0x140 to read the low voltage level from ADC.4. Set voltage on VBATT to 4.10 V.5. Send the command LVBA=5,0x19A to read the high voltage level from ADC.6. Send the command LVBA=1 to store local values into global data.7. Send the command LVBA=3 to view and record values stored in global data.
Voltage Level on VBATT (V) Min. Typ. Max. Unit
3.2 19 2E 3C HEX
25 42 60 DEC
4.1 64 7E 96 HEX
100 125 150 DEC
Table 8-7. Battery Voltage Calibration Limits
8.4 Program Operation
8.4.1 XCALMON Program Overview
When you try to calibrate the U8110 mobile phone, you should make a configuration of calibrationenvironment like Figure7-1. And if you finish making configuration, please execute the XCALMONprogram. Running the XCALMON program, you should show XCALMON program window likeFigure7-5.If XCALMON program would be executed, it checks the connection of instruments and initializes themautomatically. The result of checking and initializing instruments was shown like Figure7-6.XCALMON supports three functions. - Calibration of EGSM 900, DCS 1800, and WCDMA band- Instrument (Agilent8960, Tektronix PS2521G) control- UART communication with U8110 mobile phoneXCALMON has three windows and each window support different function.- ITP(Integrated Test Program) starting window using production loader- Calibration tree window- Command window which supports interactive ITP commands like Hyper terminal
8. CALIBRATION
- 226 -
Figure 8-5. XCALMON Window
8. CALIBRATION
- 227 -
8.4.2 XCALMON Icon Description
A. DOS Window Icon
When you click the DOS window icon, then you should see the ITP command window like DOSwindow of DOS-operating system. In ITP command window, you should communicate with U8110mobile phone which is running in ITP mode.For example, if you will enter command “VERS” and enter the return key, you should get the responseof the present running ITP version information from U8110 mobile phone.
B. Calibration Tree Window Icon
When you click the calibration window icon ”C”, then you should see the calibration tree window. Thatwill be shown all calibration items. If you want to calibrate U8110 mobile phone for all calibration items,you should select “Calibration” and push “F4” button in your keyboard. Also there are four tap view in calibration window.- OUTPUT : All results of calibration - STATUS : Summary of calibration result- INSTRUMENT : Control and view instrument connection status- UART : Control and view UART connection status
Figure 8-6. XCALMON ITP Command Window
8. CALIBRATION
- 228 -
Figure 8-7. XCALMON Calibration Tree Window (OUTPUT Tab)
Figure 8-8. XCALMON Calibration Tree Window (INSTRUMENT Tab)
8. CALIBRATION
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C. ITP Starting Window Using Production Loader
When you click the ITP starting window icon”L”, then you should see the ITP starting window. Thatdialog window just wait for power-on of U8110 mobile phone. When it will occur power-on, itautomatically start ITP running.If you want to change the start address of ITP, you could change that address directly.To change ITP start address is possible when we download “Production loader” previously.
Figure 8-9. XCALMON Calibration Tree Window (UART Tab)
8.4.3 Calibration Procedure
Calibration procedure of XCALMON was the same as below procedure.- Configuration of calibration- Running ITP using production loader- Calibration start using XCALMON- Verification of calibration result
A. Configuration of Calibration
Configure to calibrated U8110 mobile phone like Figure7-1. If configuration will be accomplished, startXCALMON program.
B. Running ITP Using Production Loader
If XCALMON will be executed, you should run ITP using “L” ITP starting icon at first.Click the “L” icon, then you will see the ITP start window like Figure7-10.When you will turn on the U8110 mobile phone, the production loader will be downloadedautomatically like Figure7-11 and then it will execute the ITP at once. If the ITP will operate normally, you should see the characters “TP, OK” in ITP command window likeFigure7-12.
8. CALIBRATION
- 230 -
Figure 8-10. XCALMON ITP Starting Window (Using Production Loader)
8. CALIBRATION
- 231 -
Figure 8-11. Production Loader Downloading
Figure 8-12. ITP Start Complete Window
C. Calibration Start Using XCALMON
If you want to calibrate U8110 mobile phone, click the calibration icon “C”.And then you will see the calibration tree window like Figure7-6. To start calibration, you should select “Calibration” item and push “F4” button in your keyboard.
D. Verification of calibration result
If the calibration will be ended, you will see several message window and the result of calibrationthrough OUTPUT & STATUS tab view. The detail explanation of those will be described in chapter 7.4.4
8.4.4 Calibration Result Message
If the calibration is over without error, “PASS” message window will show up like Figure7-13. On thecontrary, if the calibration is over with some error, “FAIL” message window will show up like Figure7-14.Additionally, in all of the cases, it is possible to check the calibration result with OUTPUT & STATUStab view.
8. CALIBRATION
- 232 -
Figure 8-13. Calibration PASS Message Window
8. CALIBRATION
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Figure 8-14. Calibration FAIL Message Window
Figure 8-15. Calibration Result from OUTPUT Tab View
8. CALIBRATION
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Figure 8-16. Calibration Result from STATUS Tab View
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NA
R1801
L10025.6nH
6.8pC1000
NA
R1800
22pC1011
N1800LP2985AIBP-2.8
2BYPASS
GND15
ON_OFF
4VIN
3VOUT
L1001
VBATI
12nH
1000pC1010
NA
R1001
0
R1851
4.7uC1811
R1825
0
C10070.01u
10uC1802
22p
10pC1009
C1012
C1001
R1850
0
10pC1002
0
R1811
0.01u
NAR1002
10p
V1001RN47A4
2
45
31
C1005
C181010u
10uC1852
DFYK61G95LBNCB
AN
T
G1
G2
G3
G4
RXTX
N1002
R1007
51
R1804
NA
0.01u10pC1008 C1004
ANTPAD
0
R1826
1000pC1801
0.033uC1851
0.1uC1850
R1810
0
C1013
22p
0
R1004
0
R1003
N1850 LP3981ILD-2.8
5BYPASS
4GND1
GN
D2
7
VEN6
VIN2
1VOUT
3VOUT_SE
ANTG1
G2RF
C18000.1u
W1001KMS-507
0
R1005
0
R1006
0.01uC1003
GND3
GND4
1315
GND5
GS
M18
00_1
900_
TX
12
GS
M18
00_R
X
2
GS
M19
00_R
X
4
GS
M90
0_R
X
16
GS
M90
0_T
X
14
VC1109
VC2
1
VC
G
11VDD
WC
DM
A
6
N1000LMSP54MA-2138
ANT
GND1
3
GND2
57
ANTSW1
ANTSW2
ANTSW0
ANTSW3
GSM_TX
DCS_TX
DCS_RX
GSM_RX
WCDMA_RX
VCCB
VCCA
V_wivi_B
V_wivi_A
WCDMA_TX
EXTLDO
VDD_A
VDD_B VCCB
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0.01uC1404
C144422p
L1411
6.8nH
10
R1740
C1400NA
C1453
0.01u
R1505NA
LK20A
Z1400
1G
1
3G
2
5G
32
IN
4O
1
6O
2
0R1401
10KR1772
L17601uH
C1452
0.01u
R1721
R14100
0
L1441100nH
27pC1423
22p
C1401
1.2pC1413
1.2pC1412
V1770
BBY58-02W
C17600.01u
C1770
C1722
0.01u
NA
22pC1750
C14412200p
4.7p
390p
C1776
22p
C1721
C1424
56p
C1778
5.6KR1720
TP1403
0
R1723
47p
C1777 C1772
100
R2108
330p
C1451
0.01u
0.01uC1448
22pC1741
10
R1430
C1421
NA
TP1402
L1402NA
C140722p
0.01u
C1454
4.7pC1773
2200pC1425
0.01uC1447
22pC1403
22p
TSX-8AB1770
13MHzGND12
4GND2
HOT1 1
3 HOT2
C1431
2GND
IN+1
IN-6
OUT+4
OUT-3
5SHIELD
Z1420TMX-M453
L142168nH
C141422p
10K
R1771
C17400.01u
22p
1000p
C1751
C1402
68nHL1422
C142227p
82pC1761
1K
R1770
R1730
10C173122p
0
R1431
0
R1760
C17205600p
1.2p
0.01uC1730
C1443
L14012.2nH
C1
K5
VC
CP
HD
VC
CP
LL
K4
B10VCCREF
K1VCCRF
VC
CR
FL
OK
9V
CC
VC
OK
8V
TU
NE
K7
C10XOIA
D10XOIB
XOOAC8
XOOBD8
H3
XO
OO
N
C7
MIXINAD1
MIXINBE1
K6
PH
DO
UT
A7
QR
AA
8Q
RB
REFONG8
RFINH1
J10RFLOOA
K10
RF
LO
OB
K3
RF
OU
T
H4
RX
ON
STROBEF3
E10VCCBUS
A3
VC
CIF
A6
VC
CL
F
VCCMIX
GN
DM
IX
GN
DP
HD
H6
H5
GN
DP
LL
GNDREFE8
H10GNDRFLO
GN
DT
UN
EH
7
GNDVCOH8
A4
IFIN
AA
5IF
INB
F10IFLOA
G10IFLOB
A1
IFO
UT
IFOUTBB1
K2
IND
BY
P
A9
IRA
IRB
A10
MC
LK
N1400LZT-108-5323
C5
CD
IC
DQ
C4
CLKE3
DATAD3
GLNAG3
GNDBIASF1
GNDBUSF8
J1GNDBYP
GNDEMEG1
C3GNDIF
GN
DL
FC
6
A2
R1440
0
R14113.3K
C1442
TP1401
2200p
VCCB
RFLO
VCCB
VCXOCONT
VCCB
RXQA
RXQB
RXIA
RXIB
MCLK
RFLOBAR
WRFLOOPWCLK
WDAT
IFLO
IFLOBAR
CLKREQ
WSTR
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XOOB
GPRFCTRL
WCDMA_RX
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0
R1632
0
R1605
75L1507
C1508
2.2p
L15035.6nH
100pC1714
C1601
TP1502
0.01u
C1628
TP1504
1000p
R1703
0
C17030.01u
100KR1628
R1617
0
10pC1509
VBATI
R1629
0R1621
0
C1631
R1711
0
10p
R15100
NAL1506
L1603
22p
XO
OB
XO
OC
C1
VBATI
C1602
ST
RO
BE
TX
ON
E8
VCCBBA5
D1
VC
CB
US
J7VCCIF
G1
VC
CIF
LO
VCCIFPHDA6
VCCIFPLLA8
A10VCCIFVCO
J1V
CC
RF
VC
CR
FP
HD
E10
VC
CR
FP
LL
G10
VC
CR
FV
CO
H10
VT
UN
EIF
B10
VTUNERFJ10
C7WON
B1
IFBPJ9
IFBPBAR
E1
IFL
OIF
LO
BA
RF
1
INA4
INBARA3
MIXOUTJ5
MIXOUTBARJ6
J2OUTOUTBAR
J3
PHDIFOUTA7
PH
DR
FO
UT
F10
A2QIN
A1QINBAR
H1
RF
LO
I1R
FL
OB
AR
G8
C5C6
GNDIFPLL
GNDIFVCO1A9
D10
GN
DIF
VC
O2
J4GNDRF
H4GNDRF1GNDRF2
H5
GNDRF3H6
G3
GN
DR
FL
O1
GNDRFLO2H3
D8
GN
DR
FP
HD
GN
DR
FP
LL
F8
C8
GN
DR
FV
CO
1
GN
DR
FV
CO
2H
8
GN
DT
UIF
C10I10
GN
DT
UN
ER
F
J8LZT-108-5322
N1700
C4CLK
DA
TA
E3
GN
DB
BC
3
GN
DB
US
D3
H7GNDIF
GN
DIF
LO
F3
GNDIFPHD
15nH
L1502
L1501
15nH
NAC1636
TP1501
L1605
0.01uC1510
4p
NA
C1502
C1511
C1635
10pC15140.01u
GN
D1
GN
D2
GN
D3
GN
D4
INO
UT
R1701
10
CE0401G95DCB000-TT1N1650
22pC1704
R1630
0
10uC1623
R1501
L1604
0
C1712NA
C1710150p
1
VCTRL22
8VDETECT
TP1503
GN
D3
GN
D4
11
12GND5
13GND6
GND714
17GND8
GN
D9
20 21R
FIN
RF
OU
T10
VCC1118
19VCC12
15VCC21
16VCC22 VCC_BIAS1
4
5VCC_BIAS2
7VCC_DET
VCTRL1
N1630
RF9266
3GND1
22G
ND
10G
ND
1123
GND26
9
10R1702
22p
3300pC1711
V+ VO3
C1505
B1501
LM20BIM7X
GND12
5GND2 NC
1
4
C1715
R1997
0
100p
C1626330p
C2BATT
COMPA2
B4GND
C3LX
A3OUT
PGNDC4
A4REF
B1SYNC
_SHDNC1
A1_SKIP
N1620MAX1820ZEBC
4.7K
R1710
C150410p
C170122p 0.01uC1702
4.7uC1627
C16244.7u
10pC1512
C16320.01u
C1716
4.7p
C162222p
C150322p
C15130.01u
0
R1631
NAR1606 R1604
NA
0R1503
1G1
3G2
5G32
S_OUT
L1601
SX-S205BZ1500
4B_IN1
6B_IN2
C1501
4.7uH
L1621
47p
33KR1626
0
R1603
R1504
680
680
R1502
TP1701 TP1702
39K
R1627
8.2nHL1504
NA
R1633
L1602
L1720
NA
L150510nH
C1507
4p
0
WDCDCREF
WPAREF
V_wivi_A RTEMP
R1623
V_wivi_A
VCCWPA
WPOWERSENSE
RFLO
RFLOBAR
V_wivi_A
V_wivi_B
IFLOBAR
IFLO
V_wivi_B
VCCWPA
V_wivi_B
WCLK
WDAT
TXIATXIBTXQATXQB
WSTR
XOOBXOOA
WCDMA_TX
V_wivi_A
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11
5
Date Changed:
G
C
3
REV:
12
E
104
U8100 PT V1.3 Staggered AMD
TITLE:
NA
Drawing Number:
H
BLM15BB750SN1J
1
D
Size:
3
A
F
9
QA CHK:
8
LG ELECTRONICS INC.
91
H
DOC CTRL CHK:
12 1 8 A
A2
3G HANDSETS LAB.
2012
6
2
Changed by: Page:
MFG ENGR CHK:
DEVELOPMENT GROUP 1
R&D CHK:
C
B
F
B
125
BLM31PG601SN1
Time Changed:
D
G
A
10
8
GSM/DCS (INGELA)
1608
2012
4 76
7
Tuesday, September 04, 2003
JS Joo
JS Joo
7:25:06 pmJS Joo 4
R1121NA
C1334
22p22p
C1113
R1240
0
1KR1329
C13231200p
R1320
0
N1330LDB21897M15C
B13
B24
GN
D1
2
GN
D2
5 6N
C
UB1
V13302SD2216J
L1202
560R1340
L1300
R1342560
NAR1339
22p
C1335
C133310p
10p
3.9nHL1100
C1100
470pC1320
NA0.01uC1150 C1155C1153
NAC1151NA
0R1150
R1151
0 C11560.01u
TP1142
100KR1140
VDIG
TP1143TP1141
C1115NA
C11147p
3.3nHL1101
0.01u NAC1220
XOOCK9
XOOLAH7
C1221
A1RFHD
A5RFLA
A4RFLB
RX
ON
E3
STROBEC7
K1
TX
OH
A
J1T
XO
HB
TX
OL
AG
1T
XO
LB
F1
TX
ON
D3
VC
CB
UF
H1
VCCPLLK7 A6
VCCRF
G10
VC
CV
CO
H10
VT
UN
E
XOOBK8
K6MODD
C10
NC
1D
10N
C2
H4NC3
NC
4H
8
K2NC5
K10NC6
PC
TL
G3
J10
PH
DO
UT
H5PS
A8QRA
A7QRB
REONC4
RF
HA
C1
RF
HB
D1
A2RFHC
A3GNDRF
GN
DR
F1
B1
GN
DR
F2
E1
E10
GN
DS
ILE
NT
GN
DV
AR
G8
B10
GN
DV
CO
1
GN
DV
CO
2C
8
GN
DV
CO
3D
8
GN
DV
CO
4E
8
GN
DV
CO
5F
8
F10
GN
DV
CO
6
IRAA10A9
IRB
K3MODAMODB
K4K5
MODC
LZT-108-5325
BS
EL
F3
C5CLK
DATAC6
H3GNDBUF
C3
GN
DP
LA
NE
GNDPLLH6
1200p
N1100
C1224 C12020.01u
C120322p
C1270
1000p
L1120
0.01uC1104
22pC1103
C131510u
C1322
150p
NA
L1110
C1351
560
R1220
18nH
120
R1222
390
R1223
C1223330p
R1211
R1210
100
100
100
R1212
R1213
C1300
100
0.068u
0
R1302
VBATI
VDIG
C1271
1000p
0R11060
0
R1104R1105
R13010
C1321470p
NAR1328
R13211K
33p
C1332
10nHL1111
C1110
33p
C1222560p
33p
C1112
0R1332
NAC1250
C1240
R1113
NA
C1324100p
C1325100p
0.05
R1326
NA
0
R1250
C1326
0
R1334
C1343NA
0
R1335
C133022p
100uH
L1220
C1225
1800p
0
R1333
R1338
0
C1102
10p
33p
C1111
O2
C1101
10p
Z1100
1
G1
3
G2
5
G3
2IN
4O1
6 VDD3B7
VDD4F5F8
VDD5H6
VDD6
VSS1A1B1
VSS2VSS3
C4
VSS4E8F4
VSS5F7
VSS6VSS7
G3
VSS8G4H8
VSS9
B7714
G1MICIN
F3MICIP
NC1G2
NC2H1
PCMCLKF6
PCMDLH7
PCMSYNG6
G7PCMUL
QDATD5
QRAA6
QRBA5
RESETBD2
REXTE3
RXSTRB4
VDD1A2
VDD2B5
B8GPA0
B6GPA1GPA2
C6
GPA3C7C8
GPA4GPA5
D6
GPA6D8
GPA7D7
E5GPCLK
E6GPDAT
D1I2CCLK
D3I2CDAT
IDATA4
A8IRA
A7IRB
G8MCLK
AVDDF1
H5BEARNBEARP
G5
F2CCO
C3DAC01DAC02
B3
DAC03A3
DACCLKC2C1
DACDATD4
DACSTR
DCLKC5
E2DEC1
H2DEC2DEC3
H3B2
DEC4DEC5
E1
LZT-108-5321N1101
E7ADSTR
E4AUXI1
AUXO2H4
R1324NA
R1103
0
R1323NA
L133275
NA
R1322
NA NAC1342 C1340
1.8nH
L1340
R1325
0
0
R1327
10
R1341
B7705Z1110
G12
G2
5
IN1
O1
3
O2
4
0.068uC1144
0.068uC1143
C11400.068u
0.068uC1141
C11420.068u
TP1152TP1151
0
R1224
R1337NA
C1336NA
22p
75
C1331
R1273
L1333
NA
NA
R1272
5.6nHL1201
3B1
4B2
2G
ND
15
GN
D2
NC
61
UB
C1231NA
LDB211G8020CN1331
C1230NA
22p
L1230
C1313C1311 C13120.01u10u
TP1202
TP1203
TP1201
L1200
22pC1205
0.01u
NAC1350
C1201
L1350 2.2nH10p
33p C1352
C1341
C132733p
15nHL1331
L1330
EGSM_OUT
GND11
GND23
GND35
GN
D4
7
9GND5
GND611
GND713
15G
ND
8
6V
CC
1
8V
CC
2
33nH
AP
C14
BG
ND
017
18BGND1
BGND219B
GN
D3
20
21BGND4
BGND522
BS
16
DCS_PCS_IN2
DCS_PCS_OUT12
4EGSM_IN
10
RXON
DCS_RX
N1300CX77304-16
PULSESKIP
VDIG
VDIG_HERTA
VDIG_HERTA
RXON
RESOUT3n
QDATASYSCLK2 IDATA
I2CDATI2CCLK
DCLK
PAREG
FF_IN
VDDBUF
IOUT
EXPOUT
VDDPA
VSSPA
GPRFCTRL
BSEL0
PCTL
GSM_TX
DCS_TX
VLOOP
PASENSE+
PASENSE-
XOOA
XOOB
VCCA
VCCA
VCCA
RADCLK
RADDAT
RADSTR
TXON
GSM_RX
MODA
MODB
MODC
MODD
VCCA
9. CIRCUIT DIAGRAM
- 239 -
IRDA REGULATOR
1%
7
BACKUP BATTERY
R&D CHK:
D
12
Engineer:
1608
NA
4.7uF, 2012
G
1
CHOKE COIL
G
2012
9
1.5V REGULATOR
11
2012
H
1608 120 OHM BEAD
Time Changed:
4
2012
2
TITLE:
MFG ENGR CHK:
BLM18PG121SN1
7
E
Drawing Number:
10
3G HANDSETS LAB.
VINCENNE
1608
3
DOC CTRL CHK:
2125
2012
ELL5GM220M
H
INDICATOR LED
3.3V REG
TJATTE2
HOOK
E
F
1608
USB REGULATOR
Size:
C
SIM HOLDER
Changed by:
1608
6
REV:
1608
AUDIO AMP
10
1
8
BLM15BB750SN1J
2012
6
LG ELECTRONICS INC.
U8100 PT V1.3 Staggered AMD
3
Date Changed:
1%
KPD9D-8S-2.54SF
F
1608
A2
12 1 8 A
NA
5
4
1%
11
B
D
12
Drawn by:
OBG-15S44-C2KU
2012
1608
1608
C2302 & C2303 CLOSER TO SIM SOCKET
C
DEVELOPMENT GROUP 1
9
BLM15BB750SN1J
A
8
ROP-101-3029_2C
2
A
B
QA CHK:
5
Page:
1608
B2SD_MODESD_SEL
C2
VDDB1
VO1A3
VO2C3
mentor Tuesday, September 04, 2003 7:25:29 pm
TAE-SUNG, HA
TAE-SUNG, HA
5
BB MAIN PCB
LM4898ITL
N2601
BYPASSA2
GNDB3
A1IN+
C1IN-
0.1u
R3046
100K
C3248
100K
R3047
TP3000
33K
R2609
C261822p
C3271 C327247p
VBATI
47p
R3382
24
L2605
0R2210
100K
R3045
R30500
B
C
E Q3203DTA114EETL
22pC2614
4.7uC3013 0
R2235
R30
26
100K
R2305
15K
22pC2610
VDIG
TP3318
C3273
C3274NA
NA
R2200
0
R2614
NA
0.033uC2613
R2608
3.9K
3.3KR3378
R2213
0.22
0.22
R2208
C2280
NA
C2200
C2212
10u
VSS
0.1u
N2203
S-817A15ANB-CUE-T24
NC
VIN2 3
VOUT
1
0.1u
C2211
VDIG
R2201
0
R3385NA
VDIG
C2633
22p
1uC2603
10
R2613
4
GND2
ON_OFF3
1VIN VOUT
5LP2985IM5X-3.3
N2204
BYPASS
NAC2300
22pC2631
R2312
10K
R230647
TP3004
VBATI
R2621 0
N2603ADG702
1D
GND3
IN4
NC52
SVDD
6
R33288.2K
NA
C2634
100pC2276
R2212
0
0.1uC2210
R2607
3.9K
2GND1
GND25
NC1
4V+
3VO
0.068u
U3106
LM20BIM7X
C2615
VSSTH3G6
VSSTH30F4
VSSTH31E4
VSSTH4E5E6
VSSTH5VSSTH6
E7
VSSTH7E8F8
VSSTH8VSSTH9
G8
VSS_AH10G3
VSS_BVSS_C
C6
VSS_DE3
M1XTAL1
M2XTAL2
VSSTH15F5
VSSTH16D5
D6VSSTH17VSSTH18
D7VSSTH19
D8
G7VSSTH2
E9VSSTH20VSSTH21
F9VSSTH22
G9H9
VSSTH23VSSTH24
J8VSSTH25
J7J6
VSSTH26
J5VSSTH27VSSTH28
H4G4
VSSTH29
M11VDD_D
L12VDD_E
VDD_IOC3
VIBRB3
J12VREF
VSSADCK8
K4VSSBEAR
B1VSSBUCK
VSSCODECK5
VSSPAE10
VSSTH1F7
VSSTH10H8
VSSTH11H7H6
VSSTH12VSSTH13
H5G5
VSSTH14
TESTD4
A8TXON
A12VBAT_A
VBAT_BM12
A3VBAT_C
E1VBAT_D
B2VBUCK
M9VDDADC
VDDBEARM3
A2VDDBUCK
C12VDDBUF
VDDCODECM5
VDDLPL2
G12VDDPA_DAC
B12VDD_A
VDD_BA11
PCMSYNK1
PWRRSTB8
RESETBA9
SCLB9
SCLKJ3
C8SDA
H1SDAT
SIMCLKG1
SIMDATH3
SIMOFFC2
G2SIMRST
SIMVCCF1
SLEEPC10
H2SRST
D10SUB
SWBUCKA1
MIC1NL8
M8MIC1P
L7MIC2NMIC2P
M7
MOD1B4
A5NBUCK
ONSWAC4C5
ONSWBA7
ONSWC
D11PAREG
PASENSE+E12E11
PASENSE-
PBUCKA4
PCMCLKJ1
J2PCMI
K2PCMO
GPA1L10
GPA12J9D9
GPA13
K10GPA2
L11GPA3
K11GPA4
GPA5K12
J11GPA6
J10GPA7
INTLCKBB7
IOUTD12
IREFH12
IRQC1
LED1A6
B6LED2
MCLKK9
DACCLKA10
C9DACDAT
B5DACO1DACO2
G11
DACO3H11
B10DACSTR
DCIOE2
DEC0L5K6
DEC1K7
DEC2
EXPOUTG10
C11EXTLDO
F10FF_IN
F11FGSENSE+
FGSENSE-F12
M10GPA0
32KHZL1
C7ADSTR
M6AUXI1
AUXI2L6
L4AUXO1
AUXO2J4
B11BDATA
BEARNL3
M4BEARP
CCOL9
F3CDCDA
CDCDBF2
D1CHREG
D3CHSENSE+CHSENSE-
D2
K3CLK_REQ
C2274
N2000VINCENNE
0.1u
0.1
R2214
D1 6
D23
2 G1 G2 5
S11
4S2
47KPT1
Q2200
SI1555DL
R261722K
R2606 33K
R32
94
NA
0.51R3345
R23
14
0
NA
0C3275
100K
R21
06
R3395
D2010
1SS388
0
R2217
NA
R2615
0.1uC2209
100K
R21
01
0
R3019
R3043
100K
100uC2611
VMEM
C2301 1u
C26081u
C2635
NA
0
R2313
C2206
10u
2.2uC3051
TP3319
VBATI
C23
0310
00p
R338147K
C22140.1u
0
R33
96
51KR2233
R3384
NA
R3379
0
C2205
C3268
VDIG
VDIG
10u
47pRB521S-30D2016
L2200 22uH
1uC
2302
TP2311
2.2u
C2278
1D1
2D2
3D3
6D4
7D5D6
8
4G S
5
Si5441DCQ2201
NAC3267
C22031u
4.7uC3052
VB
AT
I
R3248
0
100K
R3042
0.1u
C2604
C3266
10p
22p
C2616
R2205
0
VCORE
0.05
C2638 NA
R22
16
6432
1
5X2602
22p
GND19
GND210
GND31112
GND4
P112
P23
P34
P4
P55
P667
P78
P8
C2630
C2272
X2300
1u
0R3376
L2608
C2621 0.1u
C3046100p
R2220
100K
C3246
0.1u
L2202
100pC3278
FB3
FB4
1IO1
IO23
IO34
6IO4
5REF1
2REF2
R2215
V2300 DALC208SC6
0.05
R3041
100K
NA
R2107
0R2618
R2610100K
R2218
0
BA3000
C2637
VEXT15
TP3316
NA
VDIG
100uC2619
0
R3002
L2606
NAC3277
0
R3397
C2607
SUMY0005601
12
NA
0.1u
X2603
C2207
1KR2203
VDIG
C3247
0.1u
NAR3386
V3202
RB521S-30
4.7u
VUSB
TP2310
VBAT
C2281
RB521S-30V2201
BYPASS4
GND2
ON_OFF3
1VIN VOUT
5
0R2202
LP2985IM5X-2.8
N3000
C2202
4.7u
C326947p
R3303
C2609
100K
C2606
0.01u
0.33u
22p
C3221
22p
C2632
VDIG
GND3
C3GND4GND5
C4C5
GND6
A1MICN
MICN_INTD1
A2MICP
D2MICP_INT
VDDB5
AFMS_LA5
D5AFMS_L_INT
B4AFMS_R
AFMS_R_INTD4
ATMSA3
ATMS_ADC2
A4ATMS_CAP
ATMS_INTD3
CCOC1
B1GND1GND2
B2B3
IP4025CX20N2602
VIRDA
R3327180K
0R2619
0.1uC2605
RB521S-30D2015
R223210K
0.068u
VCORE
VBATI
C2617
0R2620
0.068u
C2612
R30
51
100K
NAC3270
L2603
R3049
100K
R30310
VDIG
4.7uC2277
C23
12
0.1u
C2213
22p
SPKMVRTC
GPIO05
PWRRSTn
EN_LED_R
GPA6
DCIN_2
VBUS
USBSENSE
PWRRSTnIRDA_REG_CTRL
PCMDATA
EN_LED_TC
DC
IN_3
VBAT_C
PCMDATB
SPKMUTEGPA6
TGBUZZ
ADCSTR
AMPCTRL
EARP
EARM
SPKP
CLKREQ
RTEMP
VLOOPWPOWERSENSE
WRFLOOP
VBACKUP
MOTOR_BATT
DACDATDACSTRDACCLK
VSSPAVDDPA
VDDBUFPASENSE+PASENSE-
PAREGIOUT
PCMCLKPCMSYN
VBACKUP
VDD_A
VDD_B
RESOUT0nONSWAnONSWBn
ONSWC
RTCCLK
SIMDAT0SIMCLK0SIMRST0
MCLK
PWRREQn
I2CDATI2CCLK
WDCDCREFWPAREFVCXOCONT
DCIN_3
EXPOUT
EXTLDO
FF_IN
IRQ0n
TXON
VBAT_C
9. CIRCUIT DIAGRAM
- 240 -
12
G
C2100 and C2101 close to B2100
50V 1608
U8100 PT V1.1 Staggered AMD 0 .8 PITCH 9 X 12 X 1.25128/128/64128 0.8 PITCH 9 X 11.5 X 1.0
UART0
PCM I/F
USB
1
DEFAULT
7
E
1110
G
Size:
ADDRESS X DATA = 2^23 X 2^4 = 2^27 = 128MBIT
7
A22 = 128MBIT
U8100 PT V1.0 NMBI TOSHIBA
32.768KHz
0.8 PITCH 10 X 8 X 1.4
Time Changed:
9
E
Rout track on inner layer
Drawn by:
64/64/16
E
H
0.8 PITCH 9 X 12 X 1.4OPTION
MFG ENGR CHK:
10
0.8 PITCH 10 X 8 X 1.4
100K
P_M
OD
E
1.8V 3.3V U8100 WS01-5
U8100 ES01-2
U8100 WS01-4
H
A
D
0.8 PITCH 10 X 8 X 1.4
H
8
Changed by: Date Changed: Drawing Number:
VDDC 1.5V
G
F
LOW POWER MODE : LEDA VCC
11
1608
2
* MEMORY CHANGE HISTORY
1.8V
Page:REV:
7
H
128/128/64
MARITA
9
64/64/16
A
MCP
1110
3G HANDSETS LAB
C
5
B
64D/64D/16PS128L/128L
10
B
U8100 ES01-1
0.8 PITCH 10 X 8 X 1.4
64/64/16 0.8 PITCH 9 X 12 X 1.4
LCD I/F
B
A
D D
U8100 ES01-6 TOSHIBA 0.8 PITCH 9 X 12 X 1.4128/128/64128
Engineer:
6
128/128 0.8 PITCH 9 X 12 X 1.4
0.8 PITCH 10 X 8 X 1.4
RF I/F
Rout track on inner layer
1.5V
DOC CTRL CHK:
A22 = 128MBIT, A21 = 64MBIT
2
1
A
B
U8100 WS01-1
9
C
0.8 PITCH 10 X 8 X 1.4
U8100 WS01-3
0.8 PITCH 9 X 12 X 1.4ADDRESS X DATA = 2^23 X 2^4 = 2^27 = 128MBIT
4
F
128/128/64128 0.8 PITCH 9 X 12 X 1.4
U8100 PT V1.0 Staggered TOSHIBA 0.8 PITCH 9 X 12 X 1.4128/128/64128 0.8 PITCH 9 X 12 X 1.4
FLASH
OPTION
0.8 PITCH 9 X 12 X 1.4
4
64/64/16
0.8 PITCH 10 X 8 X 1.4
6
IrDA
2
0.8 PITCH 10 X 8 X 1.4
11
TITLE:
HSSL
U8100 WS01-2
5
KEY I/F
3
50V 1608
QA CHK:
F
G
64/64/16
CS2
LG ELECTRONICS INC.
64/64/16
UART1
100K
fo
r In
tel
SD(L:ACTIVE, H:SHUTDOWN)
C
D
CS 0,1,3
E
DAC
DEVELOPMENT GROUP1
0.8 PITCH 10 X 8 X 1.4
F
C
SIR TRANCEIVER
MARITA
9
JTAG I/F
64/64/16
3
64/64/16
2002.09.13
3
8
8
64/64/16
5
BB MAIN PCB
7
4
2.75V
64/64/16
0.8 PITCH 10 X 8 X 1.4
1.5V
12
0.8 PITCH 10 X 8 X 1.4
1
CAMERA I/F
12
6
mentor Tuesday, September 04, 2003 9:42:54 am
SUNG-JU, YOU
SUNG-JU, YOU
6
U8100 PT V1.3 Staggered AMD
A2
12 1 8 A
R&D CHK:
0.8 PITCH 10 X 8 X 1.4
1
0.8 PITCH 14 X 8 X 1.4
U8100 ES01-3 TOSHIBA
12
MCP 64/08.
VDDC 1.5V
6
128
8
VDDE 1.5V
0.47u
C3137
47R2109
3.3K
VDIG
TP2404
R21
22
TP
3117
NA
R21
21
100K
R33
22
0.1uC2263
C22580.1u
TP2125
TP
3111
1000pC2104
0.1uC2261
22p
C2101
470
R26
22
C22170.1u
12 3
4
VRTC
MC
-146
B21
00
32.7
68K
Hz
0.1u
Q32
02P
MS
T39
042
31
C2221
R33
303.
3K
C22620.1u
TP2100
0.1uC2216
C22470.1u
R31
100
VEXT15
4.7K
R33
29
0.1uC2243
R23
03
4.7K
RB521S-30
V2203
0
R22
41
C2102
VMEM
330p
VUSB
TP3313
100K
R21
02
TP2402
C3133
VMEM
TP2102
0.1u
VIRDA
VMEM
TP3126
R33
21N
A
100K
R31
26
TP
3101
R21
05
130K
C22440.1u
0.1uC2251
K7
_AVDG1
_CEH2
_OEJ2
_RESETD5
_WEC5
_WPF1
C22220.1u
NC
24
A7
NC
3N
C4
A8
B1
NC
5N
C6
B2
B7
NC
7N
C8
B8
C1
NC
9
C4RDY
VCC1D1
VCC2J5
F8VIO1VIO2
H1
G8VSS1
J1VSS2
K2VSS3VSS4
NC
1
NC
10C
8E
8N
C11
H7
NC
12
NC
13H
8 J8N
C14
NC
15K
1K
8N
C16
NC
17L
1L
2N
C18
NC
19L
7
NC
2A
2
L8
NC
20
NC
21M
1M
2N
C22
NC
23M
7M
8
DQ0
K3DQ1
DQ10H4
DQ11J4H5
DQ12
J6DQ13
H6DQ14DQ15
J7
G4DQ2
K4DQ3
K5DQ4DQ5
G5DQ6
K6G6
DQ7DQ8
H3DQ9
J3
A1
A17
E4A18A19
F5
E2A2
A20F4E5
A21A22
D8
C2A3A4
D2F3
A5A6
E3C3
A7
D6A8A9
C6
D4ACC
CLKE1
G3
A0G2F2
A1
E6A10A11
F6A12
D7C7
A13A14
E7F7
A15A16
G7D3
U3104AM29BDS128HD9VKI
0.1uC2260
VDIG
TP
3100
R3100NA
R33
37N
A
VCORE
0.1uC2252
R33
19
1K
TP
3116
VMEM
C3225
C3222
0.1u
0.22u
VDIG
C22570.1u
0
R22
21
R31
03
0
C22530.1u
VEXT15
R22
38
0
R23
01
NA
0.1u
TP3317
C3276
0
R22
23
0.22uC3136
VDIG
C3135
0.1u
R33
23
100K
TP
3118
TP3344
C22450.1u
7GND
LEDA1
2LEDK
RXD4
5SD
SHIELD8
3TXD
VCC6
N3100CIM-80S7B-T
0
R22
22
C22500.1u
C22180.1u
NA
R33
20
C22200.1u
100
R33
25
C22190.1u
TP2405
0.1uC2223
TP
3113
TP
3114
TP
3115
0
TP2401
R22
37
TP2403
TP
3102
TP2101
G3VSS1
J9VSS2VSS3
L4
_ADVB2
_CE1SJ2
H2_CEF1_CEF2
B5
C4_LB
H3_OE
_RESETD5
_UBD4
_WEC6
_WPC5
RTC_GND
L3
RF
U17
RF
U18
L6
L7
RF
U19
RF
U2
B6
RF
U20
L8
L9
RF
U21
B7
RF
U3
RF
U4
B8
B9
RF
U5
RF
U6
C9
F5
RF
U7
RF
U8
F6
G5
RF
U9
VCCF1J5L5
VCCF2
VCCSJ6
DQ7J8K3
DQ8
H4DQ9
A1
NC
1N
C2
A10
NC
3M
1M
10N
C4
E5RDY
B3
RF
U1
RF
U10
G6
G8
RF
U11
RF
U12
H9
K2
RF
U13
RF
U14
K6
K9
RF
U15
RF
U16
L2
ACCC2
CE2S_ZZD6
B4CLK
DQ0J3
DQ1G4
J4DQ10
K5DQ11DQ12
J7DQ13
H7DQ14
K8DQ15
H8
DQ2K4
DQ3H5
DQ4H6K7
DQ5
G7DQ6
A15D9G9
A16A17
F4A18
E4D7
A19
A2E2
E6A20A21
E9F9
A22
A3D2F3
A4A5
E3D3
A6A7
C3A8
C7E7
A9
U3103S71WS256HC0BAW00
G2A0A1
F2
A10F7C8
A11
D8A12A13
E8F8
A14
TP
3103
VCORE
R31
27
100K
0.1u
C3134
VMEM
0.1uC2255
B
C
E
VMEM
RN1107Q2100
0.1uC2242 C2259
0.1u
J18
WE_NC8
RTC_GND
VMEM
H8
VS
SE
112
A2
G4
VS
SE
200
R4
VS
SE
201
VS
SE
202
U4
R9
VS
SE
203
VS
SE
204
V8
VS
SE
205
Y16
V18
VS
SE
206
VS
SE
207
Y21
F18
VS
SE
208
VS
SE
209
A21
VS
SE
210
D16
VS
SE
211
L18
VS
SM
CK
18
R11
VS
SR
TC
VS
SU
SB
A19
K20
VD
DM
C
AA
11V
DD
RT
C
J21
VD
DU
SB
V12
VS
SA
0V
SS
A1
W13
VS
SA
2V
14E3
VS
SD
M
VS
SE
00L
4M
7V
SS
E01
W9
VS
SE
02E
4V
SS
E10
0D
15V
SS
E10
2D
13V
SS
E10
4G
10V
SS
E10
6G
9V
SS
E10
8V
SS
E11
0
VD
DE
101
B16
VD
DE
102
VD
DE
104
A13
A11
VD
DE
106
VD
DE
108
B8
VD
DE
110
A5
A3
VD
DE
112
VD
DE
200
H2
U1
VD
DE
201
AA
1V
DD
E20
2V
DD
E20
3A
A3
Y6
VD
DE
204
Y18
VD
DE
205
V20
VD
DE
206
VD
DE
207
N21
B21
VD
DE
208
VD
DE
209
R1
VD
DC
08Y
1A
A7
VD
DC
09H
20V
DD
C10
VD
DC
11A
15L
21V
DD
C12
VD
DC
13A
17
VD
DC
14B
1K
2V
DD
C15
A9
VD
DC
16V
DD
C17
B6
VD
DC
18R
20
VD
DD
ME
1
VD
DE
00M
2N
2V
DD
E01
VD
DE
02Y
10C
2
V13
R13
TS
YP
G3
TX
ON
USBDMJ20
USBDPJ15
H19USBPUEN
VD
DA
0Y
12
VD
DA
1A
A13
R14
VD
DA
2
AA
19V
DD
C00
VD
DC
01N
1R
12V
DD
C02
Y14
VD
DC
03V
DD
C04
M20
D20
VD
DC
05B
12V
DD
C06
VD
DC
07
N18
SIM
DA
T1
M19
SIM
RS
T0_
NN
19
L15
SIM
RS
T1_
N
R3SYSCLK0SYSCLK1
T2T3
SYSCLK2T
CK
W8
Y9
TD
IT
DO
AA
9
TE
MU
0_N
P11
V10
TE
MU
1_N
R10
TM
S
V9
TR
ST
_N
TS
XM
Y13
W14
TS
XP
TS
YM
RESOUT3_NU3
RESOUT4_N
RESPOW_NR2
RF
CL
KK
8
RF
DA
TG
1H
4R
FS
TR
RT
CB
DIS
_NW
10
RT
CC
LK
W12
P12
RT
CD
CO
N
V11
RT
CIN
RT
CK
Y8
RT
CO
UT
W11
RX
ON
G2
SERVICE_NL3
SIM
CL
K0
N20
M18
SIM
CL
K1
SIM
DA
T0
C21
PDIC4E18B18
PDID0PDID1
D17
PDID2C18B19
PDID3PDID4
A20
PDID5H13G14
PDID6PDID7
B20
D19PDIRES_N
PWRREQ_NT4
QD
AT
AL
7
RESOUT0_NF4L1
RESOUT1_NRESOUT2_N
P8U2
J14
J19
MM
CD
AT
MS
BS
K14
MS
SC
LK
K19
MS
SD
IOK
15
E5NCNC0
L14
D8OE_N
PC
MC
LK
V3
PC
MD
AT
AW
2
PC
MD
AT
BV
4
W1
PC
MS
YN
L8
PC
TL
C19PDIC0PDIC1
D18C20
PDIC2PDIC3
W15
KE
YIN
3_N
V15
W16
KE
YIN
4_N
P14
KE
YO
UT
0_N
KE
YO
UT
1_N
AA
17
KE
YO
UT
2_N
Y17
KE
YO
UT
3_N
W17
V16
KE
YO
UT
4_N
W18
KE
YO
UT
5_N
MCLKP13
B9MEMADV_N
MEMBE0_NC1D3
MEMBE1_N
MEMCLKG8
MEMWAIT_ND2
L19
MM
CC
LK
MM
CC
MD
GPIO47
N8HSSLRXHSSLRXCLK
N3
HSSLTXN7N4
HSSLTXCLK
Y2I2CSCLI2CSDA
W3
K3
IDA
TA
M15
IRC
TR
L
IRQ0_NV2
IRR
XP
20
IRT
XP
19
M4ISEVENT_N
M3ISSYNC_N
AA
15K
EY
IN0_
NY
15K
EY
IN1_
NK
EY
IN2_
N
GPIO27GPIO30
U18T18
GPIO31GPIO32
U19U20
GPIO33N15
GPIO34GPIO35
U21T19
GPIO36GPIO37
T20R19
GPIO40GPIO41
R18V17
GPIO42AA21
GPIO43Y19
GPIO44AA20
GPIO45GPIO46
W19Y20
GPIO07V5
GPIO10GPIO11
Y4V6
GPIO12GPIO13
W5
GPIO14Y5
AA5GPIO15GPIO16
W6V7
GPIO17W7
GPIO20GPIO21
Y7P10
GPIO22P15
GPIO23GPIO24
N14
GPIO25W20V19
GPIO26W21
D9
DACCLKP3
DACDATP2P4
DACSTR
K4
DC
LK
E2
DIR
MO
D0
J7D
IRM
OD
1D
IRM
OD
2F
3
DIR
MO
D3
F2
M14GPIO00GPIO01
P18
GPIO02R21R8
GPIO03GPIO04
P9AA2
GPIO05GPIO06
Y3W4
CS3_N
D0A7B7
D1
D10D5B3
D11D12
D4C3
D13D14
B2A1
D15
D2C7D7
D3D4
C6B5
D5D6
C5
D7D6
D8B4C4
E20E21
CID1H14
CID2CID3
F19
CID4F20
CID5G18G19
CID6CID7
G20
G21CIHSYNC
CIPCLKH18
E19CIRES_N
H15CIVSYNC
M8CLKREQ
CS0_NJ8H7
CS1_NB10
CS2_ND9
H9
A24C9
G13A3A4
C16C15
A5B15
A6A7
H12D14
A8A9
B14
P7ADCSTR
AN
TS
W0
J2 J4A
NT
SW
1A
NT
SW
2J3
AN
TS
W3
J1
BA
ND
SE
L0
H3
K7
BA
ND
SE
L1
CID0
A1C17
C14A10A11
G12B13
A12C13
A13A14
H11D12
A15A16
C12
A17G11D11
A18A19
C11
B17A2
H10A20A21
C10
A22D10
A23
VMEM
ROP-101-3035_1
D2000
R3333 NA
47
R2100
3.3K
R23
04
0.1uC2246
TP
3112
120K
R2123
VDIG
TP2106
R33
38N
A
27
R33
46
0.1uC2256C2100
NA
R24
03
22p
D2012 1SS388
R21
04
100K
MEM_ADV_NMEM_CLK
RESOUT0n
ADR(23)
DAT(13)
DAT(11)
DAT(9)
DAT(7)
DAT(5)
DAT(3)
DAT(1)
MEM_WAIT_NMEM_ADV_N
MEM_CLK
VPPFLASH
VPPFLASH
ADR(2)
VCORE
ADR(11)
ADR(10)
ADR(9)
ADR(8)
ADR(6)
ADR(4)
ADR(2)
MEM_CS3_N
MEM_CS1_NMEM_CS0_N
I2CCLKMARITATCK
MARITATDI
MARITARTCKMARITATRST
MEM_CS2_N
MEM_WE_N
GPIO05
ADR(24)
ADR(1:24)
MEM_WAIT_N
ADR(24)
ADR(1:24)
MEM_WAIT_N
ADR(1:24)
MEM_CLKMEM_ADV_N
DAT(8)
DAT(9)
MEM_OE_NMEM_WE_N
DAT(0:15)
ADR(1)
ADR(3)
ADR(5)
ADR(7)
ADR(22)
MEM_CS2_N
MARITATEMU0MARITATEMU1
CAM_FLASH_ON
ADR(23)
ADR(22)
ADR(21)
ADR(20)
ADR(19)
ADR(18)
ADR(17)
ADR(16)
ADR(15)
ADR(14)
ADR(13)
ADR(12)
ADR(13)
ADR(14)
ADR(15)
ADR(16)
ADR(17)
ADR(18)
ADR(19)
ADR(20)
ADR(21)
MEM_OE_N
MEM_BE0_NMEM_BE1_N
MEM_WE_N
RESOUT0n
DAT(15)
DAT(0)
DAT(1)
DAT(10)
DAT(11)
DAT(12)
DAT(13)
DAT(14)
DAT(2)
DAT(3)
DAT(4)
DAT(5)
DAT(6)
DAT(7)
MEM_OE_N
DAT(0:15)
CAM_REG_EN
I2CDAT
I2CCLK_CAMERA
RA
DS
TR
DAT(0:15)
DAT(15)
DAT(14)
DAT(12)
DAT(10)
DAT(8)
DAT(6)
DAT(4)
DAT(2)
DAT(0)
ADR(1:24)
ADR(1)
ADR(3)
ADR(4)
ADR(5)
ADR(6)
ADR(7)
ADR(8)
ADR(9)
ADR(10)
ADR(11)
ADR(12)
KEY_LED_ONOFF
USBPUEN
LCDCSX_SUBLCDWRXLCDRSLCDCSX_MAINLCDRDXPDID0PDID1PDID2PDID3PDID4PDID5PDID6PDID7
GP
RF
CT
RL
EN_LED_BEN_LED_GEN_LED_R
LCDVSYNCI
SYSCLK2
CLKREQ
MEM_CS3_N
MEM_CS1_NMEM_CS0_N
MEM_BE1_NMEM_BE0_N
KE
YO
UT
0K
EY
OU
T1
KE
YO
UT
2K
EY
OU
T3
KE
YO
UT
4K
EY
OU
T5
KE
YIN
0K
EY
IN1
KE
YIN
2K
EY
IN3
KE
YIN
4
CIPCLKCIVSYNCCIHSYNCCIRES_N
CID0CID1CID2CID3CID4CID5CID6CID7
LCDRESX
BL_PWL
USBDPUSBDM
IRDA_REG_CTRL
BL_EN
PULSESKIP
DACCLKDACDATDACSTRADCSTR
IDA
TA
QD
AT
AT
XO
NR
XO
NR
AD
CL
K
RA
DD
AT
BS
EL
0
AN
TS
W0
AN
TS
W1
AN
TS
W2
AN
TS
W3
PC
TL
HSSLTX
HSSLRXCLKHSSLRX
HSSLTXCLK
PC
MC
LK
PC
MS
YN
PC
MD
AT
AP
CM
DA
TB
MCLK
RTCCLK
VPPFLASH
RESOUT0n
RESOUT3n
PWRREQn
ISSYNCnISEVENTn
IRQ0n
SYSCLK1
ADR(1)
7C_LED_VDD_EN
UARTRX0UARTTX0
UARTRX1UARTTX1
UARTRTS1UARTCTS1
CAM_FLASH_SHOT
USBSENSE
TGBUZZ
CAMERA_DET
AMPCTRL
SPKMUTE
FOLDER_DET
DAT(8)
DAT(9)
DAT(10)
DAT(11)
DAT(12)
DAT(13)
DAT(14)
DAT(15)
MARITATMS
MARITATDO
SIM
DA
T0
SIM
RS
T0
SIM
CL
K0
ONSWC
MO
DA
MO
DB
MO
DC
MO
DD
DC
LK
RESOUT1n
PWRRSTn
ADR(2)
ADR(3)
ADR(4)
ADR(5)
ADR(6)
ADR(7)
ADR(8)
ADR(9)
ADR(10)
ADR(11)
ADR(12)
ADR(13)
ADR(14)
ADR(15)
ADR(16)
ADR(17)
ADR(18)
ADR(19)
ADR(20)
ADR(21)
ADR(22)
ADR(23)
DAT(0)
DAT(1)
DAT(2)
DAT(3)
DAT(4)
DAT(5)
DAT(6)
DAT(7)
9. CIRCUIT DIAGRAM
- 241 -
Time Changed:
A
QA CHK:
12
Engineer:
116
H
F
D
8
5
10
10
R&D CHK:
3216
9
DEVELOPMENT GROUP1
5V
MFG ENGR CHK:
MULTIMEDIA INTERFACE
2012
DOC CTRL CHK:
HF SPK P
CAMERA REGULATOR
NA
KEYPAD BACKLIGHT BLUE LED I/F
1608
3G HANDSETS LAB.
C
11
G
1608
1608
REV:
NA
Page:
GT059-24P-3BL-P800
Drawing Number:
15mA x 16 = 240mA
7
PDM : ENEY0003301
LG ELECTRONICS INC.
1
CONN_10_5087_060_920_829
USB FILTER
D
Date Changed:
2.75V
3 6
U8100 PT V1.3 Staggered AMD
CAMERA ROTATION DETECTOR
C
1608
CHARGE PUMP
Changed by:
I/O CONNECTOR
F
8
7
KNATTE
G
2012
E
HF DETECTION
DTC SENSE
A
B
CAMERA I/F
12
B'd to B'd CONNECTOR I/F
E
PDM : ENBY0017602
AXK7L80225
2
Drawn by:
HF SPK N
CURRENT LIMIT
2
1608
1608
SUB LCD BACKLIGHT 4.5V
1
4
5
B
SC600B
H
Size:TITLE:
BLM18PG121SN1
9
HF MIC
3
4
NA
mentor Tuesday, September 04, 2003 2:11:39 pm
S .Y SEOK
S .Y SEOK
7
BB MAIN PCB
A2
12 1 8 A
SP
3200
D20141SS388
TP3307
0R3232
TP3204
1000
pC
3219
R33
41
0
R3222 NA
C32
5820
p
SP
3201
SP
3203
1u
C2208
12
R3207
0.1u
R3220
C25
00
NA
NA
D4
56D
5
GN
D2
R3225
V32
01
SM
F05
C D1
13D
24
D3
SP
3210NA
R2501
0R3229
TP3341
300K
0R3228
R33
31
TP3339
ADJ43
EN
2GNDIN
1OUT
5
TP3338
VBATI
MIC5219BM5
U3102
D20
08E
SD
1A
1
A3
ES
D2
C1
ES
D3
ES
D4
C3
GN
DB
2
CS
PE
SD
304A
1E
SD
1
ES
D2
A3
ES
D3
C1
C3
ES
D4
B2
GN
D
CS
PE
SD
304
D20
07
SP
3205
R3357 51
0
R3388
12
R3208
0R3249
TP3203
NAR3352R3353 NA
TP3343
VBAT
A2DFMS_eDFMS_i
D3A1
DTMS_eDTMS_iD2
B2
GN
D1
B3
GN
D2
GN
D3
B4
GN
D4
C1
C2
GN
D5
C4
VC
C
VPPFLASH_eA5D5
VPPFLASH_i
N2300 IP4022CX20
A4CFMS_eCFMS_i
D4A3
CTMS_eC3
CTMS_i
CTS_ON_eB1D1
CTS_ON_iB5
DCIO_eDCIO_iC5
2
56
31
4
Q3200EMX18
2.7K
R32
09
R33
44
83VIN
1VOUT
100K
N3201 SC600BIMSTR
CF1+2 9
CF1-
10CF2+
CF2-7
6EN
FID04
5FID1
GND
20p
20p
C32
61
C32
60
R25
05
NA
D20
18E
SD
1A
1
A3
ES
D2
C1
ES
D3
ES
D4
C3
GN
DB
2
R33
32
240K
CS
PE
SD
304
R2500
51R3366
NA
R3365
SP
3208
51
192
20
3
4
5
6
7
8
9
G1 G2
G3 G4
X3201
1
10 11
12
13
14
15
16
17
18
20p
C32
55
20p
C32
59
R33
47
100K
TP3205
SP
3212
NA
R3235
Q3201
UMC4N
2
45
31
R2502
0
SP
3211
470p
1uC3200
C3243
CRS08V3200
NA
R32
52
SP
3209
VCAM
C32031u
1uC3201
C32
1210
00p
51R3360
VDIG
C32442.2u
D20
09
CS
PE
SD
304A
1E
SD
1
ES
D2
A3
ES
D3
C1
C3
ES
D4
B2
GN
D
R33
9810
0K
VBATI
0
R32
37
Q2300RN1107
B
C
E
1KR2319
VBATI
FB2
100R3390
100R3389
NA
10uC3245
R32
36
SP
3204
VDIG
TP3340
NAR3350
C22
79
VCAM
0.01
u
V2500
C320210u
RB521S-30
R25
04
NA
0.1uC3204
TP3202
NAR3233
1SS388
L2201
D2013
R3363 51
1000
pC
3213
VDIG
VCAM
29V_BAT_3
NA
R32
11
PWR_+4_2V_222
4PWR_+5V_1PWR_+5V_2
5
12PWR_GND_1
19PWR_GND_2RFR_RTS
20
RI_TMS18
RXD1314
TXD
16USB_PWR
10USB_RX
USB_TX15
25VBAT_GND_1VBAT_GND_2
26
V_BAT_127
V_BAT_228
BATT_ID1
CTS23
17DCD
DSR3
24DTR
GND13031
GND2
2HF_MODE
6ON_SW1
8PCM_CLKPCM_RXA_IN
7
PCM_SYNC9
PCM_TXA_OUT11
21PWR_+4_2V_1
X3203
OU
T21
VD
D
C32
4920
p
A32
12E
LH
N32
00
GN
D3
NA
R32
10
10pC3205
FB1
R3206
SP
3206
100K
C3215
33u
NA
R25
03
R3223
SP
3207
0
C3220
4.7
R3263
0.1u
TP3336TP3337
0.1u
C23
04
0R3227
0R3230
SP
3202
TP3200
R3364 51
R3351 NA
56575859
6
606162
789
414243444546474849
5
505152535455
272829
3
30313233343536373839
4
40
1213141516171819
2
20212223242526
X32001
1011
3_3V5
D11
3D2 D3
4
6D4
GND2
TP3342
USBUF01W6
L2500
C32
52
TP3306
20p
R3367 51
CIPCLK
CIRES_NEARM
7C_LED_VDD_EN
EN_LED_TCI2CCLK_CAMERA
VPPFLASHONSWBn
CID2
CID3
CID0
CID4
CID5
CID1
CID7
CID6
USBPUEN
USBDM
UARTCTS1
UARTRTS1
CAM_REG_EN
UARTRX1UARTTX1
CAMERA_DET
CAM_FLASH_SHOTCAM_FLASH_ON
VBACKUP
UARTTX0UARTRX0
I2CDAT
CIVSYNC
CIHSYNC
SYSCLK1
PCMDATB
PCMCLK
7C_LED_VDD
BL_PWLFOLDER_DET
LCDWRX
LCDCSX_MAIN
PDID1
USBDP
BL_EN
KEY_LED-
LCDVSYNCILCDRESX
PDID3PDID4
PDID2
PDID5PDID6PDID7
EN_LED_REN_LED_GEN_LED_B
UARTRX1
UARTTX1
VBATI
KEY_LED_ONOFF
MARITATEMU0MARITATEMU1
MARITARTCK
VBAT
VBUS
PCMDATA
PCMSYN
PDID0
LCDRS
MARITATMSMARITATDI
MARITATDOMARITATRST
MARITATCK
DCIN_2
DCIN_3
ONSWAnKEYIN0KEYIN1KEYIN2KEYIN3KEYIN4
KEYOUT1KEYOUT2
LCDRDX
EARP
SPKPSPKM
KEYOUT0
KEYOUT3KEYOUT4KEYOUT5
MOTOR_BATT
LCDCSX_SUB
7C_LED_VDD
KEY_LED-
9. CIRCUIT DIAGRAM
- 242 -
9
VEXT15 WANDAVDDA
C
LG ELECTRONICS INC.
10
4
82
4
3G HANDSETS LAB.
1%
Engineer:
4
10
F
Drawing Number:
E
3
DOC CTRL CHK:
F
12
9
Changed by:
1
1
Time Changed:
5
115
G
A
11
DDD
8
U8100 PT V1.3 Staggered AMD
A
6 12
1.5V1.5V
E
Size:
3 10
7
RF CONTROL
AA
HSSL LINK (MARITA)
124
B
9
G
F
Drawn by:
E
QA CHK:
R&D CHK:
2
11
1.5V
E
RF TX DATA
TITLE:
C
7
RF RX DATA
3
8
H
6 9
D
8
C
12
G
7
Date Changed:
10
F
WANDA
5
G
2
B B
DEVELOPMENT GROUP 1
H
7
MYUNG-LAE, CHO
8
BB MAIN PCB
A2
12 1 8 A
H
6
1.5V
B
REV:
1
Page:
6
H
C
CLK INTERFACE
3 5
VCORE WANDAVDDD
2 11
1
MFG ENGR CHK:
VINCENNE INTERFACE
mentor Tuesday, September 04, 2003 9:42:54 am
MYUNG-LAE, CHO
C22270.1u
C22300.1u
TP
2117
VEXT15
0.1uC2226
TP2116
TP2119
VCORE
R22
24
0
C2238
23 1
0.1u
0.1u
PMST3904Q3204
C2236
C22340.1u
R3326
NA
R24
01
0.1u
100K
VCORE
C2233
C22150.1u
0.1uC2235
C2400 0.1u
R33
83
2.7K
C22410.1u
0.1uC2229
C2240
C32
65
47p
0.1u
NA
C2237
R2120
VCORE
0.1u
T6
VS
S23
VS
S24
T12
VS
S3
L2
VS
S4
N3
VS
S5
R3
R4
VS
S6
T4
VS
S7
VS
S8
U15
VS
S9
U17
T11
VS
SA
_BG
VS
SA
_CS
_AP
LL
N11 T8
VS
SA
_RX
VS
SA
_TX
R8
TP
2322
D3
VS
S0
F3
VS
S1
VS
S10
P16
VS
S11
L16 J16
VS
S12
H16
VS
S13
VS
S14
F15
VS
S15
C16
B15
VS
S16
C12
VS
S17
VS
S18
B11
B10
VS
S19
VS
S2
H3
VS
S20
B7
VS
S21
C5
C3
VS
S22
VD
D2
B8
VD
D20
D2
VD
D21
B1
A12
VD
D3
B14
VD
D4
VD
D5
A17
D16
VD
D6
VD
D7
F17
VD
D8
H17
K17
VD
D9
R11
VD
DA
_BG
R12
VD
DA
_CS
_AP
LL
VD
DA
_RX
U10
VD
DA
_TX
U6
T17
VD
D_C
LK
32
VD
D_D
PL
LL
15RESET_N
N13
TE
ST
MO
DE
D15
UART_RXC13
UART_TXE12
VD
D0
A3
A6
VD
D1
VD
D10
N17
R16
VD
D11
U16
VD
D12
VD
D13
R13
VD
D14
U5
T2
VD
D15
R1
VD
D16
VD
D17
M1
K2
VD
D18
VD
D19
G1
HSSLRX_CLKC14
B16HSSLRX_DHSSLTX_CLK
A16A15
HSSLTX_D
ID_BALLD4
B12IS_EVENT_NIS_SYNC_N
A13
G17JTAG_TCK
JTAG_TDIF16G13
JTAG_TDO
G15JTAG_TMS
JTAG_TRSTNG16
U13MCLK
RADIO_CLKR17P15
RADIO_DATRADIO_STR
M13
EMIF_D9G2
F13EMU0EMU1
E15
E17EXT_FRAME_STROBE
N12EXT_MEM_UBUS10EXT_MEM_UBUS11
T14R14
EXT_MEM_UBUS12
L17
GP
O0
K13
GP
O1
K15
GP
O2
K16
GP
O3
GP
O4
J15
GP
O5
J13
H15
GP
O6
GP
O7
H13
R15HCLK
L5EMIF_D22EMIF_D23
N1
EMIF_D24M3M5
EMIF_D25P2
EMIF_D26EMIF_D27
P3R2
EMIF_D28EMIF_D29
T1
EMIF_D3E3
EMIF_D30N5U1
EMIF_D31
G5EMIF_D4EMIF_D5
E1
EMIF_D6F2F1
EMIF_D7G3
EMIF_D8
U3EMIF_AWE_N
EMIF_D0C2C1
EMIF_D1
EMIF_D10H5H1
EMIF_D11EMIF_D12
H2J2
EMIF_D13J3
EMIF_D14EMIF_D15
J5K3
EMIF_D16EMIF_D17
K5
EMIF_D18K1L1
EMIF_D19
F5EMIF_D2
EMIF_D20L3M2
EMIF_D21
C4
EM
IF_A
18E
MIF
_A19
B3
EM
IF_A
2A
10
EM
IF_A
20A
2A
1E
MIF
_A21
E5
EM
IF_A
22E
MIF
_A23
B2
C10
EM
IF_A
3E
MIF
_A4
B9
C9
EM
IF_A
5
E9
EM
IF_A
6E
MIF
_A7
C8
E8
EM
IF_A
8E
MIF
_A9
A8
EMIF_AREADYU2
EMIF_ARE_NT3
DAC_DATL13
DAC_I_OUTN8U8
DAC_I_OUT_INVU7
DAC_Q_OUTR7
DAC_Q_OUT_INV
M15DAC_STR
DAC_TXEXTREST7
E10
EM
IF_A
1
EM
IF_A
10A
7C
7E
MIF
_A11
B6
EM
IF_A
12E
MIF
_A13
E7
EM
IF_A
14A
5C
6E
MIF
_A15
EM
IF_A
16E
6B
4E
MIF
_A17
APLL_ATEST1U12
C11
AP
LL
_BY
PA
SS
U11
BG
_RE
F
C17
BO
OT
MO
DE
0B
17B
OO
TM
OD
E1
BO
OT
MO
DE
2E
13
BO
OT
MO
DE
3C
15
CLK32T16
CLKRQT15
CPU_CLKOUTM17
CPU_IACKN6
R6CPU_IRQ0
N7CPU_IRQ1
CPU_XFR5
CS
_BY
PA
SS
A11
N15DAC_CLK
ROP-101-3033_1
D2006
R10ADC_I_INADC_I_IN_INV
N10R9
ADC_Q_INADC_Q_IN_INV
T9
ADC_RXEXTREF_NN9
T10ADC_RXEXTREF_P
M16AD_STR
AN
AL
OG
_EN
AB
LE
E11
VRTC
0.1uC2231
R24
02
100K
VDIG
TP
2118
0
R22
36
TP2120
C2103330p
R33
80
3.3K
43KR2400
C22240.1u
TP
2321
0.1uC2239
0.1uC2232
0.1u
TP
2320
0.1u
C2225
WSTR
C2228
CLKREQ
HSSLTX
HSSLTXCLK
HSSLRXCLKHSSLRX
ISEVENTnISSYNCn
MCLK
RESOUT1n
RTCCLK
RXIARXIB
RXQARXQB
ADCSTR
DACCLK
TXIATXIB
TXQATXQB
DACSTR
WCLKWDAT
DACDAT
9. CIRCUIT DIAGRAM
- 243 -
1
SEND
9
LEFT
1
11
D
114
SIDE1
SIDE2
3
U8100_SIDEKEY_PAD
UP
TITLE:
12
GAMEU8100 KEY V0.8
TOSHIBA LCD I/F
CAM
4
Drawn by:
2003.11.18
Drawing Number:
LG ELECTRONICS INC.
2
8
DOC CTRL CHK:
REV:
DEVELOPMENT GROUP 1
R&D CHK:U8100 KEY PT V1.3
HSMR-C191
2
G
*
6
A
#
Size:
9
8
Engineer:
7
BACK
MULTI
7
B
10
FOLDER OPEN DETECTOR
C
F
MFG ENGR CHK:
OK
KEYPAD
3G HANDSETS LAB.
Time Changed:
LCDRESX PULL DOWN R MOVE
RIGHT
D
QA CHK:
SEARCH
BOARD TO BOARD CONECTOR
KEYPAD BACKLIGHT BLUE LED
E
1
10
Date Changed: Page:
G
A2
NA
4
DOWN
3 6
C
8 0
5
F
2004.02.09
CONN_40_AXK840145J
2
END
U8100 KEY PT V1.1 2004.01.14
3
TVS VDIG
ESD EMI FILTER -> RC Filter
5
SIDE3
12
H
CLEAER
A
E
MENU
B
9
H
Changed by:FEB,17,2003mentor 1
BB KEY PAD PCB 12 1 8 A
KB26
KB15
LD
8Q
SM
R-C
138
QS
MR
-C13
8L
D2
QS
MR
-C13
8
47
R11
33
LD
18
56789
272829
3
30313233343536373839
4
40
1213141516171819
2
20212223242526
CN9631
1011
QS
MR
-C13
8L
D7
R11
00
36
470p
LD
6Q
SM
R-C
138
470pC24C23
470
R1103
KB25
100R1135R1134 100
LD
17Q
SM
R-C
138
1234
VBATI_4.2V
CN964
KB21
R1152 270
VA
3A
VL
14K
0220
0
KB17
LD
3Q
SM
R-C
138
10pC21
KB8
KB4
KB6
QS
MR
-C13
8L
D10
R1130
100K
470R1154
QS
MR
-C13
8L
D12
545556575859
6
6061626364
789
4
40414243444546474849
5
50515253
2526272829
3
30313233343536373839
10111213141516171819
2
2021222324
CN9621
LD
14Q
SM
R-C
138
QS
MR
-C13
8L
D4
LD
9Q
SM
R-C
138
NA
INS
TP
AR
R10
97 TV
S2
UC
LA
MP
0501
H
LD
1Q
SM
R-C
138
KB1
0.1u
KB20
C26
R10
99
QS
MR
-C13
8L
D13
36
30p
C46C45
30p 30p
C44
R1151 270
47p
C28
C39
30p 30p30p
C38C37
30p
C36
R1104
470C31
30p30p
C30
30p
C29
100R1150R1149 100
100R1148R1147 100R1146
R1144 100
100
100R1143R1142 100
100R1141R1140 100
0R1139
R1136 100
VDIG_2.8V
KB7
UC
LA
MP
0501
H
TV
S1
INS
TP
AR
D1
1SS388
U1
A32
12E
LH
GN
D3
OU
T21
VD
D
LD
19
QS
MR
-C13
8L
D20
QS
MR
-C13
8
AV
L14
K02
200
VA
2
470pC22
KB13 KB23
R10
98
36
KB12
270R1153
LD
11Q
SM
R-C
138
C43
30p
C40
VBATI_4.2V
30p30p
C35
30p30p
C34C32 C33
KB9
30p
KB2
R11
31
36
QS
MR
-C13
8L
D5
D1
1 3D
24
D3
D4
5 6D
5
GN
D2 SMF05CD2
VBATI_4.2V
R1102
470
100R1145
100R1137
KB3
KB11
VDIG_2.8V
KB14
C250.1u
R1138 100
KB24
KB10
KB19
KB18
KB5
47p30p
C42
VDIG_2.8V
C41
47p
C27
KB22
7C_LED_VDD
7C_LED_VDD
KB16
QS
MR
-C13
8L
D16
VA
1A
VL
14K
0220
0
PDID3PDID5PDID7
LCDWRX
LCDCSX_MAINLCDRESX
LCDVSYNCILCDCSX_SUB
LCDRSLCDRDX
PDID6PDID4PDID2
SPKM
PDID0BL_EN
CAM_FLASH_SHOT
CAM_FLASH_ON
KEY_LED-
LCDRESX
KEYOUT0
KE
YIN
0
KE
YIN
1
KE
YIN
2
KE
YIN
3
KE
YIN
4
CAM_FLASH_SHOT
MOTOR_BATTSPKP
EN_LED_BEN_LED_R
EARPEARM
BL_PWLPDID1
PDID6PDID7
EN_LED_REN_LED_GEN_LED_B
CAM_FLASH_ON
BL_EN
FOLDER_DET
KEYOUT1
KEYOUT2
KEYOUT3
KEYOUT4
KEYOUT5
MARITATCKMARITATMSMARITATDI
MARITATRSTMARITATDO
MARITARTCK
MARITATEMU1MARITATEMU0
FOLDER_DET
EN_LED_G
ON
SW
An
LCDRDX
SPKM
EARM
KEYOUT0KEYOUT1KEYOUT2KEYOUT3KEYOUT4KEYOUT5
KEYIN0KEYIN1KEYIN2KEYIN3KEYIN4
ONSWAn
SPKP
EARP
MOTOR_BATT
LCDCSX_SUB
PDID0
LCDCSX_MAIN
LCDWRXLCDRS
PDID1
BL_PWL
KEY_LED-
LCDVSYNCI
PDID2PDID3PDID4PDID5
9. CIRCUIT DIAGRAM
- 244 -
10. PCB LAYOUT
- 245 -
10. PCB LAYOUT
- 246 -
10. PCB LAYOUT
- 247 -
10. PCB LAYOUT
- 248 -
11. EXPLODED VIEW & REPLACEMENT PART LIST
11.1 EXPLODED VIEW
Level Location No. Description Part Number Specification SVC Color Remark
1 IMT,FOLDER TIFF0001002 N Silver
2 ABEZ00 BOX ASSY ABEZ0037901 BOX ASSY(for U8110 HUK) N Silver
3 MBAD00 BAG,VINYL(PE) MBAD0005201 BAG,VINYL(PE)_GSM Phone(LDPE 0.05t x 85 x 195) Y DarkBlue
3 MBAZ00 BAG MBAZ0002401 BAG(for G5300iVDF to pallet)(255*325) Y Silver
3 MBEE00 BOX,MASTER MBEE0044101 BOX,MASTER(for U8110 HUK) N Silver
3 MBEF00 BOX,UNIT MBEF0053401 BOX,UNIT(for U8110 HUK) Y Silver
3 MLAJ00 LABEL,MASTER BOX MLAJ0002201 LABEL,MASTER BOX(G4010 for Cingular) N MetalicSilver
3 MLAQ00 LABEL,UNIT BOX MLAQ0001601 Y DarkGray
3 MPAD00 PACKING,SHELL MPAD0004601 PACKING,SHELL(for U8110 HUK_Upper(Top)) Y Silver
3 MPAD01 PACKING,SHELL MPAD0004602 PACKING,SHELL(for U8110 HUK_Lower(Bottom)) Y DarkBlue
3 MPBZ00 PAD MPBZ0043101 PAD(for H3G_Substitute for H3G Manual) Y DarkBlue
3 MPCY00 PALLET MPCY0009501 PALLET(G7100 for Orange UK_EUR) N Black
3 MPCY01 PALLET MPCY0010901 PALLET(for H3G Main package_Cap) N DarkBlue
3 MPCY02 PALLET MPCY0010902 PALLET(for H3G Main package_Angle) N DarkBlue
2 AMBA00 MANUAL ASSY,OPERATION AMBA0030501 U8110 Manual ASSY for Hutchison in U.K. Y
3 MMBB00 MANUAL,OPERATION MMBB0113401 U8110 User Manual for Hutchison in UK Y
2 APEY00 PHONE APEY0070022 U8110 HUKSV N Silver
3 ABGA00 BUTTON ASSY,DIAL ABGA0002401 Y Silver M18
3 ACGG00 COVER ASSY,FOLDER ACGG0033302 Y Silver M40
4 ACGH00 COVER ASSY,FOLDER(LOWER) ACGH0012002 Y Silver M11
5 MCCZ00 CAP MCCZ0005402 N
5 MCJH00 COVER,FOLDER(LOWER) MCJH0009603 N Silver
5 MDAC00 DECO,SIDE MDAC0006301 0.2t N Silver
5 MDAH DECO,RECEIVER MDAH0002001 INNER_2 N Silver
5 MDAH00 DECO,RECEIVER MDAH0001901 OUTER DECO_1 N Silver
5 MGAD00 GASKET,SHIELD FORM MGAD0035201 5.0x4.5x3.0 KW2000 FOLDER LOWER Y Gold M7
5 MMAZ00 MAGNET MMAZ0000101 D3*1.5t Y
5 MTAA TAPE,DECO MTAA0023301 DECO SIDE Y
5 MTAA00 TAPE,DECO MTAA0023101 DECO RECEIVER OUTER Y
5 MTAA01 TAPE,DECO MTAA0023201 DECO RECEIVER INNER Y
4 ACGJ00 COVER ASSY,FOLDER(UPPER) ACGJ0028701 Y Silver M2
5 MCJJ00 COVER,FOLDER(UPPER) MCJJ0021501 N Silver
5 MDAY00 DECO MDAY0006801 0.2t N
11.2 Replacement Parts <Mechanic component>
-249-
Level Location No. Description Part Number Specification SVC Color Remark
5 MFBC00 FILTER,SPEAKER MFBC0007401 Y
5 MICA00 INSERT,FRONT MICA0001201 LG-G510,511,512 common use, DIA = 1.7mm+2.3t Y
5 MPBG00 PAD,LCD MPBG0018201 2.2t Y Silver
5 MPBQ00 PAD,LCD(SUB) MPBQ0013101 Y Black
5 MTAE00 TAPE,WINDOW(SUB) MTAE0013301 0.2t Y
4 ACGK00 COVER ASSY,FRONT ACGK0020902 Y Silver M17
5 MBJL00 BUTTON,SIDE MBJL0008102 N
5 MCCC00 CAP,EARPHONE JACK MCCC0007801 N Silver
5 MCJK00 COVER,FRONT MCJK0014602 N Silver
5 MICB00 INSERT,FRONT(LOWER) MICB0000601 N
5 MWAG00 WINDOW,IRDA MWAG0002301 N Brown
4 ALAY00 LCD ASSY ALAY0005301 N
5 AFBZ00 FRAME ASSY AFBZ0004402 Y M9
6 MFEZ00 FRAME MFEZ0002302 N
6 MPBG00 PAD,LCD MPBG0010602 0.3t N Gray
6 MPBS00 PAD,FOLDER MPBS0002301 55.80*41.80 t0.3 N Silver
5 MGAD0 GASKET,SHIELD FORM MGAD0044101 0.2t_LCD Y Silver
5 MGAD00 GASKET,SHIELD FORM MGAD0035201 5.0x4.5x3.0 KW2000 FOLDER LOWER Y Gold
5 SACY00 PCB ASSY,FLEXIBLE SACY0016001 Y M8
6 EDLM00 DIODE,LED,MODULE EDLM0004301 WHITE ,3 LED,3.5*3.5*1.0 ,R/TP ,MINI FLASH LED Y
6 R1 RES,CHIP ERHY0000203 10 ohm,1/16W,J,1005,R/TP Y
6 R2 RES,CHIP ERHY0000203 10 ohm,1/16W,J,1005,R/TP Y
6 R3 RES,CHIP ERHY0000203 10 ohm,1/16W,J,1005,R/TP Y
6 SPCY00 PCB,FLEXIBLE SPCY0026701 POLYI , mm,DOUBLE , Y
4 AWAB00 WINDOW ASSY,LCD AWAB0009201 IN-MOLD Y DarkBlue
M1
5 BFAA00 FILM,INMOLD BFAA0014001 Dark Blue N DarkBlue
5 MWAF00 WINDOW,LCD(SUB) MWAF0017001 N DarkBlue
4 GMZZ00 SCREW MACHINE GMZZ0003201 3.5 mm,3.5 mm,MSWR3(FN) ,N ,STR ,- , M1.7X3.5DIA3.5
Y Silver M12
4 MCCH00 CAP,SCREW MCCH0012101 FOLDER Y Gray M13
4 MDAF00 DECO,FOLDER(LOWER) MDAF0003203 Y MetalicSilver
M16
4 MHFD00 HINGE,FOLDER MHFD0006901 Y MetalicSilver
M10
4 MTAA00 TAPE,DECO MTAA0023401 DECO FOLDER LOWER Y M15
4 MTAB TAPE,PROTECTION MTAB0036801 KW2000, U8100, U8110, U8120 Y
4 MTAB00 TAPE,PROTECTION MTAB0020101 KW2000,FOLDER LOWER Y
4 MWAC00 WINDOW,LCD MWAC0025801 Y M14
4 SJMY00 VIBRATOR,MOTOR SJMY0004201 3 V,0.12 A,12*3.4 ,G8000 VIBRATOR Y M4
-250-
Level Location No. Description Part Number Specification SVC Color Remark
4 SUVT00 TWO-WAY MODE SPEAKER SUVT0002701 8 ohm,32 ohm,90 dB,108 dB,19 mm,2-WAY MODESPEAKER for KW-2000
Y M3
4 SVLM00 LCD MODULE SVLM0005401 , , Y M5
3 ACGM00 COVER ASSY,REAR ACGM0017802 Y Silver M33
4 ACFY00 CONTACT ASSY,ANTENNA ACFY0000501 LG-G510,511,512 common use, MAIN REAR Y
4 MCJN00 COVER,REAR MCJN0011802 Y Silver
4 MDAK00 DECO,REAR MDAK0001102 Y Silver
4 MGAD00 GASKET,SHIELD FORM MGAD0044101 0.2t_LCD Y Silver M6
4 MIDZ INSULATOR MIDZ0039401 N DarkBlue
4 MIDZ00 INSULATOR MIDZ0036101 N Silver
4 MLEA LOCKER,BATTERY MLEA0008901 RIGHT N Silver
4 MLEA00 LOCKER,BATTERY MLEA0008801 LEFT N Silver
4 MPBT00 PAD,CAMERA MPBT0004601 2.2t Y Silver
4 MSDC00 SPRING,LOCKER MSDC0003901 Y
3 ACGN00 COVER ASSY,CAMERA ACGN0001101 Y Silver M41
4 ACGP00 COVER ASSY,CAMERA(FRONT) ACGP0000301 N Silver M28
5 MCJP00 COVER,CAMERA(FRONT) MCJP0000901 N Silver
5 MMAZ00 MAGNET MMAZ0000301 2500 Gauss (+-500) N MetalicSilver
5 MSDZ00 SPRING MSDZ0000801 0.15t N Gold
5 MTAA00 TAPE,DECO MTAA0035901 N Silver
4 MBIC00 BUSHING,CAMERA(LEFT) MBIC0000201 N White M27
4 MBIZ00 BUSHING MBIZ0001301 N Silver M31
4 MCCK00 CAP,CAMERA MCCK0000301 N M29
4 MDAD00 DECO,CAMERA MDAD0002501 N Black M24
4 MDAD01 DECO,CAMERA MDAD0002601 Cr N MetalicSilver
M25
4 MWAE00 WINDOW,CAMERA MWAE0000301 0.5t N M26
4 SMZY00 MODULE,ETC SMZY0006501 VGA CMOS CAMERA MODULE Y M30
3 GMZZ00 SCREW MACHINE GMZZ0003201 3.5 mm,3.5 mm,MSWR3(FN) ,N ,STR ,- , M1.7X3.5DIA3.5
Y Silver M35
3 MCCF00 CAP,MOBILE SWITCH MCCF0008501 Y Silver M37
3 MCCH00 CAP,SCREW MCCH0012201 REAR Y Silver M36
3 MCJA00 COVER,BATTERY MCJA0004202 Y Silver M39
3 MFEA00 FRAME,SHIELD MFEA0003501 Y M23
3 MLAK00 LABEL,MODEL MLAK0007202 Y Silver
-251-
Level Location No. Description Part Number Specification SVC Color Remark
3 SAEY00 PCB ASSY,KEYPAD SAEY0025801 Y M21
4 ADCA00 DOME ASSY,METAL ADCA0010901 N M19
4 SAEA00 PCB ASSY,KEYPAD,AUTO SAEA0010301 N
5 C21 CAP,CERAMIC,CHIP ECCH0000110 10 pF,50V,D,NP0,TC,1005,R/TP N
5 C22 CAP,CERAMIC,CHIP ECCH0000139 470 pF,50V,K,X7R,HD,1005,R/TP N
5 C23 CAP,CERAMIC,CHIP ECCH0000139 470 pF,50V,K,X7R,HD,1005,R/TP N
5 C24 CAP,CERAMIC,CHIP ECCH0000139 470 pF,50V,K,X7R,HD,1005,R/TP N
5 C25 CAP,CERAMIC,CHIP ECCH0000182 0.1 uF,10V ,K ,X5R ,HD ,1005 ,R/TP N
5 C26 CAP,CERAMIC,CHIP ECCH0000182 0.1 uF,10V ,K ,X5R ,HD ,1005 ,R/TP N
5 C27 CAP,CERAMIC,CHIP ECCH0000122 47 pF,50V,J,NP0,TC,1005,R/TP N
5 C28 CAP,CERAMIC,CHIP ECCH0000122 47 pF,50V,J,NP0,TC,1005,R/TP N
5 C29 CAP,CERAMIC,CHIP ECCH0000118 30 pF,50V,J,NP0,TC,1005,R/TP Y
5 C30 CAP,CERAMIC,CHIP ECCH0000118 30 pF,50V,J,NP0,TC,1005,R/TP Y
5 C31 CAP,CERAMIC,CHIP ECCH0000118 30 pF,50V,J,NP0,TC,1005,R/TP Y
5 C32 CAP,CERAMIC,CHIP ECCH0000118 30 pF,50V,J,NP0,TC,1005,R/TP Y
5 C33 CAP,CERAMIC,CHIP ECCH0000118 30 pF,50V,J,NP0,TC,1005,R/TP Y
5 C34 CAP,CERAMIC,CHIP ECCH0000118 30 pF,50V,J,NP0,TC,1005,R/TP Y
5 C35 CAP,CERAMIC,CHIP ECCH0000118 30 pF,50V,J,NP0,TC,1005,R/TP Y
5 C36 CAP,CERAMIC,CHIP ECCH0000118 30 pF,50V,J,NP0,TC,1005,R/TP Y
5 C37 CAP,CERAMIC,CHIP ECCH0000118 30 pF,50V,J,NP0,TC,1005,R/TP Y
5 C38 CAP,CERAMIC,CHIP ECCH0000118 30 pF,50V,J,NP0,TC,1005,R/TP Y
5 C39 CAP,CERAMIC,CHIP ECCH0000118 30 pF,50V,J,NP0,TC,1005,R/TP Y
5 C40 CAP,CERAMIC,CHIP ECCH0000118 30 pF,50V,J,NP0,TC,1005,R/TP Y
5 C41 CAP,CERAMIC,CHIP ECCH0000118 30 pF,50V,J,NP0,TC,1005,R/TP Y
5 C42 CAP,CERAMIC,CHIP ECCH0000122 47 pF,50V,J,NP0,TC,1005,R/TP Y
5 C43 CAP,CERAMIC,CHIP ECCH0000118 30 pF,50V,J,NP0,TC,1005,R/TP Y
5 C44 CAP,CERAMIC,CHIP ECCH0000118 30 pF,50V,J,NP0,TC,1005,R/TP Y
5 C45 CAP,CERAMIC,CHIP ECCH0000118 30 pF,50V,J,NP0,TC,1005,R/TP Y
5 C46 CAP,CERAMIC,CHIP ECCH0000118 30 pF,50V,J,NP0,TC,1005,R/TP Y
5 CN962 CONNECTOR,BOARD TO BOARD ENBY0004302 60 PIN,0.5 mm,STRAIGHT ,Au ,B to B CNT(Socket) N
5 CN963 CONNECTOR,BOARD TO BOARD ENBY0013004 40 PIN,0.4 mm,ETC ,Au over Ni , N
5 D1 DIODE,SWITCHING EDSY0010401 1-1G1A ,40 V,300 A,R/TP ,Silicon Epitaxial SchottkyBarrier Type Diode
N
5 LD1 DIODE,LED,CHIP EDLH0004502 BLUE ,1608 ,R/TP ,0.35T Y
5 LD10 DIODE,LED,CHIP EDLH0004502 BLUE ,1608 ,R/TP ,0.35T Y
5 LD11 DIODE,LED,CHIP EDLH0004502 BLUE ,1608 ,R/TP ,0.35T Y
5 LD12 DIODE,LED,CHIP EDLH0004502 BLUE ,1608 ,R/TP ,0.35T Y
11.2 Replacement Parts <Main component>
-252-
Level Location No. Description Part Number Specification SVC Color Remark
5 LD13 DIODE,LED,CHIP EDLH0004502 BLUE ,1608 ,R/TP ,0.35T Y
5 LD14 DIODE,LED,CHIP EDLH0004502 BLUE ,1608 ,R/TP ,0.35T Y
5 LD16 DIODE,LED,CHIP EDLH0004502 BLUE ,1608 ,R/TP ,0.35T Y
5 LD17 DIODE,LED,CHIP EDLH0004502 BLUE ,1608 ,R/TP ,0.35T Y
5 LD18 DIODE,LED,CHIP EDLH0004502 BLUE ,1608 ,R/TP ,0.35T Y
5 LD19 DIODE,LED,CHIP EDLH0004502 BLUE ,1608 ,R/TP ,0.35T Y
5 LD2 DIODE,LED,CHIP EDLH0004502 BLUE ,1608 ,R/TP ,0.35T Y
5 LD20 DIODE,LED,CHIP EDLH0004502 BLUE ,1608 ,R/TP ,0.35T Y
5 LD3 DIODE,LED,CHIP EDLH0004502 BLUE ,1608 ,R/TP ,0.35T Y
5 LD4 DIODE,LED,CHIP EDLH0004502 BLUE ,1608 ,R/TP ,0.35T Y
5 LD5 DIODE,LED,CHIP EDLH0004502 BLUE ,1608 ,R/TP ,0.35T Y
5 LD6 DIODE,LED,CHIP EDLH0004502 BLUE ,1608 ,R/TP ,0.35T Y
5 LD7 DIODE,LED,CHIP EDLH0004502 BLUE ,1608 ,R/TP ,0.35T Y
5 LD8 DIODE,LED,CHIP EDLH0004502 BLUE ,1608 ,R/TP ,0.35T Y
5 LD9 DIODE,LED,CHIP EDLH0004502 BLUE ,1608 ,R/TP ,0.35T Y
5 R1098 RES,CHIP ERHY0006603 36 ohm,1/16W ,J ,1005 ,R/TP N
5 R1099 RES,CHIP ERHY0006603 36 ohm,1/16W ,J ,1005 ,R/TP N
5 R1100 RES,CHIP ERHY0006603 36 ohm,1/16W ,J ,1005 ,R/TP N
5 R1102 RES,CHIP ERHY0000233 470 ohm,1/16W,J,1005,R/TP N
5 R1103 RES,CHIP ERHY0000233 470 ohm,1/16W,J,1005,R/TP N
5 R1104 RES,CHIP ERHY0000233 470 ohm,1/16W,J,1005,R/TP N
5 R1130 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP N
5 R1131 RES,CHIP ERHY0006603 36 ohm,1/16W ,J ,1005 ,R/TP N
5 R1133 RES,CHIP ERHY0000213 47 ohm,1/16W,J,1005,R/TP N
5 R1134 RES,CHIP ERHY0000220 100 ohm,1/16W,J,1005,R/TP Y
5 R1135 RES,CHIP ERHY0000220 100 ohm,1/16W,J,1005,R/TP Y
5 R1136 RES,CHIP ERHY0000220 100 ohm,1/16W,J,1005,R/TP Y
5 R1137 RES,CHIP ERHY0000220 100 ohm,1/16W,J,1005,R/TP Y
5 R1138 RES,CHIP ERHY0000220 100 ohm,1/16W,J,1005,R/TP Y
5 R1139 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP Y
5 R1140 RES,CHIP ERHY0000220 100 ohm,1/16W,J,1005,R/TP Y
5 R1141 RES,CHIP ERHY0000220 100 ohm,1/16W,J,1005,R/TP Y
5 R1142 RES,CHIP ERHY0000220 100 ohm,1/16W,J,1005,R/TP Y
5 R1143 RES,CHIP ERHY0000220 100 ohm,1/16W,J,1005,R/TP Y
5 R1144 RES,CHIP ERHY0000220 100 ohm,1/16W,J,1005,R/TP Y
5 R1145 RES,CHIP ERHY0000220 100 ohm,1/16W,J,1005,R/TP Y
5 R1146 RES,CHIP ERHY0000220 100 ohm,1/16W,J,1005,R/TP Y
5 R1147 RES,CHIP ERHY0000220 100 ohm,1/16W,J,1005,R/TP Y
5 R1148 RES,CHIP ERHY0000220 100 ohm,1/16W,J,1005,R/TP Y
-253-
Level Location No. Description Part Number Specification SVC Color Remark
5 R1149 RES,CHIP ERHY0000220 100 ohm,1/16W,J,1005,R/TP Y
5 R1150 RES,CHIP ERHY0000220 100 ohm,1/16W,J,1005,R/TP Y
5 R1151 RES,CHIP ERHY0000228 270 ohm,1/16W,J,1005,R/TP N
5 R1152 RES,CHIP ERHY0000228 270 ohm,1/16W,J,1005,R/TP N
5 R1153 RES,CHIP ERHY0000228 270 ohm,1/16W,J,1005,R/TP Y
5 R1154 RES,CHIP ERHY0000233 470 ohm,1/16W,J,1005,R/TP Y
5 SPEY00 PCB,KEYPAD SPEY0019202 FR-4 ,.4 mm,DOUBLE , N
5 TVS1 DIODE,TVS EDTY0007301 SOD-523 ,5 V,240 W,R/TP ,SINGLE LINE TVS DIODEFOR ESD
N
5 TVS2 DIODE,TVS EDTY0007301 SOD-523 ,5 V,240 W,R/TP ,SINGLE LINE TVS DIODEFOR ESD
N
5 U1 IC EUSY0129501 SC-74A FIT ,3 PIN,R/TP ,HALL EFFECT SWITCH N
5 VA1 VARISTOR SEVY0000702 14 V,10% ,SMD , N
5 VA2 VARISTOR SEVY0000702 14 V,10% ,SMD , N
5 VA3 VARISTOR SEVY0000702 14 V,10% ,SMD , N
4 SAKY00 PCB ASSY,SIDEKEY SAKY0002602 N M20
3 SAFY00 PCB ASSY,MAIN SAFY0084201 Y M32
4 MLAB00 LABEL,A/S MLAB0000601 HUMIDITY STICKER Y
4 SAFA00 PCB ASSY,MAIN,AUTO SAFA0031301 N
5 B1501 IC EUSY0170601 SC70 ,5 PIN,R/TP ,TEMPERATURE SENSOR N
5 B1770 X-TAL EXXY0016801 13 MHz,19 PPM,10 pF,40 ohm,SMD ,5*3.20*0.7 , Y
5 B2100 X-TAL EXXY0004601 0.32768 MHz,20 PPM,12.5 pF,65000 ohm,SMD,6.9*1.4*1.3 ,
Y
5 C1000 CAP,CERAMIC,CHIP ECCH0001001 6.8 pF,50V ,C ,NP0 ,TC ,1005 ,R/TP Y
5 C1001 CAP,CERAMIC,CHIP ECCH0000110 10 pF,50V,D,NP0,TC,1005,R/TP N
5 C1002 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP N
5 C1003 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP N
5 C1004 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP N
5 C1005 CAP,CERAMIC,CHIP ECCH0000110 10 pF,50V,D,NP0,TC,1005,R/TP N
5 C1007 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP N
5 C1008 CAP,CERAMIC,CHIP ECCH0000110 10 pF,50V,D,NP0,TC,1005,R/TP N
5 C1009 CAP,CERAMIC,CHIP ECCH0000110 10 pF,50V,D,NP0,TC,1005,R/TP N
5 C1010 CAP,CERAMIC,CHIP ECCH0000143 1 nF,50V,K,X7R,HD,1005,R/TP N
5 C1011 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP N
5 C1012 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP N
5 C1013 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP N
5 C1100 CAP,CERAMIC,CHIP ECCH0000110 10 pF,50V,D,NP0,TC,1005,R/TP N
5 C1101 CAP,CERAMIC,CHIP ECCH0000110 10 pF,50V,D,NP0,TC,1005,R/TP N
5 C1102 CAP,CERAMIC,CHIP ECCH0000110 10 pF,50V,D,NP0,TC,1005,R/TP N
5 C1103 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP N
5 C1104 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP N
-254-
Level Location No. Description Part Number Specification SVC Color Remark
5 C1110 CAP,CERAMIC,CHIP ECCH0000186 33 pF,50V ,J ,NP0 ,TC ,1005 ,R/TP N
5 C1111 CAP,CERAMIC,CHIP ECCH0000186 33 pF,50V ,J ,NP0 ,TC ,1005 ,R/TP N
5 C1112 CAP,CERAMIC,CHIP ECCH0000186 33 pF,50V ,J ,NP0 ,TC ,1005 ,R/TP N
5 C1113 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP N
5 C1114 CAP,CERAMIC,CHIP ECCH0000108 7 pF,50V,D,NP0,TC,1005,R/TP N
5 C1140 CAP,CERAMIC,CHIP ECCH0000165 68 nF,6.3V,K,X5R,HD,1005,R/TP N
5 C1141 CAP,CERAMIC,CHIP ECCH0000165 68 nF,6.3V,K,X5R,HD,1005,R/TP N
5 C1142 CAP,CERAMIC,CHIP ECCH0000165 68 nF,6.3V,K,X5R,HD,1005,R/TP N
5 C1143 CAP,CERAMIC,CHIP ECCH0000165 68 nF,6.3V,K,X5R,HD,1005,R/TP N
5 C1144 CAP,CERAMIC,CHIP ECCH0000165 68 nF,6.3V,K,X5R,HD,1005,R/TP N
5 C1150 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP N
5 C1156 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP N
5 C1201 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP N
5 C1202 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP N
5 C1203 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP N
5 C1205 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP N
5 C1221 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP N
5 C1222 CAP,CERAMIC,CHIP ECCH0000140 560 pF,50V,K,X7R,HD,1005,R/TP N
5 C1223 CAP,CERAMIC,CHIP ECCH0000137 330 pF,50V ,K ,X7R ,HD ,1005 ,R/TP N
5 C1224 CAP,CERAMIC,CHIP ECCH0000144 1.2 nF,50V,K,X7R,HD,1005,R/TP N
5 C1225 CAP,CERAMIC,CHIP ECCH0000146 1.8 nF,50V,K,X7R,HD,1005,R/TP N
5 C1270 CAP,CERAMIC,CHIP ECCH0000143 1 nF,50V,K,X7R,HD,1005,R/TP N
5 C1271 CAP,CERAMIC,CHIP ECCH0000143 1 nF,50V,K,X7R,HD,1005,R/TP N
5 C1300 CAP,CERAMIC,CHIP ECCH0000165 68 nF,6.3V,K,X5R,HD,1005,R/TP N
5 C1311 CAP,CERAMIC,CHIP ECCH0006501 10 uF,6.3V ,K ,X5R ,TC ,2012 ,R/TP Y
5 C1312 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP N
5 C1313 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP N
5 C1315 CAP,CERAMIC,CHIP ECCH0006501 10 uF,6.3V ,K ,X5R ,TC ,2012 ,R/TP Y
5 C1320 CAP,CERAMIC,CHIP ECCH0000139 470 pF,50V,K,X7R,HD,1005,R/TP N
5 C1321 CAP,CERAMIC,CHIP ECCH0000139 470 pF,50V,K,X7R,HD,1005,R/TP N
5 C1322 CAP,CERAMIC,CHIP ECCH0000130 150 pF,50V,J,SL,TC,1005,R/TP N
5 C1323 CAP,CERAMIC,CHIP ECCH0000144 1.2 nF,50V,K,X7R,HD,1005,R/TP N
5 C1324 CAP,CERAMIC,CHIP ECCH0000128 100 pF,50V,J,NP0,TC,1005,R/TP N
5 C1325 CAP,CERAMIC,CHIP ECCH0000128 100 pF,50V,J,NP0,TC,1005,R/TP N
5 C1327 CAP,CERAMIC,CHIP ECCH0000186 33 pF,50V ,J ,NP0 ,TC ,1005 ,R/TP N
5 C1330 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP N
5 C1331 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP N
5 C1332 CAP,CERAMIC,CHIP ECCH0000186 33 pF,50V ,J ,NP0 ,TC ,1005 ,R/TP N
5 C1333 CAP,CERAMIC,CHIP ECCH0000110 10 pF,50V,D,NP0,TC,1005,R/TP N
-255-
Level Location No. Description Part Number Specification SVC Color Remark
5 C1334 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP N
5 C1335 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP N
5 C1341 CAP,CERAMIC,CHIP ECCH0000186 33 pF,50V ,J ,NP0 ,TC ,1005 ,R/TP N
5 C1352 CAP,CERAMIC,CHIP ECCH0000110 10 pF,50V,D,NP0,TC,1005,R/TP N
5 C1401 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP N
5 C1402 CAP,CERAMIC,CHIP ECCH0000143 1 nF,50V,K,X7R,HD,1005,R/TP N
5 C1403 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP N
5 C1404 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP N
5 C1407 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP N
5 C1412 CAP,CERAMIC,CHIP ECCH0000701 1.2 pF,50V ,C ,NP0 ,TC ,1005 ,R/TP N
5 C1413 CAP,CERAMIC,CHIP ECCH0000701 1.2 pF,50V ,C ,NP0 ,TC ,1005 ,R/TP N
5 C1414 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP N
5 C1422 CAP,CERAMIC,CHIP ECCH0000117 27 pF,50V,J,NP0,TC,1005,R/TP N
5 C1423 CAP,CERAMIC,CHIP ECCH0000117 27 pF,50V,J,NP0,TC,1005,R/TP N
5 C1424 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP N
5 C1425 CAP,CERAMIC,CHIP ECCH0000147 2.2 nF,50V,K,X7R,HD,1005,R/TP N
5 C1431 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP N
5 C1441 CAP,CERAMIC,CHIP ECCH0000147 2.2 nF,50V,K,X7R,HD,1005,R/TP N
5 C1442 CAP,CERAMIC,CHIP ECCH0000147 2.2 nF,50V,K,X7R,HD,1005,R/TP N
5 C1443 CAP,CERAMIC,CHIP ECCH0000701 1.2 pF,50V ,C ,NP0 ,TC ,1005 ,R/TP N
5 C1444 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP N
5 C1447 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP N
5 C1448 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP N
5 C1451 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP N
5 C1452 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP N
5 C1453 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP N
5 C1454 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP N
5 C1501 CAP,CERAMIC,CHIP ECCH0000122 47 pF,50V,J,NP0,TC,1005,R/TP N
5 C1502 CAP,CERAMIC,CHIP ECCH0000105 4 pF,50V,C,NP0,TC,1005,R/TP N
5 C1503 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP N
5 C1504 CAP,CERAMIC,CHIP ECCH0000110 10 pF,50V,D,NP0,TC,1005,R/TP N
5 C1505 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP N
5 C1507 CAP,CERAMIC,CHIP ECCH0000105 4 pF,50V,C,NP0,TC,1005,R/TP N
5 C1508 CAP,CERAMIC,CHIP ECCH0000901 2.2 pF,50V ,C ,NP0 ,TC ,1005 ,R/TP N
5 C1509 CAP,CERAMIC,CHIP ECCH0000110 10 pF,50V,D,NP0,TC,1005,R/TP N
5 C1510 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP N
5 C1511 CAP,CERAMIC,CHIP ECCH0000110 10 pF,50V,D,NP0,TC,1005,R/TP N
5 C1512 CAP,CERAMIC,CHIP ECCH0000110 10 pF,50V,D,NP0,TC,1005,R/TP N
5 C1513 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP N
-256-
Level Location No. Description Part Number Specification SVC Color Remark
5 C1514 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP N
5 C1601 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP N
5 C1602 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP N
5 C1622 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP N
5 C1623 CAP,CERAMIC,CHIP ECCH0006501 10 uF,6.3V ,K ,X5R ,TC ,2012 ,R/TP Y
5 C1624 CAP,CERAMIC,CHIP ECCH0003803 4.7 uF,10V ,Z ,Y5V ,HD ,2012 ,R/TP N
5 C1626 CAP,CERAMIC,CHIP ECCH0000137 330 pF,50V ,K ,X7R ,HD ,1005 ,R/TP N
5 C1627 CAP,CERAMIC,CHIP ECCH0003803 4.7 uF,10V ,Z ,Y5V ,HD ,2012 ,R/TP N
5 C1628 CAP,CERAMIC,CHIP ECCH0000143 1 nF,50V,K,X7R,HD,1005,R/TP N
5 C1631 CAP,CERAMIC,CHIP ECCH0000110 10 pF,50V,D,NP0,TC,1005,R/TP N
5 C1632 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP N
5 C1701 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP N
5 C1702 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP N
5 C1703 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP N
5 C1704 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP N
5 C1710 CAP,CERAMIC,CHIP ECCH0000130 150 pF,50V,J,SL,TC,1005,R/TP N
5 C1711 CAP,CERAMIC,CHIP ECCH0000149 3.3 nF,50V,K,X7R,HD,1005,R/TP N
5 C1714 CAP,CERAMIC,CHIP ECCH0000128 100 pF,50V,J,NP0,TC,1005,R/TP N
5 C1715 CAP,CERAMIC,CHIP ECCH0000128 100 pF,50V,J,NP0,TC,1005,R/TP N
5 C1716 CAP,CERAMIC,CHIP ECCH0000181 4.7 pF,50V ,C ,NP0 ,TC ,1005 ,R/TP N
5 C1720 CAP,CERAMIC,CHIP ECCH0000152 5.6 nF,25V,K,X7R,HD,1005,R/TP N
5 C1721 CAP,CERAMIC,CHIP ECCH0000138 390 pF,50V,K,X7R,HD,1005,R/TP N
5 C1730 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP N
5 C1731 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP N
5 C1740 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP N
5 C1741 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP N
5 C1750 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP N
5 C1751 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP N
5 C1760 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP N
5 C1761 CAP,CERAMIC,CHIP ECCH0000127 82 pF,50V,J,NP0,TC,1005,R/TP N
5 C1770 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP N
5 C1772 CAP,CERAMIC,CHIP ECCH0000137 330 pF,50V ,K ,X7R ,HD ,1005 ,R/TP N
5 C1773 CAP,CERAMIC,CHIP ECCH0000181 4.7 pF,50V ,C ,NP0 ,TC ,1005 ,R/TP N
5 C1776 CAP,CERAMIC,CHIP ECCH0000181 4.7 pF,50V ,C ,NP0 ,TC ,1005 ,R/TP N
5 C1777 CAP,CERAMIC,CHIP ECCH0000122 47 pF,50V,J,NP0,TC,1005,R/TP N
5 C1778 CAP,CERAMIC,CHIP ECCH0000124 56 pF,50V,J,NP0,TC,1005,R/TP N
5 C1800 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C1801 CAP,CERAMIC,CHIP ECCH0000143 1 nF,50V,K,X7R,HD,1005,R/TP N
5 C1802 CAP,CERAMIC,CHIP ECCH0006501 10 uF,6.3V ,K ,X5R ,TC ,2012 ,R/TP Y
-257-
Level Location No. Description Part Number Specification SVC Color Remark
5 C1810 CAP,CERAMIC,CHIP ECCH0006501 10 uF,6.3V ,K ,X5R ,TC ,2012 ,R/TP Y
5 C1811 CAP,CERAMIC,CHIP ECCH0006501 10 uF,6.3V ,K ,X5R ,TC ,2012 ,R/TP N
5 C1850 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C1851 CAP,CERAMIC,CHIP ECCH0000161 33 nF,16V,K,X7R,HD,1005,R/TP N
5 C1852 CAP,CERAMIC,CHIP ECCH0006501 10 uF,6.3V ,K ,X5R ,TC ,2012 ,R/TP Y
5 C2100 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP N
5 C2101 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP N
5 C2102 CAP,CERAMIC,CHIP ECCH0000137 330 pF,50V ,K ,X7R ,HD ,1005 ,R/TP N
5 C2103 CAP,CERAMIC,CHIP ECCH0000137 330 pF,50V ,K ,X7R ,HD ,1005 ,R/TP N
5 C2104 CAP,CERAMIC,CHIP ECCH0000143 1 nF,50V,K,X7R,HD,1005,R/TP N
5 C2200 CAP,CERAMIC,CHIP ECCH0006501 10 uF,6.3V ,K ,X5R ,TC ,2012 ,R/TP Y
5 C2202 CAP,CERAMIC,CHIP ECCH0003803 4.7 uF,10V ,Z ,Y5V ,HD ,2012 ,R/TP N
5 C2203 CAP,CERAMIC,CHIP ECCH0000276 1 uF,10V,Z,Y5V,HD,1608,R/TP N
5 C2205 CAP,CERAMIC,CHIP ECCH0006501 10 uF,6.3V ,K ,X5R ,TC ,2012 ,R/TP Y
5 C2206 CAP,CERAMIC,CHIP ECCH0006501 10 uF,6.3V ,K ,X5R ,TC ,2012 ,R/TP Y
5 C2207 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C2208 CAP,CERAMIC,CHIP ECCH0000276 1 uF,10V,Z,Y5V,HD,1608,R/TP N
5 C2209 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C2210 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C2211 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C2212 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C2213 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C2214 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C2215 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C2216 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C2217 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C2218 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C2219 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C2220 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C2221 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C2222 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C2223 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C2224 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C2225 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C2226 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C2227 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C2228 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C2229 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C2230 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
-258-
Level Location No. Description Part Number Specification SVC Color Remark
5 C2231 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C2232 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C2233 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C2234 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C2235 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C2236 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C2237 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C2238 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C2239 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C2240 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C2241 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C2242 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C2243 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C2244 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C2245 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C2246 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C2247 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C2250 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C2251 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C2252 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C2253 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C2255 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C2256 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C2257 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C2258 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C2259 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C2260 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C2261 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C2262 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C2263 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C2272 CAP,CERAMIC,CHIP ECCH0000276 1 uF,10V,Z,Y5V,HD,1608,R/TP N
5 C2274 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C2276 CAP,CERAMIC,CHIP ECCH0000128 100 pF,50V,J,NP0,TC,1005,R/TP N
5 C2277 CAP,CERAMIC,CHIP ECCH0003803 4.7 uF,10V ,Z ,Y5V ,HD ,2012 ,R/TP N
5 C2278 CAP,CERAMIC,CHIP ECCH0000380 2.2 uF,16V ,Z ,Y5V ,HD ,2012 ,R/TP N
5 C2279 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP N
5 C2281 CAP,CERAMIC,CHIP ECCH0003803 4.7 uF,10V ,Z ,Y5V ,HD ,2012 ,R/TP N
5 C2301 CAP,CERAMIC,CHIP ECCH0000276 1 uF,10V,Z,Y5V,HD,1608,R/TP N
5 C2302 CAP,CERAMIC,CHIP ECCH0000276 1 uF,10V,Z,Y5V,HD,1608,R/TP N
-259-
Level Location No. Description Part Number Specification SVC Color Remark
5 C2303 CAP,CERAMIC,CHIP ECCH0000143 1 nF,50V,K,X7R,HD,1005,R/TP N
5 C2304 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C2312 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP N
5 C2400 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C2500 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C2603 CAP,CERAMIC,CHIP ECCH0000276 1 uF,10V,Z,Y5V,HD,1608,R/TP N
5 C2604 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C2605 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C2606 CAP,CERAMIC,CHIP ECCH0000275 0.33 uF,16V,Z,Y5V,HD,1608,R/TP N
5 C2608 CAP,CERAMIC,CHIP ECCH0000276 1 uF,10V,Z,Y5V,HD,1608,R/TP N
5 C2609 CAP,CERAMIC,CHIP ECCH0000155 10 nF,16V,K,X7R,HD,1005,R/TP N
5 C2610 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP N
5 C2611 CAP,TANTAL,CHIP,MAKER ECTZ0002802 100 uF,6.3V ,M ,L_ESR ,ETC ,R/TP N
5 C2612 CAP,CERAMIC,CHIP ECCH0000165 68 nF,6.3V,K,X5R,HD,1005,R/TP N
5 C2613 CAP,CERAMIC,CHIP ECCH0000161 33 nF,16V,K,X7R,HD,1005,R/TP N
5 C2614 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP N
5 C2615 CAP,CERAMIC,CHIP ECCH0000165 68 nF,6.3V,K,X5R,HD,1005,R/TP N
5 C2616 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP N
5 C2617 CAP,CERAMIC,CHIP ECCH0000165 68 nF,6.3V,K,X5R,HD,1005,R/TP N
5 C2618 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP N
5 C2619 CAP,TANTAL,CHIP,MAKER ECTZ0002802 100 uF,6.3V ,M ,L_ESR ,ETC ,R/TP N
5 C2621 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C2630 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP N
5 C2631 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP N
5 C2632 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP N
5 C2633 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP N
5 C3013 CAP,CERAMIC,CHIP ECCH0003803 4.7 uF,10V ,Z ,Y5V ,HD ,2012 ,R/TP N
5 C3046 CAP,CERAMIC,CHIP ECCH0000128 100 pF,50V,J,NP0,TC,1005,R/TP N
5 C3051 CAP,CERAMIC,CHIP ECCH0000380 2.2 uF,16V ,Z ,Y5V ,HD ,2012 ,R/TP N
5 C3052 CAP,CERAMIC,CHIP ECCH0003803 4.7 uF,10V ,Z ,Y5V ,HD ,2012 ,R/TP N
5 C3133 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C3134 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C3135 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C3136 CAP,CERAMIC,CHIP ECCH0000274 0.22 uF,16V,Z,Y5V,HD,1608,R/TP N
5 C3137 CAP,CERAMIC,CHIP ECCH0000279 0.47 uF,10V ,Z ,Y5V ,HD ,1608 ,R/TP N
5 C3200 CAP,CERAMIC,CHIP ECCH0000276 1 uF,10V,Z,Y5V,HD,1608,R/TP N
5 C3201 CAP,CERAMIC,CHIP ECCH0000276 1 uF,10V,Z,Y5V,HD,1608,R/TP N
5 C3202 CAP,CERAMIC,CHIP ECCH0006501 10 uF,6.3V ,K ,X5R ,TC ,2012 ,R/TP Y
5 C3203 CAP,CERAMIC,CHIP ECCH0000276 1 uF,10V,Z,Y5V,HD,1608,R/TP N
-260-
Level Location No. Description Part Number Specification SVC Color Remark
5 C3204 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C3205 CAP,CERAMIC,CHIP ECCH0000110 10 pF,50V,D,NP0,TC,1005,R/TP N
5 C3212 CAP,CERAMIC,CHIP ECCH0000143 1 nF,50V,K,X7R,HD,1005,R/TP N
5 C3213 CAP,CERAMIC,CHIP ECCH0000143 1 nF,50V,K,X7R,HD,1005,R/TP N
5 C3215 CAP,TANTAL,CHIP,MAKER ECTZ0000318 33 uF,10V ,M ,L_ESR ,ETC ,R/TP N
5 C3219 CAP,CERAMIC,CHIP ECCH0000143 1 nF,50V,K,X7R,HD,1005,R/TP N
5 C3220 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C3221 CAP,CERAMIC,CHIP ECCH0000115 22 pF,50V,J,NP0,TC,1005,R/TP N
5 C3222 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C3225 CAP,CERAMIC,CHIP ECCH0000274 0.22 uF,16V,Z,Y5V,HD,1608,R/TP N
5 C3243 CAP,CERAMIC,CHIP ECCH0000139 470 pF,50V,K,X7R,HD,1005,R/TP N
5 C3244 CAP,CERAMIC,CHIP ECCH0000380 2.2 uF,16V ,Z ,Y5V ,HD ,2012 ,R/TP N
5 C3245 CAP,TANTAL,CHIP,MAKER ECTZ0003601 10 uF,10V ,M ,STD ,2012 ,R/TP Y
5 C3246 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C3247 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C3248 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP N
5 C3249 CAP,CERAMIC,CHIP ECCH0000114 20 pF,50V,J,NP0,TC,1005,R/TP N
5 C3252 CAP,CERAMIC,CHIP ECCH0000114 20 pF,50V,J,NP0,TC,1005,R/TP N
5 C3255 CAP,CERAMIC,CHIP ECCH0000114 20 pF,50V,J,NP0,TC,1005,R/TP N
5 C3258 CAP,CERAMIC,CHIP ECCH0000114 20 pF,50V,J,NP0,TC,1005,R/TP N
5 C3259 CAP,CERAMIC,CHIP ECCH0000114 20 pF,50V,J,NP0,TC,1005,R/TP N
5 C3260 CAP,CERAMIC,CHIP ECCH0000114 20 pF,50V,J,NP0,TC,1005,R/TP N
5 C3261 CAP,CERAMIC,CHIP ECCH0000114 20 pF,50V,J,NP0,TC,1005,R/TP N
5 C3265 CAP,CERAMIC,CHIP ECCH0000122 47 pF,50V,J,NP0,TC,1005,R/TP N
5 C3266 CAP,CERAMIC,CHIP ECCH0000110 10 pF,50V,D,NP0,TC,1005,R/TP Y
5 C3268 CAP,CERAMIC,CHIP ECCH0000122 47 pF,50V,J,NP0,TC,1005,R/TP N
5 C3269 CAP,CERAMIC,CHIP ECCH0000122 47 pF,50V,J,NP0,TC,1005,R/TP N
5 C3271 CAP,CERAMIC,CHIP ECCH0000122 47 pF,50V,J,NP0,TC,1005,R/TP N
5 C3272 CAP,CERAMIC,CHIP ECCH0000122 47 pF,50V,J,NP0,TC,1005,R/TP N
5 C3276 CAP,CERAMIC,CHIP ECCH0000168 0.1 uF,16V,Z,Y5V,HD,1005,R/TP Y
5 C3278 CAP,CERAMIC,CHIP ECCH0000128 100 pF,50V,J,NP0,TC,1005,R/TP Y
5 D2000 IC EUSY0135001 u289 BGA ,289 PIN,R/TP ,ASIC / BASEBANDCONTROLLER / MARITA
Y
5 D2006 IC EUSY0135201 u181 BGA ,181 PIN,R/TP ,ASIC / WCDMA AIRINTERFACE / WANDA
Y
5 D2007 DIODE,TVS EDTY0006701 CSP ,15 KV,200 mW,R/TP ,4 CHANNEL ESD ARRAY N
5 D2008 DIODE,TVS EDTY0006701 CSP ,15 KV,200 mW,R/TP ,4 CHANNEL ESD ARRAY N
5 D2009 DIODE,TVS EDTY0006701 CSP ,15 KV,200 mW,R/TP ,4 CHANNEL ESD ARRAY N
-261-
Level Location No. Description Part Number Specification SVC Color Remark
5 D2010 DIODE,SWITCHING EDSY0010401 1-1G1A ,40 V,300 A,R/TP ,Silicon Epitaxial SchottkyBarrier Type Diode
N
5 D2012 DIODE,SWITCHING EDSY0010401 1-1G1A ,40 V,300 A,R/TP ,Silicon Epitaxial SchottkyBarrier Type Diode
N
5 D2013 DIODE,SWITCHING EDSY0010401 1-1G1A ,40 V,300 A,R/TP ,Silicon Epitaxial SchottkyBarrier Type Diode
N
5 D2014 DIODE,SWITCHING EDSY0010401 1-1G1A ,40 V,300 A,R/TP ,Silicon Epitaxial SchottkyBarrier Type Diode
N
5 D2015 DIODE,SWITCHING EDSY0011901 EMD2 ,30 V,1 A,R/TP ,VF=1.5V(IF=200mA) ,IR=30uA(VR=10V)
N
5 D2016 DIODE,SWITCHING EDSY0011901 EMD2 ,30 V,1 A,R/TP ,VF=1.5V(IF=200mA) ,IR=30uA(VR=10V)
N
5 D2018 DIODE,TVS EDTY0006701 CSP ,15 KV,200 mW,R/TP ,4 CHANNEL ESD ARRAY N
5 FB1 FILTER,BEAD,CHIP SFBH0002302 120 ohm,1608 ,CHIP BEAD, 2000mA N
5 FB2 FILTER,BEAD,CHIP SFBH0002302 120 ohm,1608 ,CHIP BEAD, 2000mA N
5 FB3 FILTER,BEAD,CHIP SFBH0008901 30 ohm,2012 ,3000mA, BEAD for LARGE CURRENT Y
5 FB4 FILTER,BEAD,CHIP SFBH0008901 30 ohm,2012 ,3000mA, BEAD for LARGE CURRENT Y
5 L1001 INDUCTOR,CHIP ELCH0005003 12 nH,J ,1005 ,R/TP , Y
5 L1002 INDUCTOR,CHIP ELCH0001407 5.6 nH,S,1005,R/TP Y
5 L1100 INDUCTOR,CHIP ELCH0001420 3.9 nH,S ,1005 ,R/TP ,CDMA N
5 L1101 INDUCTOR,CHIP ELCH0001405 3.3 nH,S,1005,R/TP N
5 L1110 INDUCTOR,CHIP ELCH0001402 18 nH,J,1005,R/TP N
5 L1111 INDUCTOR,CHIP ELCH0001001 10 nH,J,1005,R/TP Y
5 L1120 FILTER,BEAD,CHIP SFBH0007103 75 ohm,1005 ,CHIP BEAD, 300mA Y
5 L1200 FILTER,BEAD,CHIP SFBH0007103 75 ohm,1005 ,CHIP BEAD, 300mA Y
5 L1201 INDUCTOR,CHIP ELCH0007404 5.6 uH,K ,1608 ,R/TP , N
5 L1202 FILTER,BEAD,CHIP SFBH0007103 75 ohm,1005 ,CHIP BEAD, 300mA Y
5 L1220 INDUCTOR,CHIP ELCH0007403 100 uH,K ,2012 ,R/TP , N
5 L1230 FILTER,BEAD,CHIP SFBH0007103 75 ohm,1005 ,CHIP BEAD, 300mA N
5 L1300 FILTER,BEAD,CHIP SFBH0007802 600 ohm,3216 ,CHIP FERRITE BEAD N
5 L1330 INDUCTOR,CHIP ELCH0005006 33 nH,J ,1005 ,R/TP , N
5 L1331 INDUCTOR,CHIP ELCH0001401 15 nH,J,1005,R/TP N
5 L1332 FILTER,BEAD,CHIP SFBH0007103 75 ohm,1005 ,CHIP BEAD, 300mA N
5 L1333 FILTER,BEAD,CHIP SFBH0007103 75 ohm,1005 ,CHIP BEAD, 300mA N
5 L1340 INDUCTOR,CHIP ELCH0005010 1.8 nH,S ,1005 ,R/TP , N
5 L1350 INDUCTOR,CHIP ELCH0001427 2.2 nH,S ,1005 ,R/TP , N
5 L1401 INDUCTOR,CHIP ELCH0001427 2.2 nH,S ,1005 ,R/TP , N
5 L1411 INDUCTOR,CHIP ELCH0001408 6.8 nH,S,1005,R/TP N
5 L1421 INDUCTOR,CHIP ELCH0000716 68 nH,J,1608,R/TP N
5 L1422 INDUCTOR,CHIP ELCH0000716 68 nH,J,1608,R/TP N
5 L1441 INDUCTOR,CHIP ELCH0001511 100 nH,J,1608,R/TP N
5 L1501 INDUCTOR,CHIP ELCH0001401 15 nH,J,1005,R/TP N
-262-
Level Location No. Description Part Number Specification SVC Color Remark
5 L1502 INDUCTOR,CHIP ELCH0001401 15 nH,J,1005,R/TP N
5 L1503 INDUCTOR,CHIP ELCH0001407 5.6 nH,S,1005,R/TP N
5 L1504 INDUCTOR,CHIP ELCH0001004 8.2 nH,J,1005,R/TP N
5 L1505 INDUCTOR,CHIP ELCH0001001 10 nH,J,1005,R/TP N
5 L1507 FILTER,BEAD,CHIP SFBH0007103 75 ohm,1005 ,CHIP BEAD, 300mA N
5 L1601 FILTER,BEAD,CHIP SFBH0002302 120 ohm,1608 ,CHIP BEAD, 2000mA N
5 L1602 FILTER,BEAD,CHIP SFBH0002302 120 ohm,1608 ,CHIP BEAD, 2000mA N
5 L1603 FILTER,BEAD,CHIP SFBH0002302 120 ohm,1608 ,CHIP BEAD, 2000mA N
5 L1621 INDUCTOR,SMD,POWER ELCP0005101 4.7 uH,M ,3.8*3.8*1.8 ,R/TP , N
5 L1760 INDUCTOR,CHIP ELCH0003811 1000 nH,K ,1608 ,R/TP ,COIL TYPE N
5 L2200 INDUCTOR,SMD,POWER ELCP0004701 22 uH,M ,5.2*5.2*1.5 ,R/TP , N
5 L2201 FILTER,BEAD,CHIP SFBH0002302 120 ohm,1608 ,CHIP BEAD, 2000mA N
5 L2202 FILTER,BEAD,CHIP SFBH0002302 120 ohm,1608 ,CHIP BEAD, 2000mA N
5 L2500 IC EUSY0163501 SOT323-6L ,6 PIN,R/TP ,EMI FILTER & LINETERMINATION for USB
N
5 L2603 FILTER,BEAD,CHIP SFBH0007103 75 ohm,1005 ,CHIP BEAD, 300mA N
5 L2605 FILTER,BEAD,CHIP SFBH0007103 75 ohm,1005 ,CHIP BEAD, 300mA N
5 L2606 FILTER,BEAD,CHIP SFBH0007103 75 ohm,1005 ,CHIP BEAD, 300mA N
5 L2608 FILTER,BEAD,CHIP SFBH0007103 75 ohm,1005 ,CHIP BEAD, 300mA N
5 N1000 FILTER,SEPERATOR SFAY0003101 900 ,2100 ,1.0 dB,1.4 dB,40 dB,40 dB,ETC ,5.2*4.0*1.8ANTENNA SWITCH MODULE
N
5 N1002 DUPLEXER,IMT SDMY0000301 1950 MHz,2140 MHz,1.25 dB,2.0 dB,25 dB,15dB,10*5.3*1.94 ,SMD ,
N
5 N1100 IC EUSY0132801 56 ball ,56 PIN,R/TP ,RFIC Y
5 N1101 IC EUSY0133101 BGA64 ,64 PIN,R/TP ,U8000 RF IC Y
5 N1300 PAM SMPY0002901 30 dBm,45 %,80 A,50 dBc,23.5 dB,11.6*9.1*1.5 ,SMD , Y
5 N1330 TRANSFORMER,MATCHING STMY0018402 6 PIN,SMD ,GSM Tx Balun Y
5 N1331 TRANSFORMER,MATCHING STMY0018401 6 PIN,SMD ,DCS TX BALUN Y
5 N1400 IC EUSY0133001 uBGA ,56 PIN,R/TP ,U8000 RF IC Y
5 N1620 IC EUSY0136001 3 X 4 UCSP ,10 PIN,R/TP ,600 mA BUCKREGULATORS / DYNAMIC OUTPUT VOLTAGE
Y
5 N1630 PAM SMPY0002801 26 dBm,40 %,83 A,-58 dBc,23.5 dB,8.0*6.0*1.4 ,SMD , Y
5 N1650 ISOLATOR,IMT SQMY0000201 1950 MHz,4.0*4.0*1.9 ,SMD ,1920~1980MHz N
5 N1700 IC EUSY0132901 56 ,56 PIN,R/TP ,WCDMA TXIC Wivi Y
5 N1850 IC EUSY0122502 LLP-6 ,6 PIN,R/TP ,300mA CMOS LDO / 2.8V Y
5 N2000 IC EUSY0132701 u143 BGA ,143 PIN,R/TP ,ASIC / POWERMANAGEMENT IC / VINCENNE
Y
5 N2203 IC EUSY0122402 SC-82AB ,4 PIN,R/TP ,CMOS LDO 1.5V OUTPUT/ 2.0X 2.1
Y
5 N2204 IC EUSY0171302 SOT-23 ,5 PIN,R/TP ,150mA 3.3V LDO Y
5 N2300 IC EUSY0171401 CSP ,20 PIN,R/TP ,7 CHANNEL ESD FILTER ARRAY,KNATTE
N
-263-
Level Location No. Description Part Number Specification SVC Color Remark
5 N2601 IC EUSY0196101 BUMP MICRO SMD ,9 PIN,R/TP ,1W AUDIO AMP Y
5 N2602 IC EUSY0171201 CSP ,25 PIN,R/TP ,6 CHANNEL ESD FILTER, EMPSOLUTION
Y
5 N2603 IC EUSY0148801 SOT23-6 ,6 PIN,R/TP ,SPST SWITCH / 2 OHM Y
5 N3000 IC EUSY0171301 SOT-23 ,5 PIN,R/TP ,150mA 2.8V LDO Y
5 N3100 IC EUSY0122301 SURFACE MOUNT ,7 PIN,R/TP ,IRDA DATA 1.3 LOWPOWER TRANSCEIVER / 115.2kb/s
Y
5 N3200 IC EUSY0129501 SC-74A FIT ,3 PIN,R/TP ,HALL EFFECT SWITCH Y
5 N3201 IC EUSY0088502 MSOP-10 ,10 PIN,R/TP ,CHARGER PUMP // LEDDRIVER / 4.5V 120mA
Y
5 PT1 THERMISTOR SETY0005701 NTC ,47 Kohm,SMD ,F GRADE Y
5 Q2100 TR,BJT,NPN EQBN0013301 2-2H1A ,100 mW,R/TP ,VEBO=6V N
5 Q2200 TR,FET,P-CHANNEL EQFP0003601 SOT-363 ,0.27 W,20 V,0.66 A,R/TP ,Dual(P-channel:PD=0.27W,VDS=-8V,ID=0.57
N
5 Q2201 TR,FET,P-CHANNEL EQFP0004401 1206-8 chipFET ,2.5 W,-20 V,20 A,R/TP,3.10*1.975*1.1(t)
N
5 Q2300 TR,BJT,NPN EQBN0013301 2-2H1A ,100 mW,R/TP ,VEBO=6V N
5 Q3200 TR,BJT,NPN EQBN0013701 EMT6 ,150 mW,R/TP ,DUAL TRANSISTORS N
5 Q3202 TR,BJT,NPN EQBN0014901 SOT323 ,200 mW,R/TP ,NPN SWITCHING TR N
5 Q3203 TR,BJT,PNP EQBP0002401 EMT3 ,.201 W,R/TP , N
5 Q3204 TR,BJT,NPN EQBN0014901 SOT323 ,200 mW,R/TP ,NPN SWITCHING TR N
5 R1003 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R1004 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R1005 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R1006 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R1007 RES,CHIP ERHY0000214 51 ohm,1/16W,J,1005,R/TP N
5 R1103 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R1104 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R1105 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R1106 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R1113 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R1140 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP N
5 R1150 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R1151 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R1210 RES,CHIP ERHY0000220 100 ohm,1/16W,J,1005,R/TP N
5 R1211 RES,CHIP ERHY0000220 100 ohm,1/16W,J,1005,R/TP N
5 R1212 RES,CHIP ERHY0000220 100 ohm,1/16W,J,1005,R/TP N
5 R1213 RES,CHIP ERHY0000220 100 ohm,1/16W,J,1005,R/TP N
5 R1220 RES,CHIP ERHY0000235 560 ohm,1/16W,J,1005,R/TP N
5 R1222 RES,CHIP ERHY0000222 120 ohm,1/16W,J,1005,R/TP N
5 R1223 RES,CHIP ERHY0000231 390 ohm,1/16W,J,1005,R/TP N
5 R1224 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
-264-
Level Location No. Description Part Number Specification SVC Color Remark
5 R1240 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R1250 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R1301 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R1302 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R1320 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R1321 RES,CHIP ERHY0000241 1K ohm,1/16W,J,1005,R/TP N
5 R1325 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R1326 RES,CHIP ERHY0008601 0.05 ohm,1/4W ,J ,2012 ,R/TP N
5 R1327 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R1329 RES,CHIP ERHY0000241 1K ohm,1/16W,J,1005,R/TP N
5 R1332 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R1333 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R1334 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R1335 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R1338 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R1340 RES,CHIP ERHY0000224 180 ohm,1/16W,J,1005,R/TP N
5 R1341 RES,CHIP ERHY0000210 30 ohm,1/16W,J,1005,R/TP N
5 R1342 RES,CHIP ERHY0000224 180 ohm,1/16W,J,1005,R/TP N
5 R1401 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R1410 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R1411 RES,CHIP ERHY0000250 3.3K ohm,1/16W,J,1005,R/TP N
5 R1430 RES,CHIP ERHY0000203 10 ohm,1/16W,J,1005,R/TP N
5 R1431 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R1440 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R1501 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R1502 RES,CHIP ERHY0000111 680 ohm,1/16W,F,1005,R/TP N
5 R1503 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R1504 RES,CHIP ERHY0000111 680 ohm,1/16W,F,1005,R/TP N
5 R1510 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R1603 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R1605 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R1617 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R1621 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R1623 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R1626 RES,CHIP ERHY0000138 33K ohm,1/16W,F,1005,R/TP N
5 R1627 RES,CHIP ERHY0000271 39K ohm,1/16W,J,1005,R/TP N
5 R1628 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP N
5 R1629 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R1630 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
-265-
Level Location No. Description Part Number Specification SVC Color Remark
5 R1631 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R1632 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R1701 RES,CHIP ERHY0000203 10 ohm,1/16W,J,1005,R/TP N
5 R1702 RES,CHIP ERHY0000203 10 ohm,1/16W,J,1005,R/TP N
5 R1703 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R1710 RES,CHIP ERHY0000254 4.7K ohm,1/16W,J,1005,R/TP N
5 R1711 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R1720 RES,CHIP ERHY0000255 5.6K ohm,1/16W,J,1005,R/TP N
5 R1721 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R1723 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R1730 RES,CHIP ERHY0000203 10 ohm,1/16W,J,1005,R/TP N
5 R1740 RES,CHIP ERHY0000203 10 ohm,1/16W,J,1005,R/TP N
5 R1760 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R1770 RES,CHIP ERHY0000241 1K ohm,1/16W,J,1005,R/TP N
5 R1771 RES,CHIP ERHY0000261 10K ohm,1/16W,J,1005,R/TP N
5 R1772 RES,CHIP ERHY0000261 10K ohm,1/16W,J,1005,R/TP N
5 R1810 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R1811 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R1825 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R1826 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R1850 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R1851 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R1997 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R2100 RES,CHIP ERHY0000213 47 ohm,1/16W,J,1005,R/TP N
5 R2101 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP N
5 R2102 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP N
5 R2104 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP N
5 R2105 RES,CHIP ERHY0000283 130K ohm,1/16W,J,1005,R/TP N
5 R2106 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP N
5 R2108 RES,CHIP ERHY0000220 100 ohm,1/16W,J,1005,R/TP N
5 R2109 RES,CHIP ERHY0000213 47 ohm,1/16W,J,1005,R/TP N
5 R2122 RES,CHIP ERHY0000250 3.3K ohm,1/16W,J,1005,R/TP N
5 R2123 RES,CHIP ERHY0000282 120K ohm,1/16W,J,1005,R/TP N
5 R2200 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R2201 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R2202 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R2203 RES,CHIP ERHY0000445 1K ohm,1/16W,J,1608,R/TP N
5 R2205 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R2208 RES,CHIP ERHY0008701 0.22 ohm,1/4W ,J ,2012 ,R/TP N
-266-
Level Location No. Description Part Number Specification SVC Color Remark
5 R2210 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R2212 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R2213 RES,CHIP ERHY0008701 0.22 ohm,1/4W ,J ,2012 ,R/TP N
5 R2214 RES,CHIP ERHY0008602 0.1 ohm,1/4W ,J ,2012 ,R/TP N
5 R2215 RES,CHIP ERHY0008601 0.05 ohm,1/4W ,J ,2012 ,R/TP N
5 R2216 RES,CHIP ERHY0008601 0.05 ohm,1/4W ,J ,2012 ,R/TP N
5 R2217 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R2218 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R2220 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP N
5 R2221 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R2222 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R2223 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R2224 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R2232 RES,CHIP ERHY0000261 10K ohm,1/16W,J,1005,R/TP N
5 R2233 RES,CHIP ERHY0000274 51K ohm,1/16W,J,1005,R/TP N
5 R2235 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R2236 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R2237 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R2238 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R2241 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R2303 RES,CHIP ERHY0000254 4.7K ohm,1/16W,J,1005,R/TP N
5 R2304 RES,CHIP ERHY0000250 3.3K ohm,1/16W,J,1005,R/TP N
5 R2305 RES,CHIP ERHY0000263 15K ohm,1/16W,J,1005,R/TP N
5 R2306 RES,CHIP ERHY0000213 47 ohm,1/16W,J,1005,R/TP N
5 R2312 RES,CHIP ERHY0000261 10K ohm,1/16W,J,1005,R/TP N
5 R2313 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R2314 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R2319 RES,CHIP ERHY0000241 1K ohm,1/16W,J,1005,R/TP N
5 R2400 RES,CHIP ERHY0000143 43K ohm,1/16W,F,1005,R/TP N
5 R2401 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP N
5 R2402 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP N
5 R2502 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R2606 RES,CHIP ERHY0000138 33K ohm,1/16W,F,1005,R/TP N
5 R2607 RES,CHIP ERHY0000252 3.9K ohm,1/16W,J,1005,R/TP N
5 R2608 RES,CHIP ERHY0000252 3.9K ohm,1/16W,J,1005,R/TP N
5 R2609 RES,CHIP ERHY0000138 33K ohm,1/16W,F,1005,R/TP N
5 R2610 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP N
5 R2613 RES,CHIP ERHY0000203 10 ohm,1/16W,J,1005,R/TP N
5 R2617 RES,CHIP ERHY0000266 22K ohm,1/16W,J,1005,R/TP N
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Level Location No. Description Part Number Specification SVC Color Remark
5 R2618 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R2619 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R2620 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R2621 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R2622 RES,CHIP ERHY0000233 470 ohm,1/16W,J,1005,R/TP N
5 R3002 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R3019 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R3026 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP N
5 R3031 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R3041 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP N
5 R3042 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP N
5 R3043 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP N
5 R3045 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP N
5 R3046 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP N
5 R3047 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP N
5 R3049 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP N
5 R3050 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R3051 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP N
5 R3103 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R3110 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R3126 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP N
5 R3127 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP N
5 R3206 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP N
5 R3207 RES,CHIP ERHY0000204 12 ohm,1/16W,J,1005,R/TP N
5 R3208 RES,CHIP ERHY0000204 12 ohm,1/16W,J,1005,R/TP N
5 R3209 RES,CHIP ERHY0000249 2.7K ohm,1/16W,J,1005,R/TP N
5 R3223 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R3227 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R3228 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R3229 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R3230 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R3232 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R3237 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R3248 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R3249 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R3263 RES,CHIP ERHY0000202 4.7 ohm,1/16W,J,1005,R/TP N
5 R3303 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP N
5 R3319 RES,CHIP ERHY0000241 1K ohm,1/16W,J,1005,R/TP N
5 R3322 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP N
-268-
Level Location No. Description Part Number Specification SVC Color Remark
5 R3323 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP N
5 R3325 RES,CHIP ERHY0000220 100 ohm,1/16W,J,1005,R/TP N
5 R3327 RES,CHIP ERHY0000160 180K ohm,1/16W,F,1005,R/TP N
5 R3328 RES,CHIP ERHY0008603 8.2 Kohm,1/16W ,F ,1005 ,R/TP N
5 R3329 RES,CHIP ERHY0000254 4.7K ohm,1/16W,J,1005,R/TP N
5 R3330 RES,CHIP ERHY0000250 3.3K ohm,1/16W,J,1005,R/TP N
5 R3331 RES,CHIP ERHY0000290 300K ohm,1/16W,J,1005,R/TP N
5 R3332 RES,CHIP ERHY0000288 240K ohm,1/16W,J,1005,R/TP N
5 R3341 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R3344 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP N
5 R3345 RES,CHIP ERHY0000714 0.51 ohm,1/8W ,J ,2012 ,R/TP Y
5 R3346 RES,CHIP ERHY0000209 27 ohm,1/16W,J,1005,R/TP N
5 R3347 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP N
5 R3357 RES,CHIP ERHY0000214 51 ohm,1/16W,J,1005,R/TP N
5 R3360 RES,CHIP ERHY0000214 51 ohm,1/16W,J,1005,R/TP N
5 R3363 RES,CHIP ERHY0000214 51 ohm,1/16W,J,1005,R/TP N
5 R3364 RES,CHIP ERHY0000214 51 ohm,1/16W,J,1005,R/TP N
5 R3365 RES,CHIP ERHY0000214 51 ohm,1/16W,J,1005,R/TP N
5 R3366 RES,CHIP ERHY0000214 51 ohm,1/16W,J,1005,R/TP N
5 R3367 RES,CHIP ERHY0000214 51 ohm,1/16W,J,1005,R/TP N
5 R3376 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R3378 RES,CHIP ERHY0000250 3.3K ohm,1/16W,J,1005,R/TP N
5 R3379 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R3380 RES,CHIP ERHY0000250 3.3K ohm,1/16W,J,1005,R/TP N
5 R3381 RES,CHIP ERHY0000273 47K ohm,1/16W,J,1005,R/TP N
5 R3382 RES,CHIP ERHY0000202 4.7 ohm,1/16W,J,1005,R/TP Y
5 R3383 RES,CHIP ERHY0000249 2.7K ohm,1/16W,J,1005,R/TP N
5 R3388 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R3389 RES,CHIP ERHY0000220 100 ohm,1/16W,J,1005,R/TP N
5 R3390 RES,CHIP ERHY0000220 100 ohm,1/16W,J,1005,R/TP N
5 R3395 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R3396 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R3397 RES,CHIP ERHY0000201 0 ohm,1/16W,J,1005,R/TP N
5 R3398 RES,CHIP ERHY0000280 100K ohm,1/16W,J,1005,R/TP N
5 SPFY00 PCB,MAIN SPFY0061403 FR-4 ,.8 mm,NMBI 8 , N
5 U3102 IC EUSY0045305 SOT-23-5 ,5 PIN,R/TP ,ADj. V / 500 mA PEAK LDOREGULATOR
Y
5 U3103 IC EUSY0192901 BGA ,115 PIN,R/TP ,256FLASH 64PSRAM (1.8V) Y
5 U3104 IC EUSY0192801 FBGA ,80 PIN,R/TP ,128M FLASH MEMORY(1.8V) Y
5 V1001 TR,BJT,ARRAY EQBA0002501 USV ,200 mW,R/TP ,NPN // PNP & R. BUILT-IN TR N
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Level Location No. Description Part Number Specification SVC Color Remark
5 V1770 DIODE,VARIABLE CAP EDVY0001801 SCD80 ,0.09 pF,R/TP , N
5 V2201 DIODE,SWITCHING EDSY0011901 EMD2 ,30 V,1 A,R/TP ,VF=1.5V(IF=200mA) ,IR=30uA(VR=10V)
N
5 V2203 DIODE,SWITCHING EDSY0011901 EMD2 ,30 V,1 A,R/TP ,VF=1.5V(IF=200mA) ,IR=30uA(VR=10V)
N
5 V2300 DIODE,TVS EDTY0007001 SOT23-6 ,9 V, W,R/TP ,TVS DIODE ARRAY N
5 V3201 DIODE,TVS EDTY0006401 SC70-6L ,5 V,100 W,R/TP , N
5 V3202 DIODE,SWITCHING EDSY0011901 EMD2 ,30 V,1 A,R/TP ,VF=1.5V(IF=200mA) ,IR=30uA(VR=10V)
N
5 W1001 CONN,RF SWITCH ENWY0003001 STRAIGHT ,SMD ,0.6 dB,3.8X3.0X3.6T Y
5 X2300 CONN,SOCKET ENSY0009901 8 PIN,ETC ,SMD ,2.54 mm,2.2T UIM CONNECTORWITH BRIDGE
Y
5 X2602 CONN,JACK/PLUG,EARPHONE ENJE0003401 , PIN, Y
5 X3200 CONNECTOR,BOARD TO BOARD ENBY0004202 60 PIN,0.5 mm,STRAIGHT ,Au ,B to B CNT(Header) Y
5 X3201 CONNECTOR,BOARD TO BOARD ENBY0017602 20 PIN,0.4 mm,STRAIGHT ,AU ,0.9t, SOCKET forCAMERA
N
5 X3203 CONN,RECEPTACLE ENEY0004101 24 PIN,3 , ,25.3*10*(3+1.5)T Y
5 Z1100 FILTER,SAW SFSY0012901 1842.5 MHz,2.0*2.5*0.8 ,SMD , DCS RX RF SAW Y
5 Z1110 FILTER,SAW SFSY0013001 942.5 MHz,2.0*2.5*0.8 ,SMD ,GSM RX RF SAW Y
5 Z1400 FILTER,SAW SFSY0014201 2140 MHz,2.5*2.0*0.8 ,SMD ,WCDMA Rx RF SAW Y
5 Z1420 FILTER,SAW SFSY0012501 190 MHz,3.8*3.8*1.2 ,SMD ,WCDMA RX IF SAW N
5 Z1500 FILTER,SAW SFSY0014301 1900 MHz,2.5*2.0*1.0 ,SMD ,UMTS Tx RF SAW N
3 SBEY00 BATTERY,ETC SBEY0002901 1.5 V,1.15 mAh,U8100 BACK-UP BATTERY 1.9T Y M38
3 SNMF00 ANTENNA,MOBILE,FIXED SNMF0007401 , dB,U8100 DUAL BAND(GSM,WCDMA) Y M34
3 SUMY00 MICROPHONE SUMY0005601 ASSY ,-44 dB,6.0*1.8 ,U8100 MIC Y M22
-270-
Level Location No. Description Part Number Specification SVC Color Remark
2 MHBY00 HANDSTRAP MHBY0000404 130mm Y DarkGray
2 SBPL00 BATTERY PACK,LI-ION SBPL0072201 3.7 V,1200 mAh,1 CELL,PRISMATIC ,U8150 STDBATTERY PACK
Y
2 SGDY00 DATA CABLE SGDY0005601 DK-40G ,K8000 24PIN I/O + USB A TYPE Y
2 SGEY00 EAR PHONE/EAR MIKE SET SGEY0003701 U8110 ,Cresyn Y
2 SSAD00 ADAPTOR,AC-DC SSAD0007835 FREE ,50 Hz,5.2 V,800 mA,CE,CB ,UK(IO.24P) Y
2 WSYY00 SOFTWARE WSYY0115011 V074I N
2 WSYY01 SOFTWARE WSYY0115211 Bundle CD SW Version 1.0 N
11.3 Accessory
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