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CMOS Operational Amplifier Design
Lesson 2pp. 1-36
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Two stage op amp design
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DC Balance conditions for the two stage op amp
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Design relationships for the two stage op amp
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Op Amp specification
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Unbuffered Op Amp Design Procedure
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Unbuffered Op Amp Design Procedure
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Unbuffered Op Amp Design Procedure
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Example 1 Design of a two-stage op amp
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Example 1
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Example 1
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Example 1
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Example 1
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Incorporating the nulling resistor into the Miller compensated two-stage op amp
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Design of the nulling resistor (M8)
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Example 2 – RHP Zero Compensation
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Example 2
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An alternate form of nulling resistor
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Programmability of the two-stage op amp
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Simulation of the electrical design
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5-to-1 Current Mirror with different physical performances
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Reduction of Parasitics
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Technique for reducing the overlap capacitance
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Chip voltage bias distribution scheme
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PSRR of the two-stage op amp
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Positive PSRR of the two-stage op amp
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Positive PSRR of the two-stage op amp
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Positive PSRR of the two-stage op amp
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Concept of the PSRR+ for the two-stage op amp
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Negative PSRR of the two-stage op amp with Vbias, grounded
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Negative PSRR of the two-stage op amp with Vbiasgrounded
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Negative PSRR of the two-stage op amp with Vbiasconnected to VSS
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Negative PSRR of the two-stage op amp with Vbiasconnected to VSS
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Frequency response of the negative PSRR of the two-stage op amp with VBias connected to VSS
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Approximate model for negative PSRR with VBiasconnected to ground
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Approximate model for negative PSRR with VBiasconnected to VSS
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