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Leo Greiner IPHC DAQ 2007-10 1
Readout for the PIXEL detector for the Heavy Flavor Tracker
upgrade at STAR
Leo Greiner IPHC DAQ 2007-10 2
Talk Structure
• Review of Sensor development and coupled RDO development
• System design
• Detailed system structure
• Data Rates
• Ultimate sensor system discussion
Leo Greiner IPHC DAQ 2007-10 3
IPHC Functional Sensor Development
Data Processing in RDO and on chip by generation of sensor.
The RDO system design evolves with the sensor generation.
•30 x 30 µm pixels•CMOS technology•Full Reticule = 640 x 640 pixel array
Mimostar 2 => full functionality 1/25 reticule, 1.7 ms integration time (1 frame@50 MHz clk), analog output. (in hand and tested)
All sensor families:
Phase-1 and Ultimate sensors => digital output (in development)
SensorPixels
AnalogSignals ADC /
Disc.CDS
DataSparsification
RDOto
DAQ
Mimostar sensors
Phase-1sensors - 640 us integration time
Ultimate sensors - < 200 us integration time
Leo Greiner IPHC DAQ 2007-10 4
System Design – PIXEL Structure
Current Conceptual DesignALICE Style Structure – carbon fiber box beam
•10 sensors / ladder•4 ladders / carrier unit•10 carrier units in the detector
-1 < eta < 1
Inner radius ~ 2.5 cm
Outer radius ~ 8.0 cm
Leo Greiner IPHC DAQ 2007-10 5
System Design – System Blocks• This is a highly parallel system – a schematic representation is shown
below.
Carrier X10
Ladder X 4
Sensor X 10 LU protectedVoltageRegulators
X 40
LVDS, signal,controlMass TerminationPatch
PowerSupplies
RDO Boards
RDO PCs
Trigger,Control,Monitor
DAQ,Control,Monitor
X 10? TBD
X TBD
Leo Greiner IPHC DAQ 2007-10 6
1 m – Low mass twisted pair
3 m - twisted pair
System Design – Physical Layout
Sensors, Ladders, Carriers(interaction point)
LU Protected Regulators,Mass cable termination
RDO Boards DAQ PCs
Magnet Pole Face(Low Rad Area)
DAQ Room
PowerSupplies
Platform
30 m
100 m - Fiber optic cables
Leo Greiner IPHC DAQ 2007-10 7
Detailed System Structure – Sensors and Cables
PIXEL Ladder
40 LVDS Sensor output pairs clock, control, JTAG, power,ground.
10 MAPS Detectors
low mass / stiffnesscables
to motherboard
LVDS drivers
Early prototype cable with 40 differential pair output, clock and control routed under sensorarea.
•4 LVDS outputs / sensor
Cable•4 layer - 150 micron thickness•Aluminum Conductor•Radiation Length ~ 0.1 %•40 LVDS pair signal traces•Clock, JTAG, sync, marker
Fine twisted pair cables125 micron diameter wireSoldered directly to cableLow stiffness / mass
Leo Greiner IPHC DAQ 2007-10 8
Detailed System Structure – LU Protection and Mass Termination
Power Reg.LU detection
Power Reg.LU detection
Power Reg.LU detection
Power Reg.LU detection
1 ladder of 10 sensorssignal, pwr, gnd, clk, etc.Signal + misc. 150 micron dia wirepower, gnd = larger dia.
Main Board
Cable to RDOBoard
Molex typePower connection soldered
connection
mass terminationconnectors to RDOBoard
mass terminationconnector to MainBoard
Connector toMain Board
1 Main Boardper carrier
10 carriers inthe PIXELdetector
Leo Greiner IPHC DAQ 2007-10 9
Detailed System Structure – RDO Board(s)
New motherboard
Two board System – Virtex-5 Development board mated to a new HFT motherboard
Xilinx Virtex-5 Development Board
•Digital I/O LVDS Drivers•4 X >80 MHz ADCs•PMC connectors for SIU•Cypress USB chipset•SODIMM Memory slot•Serial interface•Trigger / Control input
•FF1760 Package•800 – 1200 I/O pins•4.6 – 10.4 Mb block RAM•550 MHz internal clock
Note – This board is designed for development and testing.Not all features will be loadedfor production.
Leo Greiner IPHC DAQ 2007-10 10
Detailed System Structure – RDO Functional Data Path – Phase 1
AddressCounter
Run LengthEncoding?
EventBufferX10?
EventBufferX10?
EventBufferX10?
EventBufferX10?
EventBufferX10?
EventBufferX10?
EventBufferX10?
EventBufferX10?
EventBufferX10?
EventBufferX10?
ONE UNIT PER SENSOR STREAM
EventBuilder
DDL SIUFiber OpticModule
RDOBuffer
ONE UNIT PER MOTHERBOARD
ControlLogic
Motherboard / VIRTEX-5
160 MHz LVDSSensor Data4 Streams / Sensor
Events to DAQ PC
Leo Greiner IPHC DAQ 2007-10 11
Detailed System Structure – RDO Function Data Path – Ultimate
Assumptions – • Data sparsification with rolling shutter architecture. Output from
sensor is a series of addresses – BUT – processing / readout time varies with event occupancy.
• Addition of a trigger input and a frame marker flag that strobes one frame after receipt of a trigger input. But this needs to be pipelined as well. Other simpler methods are also possible.
Rolling ShutterUltimate Sensor
sync
first pixel
trigger
frame marker
LVDS data out
clock
JTAG
pwr, gnd
Leo Greiner IPHC DAQ 2007-10 12
Detailed System Structure – RDO Functional Data Path – Ultimate
EventBufferX10?
EventBufferX10?
EventBufferX10?
EventBufferX10?
EventBufferX10?
EventBufferX10?
EventBufferX10?
EventBufferX10?
EventBufferX10?
EventBufferX10?
ONE UNIT PER SENSOR STREAM
EventBuilder
DDL SIUFiber OpticModule
RDOBuffer
ONE UNIT PER MOTHERBOARD
ControlLogic
Motherboard / VIRTEX-5
160 MHz LVDSSensor Data1 Streams / Sensor
Events to DAQ PC
Leo Greiner IPHC DAQ 2007-10 13
Detailed System Structure – System Level Functioning
PowerSupplies
RDO PCs
DAQ,Control,Monitor
RDO Boards
event data
JTAG to ladder
JTAG to RDO
trig
ger
cont
rol
mo
nito
r
syn
c
LVDS, signal,controlMass TerminationPatch
LU protectedVoltageRegulators
address data
JTAG to ladder
sync
clk, marker, sync clk, marker, sync
LU detect / reset
address data
JTAG to ladder
sync
clk, marker, syncLadder X 4
Sensor X 10
LU protected powerpower
frame marker* frame marker*
trigger*trigger*
* - required for Ultimate Sensor?
Leo Greiner IPHC DAQ 2007-10 14
Data Rates - Parameters
• Rates as per Jim Thomas, L = 3 x 1027 for Phase-1, L = 8 x 1027 for Ultimate.
• 2.5 hits / cluster.• 1 kHz average event rate.• 10 inner ladders, 30 outer ladders.• Factor of 1.6 for event format overhead (can be
lowered).• No run length encoding.
61.5 6.0
157.0 15.0
R = 2.5 R = 8.0
200 us
640 us
Hits / Sensor at L = 8 x 1027.
IntegrationTime
Radius
Leo Greiner IPHC DAQ 2007-10 15
Data Rates
• Ultimate => 49.7 MB / s raw addresses.
=> 79.5 MB / s data rate.
• Phase–1 => 59.6 MB / s raw addresses
=> 95.4 MB / s data rate.
The dead-time is primarily limited by the number of externally allocated readout buffers!
Leo Greiner IPHC DAQ 2007-10 16
Data Rates – Dead time and Latencies
• Average Ultimate inner sensor event size is 3.1 kb.
• RDO at 160MHz on 1 LVDS link / sensor takes 19.4 us (< 200 us integration time)
• What is the latency for data sparsification?• If the system were dead during the integration
time (after trigger) and one serial RDO time we would be 21.9% dead at 1 kHz.
• Look for ways to improve, earlier method is just one.
Leo Greiner IPHC DAQ 2007-10 17
Ultimate Sensor System Discussion
• The design of the Ultimate SYSTEM should be an integrated design with the sensor and RDO designed to complement each other's capabilities.
• Question – is it advantageous to use the processing capabilities inherent in an FPGA based RDO system to offload some of the functionality of the sensor? Would this help the overall system design?
Leo Greiner IPHC DAQ 2007-10 18
fin